.

The research thesis was done under the supervision of Prof. Dan Ritter and Dr. Miki
Moyal in the Faculty of Electrical Engineering and Microelectronics Research Center, in collaboration with Fraunhofer-Institut f ¨ur Angewandte Festk ¨orperphysik (IAF),
Freiburg, Germany
The generous financial help of the Technion is gratefully acknowledged
It would not have been possible to write this doctoral thesis without the help and support of the kind people around me, to only some of whom it is possible to give particular mention here:
1. I would like to thank the Technion, the Faculty of Electrical Engineering, and the
Microelectronics Research Center, in which the research was carried out.
2. Deep thanks to Prof. Dan Ritter and Dr. Miki Moyal for their dedicated supervision and for the support, help, and inspiration along the way.
3. I am indebted to my colleagues in Prof. Dan Ritter’s research group: Arkadi Gavrilov,
Shimon Cohen, Doron Cohen-Elias, Eli Bloch, Avi Sayag, Alona Mashaal, Eilam
Yalon, Kobi Greenberg, Ran Halevi, Alex Sulkin, and David Mistele, for thousands of invaluable small assistances.
4. I owe my deepest gratitude to the Israeli Ministry of Defense for supporting the research project. In particular, special thanks are given to Dr. David Rosenfeld for his extensive support.
5. In the collaboration with Fraunhofer IAF I have been blessed with a friendly and cheerful group of researchers and friends. I would like to thank all of them, and in particular, Prof. Dr. Oliver Ambacher, Dr. Michael Schlechtweg, Prof. Dr. Ingmar
Kallfass, Dr. Robert Elvis Makon, Dr. Rachid Driad, Dr. Josef Rosenzweig, Dr.
Ulrich Nowotny, and Ms. Hildegard Brucher.
6. This thesis would not have been possible without the indispensable help and continuous support from my parents, Leah and Jehoshua Kraus, and my parents inlaw, Sarah and Elimelech Westreich, to whom my gratitude is given.
7. Finally, special thanks are given to my wife, Naama, and my children – Mattan,
Noa, and Yuval – for their patience and solidarity, and being a great family that gave me vitality to do the research and complete it.

.

.
1. S. Kraus, I. Kallfass, R.E. Makon, R. Driad, M. Moyal, and D. Ritter, “A 10-GS/s multibit delta-sigma analog-to-digital converter in an InP HBT technology”, Proceedings of COMCAS 2011 , November 2011.
2. Shraga Kraus, Ingmar Kallfass, Robert E. Makon, Rachid Driad, Michael Moyal, and Dan Ritter, “A 20-GHz bipolar latched comparator with improved sensitivity implemented in InP HBT technology”, IEEE Transactions on Microwave Theory and
Techniques , Vol. 59, No. 3, pp. 707-715, March 2011.
3. S. Kraus, R.E. Makon, I. Kallfass, R. Driad, M. Moyal, and D. Ritter, “Sensitivity of a 20- GS/s InP DHBT latched comparator”, Proceedings of IPRM 2010 , pp. 115-118,
June 2010.
4. S. Kraus, I. Kallfass, R.E. Makon, J. Rosenzweig, R. Driad, M. Moyal, and D. Ritter, “High linearity 2-bit current steering InP/GaInAs DHBT digital-to-analog converter”, Proceedings of IPRM 2010 , pp. 317-320, June 2010.
5. S. Kraus, D. Cohen-Elias, S. Cohen, A. Gavrilov, O. Karni, Y. Swirski, G. Eisenstein, and D. Ritter, “High-Gain Top-Illuminated Optoelectronic Integrated Receiver”,
Proceedings of IPRM 2007 , pp. 77-80, May 2007.
6. Shraga Kraus, David Gidony, Mario Zajac, Arkadi Gavrilov, Shimon Cohen, Ingmar Kallfass, Robert E. Makon, Rachid Driad, Michael Moyal, and Dan Ritter,
“Gain-enhanced fully-differential amplifier for both 45 nm digital CMOS and InP/
GaInAs HBT technologies”, in preparation.
7. D. Cohen Elias, S. Kraus, S. Cohen, A. Gavrilov, and D. Ritter, “A double-heterojunction bipolar transistor having a degenerately doped emitter and backwarddiode base contact”, IEEE Transactions on Electron Devices , Vol. 58, No. 7, pp. 1952-
1956, July 2011.
8. D. Cohen Elias, A. Gavrilov, S. Cohen, S. Kraus, and D. Ritter, “InP DHBTs having simultaneously deposited base and emitter contacts”, Proceedings of IPRM 2010 ,
June 2010.

9. D. Cohen Elias, A. Gavrilov, S. Cohen, S. Kraus, and D. Ritter, “InP DHBTs having sidewall and lateral collector Schottky contacts”, Proceedings of IPRM 2010 , June
2010.
10. D. Cohen Elias, A. Gavrilov, S. Cohen, S. Kraus, A. Sayag, and D. Ritter, “Abrupt delta-doped InP/GaInAs/InP DHBTs with 0.45µ m -wide T-shaped emitter contacts”, IEEE Electron Device Letters , Vol. 29, No. 9, pp. 971-973, September 2008.
11. Evgeny Shumakher, Tsufit Magrisso, Shraga Kraus, Doron Cohen-Elias, Arkady
Gavrilov, Shimon Cohen, Gadi Eisenstein, and Dan Ritter, “An InP HBT-based oscillator monolithically integrated with a photodiode”, IEEE Journal of Lightwave
Technology , Vol. 26, No. 15, pp. 2679-2683, August 2008.
12. D. Cohen Elias, A. Gavrilov, S. Cohen, S. Kraus, and D. Ritter, “DHBT with Esaki base emitter junction having a 60 nm wide emitter contact”, Proceedings of IPRM
2008 , May 2008.
13. T. Magrisso, D. Elad, N. Buadana, S. Kraus, D. Cohen Elias, A. Gavrilov, S. Cohen, and D. Ritter, ”An X-band low noise InP-HBT VCO with separate optimized varactor layers”, MTT-S International Microwave Symposium Digest , pp. 661-664, June
2007.
14. D. Cohen Elias, S. Kraus, A. Gavrilov, S. Cohen, N. Buadana, V. Sidorov, and D. Ritter, “Design and performance of InP/GaInAs/InP abrupt DHBTs”, Proceedings of
IPRM 2005 , pp. 449-451, May 2005.
15. D. Cohen Elias, S. Kraus, A. Gavrilov, S. Cohen, N. Buadana, V. Sidorov, and D. Ritter, “An abrubt InP-GaInAs-InP DHBT”, IEEE Electron Device Letters , Vol. 26, No. 1, pp. 14-16, January 2005.

Abstract
List of Acronyms
List of Symbols
1 Introduction 9
1.1
Scientific Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
1.1.1
Analog-to-Digital Conversion . . . . . . . . . . . . . . . . . . . . . .
10
1.1.2
The ∆Σ ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12
1.2
State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
1.3
Research Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
1.3.1
Building Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
1.3.2
Complete ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
References for Chapter 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
2 Comparator 23
2.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
2.2
Analysis of Comparator Performance . . . . . . . . . . . . . . . . . . . . .
24
2.2.1
Speed Limits of the ECL Comparator . . . . . . . . . . . . . . . . .
24
2.2.2
Speed Enhancement Techniques . . . . . . . . . . . . . . . . . . . .
28
2.2.3
Sensitivity Enhancement Techniques . . . . . . . . . . . . . . . . . .
29
2.3
Improved Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
2.3.1
Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
30
2.3.2
Comparator Design and Simulations . . . . . . . . . . . . . . . . . .
32
2.4
Circuit Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
2.5
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
References for Chapter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
3 2-Bit DAC 43
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
3.2
DAC Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
1
3
5

ii TABLE OF CONTENTS
3.3
DAC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
3.4
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
48
References for Chapter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49
4 Operational Amplifier 51
4.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
52
4.2
Gain Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
4.3
CMOS Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
4.3.1
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
4.3.2
Process Variation Compensation . . . . . . . . . . . . . . . . . . . .
55
4.3.3
Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
4.4
HBT Op Amp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
4.4.1
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
4.4.2
Process Variation Compensation . . . . . . . . . . . . . . . . . . . .
60
4.4.3
Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
4.4.4
Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
4.4.5
Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
4.5
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
References for Chapter 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
65
5 ∆Σ ADC 67
5.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
5.2
System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
5.2.1
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
5.2.2
System-Level Simulations . . . . . . . . . . . . . . . . . . . . . . . .
72
5.3
Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
5.3.1
Loop Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
5.3.2
2-Bit Quantizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
5.3.3
Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
5.3.4
Measurement Auxiliary Circuits . . . . . . . . . . . . . . . . . . . .
80
5.3.5
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
82
5.4
Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
5.4.1
SNR Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
5.4.2
Linearity Measurement . . . . . . . . . . . . . . . . . . . . . . . . .
86
5.4.3
Time Domain Measurement . . . . . . . . . . . . . . . . . . . . . . .
87
5.5
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
References for Chapter 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
6 Summary 95
6.1
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
6.2
2-Bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
6.3
Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96

TABLE OF CONTENTS iii
6.4
∆Σ ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
96
A Technion’s HBT Technology 99
A.1 Layer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
A.2 Wafer Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
References for Appendix A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
B A GUI for ∆Σ Modulator Design 103
B.1 MATLAB Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
B.2 MATLAB Figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

iv TABLE OF CONTENTS

1.1
Sampling in the frequency domain . . . . . . . . . . . . . . . . . . . . . . .
11
1.2
Block diagram of a first order ∆Σ ADC and equivalent linear model of a lowpass ∆Σ ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
1.3
Block diagram of a second order ∆Σ ADC . . . . . . . . . . . . . . . . . . .
14
1.4
Sinusoidal signal sampled by a simulated ideal 2-bit second order ∆Σ ADC 15
2.1
Logic diagram of a master-slave D-FF . . . . . . . . . . . . . . . . . . . . .
25
2.2
Circuit diagram of a fully differential ECL D-latch . . . . . . . . . . . . . .
25
2.3
Waveforms of D-latch’s outputs . . . . . . . . . . . . . . . . . . . . . . . . .
26
2.4
Circuit diagram of a D-latch with peaking inductors . . . . . . . . . . . . .
28
2.5
Circuit diagram of a D-latch with keep-alive tail current . . . . . . . . . . .
30
2.6
Circuit diagram of an improved D-latch . . . . . . . . . . . . . . . . . . . .
31
2.7
Simplified circuit diagram of the master-slave ECL comparator . . . . . .
33
2.8
Simulated waveforms of the comparator at 20 GS/s . . . . . . . . . . . . .
33
2.9
Simulated sensitivity of the comparator at 20 GS/s versus degeneration resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
34
2.10 Microphotographs of the comparators . . . . . . . . . . . . . . . . . . . . .
35
2.11 Schematic diagrams of the measurement setups . . . . . . . . . . . . . . .
36
2.12 Measured waveform of the comparator differential output using the fully synchronized setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
2.13 Measured waveforms of the comparators differential output using the sensitivity measurement setup . . . . . . . . . . . . . . . . . . . . . . . . .
38
3.1
Schematic circuit diagram of the DAC . . . . . . . . . . . . . . . . . . . . .
44
3.2
Layout of the DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
3.3
Closeup of the layout of the current source devices . . . . . . . . . . . . . .
46
3.4
Microphotograph of the circuit . . . . . . . . . . . . . . . . . . . . . . . . .
46
3.5
Measured DC transfer function of the DAC . . . . . . . . . . . . . . . . . .
47
3.6
Measured integral and differential nonlinearities of the DAC . . . . . . . .
47
3.7
Measured waveforms of the DAC output . . . . . . . . . . . . . . . . . . .
48
3.8
Simulated waveform of the DAC output at 20 GS/s . . . . . . . . . . . . .
49

vi LIST OF FIGURES
4.1
Examples of partial positive feedback gain-enhanced amplifiers . . . . . .
53
4.2
Schematic diagram of the proposed gain-enhanced CMOS amplifier . . . .
54
4.3
Schematic diagram of the proposed CMOS amplifier with an output stage and common mode feedback . . . . . . . . . . . . . . . . . . . . . . . . . .
56
4.4
The proposed CMOS amplifier with biasing circuitry for compensating the effect of process variations . . . . . . . . . . . . . . . . . . . . . . . . . .
57
4.5
Simulated open loop gain, phase, and input-referred noise of the CMOS amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
4.6
Schematic diagram of the proposed gain-enhanced bipolar amplifier . . .
59
4.7
The proposed bipolar amplifier with additional diodes for compensating the effect of process variations . . . . . . . . . . . . . . . . . . . . . . . . . .
61
4.8
Schematic diagram of the proposed HBT-based amplifier with a second amplification stage, output stage, and common mode feedback . . . . . .
62
4.9
Simulated open loop gain, phase, and input-referred noise of the HBTbased amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
63
4.10 Schematic diagram of the closed loop circuit used for op amp characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
4.11 Layout and microphotograph of the closed loop amplifier . . . . . . . . .
64
5.1
Block diagram of a second order ∆Σ ADC . . . . . . . . . . . . . . . . . . .
69
5.2
Schematic diagram of the loop filter . . . . . . . . . . . . . . . . . . . . . .
70
5.3
Diagrams used for the linear model and derivation of signal transfer function, noise transfer function, and loop transmission . . . . . . . . . . . . .
71
5.4
GUI of the MATLAB program used for designing loop stability . . . . . .
73
5.5
Simulated waveform of the complete ADC clocked at 20 GS/s . . . . . . .
73
5.6
Top level schematic diagram of a second order ∆Σ ADC . . . . . . . . . . .
74
5.7
Schematic diagram of the op amp . . . . . . . . . . . . . . . . . . . . . . . .
75
5.8
Schematic diagram of the differential 2-bit flash ADC . . . . . . . . . . . .
76
5.9
Schematic diagram of the comparator’s preamplifier . . . . . . . . . . . . .
77
5.10 Schematic diagram of the comparator’s master-slave latch . . . . . . . . .
78
5.11 Schematic diagram of the 2-bit DAC . . . . . . . . . . . . . . . . . . . . . .
79
5.12 Structure of the clock distribution manifold . . . . . . . . . . . . . . . . . .
80
5.13 Schematic diagram of the output buffer . . . . . . . . . . . . . . . . . . . .
81
5.14 Layout of the building blocks of the ∆Σ ADC . . . . . . . . . . . . . . . . .
83
5.15 Layout of the ∆Σ ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
5.16 Microphotograph of the ∆Σ ADC . . . . . . . . . . . . . . . . . . . . . . . .
85
5.17 Measurement setup used for SNR evaluation . . . . . . . . . . . . . . . . .
86
5.18 Spectrum of the ADC’s output during SNR measurement . . . . . . . . . .
87
5.19 Two-tone measurement setup and results . . . . . . . . . . . . . . . . . . .
88
5.20 Time domain measurement setup . . . . . . . . . . . . . . . . . . . . . . . .
89
5.21 Output DAC levels measured on the output histogram . . . . . . . . . . .
89

LIST OF FIGURES vii
A.1 SEM images of a transistor at various processing stages . . . . . . . . . . . 102
B.1 MATLAB figure of delsig2 design . . . . . . . . . . . . . . . . . . . . . . . 114

viii LIST OF FIGURES

1.1
Recent publications on HBT-based ∆Σ ADCs . . . . . . . . . . . . . . . . .
18
2.1
Recently published fast comparators . . . . . . . . . . . . . . . . . . . . . .
39
4.1
Comparison of CMOS 1-V gain-enhanced amplifiers . . . . . . . . . . . . .
57
5.1
Summary of ADC performance . . . . . . . . . . . . . . . . . . . . . . . . .
90
5.2
Comparison of this work to recent publications on HBT-based ∆Σ ADCs .
91
A.1 Layer properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

x LIST OF TABLES

NALOG-to-digital converters ( ADC s) based upon heterojunctio bipolar transistor ( HBT ) technologies have reached record breaking sampling rates.
However, the existing technologies set strict limitation on the maximum number of transistors that can be incorporated in a single circuit. As a result, HBT-based ADCs usually rely upon the flash and delta-sigma ( ∆Σ ) architectures.
∆Σ ADCs consist of a feedback loop of data conversion, typically of low resolution, namely 1 to 3 bits. Nevertheless, the linearity of some of the elements embedded in the loop must be sufficiently high to support the final resolution of the ∆Σ ADC. Since digital methods of nonlinearity correction are too complex for HBT technologies, all HBT-based
∆Σ ADCs known to us incorporated a single-bit DAC, which is linear by definition. Here, we present a multibit ∆Σ ADC based upon the InP HBT technology, which incorporated an internal resolution of 2 bits.
The research consists of two stages. The first stage focuses on the building blocks of the converter: a sensitivity-enhanced latched comparator, gain-enhanced amplifier, and high linearity DAC were investigated. In the second stage of the research the building blocks were combined to demonstrate a 10 GS/s second order 2-bit low pass ∆Σ ADC.
Architecture, performance, stability, and other design parameters were studied.
The research was done in the Faculty of Electrical Engineering and Microelectronics
Research Center, Technion – Israel Institute of technology, in collaboration with Fraunhofer-Institut f ¨ur Angewandte Festk ¨orperphysik ( IAF ), Freiburg, Germany.

2 Abstract

AC
ACP
ADC
ADS
Alternating Current
Adjacent Channel Power
Analog-to-Digital Converter
Advanced Design System ( Agilent ADS )
BER Bit Error rate
CMFB Common Mode FeedBack
CMOS Complementary Metal-Oxide-Semiconductor
CMRR Common Mode Rejection Ratio
CPW CoPlanar Waveguide
CT ∆Σ Continuous-Time Delta-Sigma
DAC Digital-to-Analog Converter
DC
DRC
Direct Current
Design Rule Check
DHBT Double-Heterojunction Bipolar Transistor
DNL Differential NonLinearity
DT ∆Σ Discrete-Time Delta-Sigma
DUT Device Under Test
ECL Emitter-Coupled Logic
ENOB Effective Number Of Bits
FET
FoM
Field-Effect Transistor
Figure of Merit
GPIB
GUI
General Purpose Interface Bus ( IEEE 488 )
Graphical User Interface
HBT Heterojunction Bipolar Transistor
HP ∆Σ HighPass Delta-Sigma
IAF
IIT
INL
Institut f ¨ur Angewandte Festk ¨orperphysik ( Fraunhofer IAF )
Israel Institute of Technology ( Technion – IIT )
Integral NonLinearity

4
RMS
SEM
SHBT
SI
SFDR
SNDR
SNR
SPA
STF
TLM
UGB
VBIC
∆Σ
NPN
NTF
OSR
PC
PMOS
PN
PSRR
RF
LF
LP ∆Σ
LSB
Low Frequency
LowPass Delta-Sigma
Least-Significant Bit
LVS Layout Versus Schematic
MOMBE Metal Organic Molecular Beam Epitaxy
MOS
NMOS
Metal-Oxide-Semiconductor ( MOS transistor
N-channel Metal-Oxide-Semiconductor (
)
NMOS transistor )
N-type – P-type – N-type (
Noise Transfer Function
Over-Sampling Ratio
Personal Computer
P-type – N-type (
Radio Frequency
NPN transistor
P-channel Metal-Oxide-Semiconductor (
PN junction )
Power Supply Rejection Ratio
)
PMOS transistor )
Root Mean Square
Scanning Electron Microscope
Single-Heterojunction Bipolar Transistor
Semi-Insulator
Spurious Free Dynamic Range
Signal-to-(Noise-and-Distortion) Ratio
Signal-to-Noise Ratio
Semiconductor Parameter Analyzer
Signal Transfer Function
Transfer Length Method
Unity-Gain Bandwidth
Vertical Bipolar Inter-Company (
Delta-Sigma
VBIC model )
List of Acronyms

A
A
E f s f sig g m
G n a
A j
A q
BW sig
C bc
C be
C
L
C par
H
1
H
2
H
I
H q
K
L
I bias i n open loop gain of an op amp gain of a comparator’s latching pair flicker noise empirical exponential coefficient junction area quantizer’s gain signal bandwidth transistor’s base-collector capacitance transistor’s base-emitter capacitance load capacitance interconnect parasitic capacitance quantization error sampling frequency signal frequency transistor’s transconductance gain of the n th loop filter of a ∆Σ ADC transfer function of the 1 st transfer function of the 2 nd loop filter loop filter transfer function of an integrator transfer function of the quantizer biasing current noise current
Boltzmann’s constant loop order of a ∆Σ ADC
LT
M m
N loop transmission final resolution of a number of bits loop resolution of a
∆Σ
∆Σ
NTF noise transfer function
ADC (in bits)
ADC (in bits)

6 List of Symbols
SNR
SNR
CK J
SNR max
STF
T t alloc t t charge
∗ charge t latch t rec t reg
T s t track
V
BE
V be v be
V dsat
V in v min
OSR
P
P qn r e
R
E r ce r
D r ds r ee
P
MS
P sig q
Q n
R
L
R
L , e f f
S , s
SNR over-sampling ratio power consumption quantization noise power probability of metastability input signal power electron’s electric charge quantization noise base contact parasitic resistance emitter degeneration resistance transistor’s colletor-emitter resistance small signal resistance of a forward biased diode transistor’s drain-source resistance emitter contact parasitic resistance load resistance effective load resistance sampling function (in the frequency/time domain) signal-to-noise ratio signal-to-noise ratio signal-to-noise ratio originating by clock jitter maximum signal-to-noise ratio of a ∆Σ ADC signal transfer function temperature the time allocated for a comparator’s latching pair to switch charging time of a comparator’s latching pair transistors charging time of a comparator’s tracking pair transistors comparator total delay during the latching phase recovery time of a comparator’s tracking pair regeneration time of a comparator’s latching pair sampling time interval comparator total delay during the tracking phase transistor’s base-emitter voltage (DC) transistor’s base-emitter voltage (large signal) transistor’s base-emitter voltage (small signal) drain-source saturation voltage of a MOS transistor input voltage the minimum voltage at the input of a comparator’s latching pair that can be regenerated to full scale voltage

V re f
V
T
X , x
Y , y
β
∆
∆ V
δ v
∆ V be
∆ V par
η
τ load
τ
∗ load
τ q the analog range of an ADC threshold voltage of a MOS transistor input signal (in the frequency/time domain) output signal (in the frequency/time domain) forward current gain of a bipolar transistor the analog range represented by the LSB comparator’s output voltage swing (full scale) comparator’s output voltage in the beginning of the latching process the change in a transistor’s base-emitter voltage the change in the voltage across an interconnect parasitic capacitance loop gain of gain enhancement positive feedback load RC constant of a comparator during the latching phase load RC constant of a comparator during the tracking phase quantizer’s delay
7

8 List of Symbols

HIS chapter introduces the background of the research thesis. The basics of analog-to-digital conversion and the delta-sigma ( ∆Σ ) analog-to-digital converter ( ADC ) are presented in the first section. The second section of the chapter surveys state of the art in the field of fast ∆Σ ADCs. Structure of the thesis is the subject of the third section. The thesis consists of two stages: the first stage deals with the building blocks of the ADC, while in the second stage the blocks are put together to form a complete ∆Σ converter. The challenges concerned with each stage are also discussed in this section.

10 Chapter 1. Introduction
1.1.1
Analog-to-Digital Conversion
In analog-to-digital conversion an analog signal, which is continuous both in time and value, is sampled and quantized. The sampling transforms the signal to the discrete time domain, while the quantization provides discrete value. This section outlines the basics of analog-to-digital conversion and ADCs.
Aliasing
Ideal sampling of an analog signal, x ( t ) , at constant time interval, T s
, yields a sampled signal, y ( t ) : y ( t ) = x ( t ) s ( t ) , (1.1) where s ( t ) is the sampling function, s ( t ) =
+ ∞
n = − ∞
δ ( t − nT s
) .
In the frequency domain
S ( f ) =
+ ∞
m = − ∞
δ ( f − m f s
) , where f s
= 1
T s is the sampling frequency. The sampled signal is now
Y ( f ) = X ( f ) ∗ S ( f ) ,
(1.2)
(1.3)
(1.4) where Y ( f ) and X ( f ) are the spectrum of y ( t ) and x ( t ) , respectively. The convolution creates infinite duplicates of the signal’s spectrum around the impulses of S ( f ) . This duplication is referred to as aliasing [1]. Nyquist sampling is shown in Fig. 1.1(a), and over-sampling in Fig. 1.1(b). In case of under-sampling (Fig. 1.1(c)) overlap of the duplicates results in distortion of the signal in the overlapping frequency ranges.
Resolution and Quantization
An ADC converts an analog quantity within a specific range into a digital number of a certain number of bits, denoted m . When voltage is sampled within the range of V re f
, the analog range represented by the least-significant bit ( LSB ) is given by
∆ =
V re f
2 m
.
(1.5)
The error caused by rounding the sampled value to an integer of a limited range is the quantization error , or quantization noise , when referred back to the analog input, denoted by Q n
.

1.1. Scientific Background 11
(a)
(b)
(c)
Figure 1.1: Sampling in the frequency domain: (a) Nyquist sampling,
(b) over-sampling, and (c) under-sampling
Assuming that the quantization noise is uniformly distributed between −
∆
2 its power is given by [1]
∆ 2
P qn
= Q 2 n
=
12
.
and +
∆
2
,
(1.6)
Due to the uniform distribution quantization noise is white in the frequency domain. If the signal introduced at the input is a sine wave with an amplitude of
V re f
2
, the power of the signal is
P sig
= 2
2 m − 3
∆
2
, (1.7) and the signal-to-noise ratio ( SNR ) at the output is therefore
SNR =
P sig
P qn
=
3
2
· 2
2 m
.
(1.8)
In decibels (1.8) can be rewritten as
SNR dB
= 10 log
10
( SNR ) = 6.02
m + 1.76 .
(1.9)
For a given SNR , the resolution of an ADC, in terms of effective number of bits ( ENOB ), equals to
ENOB =
SNR dB
− 1.76
6.02
, (1.10) implying that if the input-referred noise is higher than the quantization noise, ENOB is reduced.

12 Chapter 1. Introduction
Over-Sampling
In the Nyquist sampling case, an anti-aliasing filter introduced at the input should exhibit a very steep slope exactly at the Nyquist frequency. However, if the signal is oversampled the requirements from the filter are relaxed, as Fig. 1.1(b) implies. Another outcome of over-sampling is that quantization noise at frequencies higher than the signal’s bandwidth can be digitally filtered out. This increases SNR by about 3 dB (
1
2 bit) for every doubling of the over-sampling ratio ( OSR ) – the ratio between the Nyquist and the signal bandwidths.
ADC Figures of Merit and Characterization
ADCs are characterized by sampling rate, OSR , ENOB , input dynamic range, and power consumption. In order to determine the value of ENOB a continuous sine wave is applied at the input, and data are sampled at the output. Conversion of the sampled data to the frequency domain facilitates the calculation of noise and signal power. Note that in a practical ADC the input-referred noise includes also other noise mechanisms than quantization noise, such as amplifier noise and nonlinearity. Powers of all noise mechanisms sum up to the total noise power that determines ENOB .
Due to limitations of lab instruments it is common to characterize an ADC in two steps: in the first step only the quantization and conventional noises are taken into the calculation of SNR ; in the second step only the nonlinearity is treated. The total signalto-(noise-and-distortion) ratio ( SNDR ) is then substituted in (1.10).
Since data acquisition at very high frequencies is an involved task a different measurement method was used in this work (refer to Section 5.3.4).
1.1.2
The
ADC
A delta-sigma ADC ( ∆Σ ADC ) is a feedback structured over-sampling ADC. For historical reasons, ∆Σ ADC is often called ∆Σ modulator . This section outlines ∆Σ ADC basics.
Structure
A schematic diagram of a simple ∆Σ ADC is shown in Fig. 1.2(a). The converter consists of a noise shaping filter, N -bit ADC (usually 1- to 3-bit flash quantizer), delay element
(usually the latched comparators of the ADC provide the desired delay), N -bit digitalto-analog converter ( DAC ), and decimation filter [2]. The latter is a digital filter that converts the N -bit data coming from the N -bit ADC into M -bit data ( M ≫ N ). The feedback manipulates the spectrum of the quantization noise. This effect is referred to as “ noise shaping ”, increasing the resolution in a bandwidth of interest, at the expense of excessive noise in the rest of the Nyquist band. Both lowpass and bandpass ∆Σ ( LP ∆Σ and BP ∆Σ ) are of interest. The noise shaping filter in a LP ∆Σ is an integrator, and in a
BP ∆Σ a bandpass filter.

1.1. Scientific Background
Analog In
X
Noise
Shaping
Analog Region
N-bit
ADC
N-bit
DAC integrator
1
1 – Z
-1
Delay
Z –1
Digital Region
(a)
E delay
Z
-1
Decimation
Filter
Digital Out
M bits
Y
(b)
Figure 1.2: (a) Block diagram of a first order ∆Σ ADC; (b) equivalent linear model of a lowpass ∆Σ ADC
13
The modulator is analyzed using the linear model of Fig. 1.2(b). The quantizer (containing the ADC and DAC) is modeled as a delay with quantization noise. The loop equation in the z domain is
Y =
X z
+ E 1 −
1 z
, (1.11) where X is the input signal, Y the output signal, and E the quantization error. The signal transfer function (for E = 0) is given by
STF ( z ) = z
− 1
, (1.12) and the noise transfer function (for X = 0) is
NTF ( z ) = 1 − z
− 1
.
Substituting z = e j · 2 π f s = e j ω s yields the noise power spectral density:
(1.13)
| NTF ( ω ) |
2
= 2 sin π
ω
ω s
2
.
(1.14)
The spectral density approaches 0 when ω pass filtering.
→ 0, and 4 when ω →
ω s
2
, providing high-

14 Chapter 1. Introduction
Analog In
Noise
Shaping
Noise
Shaping
Analog Region
N-bit
ADC
N-bit
DAC
Delay
Z
–1
Digital Region
Decimation
Filter
Digital Out
M bits
Figure 1.3: Block diagram of a second order ∆Σ ADC
Resolution can be enhanced by an additional feedback loop and additional noise shaping filter, and possibly another DAC [3, 4] – as illustrated in Fig. 1.3. The loop equation is now
2
Y =
X z
+ E 1 −
1 z
, (1.15) and the noise power spectral density becomes
| NTF ( ω ) |
2
= 2 sin π enhancing resolution at low frequencies.
ω
ω s
4
, (1.16)
Performance
The M -bit ADC resolution is determined by loop resolution, N (in bits), order of the
ADC (number of nested feedback loops), L , and OSR . The maximum SNR that can be achieved by an ideal ∆Σ ADC with unity gain feedback loops is [5]
SNR max
= 10 log
3
2
2
N
− 1
2
·
( 2 L + 1 ) OSR 2 L + 1
π 2 L
.
(1.17)
For example, a 2-bit first order ADC with OSR = 16 yields SNR max of 42.25 dB , namely, a resolution of 6.73 bits. To enhance stability loop gains are reduced, and (1.17) becomes
SNR max
= 10 log
3
2
2
N
− 1
2
·
( 2 L + 1 ) OSR
2 L + 1
π 2 L
· G
1
· G
2
· · · G
L
, (1.18) where G
1
. . .
G
L are the loop gains.
The effect of noise shaping is demonstrated in Fig. 1.4, in which simulation results of an ideal 2-bit second order ∆Σ ADC are shown. The loop gains have been set to 2 and
0.5 to improve stability. With OSR = 16 the ADC yielded an SNR of 54.64 dB (resolution of 8.78 bits), in good agreement with (1.18).

1.1. Scientific Background
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
SNR (full) = 1.96244 dB
ENOB (full) = 0.0336279
SNR (
1
/
ENOB (
16
1
/
) = 54.6397 dB
16
) = 8.78401
0.1
0.2
0.3
0.4
0.5
0.6
normalized frequency
0.7
0.8
0.9
1
Figure 1.4: Sinusoidal signal sampled by a simulated ideal 2-bit second order
∆Σ ADC ( OSR = 16)
15
Stability and Higher Loop Orders
Till this point analysis of the ∆Σ ADC was based on its linear model. However, many nonlinear phenomena occur in every ∆Σ converter and must not be neglected [3,4]. Some of these phenomena may result in instability – a situation at which the output amplitude of one (or more) of the loop filters is increasing more and more. Apparently, instability is undesirable and must be avoided. Once the stability of a 1 st or 2 nd order ∆Σ ADC is ensured by the linear model, the converter is unconditionally stable for every input signal, in spite of the nonlinear behavior.
A ∆Σ ADC can be implemented with a loop order higher than 2, that is, with more than two nested feedback loops. Although the higher order enhances the resolution (see
(1.18)), it evokes further stability issues – both linear and nonlinear. In this case stability in the linear model is essential but insufficient; the stability of the converter in practice can be proven only if the input signal follows several conditions. A 3 rd or higher order
∆Σ ADC is therefore considered as conditionally stable .
Challenges
As evident in Fig. 1.3, the DAC’s output is directly introduced at the input of the ∆Σ
ADC. This means that every noise generated by the DAC is referred to the input as is, with no shaping. Consequently, the DAC is the most critical element of a ∆Σ ADC as it must exhibit high linearity – high enough to keep the ADC’s ENOB above the desired level. In the case of N = 1 the DAC is perfectly linear, since it has no intermediate

16 Chapter 1. Introduction levels. When N
>
1 DAC linearity can be significantly improved by dynamic shuffling
– a method that requires very large scale integration of digital circuits. This method is not feasible in most HBT technologies, in which transistor count of a single circuit is limited to several hundreds. For the above reason, all published ∆Σ ADCs based upon HBTs have a loop resolution of 1 bit. This results in large die area and high power consumption for a given resolution, as high order is implemented, and sub-circuits are duplicated for each loop. In this research a high linearity 2-bit DAC was demonstrated and incorporated into the ADC. This is described in Chapter 3.
Measurements at high sample rates set another challenge which was addressed in this work. A common method of measurement of ∆Σ ADCs is by feeding the bit stream coming from the output into a logic analyzer that logs the digital data in a file. Then data are processed off-line by a mathematical software [6]. This method is limited by the speed of the logic analyzer, usually several hundred MHz. In addition, the number of probes required for such a measurement equals, at least, to the number of bits of the
DACs. Acquisition speed can be slowed down by buffering the output in a shift register, but bit number is then multiplied accordingly [7] [8].
If the ADC loop resolution is 1 bit, the digital output can be treated as an analog signal and fed directly into a spectrum analyzer, to obtain SNR and linearity [9]. Since our loop resolution was 2 bits, a different method of measurement was required. This is accounted in Section 5.3.4.

1.2. State of the Art 17
Previous research on fast ∆Σ ADCs based upon InP and SiGe HBTs is summarized in Table 1.1. The SiGe technology facilitates using both HBTs and CMOS transistors, but suffers from low breakdown voltage, and poor output resistance. These limit the dynamic range of the analog input and consequently reduce SNR and resolution. InP-based HBTs offer higher breakdown voltage and output resistance, and are therefore excellent candidates for the design of high-speed ADCs, especially of the ∆Σ architecture.
In CMOS and other FET technologies switches are easy to design and are composed of very few transistors. Bipolar switches, on the other hand, consist on complex diodebridge structure and comprise many transistors. For this reason, architectures that employ many switches, such as pipeline, discrete-time ∆Σ ( DT ∆Σ ), or successive approximation, are difficult to realize in bipolar technologies. Architectures such as flash, folding, and continuous-time ∆Σ ( CT ∆Σ ) are more adequate. Consequently, research on fast
ADCs in HBT technologies is aimed at these architectures.
As evident in Table 1.1, the loop resolution of all the HBT-based ∆Σ ADCs is 1 bit.
This ensures high linearity of the DAC, but can achieve limited resolution. An ADC with the same loop order, sample rate, and signal bandwidth, but higher loop resolution can reach higher resolution.
A common figure of merit used for ADC characterization measures energy per conversion, that is, the energy required for distinguishing between two adjacent ∆ s, considering the signal bandwidth and the required sampling speed. Its value is given by
FoM =
P
2 · BW sig
· 2 ENOB
(1.19) where P is the total power consumption of the ADC, and BW sig is the signal bandwidth.
Although this figure of merit accounts for the resolution, signal bandwidth, and power consuption, it does not include any information on other important characteristics of the ADC, such as die area and the ability to adjust the center frequency of the signal
(“tunable channel”). Therefore, it does not provide full picture of the ADC, and should be used carefully.

18 Chapter 1. Introduction

1.3. Research Structure 19
The first stage focuses on the building blocks of the converter: a sensitivity-enhanced latched comparator, gain-enhanced amplifier, and high linearity DAC were investigated.
In the second stage of the research the building blocks were combined to demonstrate a
10 GS/s second order 2-bit low pass ∆Σ ADC. Architecture, performance, stability, and other design parameters were studied.
1.3.1
Building Blocks
Three building blocks were studied in the first stage. A method for improving the sensitivity (or speed) of a master-slave emitter-coupled logic ( ECL ) comparator using emitter degeneration resistors is presented in Chapter 2. A high linearity 2-bit digital-to-analog converter implemented in an InP/ GaInAs DHBT technology is the subject of Chapter 3.
Finally, two gain-enhanced fully-differential amplifiers are discussed in Chapter 4. The first amplifier was designed in a digital CMOS technology, while the second one, based upon the same active bootstrap technique, was designed in the InP HBT technology. The active bootstrap technique can enhance the gain to any desired level, but is very sensitive to process variations. A process variation self correction circuit was incorporated to each circuit, to obtain high gain at all process corners.
1.3.2
Complete ADC
Continuous time ∆Σ ( CT ∆Σ ) ADCs are capable of sampling at much higher rates than discrete time ∆Σ s. This makes HBT technologies excellent candidates for the implementation of fast CT ∆Σ ADCs. Due to linearity considerations, all HBT-based ∆Σ ADCs known to us incorporated a single-bit DAC. In the second stage of the research the building blocks were put together to form a multibit ∆Σ ADC based upon InP HBTs.
A 10 GS/s second order 2-bit low pass ∆Σ ADC was demonstrated. Architecture, performance, stability, and other design parameters were studied, and are the subject of
Chapter 5.

20 Chapter 1. Introduction
[1] Behzad Razavi, Principles of Data Conversion System Design , Wiley–IEEE Press, 1995.
[2] Hiroshi Inose and Yasuhiko Yasuda, “A unity bit coding method by negative feedback”, Proceedings of the IEEE , vol. 51, no. 11, pp. 1524–1535, November 1963.
[3] Steven R. Norsworthy, Richard Schreier, and Gabor C. Temes, Delta-Sigma Data
Converters: Theory, Design, and Simulation , Wiley–IEEE Press, 1997.
[4] Richard Schreier and Gabor C. Temes, Understanding Delta-Sigma Data Converters ,
Wiley–IEEE Press, 2005.
[5] Arnold R. Feldman, Bernhard E. Boser, and Paul R. Gray, “A 13-bit, 1.4-MS/s sigmadelta modulator for RF baseband channel applications”, IEEE Journal of Solid-State
Circuits , vol. 33, no. 10, pp. 1462–1469, October 1998.
[6] Michael Inerfield, William Skones, Steve Nelson, Daniel Ching, Peter Cheng, and
Colin Wong, “High dynamic range InP HBT delta-sigma analog-to-digital converters”, IEEE Journal of Solid-State Circuits , vol. 38, no. 9, pp. 1524–1532, September
2003.
[7] Sundararajan Krishnan, Dennis Scott, Zach Griffith, Miguel Urteaga, Yun Wei,
Navin Parthasarathy, and Mark Rodwell, “An 8-GHz continuous-time Σ – ∆ analog– digital converter in an InP-based HBT technology”, IEEE Transactions on Microwave
Theory and Techniques , vol. 51, no. 12, pp. 2555–2561, December 2003.
[8] Albert E. Cosand, Joseph F. Jensen, H. Chris Choe, and Charles H. Fields, “IFsampling fourth-order bandpass ∆Σ modulator for digital receiver applications”,
IEEE Journal of Solid-State Circuits , vol. 39, no. 10, pp. 1633–1639, October 2004.
[9] Sundararajan Krishnan, Dennis Scott, Miguel Ycteaga, Zachary Griffrth, Yun
Wei, Mattias Dahlstrom, Navin Parthasarathq, and Mark Rodwell, “An 8-GHz continuous-time Σ – ∆ analog-digital converter in an InP-based DHBT technology”,
2003 IEEE MTT-S International Microwave Symposium Digest , vol. 2, pp. 1063–1065,
June 2003.
[10] James A. Cherry, W. Martin Snelgrove, and Weinan Gao, “On the design of a fourthorder continuous-time LC delta–sigma modulator for UHF A/D conversion”, IEEE
Transactions on Circuits and Systems–II: Analog and Digital Signal Processing , vol. 47, no. 6, pp. 518–530, June 2000.
[11] Robert Sobot, Shawn Stapleton, and Marek Syrzycki, “Fractional sigma–delta modulator in SiGe”, Canadian Conference on Electrical and Computer Engineering , pp. 530–
533, April 2007.

References for Chapter 1 21
[12] Theodoros Chalvatzis, Eric Gagnon, Morris Repeta, and Sorin P. Voinigescu, “A low-noise 40-GS/s continuous-time bandpass ∆Σ ADC centered at 2 GHz for direct sampling receivers”, IEEE Journal of Solid-State Circuits , vol. 42, no. 5, pp. 1065–1075,
May 2007.
[13] Bharath Kumar Thandri and Jose Silva-Martinez, “A 63 dB SNR, 75-mW bandpass
RF Σ∆ ADC at 950 MHz using 3.8-GHz clock in 0.25µ m SiGe BiCMOS technology”,
IEEE Journal of Solid-State Circuits , vol. 42, no. 2, pp. 269–279, February 2007.
[14] Adam Hart and Sorin P. Voinigescu, “A 1GHz bandwidth low-pass ∆Σ ADC with
20GHz to 50GHz adjustable sampling rate”, 2008 IEEE Radio Frequency Integrated
Circuits Symposium , pp. 181–184, June 2008.
[15] Martin Schmidt, Markus Grzing, Stefan Heck, Ingo Dettmann, Manfred Berroth,
Dirk Wiegner, Wolfgang Templ, and Andreas Pascht, “A 1.55 GHz to 2.45 GHz center frequency continuous-time bandpass delta-sigma modulator for frequency agile transmitters”, 2009 IEEE Radio Frequency Integrated Circuits Symposium , pp.
153–156, June 2009.
[16] P. Ostrovskyy, H. Gustat, Ch. Scheytt, and Y. Manoli, “A 9 GS/s 2.1..2.2 GHz bandpass delta-sigma modulator for class-s power amplifier”, 2009 IEEE MTT-S International Microwave Symposium Digest , pp. 1129–1132, June 2009.

22 Chapter 1. Introduction

ENSITIVITY of the comparator is a critical parameter in the design of an analog-to-digital converter. A method for improving the sensitivity (or speed) of a master-slave emitter-coupled logic ( ECL ) comparator using emitter degeneration resistors is presented in this chapter. The degeneration resistors in the latching pair reduce the transistor charging time, thus allowing more time for regeneration. Improved and standard comparators were implemented using the
InP/GaInAs HBT technology and were tested at a clock rate of 20 GHz. The improved comparator exhibited better sensitivity (by a factor of 1.7) compared to the standard design. A record low sensitivity value of 10 mV was obtained.

24 Chapter 2. Comparator
High speed analog-to-digital converters sample high frequency signals in state-of-the-art communication systems and radars. Advanced CMOS-based ADCs exhibit very high sampling frequencies [1–5], but even higher sampling frequencies are achieved by circuits based upon heterojunction bipolar transistors [6–9]. Circuit complexity of HBTbased ADCs is limited by the maximum transistor count and the associated yield supported by the technology. Consequently, most ADCs using HBT technology are of the flash or delta-sigma ( ∆Σ ) architectures.
An important concern in ADC design is avoiding metastability at the output of the comparators [10]. The probability of metastability is determined by the sensitivity of the comparator, namely, the minimum voltage difference at the input at which the comparator can make a decision. A tradeoff between sensitivity and speed is common in most comparator architectures.
Comparators in flash ADCs – including those embedded in ∆Σ ADCs – usually consist of latched comparators, which make a decision every clock rise (or fall). A common architecture of latched comparators in bipolar technologies is master-slave emittercoupled logic ( ECL ) D-latches [11]. This chapter presents a method for improving the sensitivity (or speed) of a master-slave ECL comparator by streamlining the processes taking place during the latching phase in the first D-latch. The method consists of the introduction of emitter degeneration resistors in the latching pair. The degeneration resistors reduce the transistor charging time, providing more time for the critical process of regeneration.
The method was demonstrated using the indium phosphide based HBT technology, in a comparator which is a building block of a ∆Σ ADC. The main advantage of indium phosphide based HBTs compared to SiGe HBTs is their higher breakdown voltage. This enables the implementation of ADCs with high input amplitude [6, 12], which should potentially exhibit higher resolution than similar SiGe-based ADCs.
Our experimental results show an improvement of sensitivity by a factor of 1.7 when applying the proposed method. A record low sensitivity value of 10 mV was obtained by the sensitivity enhanced comparator.
2.2.1
Speed Limits of the ECL Comparator
In order to clarify the proposed improvement of the comparator circuit, we briefly first review some basic ECL comparator concepts. Master-slave latched comparators consist of two D-latch circuits that form a D flip-flop ( D-FF ) [11,13], as illustrated in Fig. 2.1. The implementation of a D-latch in differential ECL is shown in Fig. 2.2. The tracking pair
(Q
3
, Q
4
) is an open-loop amplifier that compares the inputs (D p
, D n
) during the tracking phase, i.e. when the clock (CK) is “low”. In the latching phase (when the clock is “high”),

2.2. Analysis of Comparator Performance
,1 ' 4
&.
4
Q
' 4
&.
4
Q
287
S
287
Q
&.
Figure 2.1: Logic diagram of a master-slave D-FF. Clock and input nodes are shown single-ended for simplicity
25
V
CC
R
L
C
L
Q n
D p Q
3
Q
5
R
L
Q
6
Q
4
Q p
C
L
D n
CK n Q
1
Q
2
CK p
I bias
Figure 2.2: Circuit diagram of a fully differential ECL D-latch the latching pair (Q
5
, Q
6
) emphasizes the previous value by means of positive feedback, and holds it until the clock goes “low” in the next cycle. Shown in Fig. 2.3 are the output waveforms of the latch. The output voltage swing, ∆ V , is generated by switching the current between the two load resistors ( R
L
), and hence equals to
∆ V = R
L
I bias
, (2.1) where I bias is the value of the switched current. The required value of ∆ V is determined according to the load of the D-latch: if the load is another ECL logic gate then ∆ V must be large enough to fully switch the current in the load gate, namely, [14]
∆ V
>
4
KT q
+ I bias r ee
, (2.2)

26
Q n
Charging Recovery
Chapter 2. Comparator
Charging Regeneration
δv
∆V
Q p
CK
Tracking Phase Latching Phase
Figure 2.3: Waveforms of D-latch’s outputs where K is Boltzmann’s constant, T is temperature, q is the electron’s electric charge, and r ee is the parasitic resistance of the emitter contact. In case that the load is a current steering digital-to-analog converter ( DAC ), on the other hand, the exact value of ∆ V is determined by the desired DAC resolution. In addition, the value of RL must be large enough so that the gain of the positive feedback loop is greater than unity, that is,
R
L
>
1 g m 5
+ r ee
=
2 KT qI bias
+ r ee
.
(2.3)
The waveform of the output in the tracking phase is determined by two delaying processes: (i) charging the transistors in the tracking pair, and (ii) recovering from a full scale output of ∆ V to the value determined by the input. According to the notations in
Fig. 3, the total delay during the tracking phase is t track
= t
∗ charge
+ t rec
, (2.4) where t
∗ charge is the time required to charge the transistors through their bases, and the recovery time, namely, [15] t rec is
 t rec
= τ
∗ load 
1 + tanh
1 qV in
2 KT


, (2.5) where V in is the differential input voltage. The load RC time constant, τ
∗ load
, is given by
τ
∗ load
≈ R
L
[ C
L
+ 5 C bc
] , (2.6)

2.2. Analysis of Comparator Performance 27 where C
L is the load capacitance, and C bc is the base-collector capacitance of the transistors. The capacitance in (2.6) consists of C bc
Q
5 and Q
6 of Q
3
, and the base-collector capacitances of
, which are connected in a differential manner between the output nodes.
The latching process, taking place during the latching phase, also involves two delays: (i) charging the latching transistors, and (ii) regeneration from an initial output of
δ v to full output scale of ∆ V . The total latching time is therefore t latch
= t charge
+ t reg
,
A = g m 5
R
L
(2.7) where t charge and t reg are the charging and regeneration times, respectively. Due to the crossed connection of the latching pair, charging is done directly by I bias emitters. Therefore, the charging time is given approximately by [16] through the t charge
≈
2 C be
( V be
) ∆ V be
I bias
, (2.8) where C be
( V be
) is the base-emitter capacitance, and ∆ V be is the change in the base-emitter voltage during the charging process. The initial base-emitter voltage is zero, and the final voltage is determined by the output difference, δ v . The regeneration time is the time required for the latching pair to fully switch from an initial voltage difference of δ v to ∆ V (full scale output), given by [17] t reg
=
τ load
A − 1 ln where A is the gain of the latching pair, namely,
∆ V
δ v
, (2.9)
(2.10)
(if r ee is neglected). Due to the Miller effect,
τ load
≈ R
L
[ C be
+ C bc
( A + 2 ) + C
L
] , (2.11) hence if A ≫ 2 the term τ load
/ A equals the inverse of the unity gain bandwidth of the latching pair. However, since the value of R
L is usually chosen to be low, in order to optimize t track
, the gain is relatively low. The effect of r ee
Section 2.3.
will be discussed hereinafter, in
If the input signal is too small, the latching pair will not provide a full voltage output of ∆ V within the clock cycle time. This phenomenon gives rise to the above mentioned metastability. Metastability may cause the following logic gates to malfunction, and must therefore be avoided. Assuming that the initial input voltage is uniformly distributed between − ∆ V and + ∆ V , the probability of metastability is [18]
P
MS
= exp −
A −
τ load
1 t alloc
, (2.12) where t alloc is the time allocated for the latching pair to switch. Let T be the clock period, then the allocated time is t alloc
=
T
2
− t charge
.
(2.13)

28 Chapter 2. Comparator
According to (2.9), the minimum voltage at the input of the latching pair that can be regenerated to ∆ V is v min
= exp
∆ V
A − 1
τ load t alloc
.
(2.14)
Assuming that the tracking phase is long enough to enable the tracking pair full recovery, the minimum voltage at the D-latch’s input that can result in full scale output is v min divided by the gain of the tracking pair. This minimum distinguishable voltage is referred to as the sensitivity of the comparator.
As evident in (2.14), the sensitivity improves exponentially with t alloc
. In most practical cases, the sampling frequency is given, and the comparator design has to meet a goal of sensitivity. Therefore, the sensitivity can be improved either by speeding up the comparator or by minimizing its minimum distinguishable voltage. Both methods are discussed below.
2.2.2
Speed Enhancement Techniques
An efficient method for improving the sensitivity of a comparator is introducing inductors in series with R
L
[19], also referred to as inductive peaking, as shown in Fig. 2.4. The
V
CC
L
L
R
L
L
L
R
L
C
L
Q n
D p Q
3
Q
5
Q
6
Q
4
Q p
C
L
D n
CK n Q
1
Q
2
CK p
I bias
Figure 2.4: Circuit diagram of a D-latch with peaking inductors

2.2. Analysis of Comparator Performance 29 effective load resistance becomes
R
L , e f f
= R
L
+
ω
2
L
2
L
R
L and the load RC time constant is now
τ load
= R
L , e f f
(
[ C be
+ C bc
( A + 1 ) + C
L
] −
R
2
L
L
L
+ ω 2 L
2
L
)
.
(2.15)
(2.16)
By inserting (2.15) and (2.16) into (2.10) and (2.9), respectively, it is revealed that the latching time is reduced. This improvement is achieved without increasing power consumption, but the inductors usually occupy a large area on the die. A detailed analysis of the above method can be found in [19].
Another method to speed up the latching process is adding resistors that enhance the gain of the latching pair, and keep the gain of the tracking pair unchanged [20].
According to (2.14), this method achieves a significant improvement only when the gain is not much larger than unity.
If the available headroom is sufficiently large, reduction of t reg via τ load can be achieved by buffering the outputs of the latching pair from its inputs using an emitter follower stage [12, 15, 17, 20]. This technique eliminates the Miller capacitance from (2.11), resulting in a shorter regeneration time. In addition, the emitter followers isolate the load capacitance, C
L
, from R
L
, which speeds up both the recovery and regeneration processes.
Reducing the transistor charging time, t charge
, so that more time is allocated for latching, is yet a different approach for speed enhancement. For example, a small DC current source can be added to the latching pair [12], as illustrated in Fig. 2.5. The additional tail current source maintains the latching pair partially charged during the tracking phase, and consequently less charge must be supplied during the charging process in the following latching phase. However, the asymmetric currents drawn by the latching pair during the tracking phase may bring about undesirable offset at the input voltage.
2.2.3
Sensitivity Enhancement Techniques
There are various methods to enhance the sensitivity of a latched comparator at a given clock rate. The most straightforward method is adding a preamplifier at the input [15,17].
The preamplifier also isolates the input signal from the clock switching pair, avoiding clock kickback – crosstalk noise at the input signal caused by the clock transients.
A different D-latch architecture that reduces the kickback effect has been proposed by Van de Plassche and Baltus [21]. The reduction in kickback improves the sensitivity, if the latter is limited by kickback. Introduction of a keep-alive tail current source improves sensitivity significantly [16]. This architecture requires wider headroom, though.

30 Chapter 2. Comparator
V
CC
R
L
R
L
Q n
D p Q
3
Q
5
Q
6
Q
4
Q p
D n
CK n Q
1
Q
2
CK p
I bias
I tail
Figure 2.5: Circuit diagram of a D-latch with keep-alive tail current. Load capacitances are omitted for clarity
2.3.1
Topology
A new circuit topology that improves the sensitivity of the D-latch is proposed in Fig. 2.6.
As illustrated in the figure, the latching pair is degenerated by the resistors R
E
, which reduce the voltage drop across the base-emitter junctions of Q
5 and Q
6
. As a result, the transistor charging time, t charge
, is reduced as well. We use below small signal analysis to demonstrate this point, assuming that following the charging process the output voltage,
δ v , is relatively small. One thus obtains that
∆ V be
≈
KT q

I bias ln

+ g m 5
δ
1 + g m 5 v
R
E
2 I s


, (2.17) where I s is the saturation current of the base-emitter diode. Inserting (2.17) into (2.8) the charging time is given by t charge
KT
≈ 2 qI bias
C be
( V be
) ln

I bias

+ g m 5
δ
1 + g m 5 v
R
E
2 I s


.
(2.18)

2.3. Improved Design 31
According to (2.14) the sensitivity increases exponentially as t alloc decreases, thus combining (2.14) with (2.18) we expect that the sensitivity should increase linearly with R
E
.
Circuit simulations presented below confirm this prediction.
Inspection of (2.14) reveals that R
E should not be increased beyond some upper limit due to the following consideration. Although the charging time is reduced by the degeneration resistor, the gain denoted as A in (2.14) as well as τ load gain is high, namely A ≫ 1, the term ( A − 1 ) / τ load are reduced by R
E
. If the remains approximately unchanged by the degeneration resistor, as it equals to the gain-bandwidth product of the latching pair. The reduction of t charge
, induced by the degeneration resistor (see (2.18)), prolongs the time allocated for switching, t alloc
, in (2.14), and therefore directly affects the exponent. If the gain is low, however, introduction of a degeneration resistance results in reduction of the term ( A − 1 ) / τ load in (2.14) and no sensitivity improvement (or possibly even sensitivity degradation) is obtained.
V
CC
L
L
R
L
L
L
R
L
Q n
D p Q
3
Q
5
R
E
Q
6
R
E
Q
4
Q p
D n
CK n Q
1
I
Q
2 bias
CK p
C par
Q
5
C be r ee
R
E
Figure 2.6: Circuit diagram of an improved D-latch, featuring load inductors and degeneration resistors in the latching pair.
In the inset: base-emitter junction of Q
5 with the corresponding elements in the transistor model and the external parasitic capacitance, C par

32 Chapter 2. Comparator
The effect of R
E on sensitivity is also determined by the ratio between t charge and t alloc
. In case t charge is very short compared to t alloc
, the effect of t charge exponent in (2.14) is negligible. In this case any reduction in the term ( shortening on the
A − 1 ) / τ load may dominate the value of the exponent. On the other hand, if t charge t alloc
, the shortening of t charge is long compared to by the degeneration resistance prolongs t alloc significantly, resulting in improvement in sensitivity. However, there is an intermediate range of t charge values in which low R
E values improve the sensitivity, but higher values shorten t charge to a level at which sensitivity is degraded.
Therefore, an improvement in the sensitivity is obtained only if the shortening of time allocated for charging dominates over the reduction in the term ( A − 1 ) / τ load
. This is satisfied either when the gain is high or when t charge is long.
Circuit simulations, shown below, demonstrate that R
E must exceed a minimal value to obtain sensitivity enhancement. This effect is explained considering the parasitic circuit elements at the base-emitter junction of Q
5
, shown in the inset in Fig. 2.6: the emitter series access resistance, r ee
, and the interconnect parasitic capacitance, C par
. As a result,
(2.17) is modified to read
∆ V be
≈
KT q

I bias ln

+ g m 5
1 + g m 5
( R
δ
E v
+ r ee
)
2 I s


(2.19) and (2.8) is modified to t charge
≈
2 C be
( V be
) ∆ V be
I bias
+
2 C par
∆ V par
I bias
, where ∆ V par is the change in the voltage across C par
, given according to (2.19) by
(2.20)
∆ V par
≈ ∆ V be
+
δ v
2
·
1
1
+ g
+ g m 5 r ee m 5
( R
E
+ r ee
)
.
(2.21)
The capacitance C par shunts both C be and r ee
, therefore a significant shortening of the charging time is obtained only if R
E
≫ r ee
, as implied by (2.21); low values of degeneration resistance, on the other hand, are likely to reduce the term ( A − 1 ) / τ load in (2.14) with no significant shortening of t charge
, and result in deterioration of the sensitivity.
2.3.2
Comparator Design and Simulations
A circuit diagram of the master-slave ECL comparator having emitter degeneration resistors in its master D-latch is shown in Fig. 2.7. No emitter degeneration resistors were added to the slave D-latch because the input signal of the slave latch is already amplified by the master latch. Level shifters at the output isolate the slave D-latch from the load.
No preamplifier is included in order to directly evaluate the sensitivity of the latch, but obviously the sensitivity can be further improved if a preamplifier is added. The comparator was designed for a clock frequency of 20 GHz. We have used transmission lines for clock distribution to adjust the phase of the clock in the master and slave latches in

2.3. Improved Design 33
!
"
#
$
!
$
#
"! %
&
$
#
"!%
&
Figure 2.7: Simplified circuit diagram of the master-slave ECL comparator.
All the emitters are 4x1 µ m
2 order to optimize the performance. Transmission lines were used for the implementation of the inductors due to their low inductance values. Note that if spiral inductors are used their parasitic resistance should be subtracted from the load resistors [19]. Simulated waveforms at a clock rate of 20 GHz with a load resistance of 30 Ω , peaking inductance of 240 pH, and degeneration resistance of 15 Ω , are shown in Fig. 2.8.
Clock
In
Out
Figure 2.8: Simulated waveforms of the comparator at 20 GS/s

34 Chapter 2. Comparator
The comparator described in this work is a building block of a ∆Σ ADC, driving a current steering DAC. Since the minimum voltage required to fully switch the DAC currents is 150 mV, the comparator was designed to provide output amplitude of 300 mV in order to maintain sufficient safety margins. Accordingly, we have defined the sensitivity here as the input voltage for which the output amplitude drops by a factor of two.
The usefulness of the proposed method for enhancing the sensitivity of the comparator was first illustrated by simulation. The values of the parasitic elements of the devices were as follows. The effective total base-emitter capacitance ( C be
+ C par
) was 120 fF, the effective base-collector capacitance was 20 fF, and the emitter contact resistance was
6 Ω . The effect of the degeneration resistance on the simulated sensitivity is illustrated in
Fig.2.9. As evident, the sensitivity is significantly enhanced by a factor of about 1.5 due to the degeneration resistance, R
E
. As explained above, the sensitivity improves only when R
E is larger than the parasitic emitter resistance r ee
.
13
12
11
10
9
8
7
0 3 6 9 12
Ω
15 18
Figure 2.9: Simulated sensitivity of the comparator at 20 GS/s versus degeneration resistance
The comparator was fabricated using the Fraunhofer Institute for Applied Solid State
Physics ( IAF ) InP/GaInAs DHBT technology [22]. A microphotograph of the circuit is shown in Fig. 2.10-a. The pads were designed for probes with 100 µ m pitch in the
P-G-S-G-S-G-P configuration. Total die area was 1x1 mm
2
. In order to evaluate the effect

2.4. Circuit Characterization 35 of the emitter degeneration resistors, an additional identical comparator circuit was designed with no degeneration resistors (Fig. 2.10-b). Both circuits were fabricated side by side on the same wafer.
(a) (b)
Figure 2.10: Microphotographs of the comparators: (a) improved design
(b) reference circuit
Sensitivity evaluation at a clock frequency of 20 GHz is beyond the reach of existing instruments intended for digital circuit measurements. Hence, standard digital circuit evaluation techniques cannot be used. We have thus used the characterization method proposed by us in [23]. A fully synchronized setup to evaluate our circuit performance is shown in Fig. 2.11-a. The clock signal was generated by a Wiltron 68177B synthesized sweep generator, and divided by a power splitter. One of the splitter’s outputs was used for clocking the comparator, and the other was applied to a Fraunhofer IAF ASD201M frequency divider. The differential output of the divider was used both for the input signal and for triggering an oscilloscope. In order to reduce the effect of clock kickback in the master latch, the single-ended clock was introduced at the positive clock input (CK p
), and a DC voltage at the negative input (CK n
). The input signal was applied to the negative input (IN n
) in a similar manner. The outputs were sampled by two Agilent 86118A modules and an 86100B oscilloscope mainframe. The supply voltage was 6 V, the input
DC voltage was 3.5 V, and the clock DC voltage was 2 V. The total power consumption was 420 mW, where the comparator itself consumed 336 mW, and the auxiliary biasing circuits 84 mW.
The circuit was tested by applying a 20 GHz clock signal and 10 GHz input signal.

36 Chapter 2. Comparator
When the clock edges were aligned with the signal crests, the output toggled its value every clock cycle, as shown in Fig. 2.12 (refer also to Fig. 2.8). Although this measurement setup provides very good synchronization between the various signals, control over the input amplitude is possible only by external fixed attenuators as the frequency divider
Signal Generator
Power Splitter
Trigger
Oscilloscope
Frequency
Divider
÷ 2
Phase
Shifter
Attenuator
D Q
CK Q
(a)
Sync
Bit Generator
Signal Generator
Adjustable
Phase
Attenuator
D Q
CK Q
(b)
Oscilloscope
Figure 2.11: Schematic diagrams of the measurement setups: (a) fully synchronized setup (b) sensitivity measurement setup
Figure 2.12: Measured waveform of the comparator differential output at
20 GS/s at an input amplitude of 100 mV. Measurement carried out using the fully synchronized setup shown in Fig. 2.11-a

2.5. Conclusion 37 provides fixed output amplitude. We have therefore used another setup to observe the improvement in sensitivity of the proposed design.
Shown in Fig. 2.11-b is a diagram of the sensitivity measurement setup. Here, the input signal was generated by an Anritsu MP1758A pulse pattern generator. The MP1758A offers a convenient way to adjust the signal’s phase, as well as a continuous control of the amplitude, although in a limited range. However, using various attenuators we could cover the entire range from 1 mV to 1 V. The outputs were sampled by two HP 54752A modules and an HP 83480A digital communications analyzer oscilloscope mainframe.
The oscilloscope was triggered by one of the bit generator’s outputs.
To measure the sensitivity of the comparator the input amplitude was gradually reduced from 500 mV until the comparator’s output voltage dropped by a factor of two.
The input DC offset was adjusted manually to about 2 mV to optimize the sensitivity.
However, the exact comparator input offset could not be obtained from this DC offset due to the unknown voltage drops across the cables and the probes.
The lowest input voltage at which the comparator with degeneration resistors toggled at half amplitude was 10 mV; at an input of 9 mV no toggling was observed, as shown in Fig. 2.13-a. The reference circuit, namely the comparator without degeneration resistors, toggled properly only down to an input voltage of 17 mV, and at 16 mV no toggling was observed (Fig. 2.13-b). The sensitivity improvement by the degeneration resistors is thus unambiguously demonstrated in Fig. 2.13. Considering the accuracy of the measurements, the results are in good agreement with Fig. 2.9
We finally note that the waveforms shown in Fig. 2.13 suffer from considerable noise.
Since the upper waveform of Fig. 2.13-a should be identical to that shown in Fig. 2.12, due to the similar inputs, we concluded that the noise originates from the oscilloscope triggering jitter of the non synchronized measurement setup shown in Fig. 2.11-b. We have therefore used the upper waveform of Fig. 2.13-a as a reference for the measurements at lower input amplitudes. For clarity, the data were smoothened using the averaging sliding window method, where the window width was 5 psec.
A method for improving the sensitivity of an ECL comparator was proposed in this chapter. The method consists of the introduction of emitter degeneration resistors in the latching pair. The proposed circuit was implemented using an InP HBT technology, and compared with a standard design. Experimental results indicated that the sensitivity was enhanced from about 17 mV to about 10 mV by the proposed technique.
The technique can be applied to other topologies, such as those described in Section
2.2, to further improve their sensitivity. As the latching pair is isolated from the input nodes, degeneration still improves sensitivity when a preamplifier is used – provided that the sensitivity is not limited by the input-referred noise of the preamplifier. One must keep in mind, however (as discussed in Section 2.3), that degeneration resistors

38 Chapter 2. Comparator
(a) (b)
Figure 2.13: Measured waveforms of the comparators differential output at 20 GS/s, obtained using the sensitivity measurement setup (Fig. 2.11-b):
(a) proposed design with degeneration resistors (b) reference design without degeneration resistors.
As explained in the text, the noise is due to jitter in the non synchronized measurement setup (compare to Fig. 2.12). Since the upper left waveform here was generated by the same input amplitude as Fig. 2.12, the former was used as a reference for the measurements at lower input amplitudes. Data are presented both before and after smoothening by a 5 psec-wide sliding window (solid lines). Sensitivity improvement by degeneration resistors is evident should be used to enhance the sensitivity only if the ratio between the charging and regeneration times is high enough, so that improvement in sensitivity is obtained. In comparators that do not incorporate peaking inductors the regeneration time usually dominates the latching phase, and therefore the benefit of the proposed method must be evaluated for the specific circuit being designed.
State of the art is summarized in Table 2.1. While the proposed comparator achieved its 10-mV sensitivity consuming 336 mW, the closest sensitivity of another comparator at 20 GS/s was 12 mV, consuming 405 mW [15]. A circuit that consumes 82 mW exhibits inferior sensitivity of 40.8 mV at the same sampling rate [20]. To our knowledge, the improved design presented in this work exhibits the best sensitivity to date, compared to other comparators operating at 20 GS/s.

References for Chapter 2
Reference
[15]
[16]
[19]
[20]
[24]
This
Work technology
SiGe HBT
SiGe HBT
CMOS 0.18
µ m
SiGe HBT
CMOS 65 nm
InP HBT
Power
Consumption
405 mW
80 mW
1.85 mW
82 mW
1.3 mW
336 mW
Sampling Sensitivity
Rate
20 GS/s
30 GS/s
16 GS/s
12 mV
30 mV
20 mV
3.2 GS/s
18 GS/s
20 GS/s
7 GS/s
20 GS/s
211 mV
8.9 mV
40.8 mV only BER curves
10 mV
17 mV
(improved design)
(reference circuit)
Table 2.1: Recently published fast comparators
39
[1] Gerhard Mitteregger, Christian Ebner, Stephan Mechnig, Thomas Blon, Christophe
Holuigue, and Ernesto Romani, “A 20-mW 640-MHz CMOS continuous-time Σ∆
ADC with 20-MHz signal bandwidth, 80-dB dynamic range and 12-bit ENOB”,
IEEE Journal of Solid-State Circuits , vol. 41, no. 12, pp. 2641–2649, December 2006.
[2] Sheng-Chuan Liang, Ding-Jyun Huang, Chen-Kang Ho, and Hao-Chiao Hong, “10
GSamples/s, 4-bit, 1.2V, design-for-testability ADC and DAC in 0.13
µ m CMOS technology”, Proceedings of ASSCC 2007 , pp. 416–419, November 2007.
[3] I-Hsin Wang and Shen-Luan Liu, “A 1V 5-bit 5GSample/sec CMOS ADC for UWB receivers”, Proceedings of VLSI-DAT 2007 , pp. 1–4, April 2007.
[4] Michael Choi, Jungeun Lee, Jungho Lee, and Hongrak Son, “A 6-bit 5-GSample/s
Nyquist A/D converter in 65nm CMOS”, Proceedings of VLSI Circuits 2008 , pp. 16–
17, June 2008.
[5] Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, and Geert van der
Plas, “A 2.2mW 5b 1.75GS/s folding flash ADC in 90nm digital CMOS”, Proceedings of ISSCC 2008 , pp. 252–253;611, February 2008.
[6] Sundararajan Krishnan, Dennis Scott, Zach Griffith, Miguel Urteaga, Yun Wei,
Navin Parthasarathy, and Mark Rodwell, “An 8-GHz continuous-time Σ ∆ analog– digital converter in an InP-based HBT technology”, IEEE Transactions on Microwave
Theory and Techniques , vol. 51, no. 12, pp. 2555–2561, December 2003.
[7] Theodoros Chalvatzis, Eric Gagnon, Morris Repeta, and Sorin P. Voinigescu, “A low-noise 40-GS/s continuous-time bandpass ∆Σ ADC centered at 2 GHz for direct

40 Chapter 2. Comparator sampling receivers”, IEEE Journal of Solid-State Circuits , vol. 42, no. 5, pp. 1065–1075,
May 2007.
[8] R.A. Kertis, J.S. Humble, M.A. Daun-Lindberg, R.A. Philpott, K.A. Fritz, D.J.
Schwab, J.F. Prairie, B.K. Gilbert, and E.S. Daniel, “A 35 GS/s 5-bit SiGe BiCMOS flash ADC with offset corrected exclusive-or comparator”, Proceedings of BCTM
2008 , pp. 252–255, October 2008.
[9] Shahriar Shahramian, Sorin P. Voinigescu, and Anthony Chan Carusone, “A 35-
GS/s, 4-bit flash ADC with active data and clock distribution trees”, IEEE Journal of
Solid-State Circuits , vol. 44, no. 6, pp. 1709–1720, June 2009.
[10] Rudy van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters , Kluwer, second edition, 2003.
[11] Rob E.J. van de Grift and Rudy J. van de Plassche, “A monolithic 8-bit video A/D converter”, IEEE Journal of Solid-State Circuits , vol. SC-19, no. 3, pp. 374–378, June
1984.
[12] Michael Inerfield, William Skones, Steve Nelson, Daniel Ching, Peter Cheng, and
Colin Wong, “High dynamic range InP HBT delta-sigma analog-to-digital converters”, IEEE Journal of Solid-State Circuits , vol. 38, no. 9, pp. 1524–1532, September
2003.
[13] Tsutomu Wakimoto, Yukio Akazawa, and Shinsuke Konaka, “Si bipolar 2-GHz 6bit flash A/D conversion LSI”, IEEE Journal of Solid-State Circuits , vol. 23, no. 6, pp.
1345–1350, December 1988.
[14] Jan M. Rabaey, Digital Integrated Circuits , Prentice Hall, 1996.
[15] Wei-Min Lance Kuo, Xiangtao Li, Ramkumar Krithivasan, Yuan Lu, John D.
Cressler, Yevgen Borokhovych, Hans Gustat, Bernd Tillack, and Bernd Heinemann,
“A 32 GSample/sec SiGe HBT comparator for ultra-high-speed analog-to-digital conversion”, Proceedings of APMC 2005 , December 2005.
[16] Jonathan C. Jensen and Lawrence E. Larson, “A 16-GHz ultra-high-speed Si-SiGe
HBT comparator”, IEEE Journal of Solid-State Circuits , vol. 38, no. 9, pp. 1584–1589,
September 2003.
[17] Behzad Razavi, Principles of Data Conversion System Design , Wiley–IEEE Press, 1995.
[18] Harry J.M. Veendrick, “The behavior of flip-flops used as synchronizers and prediction of their failure rate”, IEEE Journal of Solid-State Circuits , vol. SC-15, no. 2, pp.
169–176, April 1980.
[19] Sunghyun Park and Michael P. Flynn, “A regenerative comparator structure with integrated inductors”, IEEE Transactions on Circuits and Systems I: Regular Papers , vol. 53, no. 8, pp. 1704–1711, August 2006.

References for Chapter 2 41
[20] Xiangtao Li, Wei-Min Lance Kuo, Yuan Lu, Ramkumar Krithivasan, Tianbing Chen,
John D. Cressler, and Alvin J. Joseph, “A 7-bit, 18 GHz SiGe HBT comparator for medium resolution A/D conversion”, Proceedings of BCTM 2005 , pp. 144–147, October 2005.
[21] Rudy J. van de Plassche and Peter Baltus, “An 8-bit 100-MHz full-nyquist analog-todigital converter”, IEEE Journal of Solid-State Circuits , vol. 23, no. 6, pp. 1334–1344,
December 1988.
[22] R. Driad, R.E. Makon, V. Hurm, F. Benkhelifa, R. L ¨osch, J. Rosenzweig, and
M. Schlechtweg, “InP-based DHBT technology for high-speed mixed signal and digital applications”, Proceedings of IPRM 2009 , pp. 10–15, May 2009.
[23] S. Kraus, R.E. Makon, I. Kallfass, R. Driad, M. Moyal, and D. Ritter, “Sensitivity of a 20-GS/s InP DHBT latched comparator”, Proceedings of IPRM 2010 , pp. 115–118,
June 2010.
[24] Bernhard Goll and Horst Zimmermann, “A 65nm CMOS comparator with modified latch to achieve 7GHz/1.3mW at 1.2V and 700MHz/47uW at 0.6V”, Proceedings of
ISSCC 2009 , pp. 328–329a, February 2009.

42 Chapter 2. Comparator

HIGH linearity 2-bit digital-to-analog converter implemented in an InP/
GaInAs DHBT technology is presented in this chapter. The DAC is based upon the current steering architecture. Cascode structure and layout techniques, i.e. static shuffling and dummy devices, have been used to enhance the linearity. The DAC exhibits static integral/differential nonlinearities of 5.5
· 10
− 3
LSB, equivalent to a resolution of 9.2 bits. Dynamic measurements qualitatively show proper behavior at 6 GS/s, while simulations with typical on-chip load exhibit sufficiently fast settling at 20 GS/s.

44
Chapter 3. 2-Bit DAC
Analog-to-digital converters based upon HBT technologies have reached record breaking sampling rates [1–4]. However, the existing technologies set strict limitation on the maximum number of transistors that can be incorporated in a single circuit. As a result,
HBT-based ADCs usually rely upon the flash and delta-sigma architectures.
Digital-to-analog converters embedded in standard CMOS ∆Σ ADCs are typically of low resolution, namely 1 to 3 bits. Nevertheless, the linearity of the embedded DAC must be sufficiently high to support the final resolution of the ∆Σ ADC [5]. The resolution of
HBT-based low over-sampling ∆Σ ADCs may be as high as 8 bits [6, 7], and since digital methods of nonlinearity correction are too complex for HBT technologies, all HBT-based
∆Σ ADCs known to us incorporated a single-bit DAC, which is linear by definition [6,
8]. Here, we present a high linearity current steering two-bit DAC implemented in an
InP/GaInAs HBT technology. A two-bit DAC can significantly improve the resolution of a ∆Σ ADC, compared to a single-bit ∆Σ ADC of the same complexity and sampling rate.
9
&&
Nƻ
ƻ
I)
ƻ
4 4
ƻ
I) I)
$
S
$
Q
ƻ
ƻ
ƻ
I)
'
S 6:
'
Q
'
S 6:
'
Q
'
S 6:
'
Q
4
5 ƻ
4
5 ƻ
4
5 ƻ
Nƻ
5 5
Figure 3.1: Schematic circuit diagram of the DAC. Emitter dimensions:
2x1 µ m
2 in the switches and current sources; 4x1 µ m
2 elsewhere

3.2. DAC Design 45
The DAC is based on the standard differential current steering architecture [9] with a common-base output stage in the cascode configuration, as shown in Fig. 3.1. Each input bit (D
0
–D
2
) switches the current between the outputs of a differential pair (SW
0
–SW
2
).
The digital input is provided in the thermometer coding format; hence, the switched current sources (Q
0
–Q
2
) are identical. A common base output stage (Q
3
–Q
4
) is used to increase the output resistance. Additional resistors (R
5
–R
6
) maintain the common base stage in the active mode, in case all the bits are “1”s or “0”s. Finally, the resistors R
3
–R
4 and the capacitors C
L filter out the output overshoots caused by sharp input transients.
The layout of the circuit is shown in Fig. 3.2. The switches SW
0
–SW
2
, the transistor pair Q
3
–Q
4
, and the resistor pairs R
3
–R
4 and R
5
–R
6
, are all matched in common centroid structures. The resistors R
0
–R
2 and the current sources, Q
0
–Q
2
, are shuffled in a manner that each device consists of 3 parallel devices. To enhance device uniformity, two rows of dummy transistors provide uniform metal density around the current source transistors during the etching of the transistor layers. Fig. 3.3 illustrates this method.
The DAC was fabricated by the Fraunhofer Institute for Applied Solid State Physics
( IAF ) using their InP/GaInAs DHBT technology [10]. A microphotograph of the chip is shown in Fig. 3.4. Total die area is 1 × 0.75 mm 2 .
Figure 3.2: Layout of the DAC

46 Chapter 3. 2-Bit DAC
Figure 3.3: Close up of the layout of transistors Q
0
–Q
2 and resistors R
0
–R
2 showing the static shuffling. Each element consists of three devices connected
, in parallel. Encircled are the dummy transistors
Figure 3.4: Microphotograph of the circuit
The static (DC) transfer function of the DAC, shown in Fig. 3.5, exhibits a least-significant bit ( LSB ) voltage of 241.67 mV and offset of 7.5 mV. The integral and differential nonlinearities ( INL and DNL ) were smaller than 0.0055
· LSB , indicating a spurious free dy-

3.3. DAC Performance 47 namic range ( SFDR ) of 57.2 dB, i.e. 9.2 effective bits (see Fig. 3.6). The total power consumption was 90 mW, using a supply voltage of 6 V.
100
0
-100
-200
400
300
200
-300
-400
0
1
2
3
Figure 3.5: Measured DC transfer function of the DAC
6
4
2
0
-2
-4
-6
0
1
2 3
Figure 3.6: Measured integral and differential nonlinearities of the DAC. Obtained SFDR is 57.2 dB (9.2 effective bits) indicating that multibit ∆Σ ADCs are feasible in InP HBT

48 Chapter 3. 2-Bit DAC
For the dynamic test one bit was toggled at 6 Gb/s, and the differential output was sampled by an oscilloscope. The oscilloscope output is shown in Fig. 3.7. Since we have no data on cable attenuation and mismatch at the oscilloscope inputs, the waveforms provide only qualitative information on the behavior of the DAC at high frequencies.
The attempts to measure at a higher sample rate were unsuccessful most probably due to output mismatch. Circuit performance was simulated, however, while loaded by a differential integrator with 200 Ω resistors. The simulated response at 20 GS/s is shown in Fig. 3.8. The simulated output settles to a 0.0055
· LSB band in less than a half period.
Figure 3.7: Measured waveforms of the DAC output (one bit is toggling at 6
Gb/s): differential (top) and single ended (bottom)
An InP DHBT-based current steering 2-bit DAC with static linearity of 9.2 bits was presented. Since device mismatch is not modeled, simulated and measured nonlinearities cannot be compared. Simulated output settles to a 0.0055
· LSB band in less than 25 psec, but experimental performance was demonstrated only up to 6 GHz due to output mismatch. This circuit demonstrates that high speed multibit ∆Σ ADCs can be implemented using the InP HBT technology.

References for Chapter 3 49
Figure 3.8: Simulated waveform of the DAC output at 20 GS/s. The input sequence was 3-2-2-1-2-1-1-0-3
[1] Hideyuki Nosaka, Makoto Nakamura, Minom Ida, Kenji Kurishima, Tsugumichi
Shibata, Masami Tokumitsu, and Masahiro Muraguchi, “A 24-Gsps 3-bit Nyquist
ADC using InP HBTs for electronic dispersion compensation”, Proceedings of MTT-S
2004 , pp. 101–104, June 2004.
[2] Mehran Mokhtari, Joseph F. Jensen, Todd Kaplan, Charles Fields, Douglas
McLaughlin, and Willie Ng, “4-bit flash ADC in InP-HBT technology using distributed resistor ladder”, Proceedings of Radio & Wireless 2004 , pp. 143–146, September
2004.
[3] Zheng Guo, Matt D’Amore, and Augusto Gutierrez, “A 2-bit 20 Gsps InP HBT A/D converter for optical communications”, Proceedings of CSIC 2004 , pp. 93–96, October
2004.
[4] B. Chan, B. Oyama, C. Monier, and A. Gutierrez, “An ultra-wideband 7-bit 5 Gsps
ADC implemented in submicron InP HBT technology”, Proceedings of CSIC 2007 , pp. 1–3, October 2007.
[5] George I. Bourdopoulos, Aristodemos Pnevmatikakis, Vassilis Anastassopoulos, and Theodore L. Deliyannis, Delta-Sigma Modulators Modeling, Design and Applications , Imperial College, 2003.

50 Chapter 3. 2-Bit DAC
[6] Sundararajan Krishnan, Dennis Scott, Zach Griffith, Miguel Urteaga, Yun Wei,
Navin Parthasarathy, and Mark Rodwell, “An 8-GHz continuous-time Σ – ∆ analog– digital converter in an InP-based HBT technology”, IEEE Transactions on Microwave
Theory and Techniques , vol. 51, no. 12, pp. 2555–2561, December 2003.
[7] Albert E. Cosand, Joseph F. Jensen, H. Chris Choe, and Charles H. Fields, “IFsampling fourth-order bandpass ∆Σ modulator for digital receiver applications”,
IEEE Journal of Solid-State Circuits , vol. 39, no. 10, pp. 1633–1639, October 2004.
[8] Theodoros Chalvatzis, Eric Gagnon, Morris Repeta, and Sorin P. Voinigescu, “A low-noise 40-GS/s continuous-time bandpass ∆Σ ADC centered at 2 GHz for direct sampling receivers”, IEEE Journal of Solid-State Circuits , vol. 42, no. 5, pp. 1065–1075,
May 2007.
[9] T. W. Henry, “High speed analog-to-digital and digital-to-analog techniques”, IEEE
Transactions on Nuclear Science , vol. 20, no. 5, pp. 52–66, October 1973.
[10] R. Driad, R. E. Makon, V. Hurm, F. Benkhelifa, R. L ¨osch, J. Rosenzweig, and
M. Schlechtweg, “InP-based DHBT technology for high-speed mixed signal and digital applications”, Proceedings of IPRM 2009 , pp. 10–15, May 2009.

AIN of operational amplifiers is a key parameter for accurate settling, low gain error, and high linearity, of feedback amplifiers. Two gain-enhanced fully-differential amplifiers are presented in this chapter. The first amplifier was designed in a digital CMOS technology, while the second one, based upon the same active bootstrap technique, was designed in the InP HBT technology. The active bootstrap technique can enhance the gain to any desired level, but is very sensitive to process variations. A process variation self correction circuit was incorporated to each circuit, to obtain high gain at all process corners. Simulations of a two-stage amplifier in a standard 45 nm CMOS process demonstrated gain of 109 dB and unity-gain bandwidth of 500 MHz. The process variation compensation circuit maintained the gain in excess of 48 dB at all process corners. Circuit performance is compared to that of other gain-enhanced 1-V CMOS amplifiers. Simulations of the HBT-based amplifier exhibited gain of 82 dB and unity-gain bandwidth of 62 GHz. The gain remained above 64 dB under process variations.

52 Chapter 4. Operational Amplifier
Design of analog circuits using contemporary deep submicron, e.g. 45 nm, digital CMOS processes is plagued by low transconductance ( g m
) and drain-source resistance ( r ds
), low supply voltages, and relatively high transistor threshold voltages. In particular, the low g m and r ds values reduce the intrinsic low frequency ( LF ) gain of a single stage amplifier. Due to the central role of high gain op amps in many applications, several gain enhancement techniques were suggested and adapted to modern processes [1–4]. However, the above mentioned low supply voltage and high threshold voltages complicate circuit design and considerably limit the choice of useful known topologies.
HBT-based technologies also necessitate gain enhancement since they are not complementary: only NPN transistors are available. As a result, active loads cannot be implemented, and the gain remains low in spite of the high g m and collector-emitter resistance ( r ce
) values.
An effective gain enhancement method, which is also used in this work, is the employment of partial positive feedback to enhance the effective transconductance or the load resistance of the stage [5]. This method can be implemented both in differential [1, 2, 5–7] and single ended [3, 8–11] configurations. The differential topology enhances the differential mode LF gain but not the common mode gain, and therefore exhibits a very high common mode rejection ratio ( CMRR ). As power supply noise is transferred to the differential stage as a common signal, the power supply rejection ratio
( PSRR ) is also very high. By contrast, single-ended gain enhancement circuits enhance the common mode gain as well.
This chapter presents a new topology of a fully-differential active bootstrapped gain enhanced amplifier. The topology is demonstrated both on a digital CMOS and InP HBT technologies. As in all amplifiers based upon partial positive feedback, the gain is very sensitive to process variations. Methods to compensate process variations are presented for both circuits in order to maintain high gain at all process corners.
In spite of the complex topology, the CMOS-based circuit is biased by a 1 V supply.
No bulk driving or subthreshold operation methods, which are known to increase noise, were used. The circuit is based upon a series-shunt positive feedback approach, and differential active bootstrap. All transistors operate in strong inversion mode. A high current common source output stage provides high slew rate and wide output swing.
The HBT-based circuit is biased by a 6 V supply. Also here, the gain boosting consists of series-shunt partial positive feedback and differential active bootstrap. The second stage is a standard differential pair, to which the common mode feedback ( CMFB ) is applied. A high current common collector output stage enables to load the amplifier by low resistance, e.g. 50 Ω .

4.2. Gain Enhancement 53
The partial positive feedback gain enhancement method multiplies either g m or the load resistance ( R
L
) by
1
1 − η
, (4.1) where η is the gain of the positive feedback loop [5]. Obviously, to achieve gain enhancement η should approach unity from below. In some cases, however, η may also approach unity from above [12], as outlined below.
Fig. 4.1-a depicts a g m
-enhanced amplifier [5]. In this type of amplifiers the positive feedback network is implemented in a series-series differential connection [1, 5–7]. This
R
L out n in p
M
1
M
3
R
L out p
M
2 in n
M
4 out n
M
5
M
3
M
4
M
6 out p in p
M
1
M
2 in n
(a) (b)
M
5
M
4
R
2
R
4 out in
M
1
M
3
M
2 out
R
5
V
1 in
V
3
(c) (d)
Figure 4.1: Examples of partial positive feedback gain-enhanced amplifiers:
(a) g m
-enhanced [5] (b) differential R
L
-enhanced [5] (c) single-ended R
L
enhanced [3] (d) Murray’s “current starved” amplifier [11]

54 Chapter 4. Operational Amplifier topology is tolerant to process variations as η depends only on the parameters of NMOS transistors (or only PMOS transistors), but it reduces the input swing because the feedback transistors, M
3 and M
4
, consume additional ( V
T
+ V dsat
) of the supply voltage. We have therefore opted for the R
L
Two R
L enhancement topology in this work.
enhancement topologies are shown in Fig. 4.1-b and Fig. 4.1-c [3, 5], in differential and single-ended implementations. Some R
L enhancement topologies make use of a shunt-shunt feedback connection (as in Fig. 4.1-b for example) [5, 10], whereas other employ series-shunt feedback (e.g. Fig. 4.1-c) [2–4, 7–9]. The series-shunt techniques are also referred to as active bootstrapped or current starved amplifiers. Gain enhancement by active bootstrapping was first introduced by Murray in 1960 [11], as depicted in Fig.
4.1-d. Most of the active bootstrapped circuits suffer from output swing limitations due to a level shift of at least V
T introduced somewhere in the feedback network. In the circuits presented here, however, no such level shift takes place.
The circuits described in this work are based upon the series-shunt (bootstrap) R
L enhancement method, following the concept described by Murray [11] (Fig. 4.1-d), with a unity gain degenerated differential pair replacing the single-ended follower (V
3
). A circuit diagram of the proposed topology (in a CMOS technology) is illustrated in Fig. 4.2.
The differential pair M
3
-M
4
, together with M
7 and M
8
, comprises the positive feedback network that bootstraps the load resistances, implemented by R
5
η and R
6
. To achieve
−→ 1 for maximum gain enhancement the degenerated pair should satisfy
1 + g m 3
R
S
2 g m 3
= r ds 7 k g m 3 r ds 3
R
S
2
+ r ds 3
+
R
S
2
≈ r ds 7
.
(4.2)
M
7
M
8
R out n
5 in p
M
1
M
3
R
S
M
4
R
6 out p
M
2 in n
Figure 4.2: Schematic diagram of the proposed gain-enhanced CMOS amplifier

4.3. CMOS Op Amp 55
The left hand term in (4.2) can be tuned by changing the DC current flowing through M
3 and M
4
. Acting as local feedback, the degeneration resistance reduces the capacitance seen from the gate of M
3
.
Finally, we would like to point out that the series-shunt (bootstrap) R
L enhancement method is more suitable for low noise design than the shunt-shunt method. The output noise current spectral density of the shunt-shunt feedback circuits is [5] i
2 n
= 2 h i
2 n 1
+ Ki
2 n 3
+ ( 1 − η ) 2 i
2 n 5 i
, (4.3) where i n 1
, i n 3
, and i n 5 are the noise currents of M
1
, M
3
, and M
5
(in Fig. 4.1-b), respectively, and K is a constant determined by the circuit topology and implementation. Hence, the noise generated by the load element ( i n 5
) is significantly reduced by the positive feedback, but the noise generated by the positive feedback element ( i n 3
) remains unchanged.
In the series-shunt case, on the other hand, it can be shown that i
2 n
= 2 h i
2 n 1
+ ( 1 − η ) 2 i
2 n 3
+ Ki
2 n 5 i
, (4.4) where i n 5 is the noise current generated by the bootstrapped element. Since the value of the bootstrapped impedance can be varied considerably without affecting circuit performance, its value can be optimized to obtain minimum noise. Hence, the series-shunt feedback approach potentially offers better noise performance than the shunt-shunt feedback approach.
4.3.1
Architecture
The proposed amplifier was designed in a standard 45 nm digital CMOS process. The supply voltage was 1 V, and V
T of the transistors was about 450 mV, depending on transistor dimensions and biasing current. The common voltage of the input and the output was 600 mV. In order to achieve better control over g m of M
3 and M
4 via their drain current, I
D
, long channel transistors were used. The need for this controllability will be explained in the next section. A high current common source output stage was used to provide large output headroom and high slew rate. Miller capacitors, 800 fF each, with series resistors of 2 k Ω were connected to the output stage for compensation. The common mode feedback was applied to the current source of M
1 and M
2
. A schematic diagram of the circuit is shown in Fig. 4.3.
4.3.2
Process Variation Compensation
In most CMOS R
L
-enhanced amplifiers the loop gain, η , critically depends on the ratio between the parameters of the NMOS and PMOS transistors. Consequently, the LF gain is highly sensitive to process variations, rendering these circuits impractical when

56 Chapter 4. Operational Amplifier out p
M
C
C
M
M
R
M
R
5
7
M
A
M
3 in p
M
1
R
S
M
4
M
8
R
6
M
2 in n
M
D
C
M out n
R
M
M
B out p out n
V com
V cmfb
M
9
Figure 4.3: Schematic diagram of the proposed CMOS amplifier with an output stage and common mode feedback high yield is required. The circuit described here is also very sensitive to the value of the polysilicon resistance, as implied by (4.2). Since contemporary 45 nm digital CMOS processes suffer from a very wide parameter tolerance, a method for process variation compensation is essential in practical designs.
The biasing circuit depicted in Fig. 4.4 reduces the impact of process variations. The biasing circuit controls the value of g m 3 so that equality in (4.2) is maintained and consequently the value of η remains close to unity. The circuit operates as follows. A reference current is applied to a PMOS transistor (M
12
), and then duplicated by M
13 to create the biasing of the NMOS current sources. Due to the diode connection of M
14
, any change in the ratio between r ds of the PMOS transistors and g m of the NMOS transistors will result in a corresponding change in the NMOS current sources, which in turn adjusts the value of g m 3 and g m 4
. Variations in the polysilicon resistance are corrected by the same circuit, via proportional variations in R
14
, in a similar manner.
Finally, it is important to note that if the amplifier is embedded in negative feedback connection the circuit remains stable when η exceeds unity [12]. This enables the designer to set the typical value of η very close to unity, so that high gain is retained at all process corners with no stability risk.

4.3. CMOS Op Amp
Process Variation
Compensation
Biasing Circuit
M
12 M
13
I ref
R
14
M
14
M
7
M
8
R
5
R
6
M
3
M
4 in p
M
1
M
10
R
S
M
11
M
2 in n
57
Figure 4.4: The proposed CMOS amplifier with biasing circuitry for compensating the effect of process variations
4.3.3
Simulation Results
The simulated performance of the amplifier is compared to that of previously described
1-V gain-enhanced CMOS amplifiers in Table 4.1. The open loop gain of the amplifier was 109 dB, the unity-gain bandwidth ( UGB ) 500 MHz, and the phase margin 60
◦
, as shown in Fig. 4.5-a. At the 3 σ
√
The input-referred noise was 7.6 nV/ Hz at 10 MHz, and 65 nV/
√
Hz at 10 kHz, as shown in Fig. 4.5-b. The LF CMRR was 184 dB, and the LF PSRR was 186 dB. Obviously,
Ref.
CMOS
Process
[1]
[2]
[3]
[10]
This
Work
0.35
µ m
0.35
µ m
0.35
µ m
0.65
µ m
45 nm
Supply
Voltage
[V]
1
1
0.8
0.7
1
Load
Capacitance
[pF]
5
2
4
15
2
LF
Gain
[dB]
77.5
41.7
100
56.2
109
UGB
[MHz]
50
10
7.3
8
500
Phase margin
45
58
44
◦
◦
◦
N/A
60 ◦
LF
CMRR /
PSRR
[dB]
N/A
N/A
60 / 55
N/A
184 / 186
Input-
Referred nV/
√
Hz
N/A
35
N/A
N/A
7.6
Slew
Rate
Rise/Fall
[V/ µ s]
100 / 100
8.9 / 8.3
3 / 3
N/A
260 / 260
Power
[ µ W]
170
N/A
123
N/A
1400
Table 4.1: Comparison of CMOS 1-V gain-enhanced amplifiers

58 Chapter 4. Operational Amplifier the extremely high CMRR and PSRR values are theoretical only, and in practice they are limited by mismatch between the various elements of the amplifier. To determine the slew rate the amplifier was simulated in negative unity-gain feedback configuration, with 10 k Ω external resistors. The slew rate of the differential output was 260 V/ µ s. In
(a)
(b)
Figure 4.5: Simulated open loop (a) gain, phase, and (b) input-referred noise of the CMOS amplifier

4.4. HBT Op Amp 59 all of the simulations, the amplifier was loaded by 2 pF. Including the process variation compensation circuit but excluding the common mode feedback amplifier, the total gate area was 188 µ m 2 , the total capacitance was 1.6 pF, and the total resistance was 18.3 k Ω .
Total power consumption was 1.4 mW.
4.4.1
Architecture
The proposed topology can also be implemented in HBT technologies, as shown in
Fig. 4.6. Here, the differential pair Q
3
-Q
4
, together with R
7 and R
8
, comprises the positive feedback network that bootstraps the load resistances, implemented by R
5 and R
6
.
To achieve η −→ 1 for maximum gain enhancement the degenerated pair should satisfy
1 + g m 3
R
E g m 3
= R
7 k ( g m 3 r ce 3
R
E
+ r ce 3
+ R
E
) ≈ R
7
(4.5)
(compare to (4.2)). The left hand term in (4.5) can be tuned by changing the DC current flowing through Q
3 and Q
4
. Acting as local feedback, the degeneration resistance reduces the admittance seen from the base of Q
3
.
R
7
R
8 out n
R
5
Q
3
R
E
R
E
R
6
Q
4 out p in p
Q
1
Q
2 in n
Figure 4.6: Schematic diagram of the proposed gain-enhanced bipolar amplifier

60 Chapter 4. Operational Amplifier
4.4.2
Process Variation Compensation
In order to elucidate the effect of process variations on η , we first note that (4.5) can be rewritten as
1
R
E
+ g m 3
≈ R
7
.
(4.6)
The value of g m 3 is determined by the DC current flowing in Q
3
, which is usually set by resistors and current mirrors. Since (4.6) requires a certain ratio between g m 3 and other resistors in the circuit, any change in resistor values due to process variation will be reflected in g m 3 as well. Consequently, the circuit will still satisfy (4.6). However, parasitic resistances of the transistors were not taken into account so far. Considering the parasitic resistances, (4.6) becomes
R
E
+ r ee 3
+
1 g m 3
≈ R
7
, (4.7) where r ee 3 is the contact resistance of the emitter of Q
3
. It is evident that any change in r ee 3 may affect the gain enhancement significantly. In practice, most InP HBT processes suffer from wide variations in transistor parameters (the emitter contact resistance not being an exception), which can make the proposed gain enhancement topology useless.
The circuit depicted in Fig. 4.7 reduces the impact of process variations. The diodes
D
7 and D
8 consist of transistors in diode connection. The transistors should be identical to Q
3 and Q
4
. The diodes actually introduce approximately the same parasitic resistances to the right hand term in (4.7), which now becomes
R
E
+ r ee 3
+
1 g m 3
≈ R
7
+ r
D 7
+ r ee 7
+ r b 7
β + 1
, (4.8) where r
D 7 r b 7
= α / g m 7 is the small signal resistance of the forward biased D
7
, and r are the emitter and base contact resistances of the transistor that forms D
7 ee 7 and
, respectively. The terms r ee 3 and r ee 7 are equal and therefore can be eliminated from (4.8). The ratio between g m 3 and g m 7 is known as the DC currents flowing in the corresponding transistors are well controlled. Finally, the effect of variations in r b 7 is negligible due to the division by ( β + 1 ) .
It should be noted that the additional diodes consume V
BE from the total headroom at the output of the gain-enhanced stage. However, the existence of a second amplification stage ensures that the signal remains small between the stages.
4.4.3
Implementation
The proposed amplifier was designed in the InP HBT technology of the Technion. The supply voltage was 6 V, and the transistors’ forward current gain, β , was 50. The common voltage of the input and the output was 2.5 V. Additional amplification stage isolates the load from the gain enhanced stage. Miller capacitors, 200 fF each, were connected to the second stage for compensation. The common mode feedback was applied

4.4. HBT Op Amp 61
D
7
R
7
D
8
R
8 out n
R
5
Q
3
R
E
R
E
R
6
Q
4 out p in p
Q
1
Q
2 in n
Figure 4.7: The proposed bipolar amplifier with additional diodes for compensating the effect of process variations to the current source of the second stage. A high current common collector output stage was used to provide high slew rate, even when a load of 50 Ω is connected to the output.
A schematic diagram of the circuit is shown in Fig. 4.8.
4.4.4
Simulation Results
The simulated performance of the amplifier are as follows. The open loop gain of the amplifier was 82.3 dB, the UGB 62 GHz, and the phase margin − 45
◦ when loaded by
200 fF capacitance (Fig. 4.9-a). The negative phase margin is a result of the positive feedback loop gain, which exceeds unity at some point and inverts the polarity of the gain. As mentioned before, when the amplifier is embedded in a negative feedback system, the stability is not harmed by this phenomenon. However, stability must be evaluated with the actual negative feedback network taken into account. The LF CMRR was 146 dB, and the LF PSRR was 111 dB. As explained regarding the CMOS amplifier, mismatch. The input-referred noise was 0.8 nV/
√
Hz, as illustrated in Fig. 4.9-b. Since the model of the transistor did not include information on flicker noise, the latter does not appear in the graph. The total power consumption was 344 mW.
Process corners included changes of 10% in resistor and capacitor values, 40% in

62 Chapter 4. Operational Amplifier
ƻ
' '
ƻ ƻ
ƻ
ƻ ƻ
4
ƻ
4 I)
RXW
S
RXW
Q
LQ
S
4 4
LQ
Q
P$ P$
RXW
S
RXW
Q
Nƻ
9
FRP
9
FPIE
P$
ƻ
P$
P$ P$
Figure 4.8: Schematic diagram of the proposed HBT-based amplifier with a second amplification stage, output stage, and common mode feedback. All the emitters are 10x0.7
µ m
2 transistors’ β , and 20% in transistors’ contact resistances. The gain remained higher than
64 dB at all corners.
4.4.5
Fabrication
In order to demonstrate the proposed op amp it was embedded in a closed loop amplifier, shown in Fig. 4.10. The circuit has single-ended input and output, both are matched to
50 Ω . The voltage gain of the op amp with its feedback network is 4 (12 dB). however, since the amplifier supports a multidecade band, from DC to 2 GHz, resistive matching is used at the output, at the expense of 6 dB in the gain.
Layout of the circuit was designed using the Agilent ADS software, including the built-in design rule check ( DRC ) and layout versus schematic ( LVS ) tool. The layout is illustrated in Fig. 4.11-a. Total die area is 750x900 µ m
2
. The circuit was fabricated in the Technion InP/GaInAs HBT technology (Refer to Appendix A for more details on the

4.4. HBT Op Amp
100
80
60
40
-20
-40
20
0
-60
-80
-100
10
4 gain phase
10
6 8
10 frequency (Hz)
(a)
10
-7
10
10
180
90
0
-90
-180
10
-8
10
-9
10
-10
10
4
10
6
10
8 frequency (Hz)
(b)
10
10
10
12
Figure 4.9: Simulated open loop (a) gain, phase, and (b) input-referred noise of the HBT-based amplifier. Flicker noise is not modeled hence its effect is not evident
63 technology). A microphotograph of the circuit is shown in Fig. 4.11-b. Unfortunately, the fabricated circuits were nonfunctional due to failure in the processing of the interconnect elements. Consequently, measured results are not available at the time of writing this work. New wafers are now being processed and will be reported at a later stage.

64 Chapter 4. Operational Amplifier
30 fF
800 Ω 200 Ω in
RF
67 Ω in
DC
160 Ω
50 Ω
50 Ω out idle
Figure 4.10: Schematic diagram of the closed loop circuit used for op amp characterization
(a) (b)
Figure 4.11: (a) Layout and (b) microphotograph of the closed loop amplifier
A new topology of a fully-differential active-bootstrapped amplifier for both deep submicron CMOS processes and InP HBT technologies was introduced. Gain enhancement was achieved by means of a partial positive voltage feedback, and consequently the amplifiers exhibited good noise performance. The impact of process variations on gain enhancement was studied; a circuit that compensates this effect in the CMOS amplifier was presented, as well as an additional element that was introduced to the HBT amplifier for the same purpose.

References for Chapter 4 65
[1] A. Thanachayanont and W. Chaloenlarp, “Low-voltage, rail-to-rail, Gm-enhanced pseudo-differential class-AB OTA”, Proceedings of MWSCAS 2004 , vol. 1, pp. I–53–
I–56, July 2004.
[2] Juan M. Carrillo, Guido Torelli, Raquel P´erez-Aloe, and J. Francisco Duque-Carrillo,
“1-V rail-to-rail bulk-driven CMOS OTA with enhanced gain and gain-bandwidth product”, Proceedings of 2005 European Conference on Circuit Theory and Design , vol.
1, pp. I/261–I/264, August-September 2005.
[3] Kent D. Layton, Donald T. Corner, and David J. Corner, “Bulk-driven gainenhanced fully-differential amplifier for V
T
+ 2 V dsat
CAS 2008 , pp. 77–80, May 2008.
operation”, Proceedings of IS-
[4] Mark Pude, P.R. Mukund, Prashant Singh, and Jeff Burleson, “Using positive feedback to overcome g m r o limitations in scaled CMOS amplifier design”, Proceedings of
MWSCAS 2008 , pp. 807–810, August 2008.
[5] Rongtai Wang and Ramesh Harjani, “Partial positive feedback for gain enhancement of low-power CMOS OTAs”, Analog Integrated Circuits and Signal Processing,
Kluwer , vol. 8, no. 1, pp. 21–35, 1995.
[6] Hui Pan, Masahiro Segami, Michael Choi, Jing Cao, and Asad A. Abidi, “A 3.3-V
12-b 50-MS/s A/D converter in 0.6µ m CMOS with over 80-dB SFDR”, IEEE Journal of Solid-State Circuits , vol. 35, no. 12, pp. 1769–1780, December 2000.
[7] Jan Paul Anthonie van der Wagt and Mesfin Teshome, “An 8-GHz bandwidth 1-
GS/s GaAs HBT dual track-and-hold”, Proceedings of 2001 Symposium on VLSI Circuits , pp. 215–216, June 2001.
[8] Asad A. Abidi, “An analysis of bootstrapped gain enhancement techniques”, IEEE
Journal of Solid-State Circuits , vol. SC-22, no. 6, pp. 1200–1204, December 1987.
[9] Evert Seevinck, Monuko du Plessis, Trudi-Heleen Joubert, and Arnold E. Theron,
“Active-bootstrapped gain-enhancement technique for low-voltage circuits”, IEEE
Transactions on Circuits and Systems II: Analog and Digital Signal Processing , vol. 45, no. 9, pp. 1250–1254, September 1998.
[10] Francesco Centurelli, Pietro Monsurr `o, Giuseppe Scotti, and Alessandro Trifiletti,
“A gain-enhancing technique for very low-voltage amplifiers”, Proceedings of ISCAS
2008 , pp. 2282–2285, May 2008.
[11] C.T. Murray, “A low distortion single-ended push-pull audio amplifier”, Proceedings of the I.R.E. Australia , pp. 134–137, March 1960.

66 Chapter 4. Operational Amplifier
[12] M.E. Schlarmann, S.Q. Malik, and R.L. Geiger, “Positive feedback gainenhancement techniques for amplifier design”, Proceedings of ISCAS 2002 , vol. 2, pp. II–37–II–40, May 2002.

ONTINUOUS time ∆Σ ( CT ∆Σ ) ADCs are capable of sampling at much higher rates than discrete time ∆Σ s. This makes HBT technologies excellent candidates for the implementation of fast CT ∆Σ ADCs. Due to linearity considerations, all HBT-based ∆Σ ADCs known to us incorporated a single-bit DAC. This chapter presents a multibit lowpass ∆Σ ADC based upon the
InP HBT technology, which incorporates an internal resolution of 2 bits. The ADC was clocked at 10 GHz, its total power consumption was 1.9 W, and it obtained an ENOB of
7 at signal bandwidth of 312.5 MHz.

68 Chapter 5.
∆Σ ADC
High speed continuous time delta-sigma analog-to-digital converters ( ∆Σ ADC s) have become widespread in state-of-the-art communications systems and radars. The simplicity of the ∆Σ converter enables to design and fabricate it in fast technologies, e.g. SiGe and III-V heterojunction bipolar transistors ( HBT s), despite the limit on transistor count usually set by those technologies due to yield requirements. In addition, the ability to implement bandpass samplers, which may be capable of adjusting the center frequency of the band, makes them attractive for narrow band communications applications. Compared to its discrete time counterpart, the continuous time ∆Σ ADC does not require introduction of an anti aliasing filter since the loop filters do the filtering. The absence of switched operation and the resulting requirements on settling time, enables the continuous sampler to operate at frequencies that are much closer to the transistors cutoff frequency, f
T
, than in the discrete case. However, continuous time ∆Σ converters suffer from clock jitter twice: besides the noise generated by jitter in every sampler, jitter at the internal digital-to-analog converter ( DAC ) introduces its own noise.
Contemporary HBTs sport cutoff frequencies in excess of 500 GHz [1], while commercial and semi-commercial processes reach 300 GHz [2]. As a result, very fast HBT-based
∆Σ ADCs have been demonstrated, sampling at several GS/s. Due to transistor count limitations, all of them are of the continuous time type. The converters include both lowpass [3,4] and bandpass [5–7] that consist of the basic 2 nd and 4 th order structures, respectively. A high complexity 10 th order bandpass ADC also has been reported [8], as well as tunable bandpass converters that can shift the center frequency of the band [9–11]. Of the above, two ADCs sample at 10 GS/s or faster [4, 6].
Since the internal DAC introduces its output directly to the input of the ∆Σ ADC, its noise and nonlinearity are not formed by noise shaping. The linearity of the DAC must therefore be sufficiently high to support the final resolution of the ∆Σ ADC [12–
14]. As digital methods of nonlinearity correction are too complex for HBT technologies, all HBT-based ∆Σ ADCs known to us, including the above mentioned, incorporated a single-bit DAC, which is linear by definition [3, 6]. Here, we present a multibit ∆Σ ADC based upon the InP HBT technology, which incorporates an internal resolution of 2 bits.
5.2.1
Architecture
The ADC consists of a second order ∆Σ modulator, shown in Fig. 5.1. As mentioned in
Section 1.1.2, the 2 nd order modulator is unconditionally stable, that is, once its stability is confirmed by a linear model the modulator is stable for every input signal, in spite of the nonlinear behavior [13, 14].
The proposed converter consists of a multibit modulator, in which the internal resolution is higher than 1 bit. To point out the benefit of a multibit ∆Σ ADC, (1.18) is rewritten

5.2. System Design 69
Analog In
Noise
Shaping
Noise
Shaping
2-bit
ADC
2-bit
DAC
Delay
Z
–1
Analog Region Digital Region
Figure 5.1: Block diagram of a second order ∆Σ ADC
Decimation
Filter
Digital Out here for convenience:
SNR max
= 10 log
3
2
2
N
− 1
2
·
( 2 L + 1 ) OSR 2 L + 1
π 2 L
· G
1
· G
2
· · · G
L
.
(5.1)
SNR max is the maximum signal-to-noise ratio of a ∆Σ ADC (in decibels), N is the internal resolution (in bits), L is the loop order, OSR is the over-sampling ratio, and G n of the n th noise shaping filter (also referred to as loop filter is the gain
). As implied by (5.1), the value of SNR max is approximately linear with N , and so is the effective number of bits, ENOB
(refer to (1.10)). In the ADC of this work, the internal resolution is 2 bits ( N = 2), and the ADC was designed to work with OSR of 16. Substituting the above in (5.1) gives
SNR max
= 58.6 dB, that is, maximum ENOB of 9.4.
It has been demonstrated in Chapter 3 that an HBT-based 2-bit DAC can achieve linearity of 9.2 bits, which is sufficient for the goal of this work. However, two more mechanisms dominate the output noise of a current-steering DAC: clock jitter and data jitter. Jitter in the clock of any data converter results in white noise that contributes to the total SNR the following [15]:
SNR
CK J
= − 20 log 2 π f sig
J
RMS
, (5.2) where f sig is the input signal frequency, and J
RMS is the standard deviation of the clock period (= RMS jitter). In the context of the ∆Σ ADC of this work, the DAC output noise originating from clock jitter is directly transferred to the input of the modulator. Besides using a clean clock signal, no other method of alleviating clock jitter effect is known to us.
The second noise mechanism is the so-called data jitter, referring to the case in which the input bits of the DAC change their values at different times. If the time differences are constant ( deterministic jitter ), the effect on the DAC is likely to appear only at high frequencies, probably outside the signal band; however, if the differences are random
( random jitter ), the effect is similar to that of clock jitter. In ∆Σ modulators, the source of random timing of the bits is as follows. Since the delay of a latched comparator depends

70 Chapter 5.
∆Σ ADC on the voltage difference at its input (refer to Section 2.2.1), the comparators inside the modulator’s flash ADC may provide their outputs at different times. As a result, the current sources of the DAC are switched at different times, which brings about noisy
DAC output.
To avoid data jitter, the comparators of the flash ADC consist of the master-slave structure [16, 17], in which the output is well synchronized with the sampling clock.
However, the master-slave comparator has a significant side effect: it delays its output by one half of the clock period. Although this delay has no effect on open loop data converters, it introduces excess loop delay at the ∆Σ feedback path. Instability of the modulator caused by this delay must therefore be corrected using compensation methods [18]. In this work we have used two methods: reduction of the quantizer delay and introduction of a zero to the loop transfer function. The former will be explained in
Section 5.3.3, while the latter is discussed below.
Shown in Fig. 5.2 is a schematic diagram of the integrator used as a loop filter in this work. The circuit consists of a fully differential op amp connected as a summing integrator. Let A be the open loop gain of the op amp, the transfer function of the integrator from one of the inputs to the output is given by
H
I
= A ·
1
1 + sC ( 1 + A ) R
.
(5.3)
Inserting another resistor in series with the capacitor (denoted R
Z in Fig. 5.2) introduces a zero to the transfer function, and (5.3) becomes
H
I
= A ·
1 + sC [
1
R
+ sCR
Z
Z
+ ( 1 + A ) R ]
.
(5.4)
For simplicity of calculations, A can be approximated as a single pole function.
Derivations of the modulator transfer functions were made according to the diagrams illustrated in Fig. 5.3. In the linear model of Fig. 5.3-a, X is the input, Y is the output, E is the quantization error, H
1 and H
2 are the integrators’ transfer functions, and H q is the
C
R
Z dac n in p in n dac p
R
R
R
R
C
R
Z out n out p
Figure 5.2: Schematic diagram of the loop filter

5.2. System Design
E
X
1 st
Filter
H
1
2 nd
Filter
H
2
Y
(a)
H q
Quantizer
2 nd
Filter
H
2 in
1 st
Filter
H
1 out
(b)
H q
Quantizer in
1 st
Filter
H
1
2 nd
Filter
H
2 out
H q
(c)
Quantizer
2 nd
Filter
H
2
1 st
Filter
H
1 out
(d)
H q
Quantizer in
Figure 5.3: Diagrams used for (a) the linear model and derivation of (b) signal transfer function, (c) noise transfer function, and (d) loop transmission
71 quantizer’s transfer function, given by
H q
= A q
· e
− s τ q , (5.5)

72 Chapter 5.
∆Σ ADC where A q is the gain of the quantizer, and τ q is the quantizer’s delay. The signal transfer function was derived from Fig. 5.3-b, which yields
STF =
1 + H q
H
1
H
2
H
2
+ H q
H
1
H
2
.
(5.6)
Using the diagram of Fig. 5.3-c for derivation of the noise transfer function, one obtains
NTF =
1
1 + H q
H
2
+ H q
H
1
H
2
.
(5.7)
Finally, the loop transmission LT was derived from the open loop diagram shown in
Fig. 5.3-d, and it equals to
LT = − H q
H
2
( 1 + H
1
) .
(5.8)
It is implied in (5.8) that if a zero exists in H
2 the loop transmission inherits the very same zero. Hence, we have added a zero to the second integrator using the above mentioned method of series resistor in the feedback network, R
Z
.
As for noise of the modulator, the dominant noise contributors are the input-referred noise of the first integrator and the output noise of the DAC, as both are introduces at the modulator’s input. The DAC noise consists of the noise current generated by the transistors, and noise caused by clock and data jitter, as mentioned above.
5.2.2
System-Level Simulations
Design of the system started with the stability of the loop, using the linear model equations presented in the previous section. Values of the resistors and capacitors in the integrators, as well as other data regarding the op amps of the integrators and the quantizer, were fed into a MATLAB program with a graphical user interface ( GUI ). The GUI window is shown in Fig. 5.4, along with the values used for the ADC. Note that the quantizer delay was only 45% of the clock cycle due to the structure of the clock distribution tree, as will be explained in Section 5.3.3.
The next step was to perform full system simulation using Agilent’s Advanced Design System ( ADS ) software. In the first stage the complete ∆Σ ADC was constructed of ideal elements, i.e. ideal op amps, flash ADC, and DACs. Transient simulation verified proper behavior of the system. In the second stage the op amps were replaced by practical ones, which then were tweaked for best noise and linearity performance. Next to be replaced by practical circuit was the internal DAC, and finally the practical flash ADC substituted the ideal block.
The goal of the design was a 20 GS/s ADC with OSR of 16, that is, signal bandwidth of 625 MHz. However, substituting a clock frequency of 10 GHz (and consequently quantizer delay of 47.5% ) in the GUI of Fig. 5.4 shows that the ADC is yet reasonably stable with phase margin of 40
◦
.
Shown in Fig. 5.5 is simulated waveform of the ADC clocked at 20 GHz. The input signal was a sine wave of approximately 625 MHz, with slight shift in frequency to

5.2. System Design 73
Figure 5.4: GUI of the MATLAB program used for designing loop stability
-30
-40
-50
-60
-70
0
-10
-20
-80
-90
-100
0 1 2 3 4 5 6 frequency (GHz)
7 8 9 10
Figure 5.5: Simulated waveform of the complete ADC clocked at 20 GS/s.
The input signal was a sine wave of about 625 MHz

74 Chapter 5.
∆Σ ADC ensure that the signal is incoherent with the sampling clock. According to the simulation, the ADC exhibits an SNR of 48.2 dB, which is equivalent to a resolution of 7.7 bits.
Realization of the model of Fig. 5.1 is illustrated in Fig. 5.6. The decimation filter is replaced by an additional DAC and output buffer designed to drive analog measurement instrumentation. Besides the fully differential connections, we note the 2-bit ADC that consists of a differential flash converter, which provides 3 differential output bits in thermometer code. The bits are fed into the two DACs in parallel. The supply voltage of the whole ADC is 6 V to enable high gain of the loop filters’ op amps. The implementation of each block is detailed below.
In
1 st
Integrator
2 nd
Integrator
2-bit
ADC
2-bit
DAC
Thermometer
Code
Output
Buffer
Out
2-bit
DAC
Figure 5.6: Top level schematic diagram of a second order ∆Σ ADC. The decimation filter is replaced by an additional DAC and output buffer
5.3.1
Loop Filters
The structure of the integrators used as loop filters is shown above, in Fig. 5.2. The heart of the integrator is an op amp that performs the integration and input summation according to the feedback elements attached to it. The key parameters of the op amp are the low frequency ( LF ) gain and linearity. The LF gain affects the ADC performance in both linear and nonlinear aspects. The linear effect determines the maximum noise shaping at low frequencies. In addition, high LF gain reduces the nonlinear phenomena of dead band and idle tones [14], which are undesirable. As for linearity of the ∆Σ ADC, the linearity of the op amp is most critical in the first integrator, as this distortion is referred back directly to the input of the ADC. Design of the op amp is described is this section.
Schematic diagram of the op amp is shown in Fig. 5.7. The circuit consists of 2 gain stages with standard Miller compensation. Additional class-A common-collector stage serves as an output stage. The first stage is degenerated by a resistance of 20 Ω to im-

5.3. Circuit Implementation 75
V
CC
2.3 kΩ
500 Ω out p
1 kΩ
500 Ω
1 kΩ out n
30 Ω
500 Ω
100 Ω
1 kΩ
V
COM
30 Ω in p
800 Ω
20 Ω
800 Ω 300 Ω
20 Ω in n
200 fF
70 Ω
300 Ω
50 Ω
50 Ω
200 fF
70 Ω out p out n
400 Ω 500 fF 550 Ω
Common Mode Feedback
600 Ω 80 Ω 70 Ω
2-Stage Amplifier
60 Ω 50 Ω 50 Ω
Output
Stage
Figure 5.7: Schematic diagram of the op amp. Emitter dimensions: 4x1 µ m
2 in the first stage; 8x1 µ m
2 in the second and output stages; 2x1 µ m
2 in the common mode feedback amplifier prove the linearity of the amplifier, at the expense of 8 dB in gain. However, since the linearity of the second integrator is less critical, no degeneration was applied to the op amp of the second integrator, to regain the 8 dB-gain lost in the first integrator. In order to avoid latch up problems during start up, the common mode feedback circuit controls only half of the current of the second gain stage, while the other half is fixed current.
The op amp uses the global 6 V supply voltage of the ADC and consumes 50 mA
(excluding any load current). The output common mode voltage is 2.5 V, and so is the input DC voltage.
5.3.2
2-Bit Quantizer
The quantizer consists of a differential 2-bit flash ADC and current steering DAC. Control over the quantizer gain is available via the reference voltage of the flash ADC. Since noise and linearity of the DAC are critical for the performance of the complete ∆Σ ADC, no external control is connected to the DAC.
2-Bit Flash ADC
Shown in Fig. 5.8 is a schematic diagram of the flash ADC. The transistors act as current sources the create voltage drops across the resistors of the ladders. As the voltage at V
REF sets the currents flowing along the ladders, it actually controls the dynamic range of the flash ADC. The ratio between the dynamic ranges of the flash ADC and the DAC set the

76 in p in n
100 Ω 100 Ω
100 Ω 100 Ω
C
2
D p
Q p
D n
CK p
CK
Q n n
B2 p
B2 n
C
1
D p
Q p
D n
CK p
CK
Q n n
B1 p
B1 n
C
0
D p
Q p
D n
CK p
CK
Q n n
B0 p
B0 n
Chapter 5.
∆Σ ADC
V
REF
200 Ω 200 Ω
Figure 5.8: Schematic diagram of the differential 2-bit flash ADC. The emitters are 4x1 µ m 2 total gain of the quantizer.
Each of the 3 comparators comprises a preamplifier and master-slave latch. The preamplifier improves the sensitivity and alleviates the effect of clock kickback. Illustrated in Fig. 5.9, it consists of a cascode stage followed by two emitter follower stages.
The cascaded followers isolate the output of the preamplifier from its input, and thus preventing the glitches generated by clock kickback to distort the input signal. In addition, the preamplifier has a separate biasing circuit. This prevents the clock transients from interfering via the current sources. The master-slave latch is based upon the standard ECL topology. Here, clock kickback effect is reduced by degeneration of the clock switching pair. The latching pair includes emitter followers to increase its speed by neutralizing the Miller effect [8,19–21] (refer to Section 2.2.2). Finally, the speed of the master latch is enhanced by introduction of peaking inductors [22]. The schematic diagram of the complete master-slave latch is depicted in Fig. 5.10. Simulated sensitivity of the comparator is 0.3 mV when clocked at 20 GHz.
Distribution of the clock signal between the comparators is a key issue and will be discussed in the next section. Total current consumption of the flash ADC is 173 mA.

5.3. Circuit Implementation 77
2-Bit DAC
The DAC is based on the standard differential current steering architecture [23] with simple resistive load, as shown in Fig. 5.11. Each input bit (D
0
–D
2
) switches the current between the outputs of a differential pair. The digital input is provided by the flash
ADC in the thermometer coding format; hence, the switched current sources (I
0
–I
2
) are identical. The differential pairs forming the current switches are slightly degenerated in order to reduce the output overshoots caused by sharp input transients. Similar to the circuit of Chapter 3, the differential pairs are matched in common centroid structures.
The resistors and transistors forming the current sources are shuffled in a manner that each device consists of 3 parallel devices. To enhance device uniformity, two rows of dummy transistors provide uniform metal density around the current source transistors during the etching of the transistor layers. It has been demonstrated in Chapter 3 that the technology is mature enough to fabricate a high linearity DAC that can achieve a linearity of 9.2 bits.
In the ∆Σ ADC, the DAC is loaded by the two integrators, which together introduce a 150 Ω resistance to ground at each side. In this configuration the DAC has a least significant bit value of 300 mV. The simulated settling time to a 1 mV band around the final value is 9 psec, and the total current consumption, when loaded by the integrators, is 15 mA.
V
CC
150 Ω 150 Ω
200 Ω
200 Ω
300 Ω in p in n out p out n
400 Ω 100 Ω 400 Ω 400 Ω 200 Ω 200 Ω
Figure 5.9: Schematic diagram of the comparator’s preamplifier. All the emitters are 4x1 µ m
2

78 Chapter 5.
∆Σ ADC

5.3. Circuit Implementation
V
CC
1.6 kΩ
45 Ω
220 Ω
45 Ω
A p
A n
50 Ω
D0 p
20 Ω
I
0
20 Ω
D0 n
D1 p
20 Ω
I
1
20 Ω
D1 n
D2 p
20 Ω
I
2
20 Ω
D2 n
50 Ω 50 Ω 50 Ω
79
Figure 5.11: Schematic diagram of the 2-bit DAC. Emitter dimensions: 2x1
µ m
2 in the current sources and switches; 4x1 µ m
2 in the biasing branch
5.3.3
Clock Distribution
As explained before, the comparators of the flash ADC consist of the master-slave structure to avoid data jitter. Since the master-slave comparator delays its output by one half of the clock period, it introduces excess delay at the ∆Σ feedback loop, which may results in instability of the ∆Σ modulator. One of the methods we have used in this work to overcome the excess loop delay is reduction of the quantizer delay to slightly less than half clock period. In addition, clock skew between the various comparators may result in noisy DAC output due to deterministic clock jitter. To conclude, there are two considerations in the design of the clock distribution circuitry: (1) the comparator’s delay should be reduced below 50% of the clock cycle, and (2) the clock edges must take place in all of the comparators at the same moment, especially in the slave latches.
The structure of the clock distribution manifold is depicted in Fig. 5.12. A single ended clock signal (CK p
) is introduced at the input. A coplanar waveguide follows the input pad, and then the signal is split by a divide-by-2 resistive power divider. From this point onward there are two separate paths – one goes to the master latches, and the other to the slave latches. The former comprises longer transmission lines (marked in gray in Fig. 5.12 than the lines leading to the slaves. The delay difference between the two paths sums up to about 2.5 psec. This delay difference results in shorter comparator delay at the expense of small degradation in sensitivity, as the masters have shorter time for making a decision.
To avoid clock skew, each path consists of a main transmission line, followed by a divide-by-3 resistive power divider. The next 3 parallel transmission lines are of the same

80 Chapter 5.
∆Σ ADC to C
2
’s slave
50 Ω
CK n to C
1
’s slave
50 Ω
CK n to C
0
’s slave
50 Ω
CK n
CK p to C
2
’s master
50 Ω
CK n to C
1
’s master
50 Ω
CK n to C
0
’s master
50 Ω
CK n
Figure 5.12: Structure of the clock distribution manifold. The gray transmission lines have longer delay than their white counterparts electrical length. Also here, transmission lines were realized as coplanar waveguides.
Finally, the lines are matched to 50 Ω by a shunt resistor connected to the AC ground introduced at the CK n node.
5.3.4
Measurement Auxiliary Circuits
A common method of measurement of ∆Σ ADCs is by feeding the bit stream coming from the output into a logic analyzer that logs the digital data in a file. Then data are processed off-line by a mathematical software [8]. This method is limited by the speed of the logic analyzer, usually several hundred MHz. In addition, the number of probes

5.3. Circuit Implementation 81 required for such a measurement equals, at least, to the number of bits of the DACs.
Acquisition speed can be slowed down by buffering the output in a shift register, but bit number is then multiplied accordingly [3, 9].
If the ADC loop resolution is 1 bit, the digital output can be treated as an analog signal and fed directly into a spectrum analyzer, to obtain SNR and linearity [24]. Since our loop resolution is 2 bits, a different method of measurement is required. The method proposed by us is explained below.
Due to the high sensitivity of the modulator performance to the DAC’s output, any attempt to probe this signal will significantly distort is. We have therefore located the probing point at the digital signal connecting the flash’s output with the DAC’s input.
The signal is fed to an additional DAC, which is identical to the internal DAC, and then buffered by a high current common collector stage (Fig. 5.13). Finally, the signal is introduced at the input of a spectrum analyzer.
Once the signal is sampled by the spectrum analyzer, data can be acquired by a PC.
Then SNR can be derived from the data by integrating noise power and signal power.
Alternatively, if the spectrum analyzer offers built-in adjacent channel power ( ACP ) mea-
V
CC
600 Ω in p in n
45 Ω
45 Ω out p out n
400 Ω 80 Ω 80 Ω
Figure 5.13: Schematic diagram of the output buffer. All the emitters are 8x1 µ m
2

82 Chapter 5.
∆Σ ADC surement, the instrument can derive SNR online.
It should be noted, however, that in this measurement setup the linearity might be limited by the output buffer, which may be overloaded by the spectrum analyzer. To overcome this limitation, we propose another method of measurement as follows. The output signal is applied to a high speed sampling oscilloscope. The oscilloscope is triggered manually to make a single sampling sequence. Data is then acquired by a PC and analyzed by a mathematical software. Here, the digital value of the output can be derived from the analog level at any given moment, thus the linearity of the driving circuit is not critical. In this method the data are transformed to the frequency domain, and then
SNR is calculated.
5.3.5
Layout
Layout of the circuit was designed in the Fraunhofer IAF indium phosphide DHBT technology according to the following guidelines:
• Differential pairs should be as symmetric as possible to avoid offset
• Layout of the flash ADC should support the structure of the clock manifold mentioned above
• The general structure should support the back-and-forth route of the ∆Σ feedback loop
• Space should be allocated for the output DAC and buffer
• Supply voltages must be distributed to every point in the circuit with high capacitance to ground
• Parasitics should be either minimized or well modeled due to the high frequency of operation
• The circuit will be probed by 100µ m pitch PGSGSGP probes available at the Fraunhofer IAF lab
Shown in Fig. 5.14-a is the layout of an integrator serving as a loop filter. The nodes of the differential input are located at the bottom, while the input of the DAC signal is on the right. The output is at the top. The core of the op amp is in the middle, while the biasing circuit is on the right and the common mode feedback amplifier is on the left.
Two areas were left empty for feedback elements, as evident in the figure.
Layout of a comparator is shown in Fig. 5.14-b. The preamplifier and master latch are located on the left side, followed by long lines that connect the master’s output with the slave’s input. The direction of the slave latch is opposite, that is, its input is on the top.
this structure provides the U-turn required for the feedback back-and-forth structure, and also enables to design the layout of the flash ADC so that all the masters are concentrated together on one side, and all the slaves on the other side. This is essential for

5.3. Circuit Implementation
(a)
83
(b)
(c) (d)
(e)
Figure 5.14: Layout of the building blocks of the ∆Σ ADC: (a) loop filter,
(b) comparator, (c) 2-bit flash ADC, (d) 2-bit DAC, and (e) output buffer implementing the clock manifold. These long lines, however, has significant inductance; this will be discussed in the next paragraph. The inductors of the master latch were realized by microstrip transmission lines to retain the layout as compact as possible.
Fig. 5.14-c depicts the layout of the 2-bit flash ADC. The upper half includes the clock manifold, and the resistor ladders are evident in the bottom left corner. The long lines connecting the msters with the slaves are located beneath the clock distribution structure.

84 Chapter 5.
∆Σ ADC
This actually makes them behave as transmission lines. Since they are terminated with a high impedance (the input impedance of the slave’s tracking pair) they load the master latches with a capacitive impedance. The output stage of the master latch is designed to drive such a capacitance. However, one might be concerned about the crosstalk noise injected from the clock lined to the lines of the comparator. This phenomenon has little effect on the flash ADC performance due to 2 reasons: (1) the signals at the comparators are differential, hence the interference does not affect the voltage difference between the differential lines, and (2) the master latches changes their outputs only after the clock rising, with some delay, therefore the clock edges interfere the signals only when their values are not critical. The latter also explains why the signals of the comparators do not result in clock jitter.
Layout of the 2-bit DAC is illustrated in Fig. 5.14-d. The layout is similar to the layout of the circuit introduced in Chapter 3, including static shuffling of the current sources and use of common centroid structures. Finally, the simple layout of the output buffer is shown in Fig. 5.14-e.
All the above blocks were put together to form the layout of the whole ∆Σ ADC, as illustrated in Fig. 5.15. The number of transistors sums up to 378 transistors, with the following distribution: 31 transistors in each of the op amps, 245 transistors in the flash
ADC (where each comparator includes 81 transistors), 32 transistors in each of the DACs, and 7 transistors in the output buffer.
Figure 5.15: Layout of the ∆Σ ADC

5.4. Experimental Results 85
The ∆Σ ADC was fabricated using the Fraunhofer Institute for Applied Solid State Physics
( IAF ) InP/GaInAs DHBT technology [2]. A microphotograph of the circuit is shown in
Fig. 5.16. Total die area was 2.25x2.25 mm
2
.
5.4.1
SNR Measurement
A setup for evaluating the SNR (and ENOB) of the ADC is shown in Fig. 5.17. The signals were generated by a Wiltron 68337B and Wiltron 68177B signal generators. Since the former’s minimum frequency is 2 GHz it was used for clocking the circuit, while the latter, which can go down to 10 MHz, generated the input signal. The analog output was sampled by an Agilent E4440A spectrum analyzer. The supply voltage was 6 V, the DC voltage of the inputs was 2.5 V, and the reference voltage of the flash ADC ( V re f
) was
1.7 V. All DC voltages were provided by Hameg HM 8142 power supplies. The total power consumption was 2.26 W, where the ADC itself consumed 1.89 W, and the output driving circuits 370 mW.
The circuit was tested with various clock and signal frequencies, where the signal frequency was slightly shifted from the Nyquist frequency to avoid coherent sampling. Best results were obtained with a clock frequency of 10 GHz, signal frequency of 310.779 MHz,
Figure 5.16: Microphotograph of the ∆Σ ADC

86 Chapter 5.
∆Σ ADC
Signal Generator
∆Σ
ADC
DUT
Output
DAC
Spectrum Analyzer
Signal Generator
Figure 5.17: Measurement setup used for SNR evaluation and signal power of 1.2 dBm (from which 2 dBm should be subtracted due to cable attenuation). Spectrum of the output is shown in Fig. 5.18-a. Noise shaping is clearly evident in the figure. Using the ACP function of the spectrum analyzer, the noise and signal powers were integrated and the SNR was 44.1 dB. This value is equivalent to an
ENOB of 7.01. Fig. 5.18-b illustrates the frequency ranges across which power was integrated. Note that the measured SNR is in good agreement with the simulated one (refer to Section 5.2.2).
The waveform of Fig. 5.18-a shows significant harmonies, a result of nonlinearity somewhere in the system. The nonlinearity can originate either by the ADC itself or in the probing circuit (output DAC and buffer). Two additional measurements were carried out in order to diagnose this phenomenon: two-tone linearity test and time domain measurements using an oscilloscope. Both are explained below.
5.4.2
Linearity Measurement
The two-tone measurement setup, shown in Fig. 5.19-a, is basically similar to the afore mentioned SNR measurement setup, with an additional signal generator (HP 83650B) and passive power splitter/combiner. Since no SNR calculation is involved in this measurement, we have used a HP 8565E spectrum analyzer. Two sine waves of 310 and
310.5 MHz were generated and applied to the input.
The results of the measurements taken by the setup are shown in Fig. 5.19-b. The spurious-free dynamic range ( SFDR ) decreases in a slope of 3 with the input power, then saturates at approximately 24 dB. If the source of nonlinearity is the ADC itself, this behavior is hard to explain. However, if the source is the output DAC, the saturation in SFDR can be explained as follows. At small input signals the output DAC toggles only between its two central levels, and the measured SFDR is of the ADC itself with additional distortion that might occur in the output buffer. As the input signal becomes larger, all the DAC levels become active, and SFDR is dominated by the DAC and the output buffer.

5.4. Experimental Results
-30
-40
-50
-60
-70
-80
0
-10
-20
10
0
-10
-20
10
0
-30
-40
-50
-60
-70
0 out of band noise signal in band noise
500 1000 1500 2000 2500 3000 3500 4000 4500 5000 frequency (MHz)
(a)
100 out of band noise signal in band noise
500 600 200 300 frequency (MHz)
400
(b)
Figure 5.18: Spectrum of the ADC’s output during SNR measurement: (a) full
Nyquist span (b) closeup on low frequencies
87
5.4.3
Time Domain Measurement
Due to the above we concluded that the nonlinearity is probably sourced by the probing circuit rather than the ADC itself. In Section 5.3.4 we suggested another setup that is insensitive to the performance of the probing circuit. In this setup the output signal is

88 Chapter 5.
∆Σ ADC
Signal Generator
Power Combiner
Signal Generator
DUT
∆Σ
ADC
Output
DAC
Spectrum Analyzer
Signal Generator
(a)
32
30
28
26
24
22
20
-15
40
38
36
34
-10 -5 0
(b)
5 10
Figure 5.19: (a) Two-tone measurement setup (b) Spurious-free dynamic range ( SFDR ) measured by the two-tone setup. The dashed line denotes a slope of − 3 applied to a high speed sampling oscilloscope. The oscilloscope is triggered manually to make a single sampling sequence. Data is then acquired by a PC and analyzed by a mathematical software. Since the digital value of the output can be derived from the analog level at any given moment, the linearity of the driving circuit is not critical. The setup is illustrated in Fig. 5.20. We have used the same instruments as in the previous setups, with an Agilent 86118A module and 86100B oscilloscope mainframe. The oscilloscope was triggered by the clock signal.
The results were very noisy as the oscilloscope failed to synchronize its trigger with the signal coming from the ADC due to severe jitter in the latter. Therefore, it was im-

5.4. Experimental Results 89
Signal Generator
Signal Generator
DUT
∆Σ
ADC
Output
DAC
Oscilloscope
Figure 5.20: Time domain measurement setup possible to extract the digital information from the waveform of the oscilloscope. The source of the jitter in the signal is discussed hereinafter.
Although the data could not be extracted, a histogram of the output voltage could provide information on the nonlinearity of the output driving circuit. Shown in Fig. 5.21
are measurements of the three voltage steps of the output DAC, all made on the histogram. It was assumed that the output spends more time at the final levels than in
Figure 5.21: Output DAC levels measured on the output histogram

90 Chapter 5.
∆Σ ADC transitions between levels, hence the voltages at which the histogram shown highest concentrations are the DAC levels. INL was derived from the DAC levels, and it corresponds to an SFDR of 23 dB – in good agreement with the two-tone results (Fig. 5.19-b).
As for the jitter, the reason may be one or more of the following:
• The output buffer consists of a common collector stage. This stage can become unstable when loaded by large capacitance, and therefore is probably inadequate for interfacing with measurement equipment
• The lines connecting the output DAC with the flash ADC are long, which at high frequencies can be accentuated as excess inductance. Such inductance may distort the signal on the line and even, in some cases, oscillate
The former can be corrected by designing an output buffer using a common emitter stage. The latter can be improved in layout at the expense of die area. Unfortunately, there is no more activity in the IAF DHBT process, thus the corrections cannot be carried out.
In summary, the ADC exhibits an SNR of 44.1 dB (7.01 bits), and characterization of the linearity is impossible due to jitter and nonlinearity in the output driving circuit.
It is important to note here that the resolution of an ADC is derived from its signal-to-
(noise-and-distortion) ratio ( SNDR ), as explained in Section 1.1.1. In this work, ENOB is derived only from quantization and thermal noises, and therefor is presented only for comparison purposes.
Table 5.1 summarizes the performance of the ∆Σ ADC. A continuous time multibit low-
Modulator type
Technology
No. of transistors
Supply voltage
Power consumption
Clock frequency
OSR
SNR
SNDR
FoM continuous time lowpass 2 nd order
Fraunhofer IAF InP DHBT
378
6 V
1.89 W
10 GHz
16
44.1 dB
N/A
23.5 pJ/conv
Table 5.1: Summary of ADC performance

5.5. Conclusion 91

92 Chapter 5.
∆Σ ADC pass ∆Σ ADC, clocked at 10 GHz, was demonstrated. The ADC consists of a 2 nd order modulator, which makes use of op amps rather than simple transconductance amplifiers.
The converter consumes 1.89 W and exhibits SNR of 44.1 dB. To our knowledge, this is the first multibit ∆Σ ADC implemented in an HBT technology.
Table 5.2 compares the ADC of this work to recently published comparable works.
[1] Erik Lind, Adam M. Crook, Zach Griffith, and Mark J.W. Rodwell, “560 GHz f t
, f max
InGaAs/InP DHBT in a novel dry-etched emitter process”, Proceedings of DRC
2007 , June 2007.
[2] R. Driad, R.E. Makon, V. Hurm, F. Benkhelifa, R. L ¨osch, J. Rosenzweig, and
M. Schlechtweg, “InP-based DHBT technology for high-speed mixed signal and digital applications”, Proceedings of IPRM 2009 , pp. 10–15, May 2009.
[3] Sundararajan Krishnan, Dennis Scott, Zach Griffith, Miguel Urteaga, Yun Wei,
Navin Parthasarathy, and Mark Rodwell, “An 8-GHz continuous-time Σ – ∆ analog– digital converter in an InP-based HBT technology”, IEEE Transactions on Microwave
Theory and Techniques , vol. 51, no. 12, pp. 2555–2561, December 2003.
[4] Adam Hart and Sorin P. Voinigescu, “A 1GHz bandwidth low-pass ∆Σ ADC with
20GHz to 50GHz adjustable sampling rate”, Proceedings of RFIC 2008 , pp. 181–184,
June 2008.
[5] James A. Cherry, W. Martin Snelgrove, and Weinan Gao, “On the design of a fourthorder continuous-time LC delta–sigma modulator for UHF A/D conversion”, IEEE
Transactions on Circuits and Systems–II: Analog and Digital Signal Processing , vol. 47, no. 6, pp. 518–530, June 2000.
[6] Theodoros Chalvatzis, Eric Gagnon, Morris Repeta, and Sorin P. Voinigescu, “A low-noise 40-GS/s continuous-time bandpass ∆Σ ADC centered at 2 GHz for direct sampling receivers”, IEEE Journal of Solid-State Circuits , vol. 42, no. 5, pp. 1065–1075,
May 2007.
[7] Bharath Kumar Thandri and Jose Silva-Martinez, “A 63 dB SNR, 75-mW bandpass
RF Σ∆ ADC at 950 MHz using 3.8-GHz clock in 0.25µ m SiGe BiCMOS technology”,
IEEE Journal of Solid-State Circuits , vol. 42, no. 2, pp. 269–279, February 2007.
[8] Michael Inerfield, William Skones, Steve Nelson, Daniel Ching, Peter Cheng, and
Colin Wong, “High dynamic range InP HBT delta-sigma analog-to-digital converters”, IEEE Journal of Solid-State Circuits , vol. 38, no. 9, pp. 1524–1532, September
2003.

References for Chapter 5 93
[9] Albert E. Cosand, Joseph F. Jensen, H. Chris Choe, and Charles H. Fields, “IFsampling fourth-order bandpass ∆Σ modulator for digital receiver applications”,
IEEE Journal of Solid-State Circuits , vol. 39, no. 10, pp. 1633–1639, October 2004.
[10] Martin Schmidt, Markus Grzing, Stefan Heck, Ingo Dettmann, Manfred Berroth,
Dirk Wiegner, Wolfgang Templ, and Andreas Pascht, “A 1.55 GHz to 2.45 GHz center frequency continuous-time bandpass delta-sigma modulator for frequency agile transmitters”, Proceedings of RFIC 2009 , pp. 153–156, June 2009.
[11] P. Ostrovskyy, H. Gustat, Ch. Scheytt, and Y. Manoli, “A 9 GS/s 2.1..2.2 GHz bandpass delta-sigma modulator for class-s power amplifier”, Proceedings of MTT-S 2009 , pp. 1129–1132, June 2009.
[12] George I. Bourdopoulos, Aristodemos Pnevmatikakis, Vassilis Anastassopoulos, and Theodore L. Deliyannis, Delta-Sigma Modulators: Modeling, Design and Applications , Imperial College Press, 2003.
[13] Steven R. Norsworthy, Richard Schreier, and Gabor C. Temes, Delta-Sigma Data
Converters: Theory, Design, and Simulation , Wiley–IEEE Press, 1997.
[14] Richard Schreier and Gabor C. Temes, Understanding Delta-Sigma Data Converters ,
Wiley–IEEE Press, 2005.
[15] Haruo Kobayashi, Masanao Mofumura, Kensuke Kobayashi, and Yoshitaka Onaya,
“Aperture jitter effects in wideband ADC systems”, Proceedings of SICE 1999 , pp.
1089–1094, August 1999.
[16] Rob E.J. van de Grift and Rudy J. van de Plassche, “A monolithic 8-bit video A/D converter”, IEEE Journal of Solid-State Circuits , vol. SC-19, no. 3, pp. 374–378, June
1984.
[17] Tsutomu Wakimoto, Yukio Akazawa, and Shinsuke Konaka, “Si bipolar 2-GHz 6bit flash A/D conversion LSI”, IEEE Journal of Solid-State Circuits , vol. 23, no. 6, pp.
1345–1350, December 1988.
[18] Weinan Gao, Omid Shoaei, and W. Martin Snelgrove, “Excess loop delay effects in continuous-time delta-sigma modulators and the compensation solution”, Proceedings of ISCAS 1997 , pp. 65–68, June 1997.
[19] Wei-Min Lance Kuo, Xiangtao Li, Ramkumar Krithivasan, Yuan Lu, John D.
Cressler, Yevgen Borokhovych, Hans Gustat, Bernd Tillack, and Bernd Heinemann,
“A 32 GSample/sec SiGe HBT comparator for ultra-high-speed analog-to-digital conversion”, Proceedings of APMC 2005 , December 2005.
[20] Behzad Razavi, Principles of Data Conversion System Design , Wiley–IEEE Press, 1995.

94 Chapter 5.
∆Σ ADC
[21] Xiangtao Li, Wei-Min Lance Kuo, Yuan Lu, Ramkumar Krithivasan, Tianbing Chen,
John D. Cressler, and Alvin J. Joseph, “A 7-bit, 18 GHz SiGe HBT comparator for medium resolution A/D conversion”, Proceedings of BCTM 2005 , pp. 144–147, October 2005.
[22] Sunghyun Park and Michael P. Flynn, “A regenerative comparator structure with integrated inductors”, IEEE Transactions on Circuits and Systems I: Regular Papers , vol. 53, no. 8, pp. 1704–1711, August 2006.
[23] T.W. Henry, “High speed analog-to-digital and digital-to-analog techniques”, IEEE
Transactions on Nuclear Science , vol. 20, no. 5, pp. 52–66, October 1973.
[24] Sundararajan Krishnan, Dennis Scott, Miguel Ycteaga, Zachary Griffrth, Yun
Wei, Mattias Dahlstrom, Navin Parthasarathq, and Mark Rodwell, “An 8-GHz continuous-time Σ – ∆ analog-digital converter in an InP-based DHBT technology”,
Proceedings of MTT-S 2003 , vol. 2, pp. 1063–1065, June 2003.

HE achievements of this research thesis are summarized in this chapter.
Starting with the ADC building blocks, the work on a high sensitivity
20 GS/s latched comparator is outlined, the the high linearity 2-bit DAC, as well as the gain enhanced op amps – both in CMOS and HBT technologies. Then the chapter moves to summarize the work on the complete ∆Σ ADC.

96 Chapter 6. Summary
Sensitivity of the comparator is a critical parameter in the design of an analog-to-digital converter. A method for improving the sensitivity (or speed) of a master-slave emittercoupled logic ( ECL ) comparator using emitter degeneration resistors was presented. The degeneration resistors in the latching pair reduce the transistor charging time, thus allowing more time for regeneration. Improved and standard comparators were implemented using the InP/GaInAs HBT technology and were tested at a clock rate of 20 GHz.
The improved comparator exhibited better sensitivity (by a factor of 1.7) compared to the standard design. A record low sensitivity value of 10 mV was obtained.
A high linearity 2-bit digital-to-analog converter implemented in an InP/ GaInAs DHBT technology was presented. The DAC is based upon the current steering architecture.
Cascode structure and layout techniques, i.e. static shuffling and dummy devices, have been used to enhance the linearity. The DAC exhibits static integral/differential nonlinearities of 5.5
· 10
− 3
LSB, equivalent to a resolution of 9.2 bits. Dynamic measurements qualitatively show proper behavior at 6 GS/s, while simulations with typical on-chip load exhibit sufficiently fast settling at 20 GS/s.
Gain of operational amplifiers is a key parameter for accurate settling, low gain error, and high linearity, of feedback amplifiers. Two gain-enhanced fully-differential amplifiers were presented in this work. The first amplifier was designed in a digital CMOS technology, while the second one, based upon the same active bootstrap technique, was designed in the InP HBT technology. The active bootstrap technique can enhance the gain to any desired level, but is very sensitive to process variations. A process variation self correction circuit was incorporated to each circuit, to obtain high gain at all process corners. Simulations of a two-stage amplifier in a standard 45 nm CMOS process demonstrated gain of 109 dB and unity-gain bandwidth of 500 MHz. The process variation compensation circuit maintained the gain in excess of 48 dB at all process corners.
Circuit performance is compared to that of other gain-enhanced 1-V CMOS amplifiers.
Simulations of the HBT-based amplifier exhibited gain of 82 dB and unity-gain bandwidth of 62 GHz. The gain remained above 64 dB under process variations.
Continuous time ∆Σ ( CT ∆Σ ) ADCs are capable of sampling at much higher rates than discrete time ∆Σ s. This makes HBT technologies excellent candidates for the implemen-

6.4.
∆Σ ADC 97 tation of fast CT ∆Σ ADCs. Due to linearity considerations, all HBT-based ∆Σ ADCs known to us incorporated a single-bit DAC. This work presents a multibit lowpass ∆Σ
ADC based upon the InP HBT technology, which incorporates an internal resolution of
2 bits. The ADC was clocked at 10 GHz, its total power consumption was 1.9 W, and it obtained an ENOB of 7 at signal bandwidth of 312.5 MHz. To our knowledge, this is the first multibit ∆Σ ADC implemented in an HBT technology.

98 Chapter 6. Summary

This appendix provides brief information on the HBT technology of the Technion. The
InP/GaInAs double-heterojunction bipolar transistors ( DHBT s) consist of two heterojunctions, where electron transit through the base-collector junction is possible thanks to the pulse doping technique [1–3]. Layer structure and process stages are detailed below.
Layers are grown bottom to top on a semi-insulator ( SI ) InP 2” wafer. They are grown lattice matched by a metal-organic molecular beam epitaxy ( MOMBE ) system. Layer structure and properties are summarized in Table A.1.
Lithography is made by a GCA stepper that uses 5” reticles. Data on reticle is 5 times larger than actual size on wafer. In order to reduce reticle cost we have placed several fields on a single reticle with 5-mm dark lines separating the fields from each other. On each lithography the stepper blades cover all the fields except the one being projected.
The optical axis of the stepper’s lens is aligned with the center of the reticle. Therefore, the field of the most critical lithography (emitter lithography) was placed in the center of the reticle to achieve best optical performance.
The lithography sequence is as follows:
1.
Emitter – lithography of emitter metal.
2.
TLM Emitter – lithography of large emitter patterns for large area transistors and other test patterns, e.g. TLM test fixtures for the emitter layers. After this lithography the emitter layers are etched.

100 Appendix A. Technion’s HBT Technology
Layer
Cap Layer
Emitter Contact
Emitter Contact
Emitter Bulk
Emitter
Base
Pulse
Collector
Collector Contact
Subcollector
Stop Etch
Substrate
(Wafer)
Thickness
[ ˚ ]
500
100
200
1650
150
200
35
2000
200
4000
200
500 [ µ m ]
Composition
InP
GaInAs
GaInAs
InP
InP graded
Ga
0.53
In
0.47
As →
Ga
0.43
In
0.57
As
InP
InP
GaInAs
InP
GaInAs
InP
Type undoped
N
+
N
+
N
+
N
P
+
—
Sn
Sn
Sn
Sn
C
Dopant Doping
Valve/Temp
Control
—
940
◦
C
910
◦
C
910
◦
C
715
◦
C
1.8 V
N
+ undoped
N
+
N
+ undoped semiinsulator
Si
—
Fe
Si
—
Si
3.0 V
—
3.0 V
2.0 V
—
—
Table A.1: Layer properties
3.
Base – lithography of base metal, creates base contacts that are self-aligned to the emitter.
4.
Plug – lithography of base plug.
5.
Base Protect – lithography of polyimide that covers the base and emitter, to avoid etching of the base layer between the base contact and the emitter. This lithography is followed by base and collector etching.
6.
Collector Metal – lithography of collector metal.
7.
Isolation – lithography of the subcollector that isolates the collectors of the various transistors from each other.
8.
Via Emitter and Base – lithography of polyimide that covers the transistor, with via openings to the emitter metal and base plug.
9.
Via Collector – lithography that opens a via to the collector contact.
10.
Pre-Resistor – lithography of a SiN layer that isolates the forthcoming resistor layer from the InP substrate. This is essential for controlling the sheet resistance of the resistor film.
11.
Resistor – lithography of a thin NiCr film for resistors. Sheet resistance is 50 Ω / .

References for Appendix A 101
12.
Metal 1 – lithography of the 1 st metal.
13.
Capacitor – lithography of SiN that serves as capacitor dielectric film. After this lithography the whole wafer is covered by a polyimide layer.
14.
Via 2-1 – lithography of via in the polyimide that connects Metal 2 with Metal 1.
Another lithography (with a negative photoresist) fills the via openings with metal plugs.
15.
Metal 2 – lithography of the 2 nd metal.
16.
Via 3-2 – lithography of via in the polyimide that connects Metal 3 with Metal 2.
Another lithography (with a negative photoresist) fills the via openings with metal plugs.
17.
Metal 3 – lithography of the 3 rd metal.
18.
Via GP-3 – lithography of via in the polyimide that connects Metal GP with Metal 3.
Another lithography (with a negative photoresist) fills the via openings with metal plugs.
19.
Metal GP – lithography of the 4 th metal that usually serves as ground plane.
Shown in Fig. A.1 are SEM images of a transistor at several stages of processing.
[1] D. Cohen Elias, S. Kraus, A. Gavrilov, S. Cohen, N. Buadana, V. Sidorov, and D. Ritter,
“An abrubt InP-GaInAs-InP DHBT”, IEEE Electron Device Letters , vol. 26, no. 1, pp.
14–16, January 2005.
[2] D. Cohen Elias, S. Kraus, A. Gavrilov, S. Cohen, N. Buadana, V. Sidorov, and D. Ritter,
“Design and performance of InP/GaInAs/InP abrupt DHBTs”, Proceedings of IPRM
2005 , pp. 449–451, May 2005.
[3] D. Cohen Elias, A. Gavrilov, S. Cohen, S. Kraus, A. Sayag, and D. Ritter, “Abrupt delta-doped InP/GaInAs/InP DHBTs with 0.45µ m -wide T-shaped emitter contacts”, IEEE Electron Device Letters , vol. 29, no. 9, pp. 971–973, September 2008.

102 Appendix A. Technion’s HBT Technology
(a)
(c)
(b)
(d)
(e)
Figure A.1: SEM images of a transistor at various processing stages: (a) after emitter etching (b) after creation of base plug (c) after isolation lithography
(d) after opening via holes in the transistor’s polyimide cover (e) after Metal 1 liftoff

During the work on this research I developed a program with graphical user interface
( GUI ) for designing a 2 nd order ∆Σ lowpass modulator. The program calculates the signal and noise transfer functions ( STF and NTF ) according to the modulator’s linear model, and finds the parameters required for stabilizing the loop, i.e. phase margin and gain margin.
The program runs on MATLAB 6.5 and consists of a figure file ( delsig2 design.fig
) and
MATLAB M-file ( delsig2 design.m
). Every button or text editing box in a figure has its own name ( tag ) and is connected to a callback function in the corresponding M-file. Tags can be derived from the M-file.
delsig2 design.m
function varargout = delsig2_design(varargin)
% Begin initialization code - DO NOT EDIT gui_Singleton = 1; gui_State = struct(’gui_Name’, mfilename, ...
’gui_Singleton’, gui_Singleton, ...
’gui_OpeningFcn’, @delsig2_design_OpeningFcn, ...
’gui_OutputFcn’, @delsig2_design_OutputFcn, ...
’gui_LayoutFcn’, [] , ...
’gui_Callback’, []); if nargin & isstr(varargin{1}) gui_State.gui_Callback = str2func(varargin{1}); end if nargout else
[varargout{1:nargout}] = gui_mainfcn(gui_State, varargin{:}); gui_mainfcn(gui_State, varargin{:});

104 Appendix B. A GUI for ∆Σ Modulator Design end
% End initialization code - DO NOT EDIT
% --- Executes just before delsig2_design is made visible.
function delsig2_design_OpeningFcn(hObject, eventdata, handles, varargin) handles.output = hObject; guidata(hObject, handles);
% --- Outputs from this function are returned to the command line.
function varargout = delsig2_design_OutputFcn(hObject, eventdata, handles) varargout{1} = handles.output;
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
% --- Executes during object creation, after setting all properties.
function edit_dcgain1_CreateFcn(hObject, eventdata, handles) if ispc set(hObject,’BackgroundColor’,’white’); else set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function edit_R1_CreateFcn(hObject, eventdata, handles) if ispc set(hObject,’BackgroundColor’,’white’); else set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function slider_R1_CreateFcn(hObject, eventdata, handles) usewhitebg = 1; if usewhitebg set(hObject,’BackgroundColor’,[.9 .9 .9]); else set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function edit_C1_CreateFcn(hObject, eventdata, handles) if ispc else set(hObject,’BackgroundColor’,’white’); set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function slider_C1_CreateFcn(hObject, eventdata, handles)

B.1. MATLAB Functions usewhitebg = 1; if usewhitebg else set(hObject,’BackgroundColor’,[.9 .9 .9]); set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function edit_R2_CreateFcn(hObject, eventdata, handles) if ispc set(hObject,’BackgroundColor’,’white’); else set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function slider_R2_CreateFcn(hObject, eventdata, handles) usewhitebg = 1; if usewhitebg else set(hObject,’BackgroundColor’,[.9 .9 .9]); set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function edit_C2_CreateFcn(hObject, eventdata, handles) if ispc set(hObject,’BackgroundColor’,’white’); else set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function slider_C2_CreateFcn(hObject, eventdata, handles) usewhitebg = 1; if usewhitebg else set(hObject,’BackgroundColor’,[.9 .9 .9]); set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function edit_dcgain2_CreateFcn(hObject, eventdata, handles) if ispc set(hObject,’BackgroundColor’,’white’); else set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function edit_clkfreq_CreateFcn(hObject, eventdata, handles) if ispc
105

106 Appendix B. A GUI for ∆Σ Modulator Design else set(hObject,’BackgroundColor’,’white’); set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function edit_qdelay_CreateFcn(hObject, eventdata, handles) if ispc set(hObject,’BackgroundColor’,’white’); else set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function edit_ugb1_CreateFcn(hObject, eventdata, handles) if ispc set(hObject,’BackgroundColor’,’white’); else set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function edit_ugb2_CreateFcn(hObject, eventdata, handles) if ispc set(hObject,’BackgroundColor’,’white’); else set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function edit_Rz2_CreateFcn(hObject, eventdata, handles) if ispc set(hObject,’BackgroundColor’,’white’); else set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
% --- Executes during object creation, after setting all properties.
function edit_Rz1_CreateFcn(hObject, eventdata, handles) if ispc set(hObject,’BackgroundColor’,’white’); else set(hObject,’BackgroundColor’,get(0,’defaultUicontrolBackgroundColor’)); end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_dcgain1_Callback(hObject, eventdata, handles) dcgain_string = get(hObject, ’String’); dcgain = str2num(dcgain_string);

B.1. MATLAB Functions 107 if ((dcgain >= 0) & (dcgain <= 100)) dcgain = round(dcgain); dcgain_string = sprintf(’%g’, dcgain); set(hObject, ’String’, dcgain_string); else dcgain = 100; dcgain_string = sprintf(’%g’, dcgain); set(hObject, ’String’, dcgain_string); end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_dcgain2_Callback(hObject, eventdata, handles) dcgain_string = get(hObject, ’String’); dcgain = str2num(dcgain_string); if ((dcgain >= 0) & (dcgain <= 100)) dcgain = round(dcgain); dcgain_string = sprintf(’%g’, dcgain); set(hObject, ’String’, dcgain_string); else dcgain = 100; dcgain_string = sprintf(’%g’, dcgain); set(hObject, ’String’, dcgain_string); end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_ugb1_Callback(hObject, eventdata, handles) ugb_string = get(hObject, ’String’); ugb = str2num(ugb_string); if ((ugb >= 0) & (ugb <= 300)) ugb = round(ugb*10) / 10; ugb_string = sprintf(’%0.1f’, ugb); else set(hObject, ’String’, ugb_string); ugb = 100; ugb_string = sprintf(’%0.1f’, ugb); set(hObject, ’String’, ugb_string); end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_ugb2_Callback(hObject, eventdata, handles) ugb_string = get(hObject, ’String’); ugb = str2num(ugb_string); if ((ugb >= 0) & (ugb <= 300)) ugb = round(ugb*10) / 10; ugb_string = sprintf(’%0.1f’, ugb); set(hObject, ’String’, ugb_string); else ugb = 100; ugb_string = sprintf(’%0.1f’, ugb);

108 Appendix B. A GUI for ∆Σ Modulator Design end set(hObject, ’String’, ugb_string);
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_R1_Callback(hObject, eventdata, handles)
R1_string = get(hObject, ’String’);
R1 = str2num(R1_string); if ((R1 >= 0) & (R1 <= 1000))
R1 = 5 * round(R1/5);
R1_string = sprintf(’%g’, R1); set(hObject, ’String’, R1_string); set(handles.slider_R1, ’Value’, R1/1000); else
R1 = get(handles.slider_R1, ’Value’) * 1000;
R1 = 5 * round(R1/5);
R1_string = sprintf(’%g’, R1); set(hObject, ’String’, R1_string); set(handles.slider_R1, ’Value’, R1/1000); end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function slider_R1_Callback(hObject, eventdata, handles)
R1 = get(hObject, ’Value’) * 1000;
R1 = 5 * round(R1/5);
R1_string = sprintf(’%g’, R1); set(handles.edit_R1, ’String’, R1_string); set(hObject, ’Value’, R1/1000);
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_Rz1_Callback(hObject, eventdata, handles)
Rz1_string = get(hObject, ’String’);
Rz1 = str2num(Rz1_string); if ((Rz1 >= 0) & (Rz1 <= 1000))
Rz1 = 5 * round(Rz1/5);
Rz1_string = sprintf(’%g’, Rz1); set(hObject, ’String’, Rz1_string); else
Rz1 = 0;
Rz1_string = sprintf(’%g’, Rz1); set(hObject, ’String’, Rz1_string); end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_C1_Callback(hObject, eventdata, handles)
C1_string = get(hObject, ’String’);
C1 = str2num(C1_string); if ((C1 >= 0) & (C1 <= 5))
C1 = round(C1*20) / 20;

B.1. MATLAB Functions 109
C1_string = sprintf(’%0.2f’, C1); set(hObject, ’String’, C1_string); else set(handles.slider_C1, ’Value’, C1/5);
C1 = get(handles.slider_C1, ’Value’) * 5;
C1 = round(C1*20) / 20;
C1_string = sprintf(’%0.2f’, C1); set(hObject, ’String’, C1_string); set(handles.slider_C1, ’Value’, C1/5); end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function slider_C1_Callback(hObject, eventdata, handles)
C1 = get(hObject, ’Value’) * 5;
C1 = round(C1*20) / 20;
C1_string = sprintf(’%0.2f’, C1); set(handles.edit_C1, ’String’, C1_string); set(hObject, ’Value’, C1/5);
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_R2_Callback(hObject, eventdata, handles)
R2_string = get(hObject, ’String’);
R2 = str2num(R2_string); if ((R2 >= 0) & (R2 <= 1000))
R2 = 5 * round(R2/5);
R2_string = sprintf(’%g’, R2); set(hObject, ’String’, R2_string); set(handles.slider_R2, ’Value’, R2/1000); else
R2 = get(handles.slider_R2, ’Value’) * 1000;
R2 = 5 * round(R2/5);
R2_string = sprintf(’%g’, R2); set(hObject, ’String’, R2_string); set(handles.slider_R2, ’Value’, R2/1000); end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function slider_R2_Callback(hObject, eventdata, handles)
R2 = get(hObject, ’Value’) * 1000;
R2 = 5 * round(R2/5);
R2_string = sprintf(’%g’, R2); set(handles.edit_R2, ’String’, R2_string); set(hObject, ’Value’, R2/1000);
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_Rz2_Callback(hObject, eventdata, handles)
Rz2_string = get(hObject, ’String’);
Rz2 = str2num(Rz2_string);

110 Appendix B. A GUI for ∆Σ Modulator Design if ((Rz2 >= 0) & (Rz2 <= 1000))
Rz2 = 5 * round(Rz2/5);
Rz2_string = sprintf(’%g’, Rz2); set(hObject, ’String’, Rz2_string); else
Rz2 = 0;
Rz2_string = sprintf(’%g’, Rz2); set(hObject, ’String’, Rz2_string); end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_C2_Callback(hObject, eventdata, handles)
C2_string = get(hObject, ’String’);
C2 = str2num(C2_string); if ((C2 >= 0) & (C2 <= 5))
C2 = round(C2*20) / 20; else
C2_string = sprintf(’%0.2f’, C2); set(hObject, ’String’, C2_string); set(handles.slider_C2, ’Value’, C2/5);
C2 = get(handles.slider_C2, ’Value’) * 5;
C2 = round(C2*20) / 20;
C2_string = sprintf(’%0.2f’, C2); set(hObject, ’String’, C2_string); set(handles.slider_C2, ’Value’, C2/5); end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function slider_C2_Callback(hObject, eventdata, handles)
C2 = get(hObject, ’Value’) * 5;
C2 = round(C2*20) / 20;
C2_string = sprintf(’%0.2f’, C2); set(handles.edit_C2, ’String’, C2_string); set(hObject, ’Value’, C2/5);
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_clkfreq_Callback(hObject, eventdata, handles) fck_string = get(hObject, ’String’); fck = str2num(fck_string); if ((fck >= 0) & (fck <= 50)) fck = round(fck*1000) / 1000; fck_string = sprintf(’%0.3f’, fck); else set(hObject, ’String’, fck_string); fck = 20; fck_string = sprintf(’%0.3f’, fck); set(hObject, ’String’, fck_string); end

B.1. MATLAB Functions 111
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function edit_qdelay_Callback(hObject, eventdata, handles) qdel_string = get(hObject, ’String’); qdel = str2num(qdel_string); if ((qdel >= 0) & (qdel <= 100)) qdel = round(qdel); qdel_string = sprintf(’%g’, qdel); else set(hObject, ’String’, qdel_string); qdel = 50; qdel_string = sprintf(’%g’, qdel); set(hObject, ’String’, qdel_string); end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% function calculate_Callback(hObject, eventdata, handles)
% get the values from GUI dcgain1_str = get(handles.edit_dcgain1, ’String’); dcgain1_db = str2num(dcgain1_str); ugb1_str = get(handles.edit_ugb1, ’String’); ugb1
R1
R1
C1
= str2num(ugb1_str) * 1e9; % GHz --> Hz
= get(handles.slider_R1, ’Value’) * 1000;
= 5 * round(R1/5);
= get(handles.slider_C1, ’Value’) * 5;
C1
Rz1_str
Rz1
= round(C1*20) / 20e12; % pF --> F
= get(handles.edit_Rz1, ’String’);
= str2num(Rz1_str);
R2
R2
C2
C2 dcgain2_str = get(handles.edit_dcgain2, ’String’); dcgain2_db = str2num(dcgain2_str); ugb2_str ugb2
= get(handles.edit_ugb2, ’String’);
= str2num(ugb2_str) * 1e9; % GHz --> Hz
Rz2_str
Rz2
= get(handles.slider_R2, ’Value’) * 1000;
= 5 * round(R2/5);
= get(handles.slider_C2, ’Value’) * 5;
= round(C2*20) / 20e12; % pF --> F
= get(handles.edit_Rz2, ’String’);
= str2num(Rz2_str); clkfreq_str = get(handles.edit_clkfreq, ’String’); clkfreq = str2num(clkfreq_str) * 1e9; % GHz --> Hz qdelay_str = get(handles.edit_qdelay, ’String’); qdelay = str2num(qdelay_str) / 100; % percent --> number
% create frequency vectors fexp = 3:0.01:11; f = 10 .^ fexp; w = 2*pi * f; s = j*w;

112 Appendix B. A GUI for ∆Σ Modulator Design
% calculate the integrator transfer functions dc_gain1 = 10^(dcgain1_db/20); dc_gain2 = 10^(dcgain2_db/20); w_pole1 = ugb1*2*pi / dc_gain1; w_pole2 = ugb2*2*pi / dc_gain2;
A1 = dc_gain1 ./ (1 + s./w_pole1); % op amp 1 open loop gain
A2 = dc_gain2 ./ (1 + s./w_pole2); % op amp 2 open loop gain
H1 = A1 .* (1 + s*C1*Rz1) ./ (1 + (s*C1).*(Rz1 + (1+A1)*R1));
H2 = A2 .* (1 + s*C2*Rz2) ./ (1 + (s*C2).*(Rz2 + (1+A2)*R2));
% calculate the quantizer delay transfer function
Ts = 1 / clkfreq;
Tq = Ts * qdelay;
Hq = exp(-s*Tq);
% calculate the closed loop STF and NTF
STF = (H1 .* H2) ./ (1 + Hq.*H2 + Hq.*H1.*H2);
NTF = 1 ./ (1 + Hq.*H2 + Hq.*H1.*H2);
% calculate the loop transfer function
LTF = -Hq .* H2 .* (1 + H1);
LG = db(LTF);
PM = unwrap(angle(LTF) * (180/pi));
% find phase margin below_zero_indices = find(LG <= 0); if (length(below_zero_indices) > 0) zero_index = below_zero_indices(1); else zero_index = 2; end phase_margin = PM(zero_index);
% find gain margin at the valley minimum_indices = find(PM == min(PM(1:zero_index))); minimum_index = minimum_indices(length(minimum_indices)); gain_margin = LG(minimum_index);
% find gain margin at high frequency minimum_indices = find(PM(zero_index:length(PM)) < 0); if (length(minimum_indices) > 0) minimum_index2 = minimum_indices(1) + zero_index - 1; else minimum_index2 = 3; end gain_margin2 = LG(minimum_index2);
% creat sub vectors of STF and NTF of freq above Nyquist above_nyquist_indices = find(f > (clkfreq/2)); high_f = f(above_nyquist_indices);

B.1. MATLAB Functions 113 high_STF = STF(above_nyquist_indices); high_NTF = NTF(above_nyquist_indices);
% plot all graphs h1 = handles.axes1; h2 = handles.axes2; h3 = handles.axes3; axes(h1) hold off semilogx(f, LG, ’-b’, ’LineWidth’, 2); ylabel(’loop gain (dB)’) grid on hold on semilogx(f(minimum_index), LG(minimum_index), ’om’, ’MarkerSize’, 8, ’MarkerFaceColor’, ’magenta’); semilogx(f(minimum_index2), LG(minimum_index2), ’om’, ’MarkerSize’, 8, ’MarkerFaceColor’, ’magenta’); semilogx(f(zero_index), LG(zero_index), ’ok’, ’MarkerSize’, 8, ’MarkerFaceColor’, ’black’); textGM = sprintf(’%g dB’, round(gain_margin)); textGM2 = sprintf(’%g dB’, round(gain_margin2)); text(f(minimum_index), LG(minimum_index) + 15, textGM, ’FontName’, ’Arial’, ’FontSize’, 14); text(f(minimum_index2), LG(minimum_index2) + 15, textGM2, ’FontName’, ’Arial’, ’FontSize’, 14); set(get(gca,’YLabel’), ’FontName’, ’Arial’) set(get(gca,’YLabel’), ’FontSize’, 12) set(get(gca,’YLabel’), ’FontWeight’, ’Bold’) axes(h2) hold off semilogx(f, PM, ’-r’, ’LineWidth’, 2); ylabel(’phase (deg)’) grid on hold on semilogx(f(minimum_index), PM(minimum_index), ’om’, ’MarkerSize’, 8, ’MarkerFaceColor’, ’magenta’); semilogx(f(minimum_index2), PM(minimum_index2), ’om’, ’MarkerSize’, 8, ’MarkerFaceColor’, ’magenta’); semilogx(f(zero_index), PM(zero_index), ’ok’, ’MarkerSize’, 8, ’MarkerFaceColor’, ’black’); textPM = sprintf(’%g^O’, round(phase_margin)); text(f(zero_index), PM(zero_index) - 15, textPM, ’FontName’, ’Arial’, ’FontSize’, 14); set(get(gca,’YLabel’), ’FontName’, ’Arial’) set(get(gca,’YLabel’), ’FontSize’, 12) set(get(gca,’YLabel’), ’FontWeight’, ’Bold’) axes(h3) hold off semilogx(f, db(STF), ’-m’, ’LineWidth’, 2); ylabel(’STF,NTF (dB)’) xlabel(’frequency (Hz)’) grid on hold on semilogx(f, db(NTF), ’-k’, ’LineWidth’, 2); semilogx(high_f, db(high_STF), ’-y’, ’LineWidth’, 1.5); semilogx(high_f, db(high_NTF), ’-y’, ’LineWidth’, 1.5); set(get(gca,’YLabel’), ’FontName’, ’Arial’) set(get(gca,’YLabel’), ’FontSize’, 12)

114 set(get(gca,’YLabel’), ’FontWeight’, ’Bold’) set(get(gca,’XLabel’), ’FontName’, ’Arial’) set(get(gca,’XLabel’), ’FontSize’, 12) set(get(gca,’XLabel’), ’FontWeight’, ’Bold’)
delsig2 design.fig
Appendix B. A GUI for ∆Σ Modulator Design
Figure B.1: MATLAB figure of delsig2 design

ריצקת IV
גישהו , טאוו 1.9
ךרצ , ץרה הגיג 10 לש רדתב םגד ריממה .
דיפסופ םוידניא עצמ
.
ץרה הגמ 312.5
לשטרסבחוררובעםיטיב 7 לשהיצולוזר
םיאשונהלכלעהמדקהובו , אובמהווהמןו שארהקרפה : םיקרפהששהדובעב
הקינכטב קסועינשהקרפה .
רקחמהתורטמלערבסהו , תורפסרקס , רקחמבםינודנה
לעב יגולנאל ילטיגיד ריממב קסוע ישילשה קרפה .
הוושמ לש תושיגרה רופישל
תמגדומש , תרשירבגמלרבגהתפסוהלהטיש הנ ודניעיברהקרפב .
ההובגתויראניל
יגולנאהריממב ןדישימחהקרפה .
תירלופיבהיגולונכטבןהו
CMOS
תייגולו נכטבןה
לגעמהןויפאבהלכו , םילגעמהשומימךרד , תכרעמהילוקישבלחה
–
ולוכילטיגידל
.
רקחמהתואצותתאםכסמש , ישישהקרפהםתוחהדובעהתא .
ויעוציבבו
רוצייךילהתתא ץרמנרוציקברקוס דחאה : הדובעהףוסבםיעיפומםיחפסנינש
תינכות גיצמ ינשה חפסנה .
ןוינכטב תמוצה יברועמ םיירלופיב ה םירוטסיזנרטה
אתלדילטיגידליגולנאריממלשיתכרעמןכתל , יפרגשמתשמקשממםע MATLAB
.
יראניללדומיפלע , ףיצרןמזבינשרדסמ אמגיס
, ה קינורטקלאורקימל רקחמ זכרמבו למשח תסדנהל הטלוקפב השענ רקחמה
הקיסיפל ןוכמ
–
רפוהנוארפ םע הלועפ ףותישב , לארשיל יגולונכט ןוכמ
–
ןוינכטה
.
הינמרג , גרוביירפ , ( IAF ) קצומבצמלשתישומיש

III ריצקת
לעבו םיטיב 2 לש היצולוזר םע יגולנאל ילטיגיד ריממ שמומ רקחמה ךשמהב
לעתמוצ יברועמםיירלופיב םירוטסיזנרט לשהיג ולונכטב אוהםג , ההובגתויראניל
השענ .
הליגר םרז תטסה תרוטקטיכרא לע ססובמ לגעמה .
דיפסופ םוידניא עצמ
תפסוהו יטטס בוברע
–
םילגעמ תכירע תוקינכטבו דוקסק לש הנבמב שומיש
הקידבב עיגה יגולנאל ילטיגיד ריממה .
תויראנילה רופיש ךרוצל
–
המד ירוטסיזנרט
תוחפהטיבהלשתויפלא 5.5
לש ת ילארגטניאותילאיצנרפידתויראנילרסוח לתיטטס
יתוכיאןפואבוארהתוימנידתודידמ .
םיטיב 9.2
לשהיצולוזרלהלוקשש , יתועמשמ
יסופיט סמוע םע תויצלומיס וליאו , ץרה הגיג 6 לש המיגד רדתב הניקת תוגהנתה
רדתבהלועפלוידריהמתו סנכתהןמזשילגעמל ש תוארמבבשלעבלושמהלגעמל
.
ץרה הגיג 20 לש
רבגה תאיגשל , תקיודמ תוסנכתהל חתפמ רטמרפ אוה תרש ירבגמ לש רבגה
קשממםע , רבגהתפסותםעםירבגמינש .
בושמירבגמלשההובגתויראניללוהכומנ
CMOS תייגולונכטב ןנכות ןושארה רבגמה .
וז הדובעב ורקחנ , אלמ ילאיצנרפיד
ןנכות , רבגה תפסוהל הקינכט התוא לע ססובמש , ינשה רבגמה ולי או , תילטיגיד
הטישה .
דיפסופםוידניאעצמלע תמוצ יברועמ םיירלופיבםירוטסיזנרטתייגולונכטב
ךא , איהשהמרלכלרבגההתאלידגהלהלוכיתיביטקא ( bootstrap
) חתמתביקעלש
ליבשב .
רוצייה ךילה תב תויטס בקע םיביכרה ירטמרפב םייונישל דואמ השיגר איה
תויטסלשימצעןוקיתללגעמ תתםירבגמהמדחאלכלףסוותה , וזהיעבלערבגתהל
וד רבגמ לש היצלומיס ב .
ךילהתב םייונישה לכב הובג רתונ רבגההש ךכ , רוצייב
בחורו לביצד 109 לש רבגה םגד ו ה רטמוננ 45 לש יטרדנטס
CMOS
ךילהתב יתגרד
ראשנ ךילהתב תויטס ןוקיתל לגעמל תודות .
ץרה הגמ 500 לש הדיחי רבגהב טרס
לע ססובמה רבגמ לש תויצלומיס .
ךילהתה ייוניש לכב לביצד 48 לעמ רבגהה
82 לשרבגהתוארמדיפסופםוידניאעצמלעתמוצ יברועמםיירלופיבםירוטסיזנרט
ןוקיתה לגעמל תודוה , ןאכ םג .
ץרה הגיג 62 לש הדיחי רבגה ב טרס בחורו לביצד
.
ךילהתהייונישלכבלביצד 64 לעמרתונרב גהה
ריממלשןכתךרוצלל " נהןיינבהינבאבשומישהשענרקחמהלשינשהבלשב
תואצותרואל .
ףיצרןמזבךומנספריבעמ , ינשרדסמ אמגיס אתלדילטיגידליגולנא
.
תונושה ןיינבה ינבאב םישקבתמה םייונישה וסנכוה רקחמה לש ןושארה בלשה
רשאכ , ( flash
) קזבהגוסמילטיגידליגולנאריממ שומימךרוצל שומישהשע נהוושמב
רצייגולנאלילטיגיד ה ריממה .
םיטיב 2 לשריממורציםידגנתומלוסוםיוושמהשולש
, גוחהיננסמלשםבילתאםיווהמתרשירבגמ .
quantizer התא קזבה הריממםעדחי
לגעמהלשהלודגהותובכרומבקע רבגהתפסוהלהקינכטבשומישהשענאליכםא
לע תמוצ יברועמ םיירלופיב םירוטסיזנרט תייגולונכטב רצוי ולוכ ריממה םג .
ולוכ

ריצקת II
םיינש , ל " נה םיריממה ןיבמ .
ספה לש יזכרמה רדתה תא םהב תונשל ןתינ רמולכ
.
רתויואץרה הגיג 10 לשרדתבםוגדלוננכות
, אמגיס אתלדהריממבביכרמהווהמש , ימינפהיגולנאל ילטיגידריממהשןוויכ
תויראנילהרסוחושערה , אמגיס אתלדהתסינכל תורישיולשאצומהתואתאןיזמ
אתלדה הנבמ לש ( noise shaping
) שערה בוציע ידי לע םינתשמ םניא רצוי אוהש
קיפ סמ תויהל הכירצ ימינפה יגולנאל ילטיגיד ריממה לש תויראנילה ןכל .
אמגיס
םיצורהילאההובגההיצולוזרבבשחתהב , יפוסהתואהתאתוועתאלשךכ , ההובג
שממלןתינאלתמוצ יברועמםיירלופיבםירוטסיזנרטלשתויגולונכטבוליאוה .
עיגהל
לכ , ידמתוכבוסמהלאהתוטישהשןוויכ , תויראנילרסוחןוקיתלשתוילטיגידתוטיש
, תמוצ יברועמ םיירלופיב םירוטסיזנרט לע םיססובמש , אמגיס אתלדה יר י ממ
–
דחאטיבלשתימינפהיצולוזרבםישמתשמ , הלאתורושתביתכתעבונלםיעודיה
הדובעב .
הרדגהיפלןיטולחליראנילאוהדחאטיבלשיגולנאלילטיגידריממשללגב
םירוטסיזנרט לע ססובמה , אמגיס אתלד ילטיגידל יגולנא ריממ םיגיצמ ונא וז
.
םיטיב 2 לשתימינפהיצולוזרלעב , תמוצ יברועמםיי רלופיב
: ריממה לש ןיינבה ינבאב דקמתמ ןושארה בלשה .
םיבלש ינשב השענ רקחמה
רבגה תפסות םע תרש רבגמ , תרפושמ תושיגר לעב ( comparator ) הוושמ וב ורקחנ
שומישהשענרקחמהלשינשהבלשב .
ההובגתויראניללעביגולנאלילטיגידריממו
אמגיס אתלד יגולנאל ילטיגיד ריממ תמגדהל , יתכרעמ ןכת בולישב , ןיינבה ינבאב
הזבלשב .
ץרה הגיג 10 לשהמיגדרדתלעב , ףיצרןמזבךומנספריבעמ , ינשרדסמ
תא ןלהל טרפנ .
םירחא ןכת ירטמרפו תוביציה , םיעוציבה , הרוטקטיכראה ורקחנ
.
םינושה רקחמהיבלש
.
ילטיגידל יגולנא ריממ לש ןכתב יטירק רטמרפ הווהמ םיוושמה לש תושיגרה
( master-slave
) דבע ןודאגוסמםיוושמלשתושיגרהרופישלהטישתעצומוזהדובעב
ןמז תא םירצקמ לעונה גוזב ןווינ ידגנ .( ECL ) רטימא תדמוצמ הקיגול תייגלופוטב
ינש .
ומצע הליענה ךילהתל רתוי ךורא ןמז ם יריתומו , םירוטסיזנרטה לש הניעטה
רופישה אלל המוד הוושמו , עצומה רופישה םע הוושמ : הז דצל הז ורצוי םיוושמ
םוידניא עצמ לע תמוצ יברועמ םירוטסיזנרט תייגולונכטב ורצוי םיוושמה .
ל " נה
, ןווינה ידגנ םע , רפושמה הוושמה .
ץרה הגיג 20 לש המיגד רדתב וקדבנו , דיפסופ
.
ןווינהידגנאללהוושמהלשתושיגרלהאוושהב ( 1.7
יפ ) רתויהבוטתושיגרלעי ג ה
המיגד רדתב איש תושיגר איהש , טלווילימ 10 לש תושיגר גישה רפושמה הוושמה
.
ץרה הגיג 20 לש

תונו רחאה םינשב ושענ םיריהמ אמגיס אתלד י לטיגידל יגולנא
לשםתוטשפ .
תומדקתממ " כמתוכרעמבותרושקתתוכרעמבםיצופנ
םתוא שממלו םתוא ןנכתל תרשפאמ אמגיס אתלד יריממ
תמוצ יברועמ םיירלופיב םירוטסיזנרט ןוגכ , תוריהמ תויגולונכטב
הלא תויגולונכטבש תורמל , III-V גוסמ הצחמל םיכילוממ וא SiGe רמוחהמ ( HBT )
, ןכ לע רתי .
yield ילוקישמ לגעמב יברמה םירוטסיזנרטה רפסמ לע הלבגמ תמייק
, ספהלשיזכרמהרדתהתאתונשלתורשפאםע , ספיריבעמםיריממשממלתלוכיה
תרצ תרושקת לש םימושיי רובע םייביטקרטאל אמגיס אתלדה יריממ תא תכפוה
.
ףיצ ר ןמז יריממו דידב ןמז יריממ : אמגיס אתלד יריממ לש םיגוס ינש םימייק .
טרס
החוד ןנסמב שומיש םישרוד םניא ףיצר ןמז יריממ , דידב ןמז יריממל האוושהב
לשםיימינפהגוחהיננסמידילעעצבתמןוניסהוליאוה , ( anti-aliasing filter ) לופכש
ירדתבדובעלןתינןכלו , גותימבשומישהשענאלףיצרןמזיריממב , ןכומכ .
ריממה
.
דידב ןמז יריממל האוושהב , רוטסיזנרטה לש ןו עטקה רדתל רתוי םיבורק המיגד
רבעמ : jitter מםרגנהשערמםיימעפםילבוסףיצרןמזב אמגיס אתלדיריממ , ךדיאמ
שעררצונףיצרןמזיריממב , ריממלכבםייקש , המיגדהןועשב jitter מםרגנהשערל
.
ימינפה (
DAC
) יגולנאלילטיגידהריממב jitter
ידילע
םירמוחהתכרעמלעםיססובמה , ( HBTs ) תמוצ יברועמםיירלופיב םירוטסיזנרט
; ץרה הגיג 500 לרבעמ , םיהובג ןועטיקירדתבםינייטצמ , ( InP ) דיפסופםוידניאלש
.
ץרה הגיג 300 ללעמםירדתלםיעיגמהצחמל םייתיישעתוםייתיישעתםירוטסיזנרט
, דואמ םיריהמ אמגיס אתלד ילטיגידל יגולנא יריממ המכו המכ ומגדוה , האצותכ
, םירוטסיזנרטה רפסמ לע הלבגמה ללגב .
םיצרה הגיג רפסמ לש רדתב םימגודש
םיללוכומגדוהשםיריממה .
ףיצרןמזיריממםהל " נהםיריממהלכ , ליעלהרכזוהש
לעםיססובמרשא , ( bandpass ) ספיריבעמםיריממןהו ( lowpass ) ךומנספיריממןה
ריממ ומגדוהןכומכ .
המאתהב , יעיבררדסמוינשרד סמבושמלשיסיסבההנבמה
, ןונווכלםינתינהספיריבעמםיריממו , ההובגתויכוביסלעב , ירישערדסמספריבעמ

למשחתסדנהלהטלוקפב לאיומיקימר " דו רטירןד ' פורפ תייחנהב השענרקחמה
הקיסיפלןוכמ
–
רפוהנוארפםעהלועפףותישב , הקינורטקלאורקימלרקחמזכרמבו
הינמרג , גרוביירפ , ( IAF ) קצומבצמלשתישומיש
לארשיליגולונכטןוכמ
–
ןוינכטל הנותניתדות
יתומלתשהבהבידנהתיפסכההכימתהלע
היה ןתינ אל םהידעלבשו , רקחמה עוציבל ועייסש םיברה םישנאל תודוהל ינוצרב
: לעופ ה ל א ואיצוהל
, הקינורטקלאורקימל רקחמ זכרמלו למשח תסדנהל הטלוקפל , ןוינכטל הדות .
1
תויגולונכטהו דויצה בטימ תא יתושרל ודימעהשו , רקחמה השענ םתרגסמבש
.
רקחמהךרוצל
, הכימתה לעו הרוסמה היחנהה לע לאיומ יקימ ר " דלו רטיר ןד ' פורפל הדות .
2
.
ךרדהךרואלכלדודיעהוהרזעה
, ןהכןועמש , בולירבגידקרא : רטירןד ' פורפלשרקחמהתצובקליירבחלהדות .
5
ןר , גרבנירגיבוק , ןוליםליע , לעשמהנולא , גייסיבא , ךולבילא , סאילא ןהכןורוד
.
זפבואלוסיאלשתונטקתורזעיפ לאלע , הלטסימדודוןיקלוססכלא , יולה
ותרגסמבש , טקייורפה ןומימ לע לארשי תנידמ לש ןוחטיבה דרשמל הדות .
6
.
תבחרנההכימתהלעדלפנזורדודר " דלהנותנתדחוימהדות .
רקחמהעצבתה
ףותישלע , הינמרג , גרוביירפברפוהנוארפלש IAF רקחמהןוכממייתימעלהדות .
5
לאכימר " ד , רכבמארבילואר " ד : לעופהלאואיצוה לרשפיאשרקחמבהלועפה
ר " ד , דאירדדישרר " ד , ןוקאמסיולאטרבורר " ד , ספלקרמגניא ' פורפ , גווטכלש
.
רכורבדרגדליה ' בגוינטובונשירלואר " ד , גייוצנזורףזוי
לע , ךיירטסו ךלמילאו הרש , ימחו יתומחלו , סוארק עשוהיו האל , יירוהל הדות .
7
.
ךרדהךרואלכלםיינויח הכהעויסהו הרזעה , הכימתה
תונלבסהלע
–
לבויוהעונ , ןתמ
–
יידלילו , המענ , יתשאלתדחוימהדות , ףוסבל .
8
תא תושעל שפנה תוחוכ תא יל הנתנש , האלפנ החפשמ םתויה לעו , הנבההו
.
ושיגהלורקחמה