Low-voltage InGaZnO thin-film transistors with Al2O3 gate insulator grown
by atomic layer deposition
J. B. Kim, C. Fuentes-Hernandez, W. J. Potscavage, X.-H. Zhang, and B. Kippelen
Citation: Appl. Phys. Lett. 94, 142107 (2009); doi: 10.1063/1.3118575
View online: http://dx.doi.org/10.1063/1.3118575
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APPLIED PHYSICS LETTERS 94, 142107 共2009兲
Low-voltage InGaZnO thin-film transistors with Al2O3 gate insulator grown
by atomic layer deposition
J. B. Kim, C. Fuentes-Hernandez, W. J. Potscavage, Jr., X.-H. Zhang, and B. Kippelena兲
Center for Organic Photonics and Electronics (COPE), School of Electrical and Computer
Engineering, Georgia Institute of Technology, Atlanta, Georgia 30332, USA
共Received 5 March 2009; accepted 24 March 2009; published online 9 April 2009兲
We report on low-voltage, high-performance amorphous indium gallium zinc oxide n-channel
thin-film transistors fabricated using 100-nm-thick Al2O3 grown by atomic layer deposition as the
gate dielectric layer. The Al2O3 gate dielectric shows very small current densities and has a
capacitance density of 81⫾ 1 nF/ cm2. Due to a very small contact resistance, transistors with
channel lengths ranging from 100 ␮m down to 5 ␮m yield a channel-independent, field-effect
mobility of 8 ⫾ 1 cm2 / V s, subthreshold slopes of 0.1⫾ 0.01 V / decade, low threshold voltages of
0.4⫾ 0.1 V, and high on-off current ratios up to 6 ⫻ 107 共W / L = 400/ 5 ␮m兲 at 5 V. © 2009
American Institute of Physics. 关DOI: 10.1063/1.3118575兴
Thin-film transistors 共TFTs兲 capable of low-voltage and
high-frequency operation will be required to reduce the
power consumption of next generation electronic devices
driven by microelectronic components such as inverters, ring
oscillators, and backplane circuits for mobile displays. To
produce high-performance TFTs, transparent oxide semiconductors are becoming an attractive alternative to hydrogenated amorphous silicon 共a-Si: H兲- and organic-based materials because of their high electron mobilities and low
processing temperatures, making them compatible with flexible substrates and opening the potential for low production
costs.1,2 However, oxide-based TFTs typically require large
operating voltages to achieve high mobilities and high on-off
current ratios.
In addition to using high-mobility semiconductors, operating voltages can be reduced by developing gate dielectric
materials capable of large capacitance densities with low
leakage currents that have good compatibility for the growth
of the semiconductor channel, leading to low trap densities at
the semiconductor-gate dielectric interface. Using 170-nmthick amorphous Ba0.5Sr0.5TiO3 共a-BST兲 共␧r = 28兲 as the gate
dielectric, we recently demonstrated low-voltage, highperformance amorphous indium gallium zinc oxide
共a-IGZO兲 TFTs with electron mobilities of 10 cm2 / V s,
threshold voltages 共VT兲 of 0.5 V, and very small subthreshold
slopes 共S兲 of 0.11 V/decade.3 However, the small band gap
共3.3 eV兲 and relatively large electron affinity 共4 eV兲 of
a-BST forces careful control over the TFTs geometry to reduce the leakage currents and increase its operational range.
The use of larger band gap dielectrics is then desirable to
increase the energy band offsets with respect to a-IGZO.
Here, we report on an alternative approach to increase
the capacitance density of the gate dielectric by using a 100nm-thick Al2O3 layer deposited by atomic layer deposition
共ALD兲. With a high dielectric constant of 9 and a large band
gap of 8 eV, Al2O3 is a good candidate to produce gate
dielectrics with low leakage and high capacitance density.
Furthermore, ALD is a well-known deposition process that
yields highly conformal, defect-free dielectric layers at relaa兲
Author to whom correspondence should be addressed. Electronic mail:
kippelen@ece.gatech.edu.
0003-6951/2009/94共14兲/142107/3/$25.00
tively low temperatures.4,5 Dielectric films grown by ALD
have a high resistivity and good barrier properties and have
been used to produce high-performance polycrystalline
ZnO-TFTs.6,7 However, such TFTs usually have large VT and
S, forcing them to operate at relatively high voltages. In contrast, the Al2O3共ALD兲 / a-IGZO TFTs reported here combine
a high field-effect mobility of ␮FE = 8 ⫾ 1 cm2 / V s, which is
channel independent down to 5 ␮m channel lengths, with a
low VT of 0.4⫾ 0.1 V, an on-off current ratio up to Ion-off
= 6 ⫻ 107, and an excellent S = 0.1⫾ 0.01 V / decade. The
Al2O3 gate dielectric grown by ALD shows very low leakage
current densities below 10−7 A / cm2 up to fields of 3.5
MV/cm with a field-independent capacitance density of Ci
= 81⫾ 1 nF/ cm2.
A Savannah100 ALD system from Cambridge Nanotech
Inc. was used to deposit Al2O3 dielectric films. The Al2O3
films were deposited at 80 ° C using alternating exposures of
trimethyl aluminum 关Al共CH3兲3兴 and H2O vapor at a deposition rate of approximately 0.1 nm per cycle. Each deposition
cycle 共1 ML兲 lasted 24 s, yielding a total deposition time of
around 6 h for 1000 cycles. Details about the Al2O3 films
grown by ALD are described elsewhere.4 The dielectric
properties of Al2O3 films sandwiched between Ti共6 nm兲/
Au共120 nm兲 and Ti共6 nm兲/Au共50 nm兲/Ti共6 nm兲 on glass substrates were characterized using parallel plate capacitors of
various areas ranging from 1.1⫻ 10−3 to 4.2⫻ 10−3 cm2.
Figure 1 shows a leakage current reaching a value of
10−7 A / cm2 at 3.5 MV/cm and below the noise level for
smaller electric fields. Similar values were also measured in
capacitors with different thicknesses. Using an Agilent
4284A precision LCR meter, Ci = 81⫾ 1 nF/ cm2 was measured, corresponding to a dielectric constant of ␧r = 9. As
shown in Fig. 1, variations smaller than 2% were observed
for frequencies ranging from 1 to 100 kHz and bias voltages
between ⫺30 and +35 V. Therefore, the Al2O3 layers deposited by ALD combine a small leakage current with a large
dielectric constant that is independent of voltage and frequency, which is indicative of a low defect concentration.8
The TFTs were fabricated with a geometry incorporating
a bottom gate and top-contact source and drain electrodes.
First, a trilayer of Ti共6 nm兲/Au共50 nm兲/Ti共6 nm兲 was deposited using electron-beam 共e-beam兲 at room temperature on a
94, 142107-1
© 2009 American Institute of Physics
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142107-2
Kim et al.
Appl. Phys. Lett. 94, 142107 共2009兲
FIG. 1. 共Color online兲 Capacitance density measured on a
Au/ Ti/ Al2O3 / Ti/ Au/ Ti/Glass sample as a function of electric field at 1, 10,
and 100 kHz. Current density measured on the same sample.
glass substrate 共Corning 1737兲 and patterned by photolithography followed by a lift-off process. A 100-nm-thick Al2O3
gate dielectric layer was then deposited by ALD at 80 ° C by
using Al共CH3兲3 and H2O as the precursors. Contact holes
were formed by a lift-off process to provide access to the
gate electrode. A 40-nm-thick a-IGZO 共Ga2O3 : In2O3 : ZnO
= 1 : 1 : 2 mol %兲 active layer was then deposited by rf sputtering at room temperature using a power of 125 W, a working pressure of 5 mTorr, and an O2 / Ar 共1/10兲 atmosphere.
After deposition of the a-IGZO layer, the device was annealed at 325 ° C for 30 min in air. To define the channel, the
a-IGZO layer was patterned by a wet-etching process using
hydrochloric acid 共HCl: H2O = 1 : 100兲 diluted in de-ionized
water. Then, Ti共6 nm兲 and Au共120 nm兲 were sequentially
deposited by e-beam and patterned by a lift-off process to
form the source and drain electrodes, creating a total gate to
source/drain electrode overlap area of 4 ⫻ 10−5 cm2, assuming an overlap channel length of Lov = 5 ␮m and a channel
width of W = 400 ␮m. Several Al2O3 / a-IGZO TFTs were
fabricated using a channel width of W = 400 ␮m and channel
lengths 共L兲 of 100, 20, 10, and 5 ␮m.
The transfer and output characteristics of all
Al2O3共ALD兲 / a-IGZO TFTs were measured using an Agilent
E5272A medium-power source/monitor unit connected to a
probe station. Figure 2共a兲 shows the overlapping hysteresis
transfer characteristics measured in the linear 共VDS = 0.1 V兲
and saturation 共VDS = 5 V兲 regions in a TFT with W / L
= 400/ 100 ␮m. Figure 2共b兲 shows the same behavior in a
TFT with W / L = 400/ 5 ␮m. Consistent with capacitor measurements, the leakage currents 共not shown兲 at the operating
voltages in all TFTs remained below the noise level of 10
pA. All Al2O3共ALD兲 / a-IGZO TFTs exhibited n-channel
transistor behavior operating in the enhancement mode with
saturation mobilities of ␮SAT = 9 ⫾ 1 cm2 / V s, threshold
voltages of VT = 0.4⫾ 0.1 V, and Ion-off = 6 ⫻ 107 at 5 V
共W / L = 400/ 5 ␮m兲. A linear fit of a 共IDS兲1/2 versus VGS plot
was used to estimate ␮SAT and VT, as described in Ref. 3.
The subthreshold slope 共S兲 was estimated as the minima on a
关⳵共log IDS兲 / ⳵VGS兴−1 versus VGS graph. Figure 2共c兲 shows that
S = 0.1⫾ 0.01 V / decade in the linear region for the TFTs
shown in Figs. 2共a兲 and 2共b兲. The same S values were found
in the saturation region. The average value and the standard
deviation of S, and the other parameters presented, were calculated from measurements on 20 devices with four devices
per given channel length.
FIG. 2. 共Color online兲 Hysteresis transfer characteristics of
Al2O3共ALD兲 / a-IGZO TFTs with L = 100 ␮m and W = 400 ␮m 共a兲 or W
= 5 ␮m 共b兲; 共c兲 VGS dependence of subthreshold slope in the linear region
for TFTs with L = 5 ␮m and 100 ␮m, and W = 400 ␮m. 共d兲 Output characteristics of a W / L = 400 ␮m / 5 ␮m TFT.
The subthreshold slope can be used to estimate upper
limits to the bulk and semiconductor/gate dielectric interface
density of states 共DOS兲 by using the following equation:9
S = 共kBT/q兲ln 10关共Csg/Ci兲 + 1兴,
共1兲
where kB is the Boltzmann’s constant, T is temperature, q is
the electronic charge, Ci is the capacitance density of the
gate insulator, and Csg is the equivalent capacitance contributed by subgap states in the bulk and at the semiconductor/
dielectric interface. At 300 K, a maximum subgap DOS at
the a-IGZO/ Al2O3 interface is estimated to be 3.4
⫻ 10−11 cm−2 eV−1 corresponding to a maximum bulk DOS
of 7 ⫻ 10−16 cm−3 eV−1. Subthreshold slope values around
0.1 V/decade have also been reported in a-BST共Ci
= 145 nF/ cm2兲 / a-IGZO TFTs 共Ref. 3兲 and SiO2共Ci
= 34 nF/ cm2兲 / a-IGZO TFTs 共Ref. 9兲 having gate dielectrics
with significantly different capacitance densities and surface
properties. These results complement recent observations10
indicating that, in contrast with polycrystalline TFTs, the
physics at the surface of the semiconductor/gate dielectric
interface may not be playing a dominant role in determining
the subthreshold properties of a-IGZO-based TFTs. While
detailed studies are needed to confirm this hypothesis, the
collective evidence seems to indicate that the key to achieving very small subthreshold slopes and enabling low voltage
operation lies in finding the processing conditions for
a-IGZO that minimize the bulk subgap DOS. Figure 2共d兲
exemplifies the output characteristics measured in TFTs with
L = 5 ␮m, showing good linearity at low VDS and small effects of channel length modulation approaching VDS = 5 V.
The channel length-invariant properties observed in
these TFTs suggest very small effects due to parasitic resistances. In the linear regime, these effects can be extracted
from the electrical properties of devices with different channel lengths. As described in Ref. 3 using the transmission
line method,11,12 the width-normalized contact resistance
共RcW兲 of Al2O3共ALD兲 / a-IGZO TFTs was extracted for W
= 400 ␮m and L ranging from 5 to 100 ␮m. Figure 3共a兲
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142107-3
Appl. Phys. Lett. 94, 142107 共2009兲
Kim et al.
⫻ 10−6 cm2兲 that show similar electrical performance.14
In summary, we have demonstrated high-performance,
top-contact, bottom-gate n-channel a-IGZO thin-film transistors that use 100-nm-thick Al2O3 grown by ALD as the gate
dielectric material. Al2O3 films deposited by ALD show very
small leakage current below 10−7 A / cm2 up to 3.5 MV/cm
with a field and frequency independent Ci = 81⫾ 1 nF/ cm2.
Al2O3共ALD兲 / a-IGZO TFTs operate in enhancement mode
with high ␮FE of 8 ⫾ 1 cm2 / V s, low VT of 0.4⫾ 0.1 V at
5 V, and Ion-off of 6 ⫻ 107. The very small S of
0.1⫾ 0.01 V / decade yields very small subgap DOS and allows very low operating voltages. Moreover, with RcW
= 25 ⍀ cm at 5 V, much smaller than RchW, ␮FE is channellength independent and does not limit the transconductance,
potentially allowing TFTs capable of low power operation up
to frequencies around 7.8 MHz.
FIG. 3. 共Color online兲 共a兲 Width-normalized contact resistance 共RcW兲 as a
function of channel length and width-normalized channel resistance 共RchW兲
at a channel length of 5 ␮m in the linear 共VDS = 0.05 V兲 region for
Al2O3共ALD兲 / a-IGZO TFTs. 共b兲 Transconductance 共gm兲 and field-effect mobility 共␮FE兲 vs. inverse of channel length 共1 / L兲 in the linear 共VDS = 0.1 V兲
region for Al2O3共ALD兲 / a-IGZO TFTs.
The authors acknowledge fruitful discussions with Mr.
V. Vaidya and Professor D. Wilson from the University of
Washington. This material is based upon work supported in
part by the STC Program of the National Science Foundation
共NSF兲 under Agreement No. DMR-0120967 and by the Office of Naval Research. This work was performed in part at
the Microelectronics Research Center at Georgia Institute of
Technology, a member of the National Nanotechnology Infrastructure Network, which is supported by NSF 共Grant No.
ECS-03-35765兲.
1
shows that RcW, at VDS = 0.1 V, is less than 30% of the
width-normalized channel resistance 共RchW兲 on a 5 ␮m
channel length TFT for VGS varying from 1.0 to 5.0 V. The
very small values of RcW, down to 25 ⍀ cm at VGS = 5 V,
achieved in our devices are consistent with prior experiments
in patterned gate a-IGZO TFTs that indicate that the major
contribution to the contact resistance comes from the bulk
a-IGZO layer, namely the resistance to access the channel,
rather than from the a-IGZO/source共drain兲 electrode
interface.10,13
Another consequence of achieving very small values of
RcW is that the transconductance gm = max共⳵IDS / ⳵VGS兲 兩VDS is
maximized. As shown in Fig. 3共b兲, this is confirmed by gm
being linearly dependent on L−1 and by a channel-length
independent field-effect mobility ␮FE = L gm / WCiVDS
= 8.3 cm2 / V s. Therefore, we estimate that a TFT with L
= 5 ␮m and an effective channel area of Aeff = 6
⫻ 10−5 cm2 could operate in the linear regime with a cutoff
frequency of f T = gm / 共2␲CiAeff兲 = 0.2 MHz. In the saturation
regime, we calculate a gm共VDS = VGS = 5 V兲 of 240 ␮A / V
that yields f T = 7.8 MHz. Assuming the same electrical bias,
we estimate that this value is comparable with f T values
measured in ZnO-based TFTs 共Ci = 115 nF/ cm2 , Aeff = 1
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