DDR Memory Solutions for Next Generation
Spacecraft Systems
Joseph Marshall
Space Products and Processing
BAE Systems
Courtesy of NASA
Courtesy
of NASA
Approved for public release:
ES MVA 012915 - BAE379
Courtesy
of NASA
Courtesy of NASA
Courtesy of NASA
2015 Microelectronics Reliability and Qualification Working Meeting
Courtesy
of NASA
1
Agenda
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Spacecraft Payload and Bus Evolving Architectures
DDR3 Memory Requirements and Insertion
Radiation Mitigation Solutions
RAD® DDR Radiation Effects Mitigation ASSP
COTS DDR Memory Solutions
High Density RAD® DDR3 REM DIMM
Summary
Approved for public release:
ES MVA 012915 - BAE379
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 2
RH45™ enables advanced space solutions
RADSPEED™ HB SoC (4 cores)
RAD5545™ Processor (4 cores)
RAD5510™ Processor (1 core)
RADNET™ 1848-PS
RADNET™ 1616-XP
RADNET™ SRIO-EP
The RADNET and other RH45 ASICs expand our Processor, RapidIO and SpaceWire
capabilities beyond our two 150nm RADNET SpaceWire ASICs (endpoint and 4 port
router-bridge)
Approved for public release:
ES MVA 081314 - BAE348
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 3
sRIO, PCI, SpaceWire or Custom
Expansion Plane
Expansion
Plane
(32 Pairs)
Expan
Plane
VPX VPX
1
2
VPX VPX VPX VPX
3
4
5
6
Expan
Plane
Expan
Plane
Expan
Plane
Expan
Plane
Expan
Plane
UM
1-2
Expan
Plane
VPX
9
VPX VPX VPX
10
11 12
VPX VPX
14
13
Expan
Plane
Expan
Plane
Expan
Plane
Expan
Plane
Expan
Plane
PCI Bus A
Serial RapidIO (SRIO)
Data Plane
Data Plane
(FP)
Expan
Plane
Heritage
CompactPCI Slot
Peripheral
Slot – Separate
Payload
Bridge Slot
Peripheral
Slot - Attached
Payload Slot
Payload Slot
Controller & Data
Switch w/ Bridge
Slot
Controller & Data
Switch w/ Bridge
Slot
Payload Slot
Payload Slot
Peripheral
Slot - Attached
Payload
Bridge Slot
Slot
numbers
are logical,
physical
slot
numbers
may be
different
Peripheral
Slot - Separate
SpaceVPX (VITA 78) extends
OpenVPX (VITA 65) by adding
support for dual redundant
architectures and supporting
Heritage (cPCI) modules
Heritage
CompactPCI Slot
Example SpaceVPX Standard Switch Topology:
16-slot backplane
Expan
Plane
PCI Bus B
Data
Plane
Data
Plane
Data
Plane
Data
Switch
Data
Switch
Data
Plane
Data
Plane
Data
Plane
SRIO fat pipe (FP) = 4 lanes
@ up to 5 Gbaud each
After coding overhead = 16 Gbps
TP
SpaceWire
Control Plane
Control Plane
(TP)
Contrl
Plane
Contrl
Plane
Contrl
Plane
Contrl
Plane
Contrl
Plane
Contrl
Switch
Contrl
Switch
Contrl
Plane
Contrl
Plane
Contrl
Plane
Contrl
Plane
Contrl
Plane
TP
I2C, Clocks and Reset
Utility Plane
Power and Selection
Utility Plane
Switched
Management
Plane (IPMB )
Switched
Utility Plane
includes power
Controller
Selection
A and B (HLD)
*UM – Utility Management; SW – Power,
Utility and Management Switches for each
slot
ChMC – Chassis Controller IPMC –
Individual Slot Control
Approved for public release:
ES MVA 081314 - BAE348
IPMC
IPMC
IPMC
IPMC
ChMC
ChMC
IPMC
IPMC
IPMC
IPMC
SW
Power B
Power A
SpaceVPX supports fault tolerant
dual redundant architecture
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 4
Example future spacecraft architecture
(redundancy not shown)
Single Board
Computer
Network Switch
Sensor
Sensor
RADNET™1616-XP
Crosspoint
Switch
RADNET1848-PS
Serial
RapidIO
Packet
Switch
RAM
RAM
SpaceWire
Router
RAM
NVRAM
RAM
Dual DSP RAM
RADSPEED™
DSP
RAM
RAM
RAD5545™
Quad Core
Processor
RCC
RAM
RADSPEED
DSP
RAM RADSPEED HB
NVRAM SoC Quad Core
RAM
FPGA
RAM
NVRAM
FPGA
RADNET
SRIO-EP
Serial RapidIO Data Plane
SpaceWire Control Plane
Sensor
RH45™
ASIC
RAM
NVRAM
NVRAM
RADNET
SRIO-EP
RAD750®
RADNET
CPU +
L2 cache SPW-RB4
Sensor Interface Single Board Computer
Sensor
RH45
ASIC
RADNET
SRIO-EP
RAD5510™
Single Core
CPU
RAM
SpaceVPX
On-board
Processor
Box
RADNET
SRIO-EP
RADNET
SRIO-EP
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
Recorder
RAM
NVRAM
RH45
ASIC
Communicatio
ns
Interface
Bus
Electronics
NVRAM RAD750
CPU +
RAM L2 cache
RADNET
SPW-RB4
RADNET
SPW
-RB4
ADC
DAC
Single Board Computer GNC Interface
…
Heritage
PCI Cards
RADNET
SRIO-EP
Heritage
PCI Cards
I2C Utility Plane
RADNET
SPW-EP
RADNET
SPW-EP
RADNET
SPW-RB4
Digital
Sensor
Star
Tracker
IMU
Sensor Detail
Approved for public release:
ES MVA 081314 - BAE348
The resulting modules will create the next generation
spacecraft, including high performance on-board processing
I 2C
Serial RapidIO
SpaceWire
2015 Microelectronics Reliability and Qualification Working Meeting
PCI
1553
ClearConnect bridge
PAGE 5
DDRx Radiation Effects Mitigation Requirements
The RAD® DDR REM ASSP packaged with additional ECC devices in the
RAD® DDR REM DIMM will meet this space processing need
Approved for public release:
ES MVA - 040913
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 6
COTS vs. RAD® DDRx REM DIMM
CCA with COTS DDRx DIMM
DDRx
POL
SECDED:
64 data + 8 ECC
DDRx
DDRx
Controller
within
ASIC, FPGA,
CPU, DSP, …
DDRx
Circuit Card
Assembly (CCA)
S/D8EC: 64 data + 8
SECDEC ECC + 16/32 ECC
DDRx
POL
M
DDRx
Interrupt(s) to S/W
DDRx
Controller
within
ASIC, FPGA,
CPU, DSP, …
M
REM ASSP
DDRx
CCA with RAD DDRx REM DIMM
Circuit Card
Assembly (CCA)
COTS DDR DIMM
1V
POL
M
DDRx
M
I2C, JTAG from S/W
DDRx
DDRx
DDRx
RAD DDRx REM DIMM
The DDRx-REM Assembly will be a separate multi-chip module with high
performance connections containing the DDR-REM ASIC, DDRx devices and
power switching MOSFETs(M) for each DDRx device
Approved for public release:
ES MVA - 040913
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 7
RAD® DDR REM ASSP
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Support for DDR2 or DDR3 memories (programmable 1.8V and 1.5V DDR I/O)
JEDEC Compatible 800 MHz Host DDR Interface
JEDEC Compliant 800 MHz Target DDR Interface
JTAG
I/F
Enhanced Error Correction (S8EC or D8EC) Discretes
Programmable scrub mode
I2C I/F
RH45™ Technology
Total dose: > 1 MRad (Si)
SEU: <1E-10 errors/bit-day
Latch-up: immune
Performance:
DDR2/3-800 (calibrated)
I2C @ 400 KH
Power dissipation:
4.5W worst-case
Power supplies:
0.95V +50mV Core
1.8V/1.5V DDR2/3 I/O (programmable)
1.8V/2.5V/3.3V LVCMOS I/O (programmable)
Approved for public release:
ES MVA 012915-BAE379
SkyBlue Controller
I2C
Controller
Config Settings
Interrupts
Stall Req/Gnt
Pwr Ctl
Mitigation
Monitor/Controller
Reset
Clock/Reset
I/F
Initialization/
Calibration
CLK_IN
TGT
PLL
Addr/Ctrl
Addr/Ctrl/Data
Clk/Strb
H_CK
Clk/Strb
Scrub
Queue
64
8
Test
I/F
Snoop/Flow
Control
Logic
H_CK
ECC
TEST
Registers/Mode Control
(Config/Status)
HST
PLL
Data
JTAG Slave
Module
64(72)
Host
DDR
PHY
MUXing
64(72)
Decode
ECC
64,8
TGT
DDR
PHY
Encode
ECC
Target
DDR I/F
32
ECC
Addr/Ctrl
Addr/Ctrl
Addr/Ctrl
Input Clock Domain (CLK_IN MHz)
Host Source Domain (DDR DATA RATE/2)
Data Rate Domain (DDR DATA RATE)
Trgt Source Domain (DDR DATA RATE/2)
RAD DDR REM ASSP in Physical Design
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 8
DDR Board Usage
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COTS equipment uses DIMMs
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Isolate critical routing
Most of these are mounted perpendicular to board
Thermal paths very limited
Structural support lacking for space vibration
Highest density
JEDEC standards for each
Include SECDED ECC
COTS XR-DIMM created for embedded market
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COTS XR-DIMM
Mounted parallel to board like a daughter card
Connector usable in space
Thermal and structural paths possible
DDR3 boards available for prototyping or interface checkout
XR-DIMM adopted as base assembly for DDR2 and DDR3
Approved for public release:
ES MVA 012915 - BAE379
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 9
RAD® DDR3 REM DIMM Features
Technology
• RAD DDR REM ASSP: Radiationhardened by design RH45™ circuit
library
• Trusted foundry 45nm SOI process
• Upscreened industrial DDR3 memory
• GaN MOSFET DDR3 power switching
Operating temperature range
• -40oC to +105oC
Radiation hardness
• Total ionizing dose: 100 Krad (Si)
• SEU DIMM: ECC corrected
• SEU: REM ASIC Flip-flops: 8E-14
upsets/bit-day
• SEFI: REM mitigated
• Latch-up immune
Configurations
• 2, 4, 8 or 16 GB
• x8 or x16 devices
Approved for public release:
ES MVA 062614-0294
Memory interfaces
• 72 bit DDR3 with SEC/DED EDAC
• supports up to 4 ranks and 16 GB
• 800M transfers per second peak
Input/Output interfaces
• I2C host interface
• Interrupt and status discretes
Test and debug interface
• JTAG test points for REM ASIC
Power supplies
• 12V+/-20% power switch
• 0.95 V +/- 5% REM ASIC core
• 1.5V +/- 5% DDR3 and DDR3 I/O
• 0.75V +/- 5% DDR3 reference
• 1.8V, 2.5V and/or 3.3V CMOS I/O
• 3.3V fixed I/O
Power dissipation
• 2-10 Watts @ 95oC depends on
configuration and mode
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 10
RAD® DDR3 REM DIMM Detail
RAD DDR3 REM DIMM
RAD
DDR REM
ASSP
RAD DDR3 REM DIMM design fully
placed, analyzed and ready to route
Approved for public release:
ES MVA 062614-0294
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 11
RAD® DDR3 REM DIMM Usage Summary
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Single RAD DDR3 REM DIMM design supports multiple COTS DDR3 devices
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RAD DDR3 REM DIMMs may be used with variety of controllers
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COTS DDR3 XR-DIMM may be used for bring-up of DDR3 interface
72 bit SECDED protected DDR3 interfaces
CPUs, ASICs and higher performance FPGAs
Single bit and single device errors corrected by extended error code
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Notification of errors via I2C to DDR3 controller or controlling software unit
Will continue to operate through until right time to correct
RAD DDR3 REM DIMM and its RAD DDR REM ASSP enable COTS
DDR3 memories to be used in most spaceborne environments
Approved for public release:
ES MVA 012915 - BAE379
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 12
RAD® DDR3 REM DIMM Usage Summary
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Single RAD DDR3 REM DIMM design supports multiple COTS DDR3 devices
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RAD DDR3 REM DIMMs may be used with variety of controllers
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Updated radiation testing will select best DDR3 devices to be upscreened
One or two rows may be populated – 4 to 16 GB per DIMM
COTS DDR3 XR-DIMM may be used for bring-up of DDR3 interface
72 bit SECDED protected DDR3 interfaces
CPUs, ASICs and higher performance FPGAs
One or two DIMMs per DDR3 port mounted opposite each other on board
RAD DDR3 REM DIMM equivalent to COTS DDR3 with small first access delay
Single bit and single device errors corrected by extended error code
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Log of errors in RAD DDR REM ASSP accessible through I2C
Notification of errors via I2C to DDR3 controller or controlling software unit
Scrubbing of non-SEFI errors may be done in background
Will continue to operate through until right time to correct
To correct SEFI, controller isolates memory bank and commands DDR REM ASSP to
perform power cycles, resets or initializations
RAD DDR3 REM DIMM and its RAD®DDR REM ASSP enable COTS
DDR3 memories to be used in most spaceborne environments
Approved for public release:
ES MVA 012915 - BAE379
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 13
Approved for public release:
ES MVA 012915 - BAE379
2015 Microelectronics Reliability and Qualification Working Meeting
PAGE 14