Failure Mode
Failure Analysis (FA) Introduction
(IC Failure Mode)
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Failure Mode
Structure of conventional package
gold wire
leadframe
chip
EMC
die-pad
Failure Classification
Physical Failure (Structure)
- Popcorn
- Delamination
- Crack (Package/Die)
Electrical Failure (Connection)
- Open
- Short
- Leakage
- Function
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In-Process Failure (Production)
- Front-end (before molding)
- Back-end (After molding)
- Testing (FT/Burn-in)
Reliability Failure (Qualification)
- Temperature
- Humidity
- Pressure
- Voltage
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Failure Mode
Popcorn
爆裂)
爆裂
Popcorn (爆裂
(爆裂
爆裂)
爆裂
Failure Mechanism
(1) Moisture absorption
(L-1: 85oC/85%RH)
(L-3: 30oC/60%RH)
popcorn
(2) Moisture vaporization
during heating
(Reflow, 235oC/10s)
(3) Vapor force separating
(delamination)
leadframe
(4) Popcorn forming
(package crack)
(collapsed void)
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Chip
die-pad
crack
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Failure Mode
TQFP package (bottom popcorn)
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FBGA package (top popcorn)
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Failure Mode
Delamination
離裂)
離裂
Delamination (離裂
(離裂
離裂)
離裂
(1) Die surface
(EMC/chip)
(2) Leadframe
(EMC/leadframe)
gold wire
leadframe
chip
EMC
die-pad
(4) Pad bottom
(pad/EMC)
crack
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(3) Die Attach
(chip/pad)
crack
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Failure Mode
Crack
破裂)
破裂
Crack (破裂
(破裂
破裂)
破裂
EMC Crack (膠體破裂)
Die Crack (晶片破裂)
gold wire
crack
leadframe
chip
EMC
die-pad
crack
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Failure Mode
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Failure Mode
CON Package
Assembly
Assembly Flow
Flow
Lapping
Lapping
Bondability
Dicing
Die attach
TCP Package
Leadframe
Wire bond
Dicing
ILB
TAB tape
Potting & Cure
Resin
Ink
Molding
Compound
Marking
Marking
Ink
Testing
M/V
Dejunk/Trim
Plating
Solder anode
Forming
Defect punch
Packing/Ship
Reel/Spacer
Testing
Packing /Ship
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Tube/Tray
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Failure Mode
Wiring Bondability (TSOP/BGA)
Shift bonding (short/leakage, W/B)
Ball lifted (open, W/B)
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Ball over-bonding (short, W/B)
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Failure Mode
Wiring Bondability (TSOP/BGA)
Ball neck broken (W/B)
Heel broken (open, W/B)
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Ball neck crack (W/B)
Heel broken (open, W/B)
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Failure Mode
Inner Lead Bondability (TCP/COF)
No bonding (open, ILB)
Poor bonding (open, ILB)
Thin bump (open, ILB)
Thin lead (open, ILB)
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Failure Mode
Inner Lead Bondability (TCP/COF)
Alloy bubble (short, ILB )
IL shifted (short, ILB)
Metal bridged (short, ILB)
Bump crush (short, ILB)
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Failure Mode
Bondability (Bonding Force)
(function -> Leakage -> Short)
Normal bondability
After crating testing
KNO3 solution etching
Remove gold-ball bonding
Inspect Al-pad
damaged
SiO2 layer is damaged
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X-RAY Inspection (NDT)
Failure Mode
2nd Bonding
Broken
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Open Failure
Inner wire neck broken
Failure Mode
Chip damaged to impact the wire
PinPin- 11
Foreign insulator stuck on lead
Pad contamination by Auger Spectrum
600
4000
DQ2
D Q2
D Q13
Counts
400
D Q15
DQ13
200
0
DQ15
-200
-400
2000
TiN
Ti
-600
Counts
Energy
0
Ti
TiN
Si
F
DQ2
2000
DQ13
-2000
Counts
C
-4000
0
Si
-1000
F
Al
-2000
O
500
-3000
Al
Energy
1200
Kinetic Energy (keV)
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Au
DQ15
1000
1600
Al
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Open Failure
TSOPII 54L LOC
(in-process open failed)
Failure Mode
PLCC 32L
(Reflowing open failed)
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(X-Ray Microscope)
(Optical Microscope, 40X)
(SAT C-SCAN, die surface)
Au-wire
2nd-bonding lifted
2nd bond lifted
Lead-frame
Open bonding is not easily detected by XRM
However, after EMC decapsulation, 2nd
bonding lifted is exposed by optical microscope
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(SEM, 300X)
Open bonding is not easily detected by XRM
bonding lifted is exposed by SEM
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Open Failure
Failure Mode
Bending Test
Vibration Test
+
Output Y41
Open position
Tape
Output Y41
DC test open (Fail)
SEM found concave and
micro-crack (1800x)
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TFT Panel
ACF area
SEM observed output lead
broken (2000x)
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Open Failure
TCP Product
Inner Lead Bonding Broken
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TCP Product
Resin Cause Broken
Failure Mode
TCP Product
Inner Lead Peeling
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Short Failure
Over-compressed bonding
Shifted bonding
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Failure Mode
Split epoxy between leadframe
Chip circuit burn out
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Short Failure
Failure Mode
Wire lay on substrate finger to short
After PCT tests, solder growth
Sn whisker to connect two pins
Unloading from PCB, solder bridged
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Short Failure (Tin Whisker)
Failure Mode
(Compressive Stress)
(Jay A. Brusse)
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Short Failure
Failure Mode
Sn over-plating to lead short on tape
Needle-like Sn grow to short while bonding
Chip scratched to cause circuit short
Au pad bubble to short while bonding
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Leakage Failure
IC Circuit burn-out
Failure Mode
Die crack
Top Temperature = 35.00C
Corner die crack
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Corner Chipping
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Function Failure
Failure Mode
Assembled Related – Machine/Man Damaged
Corner chipping
Chip surface scratch
Side chipping
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Function Failure
Failure Mode
Assembled Related – Environment (Particle Damaged)
Particle damaged (~20um)
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Particle damaged (~10um)
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ESD Cases of Driver ICs
D-company, EOS/ESD wiring burn-out to short
Failure Mode
H-company, internal burn-out to short, ESD under pad
(靜電防護元件~保險絲)
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Difference between ESD and EOS
ESD = ElectroStatic Discharge
(ESD)
(EOS)
Failure Mode
EOS = Electrical Over Stress
Appearance of
damage (tendency)
The location of damage is very small
and cannot be identified by visually
examining the semiconductor chip
If the energy of EOS is large of damage, such as
breaks in wiring on the chip due to melting,
discoloration, and burning of the package, can be
recognized.
If the energy is small, it is difficult to distinguish
damage caused by EOS from that caused by ESD
Process of failure
Electric charge damages the IC chip of
semiconductor device when it discharges
through the device
A semiconductor device is damaged by application of
an overvoltage or overcurrent while the device is
operating (while the characteristics of the device are
being used by the user)
Cause of failure
Discharge due to contact of a charged
body with the pins of a semiconductor
device or discharge of an electric
charge that takes place in the device
itself because of friction or other causes
Generation of Latch-up, surge due to turning power
on or off and measuring instruments on or off., shortcircuit of the load, solder chips, and patterns shortcircuit by metallic foreign objects.
Photograph of chip
Source: NEC information (1997, Guide to prevent damage for semiconductor devices by electrostatic discharge (ESD))
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Major Mode of Damages by ESD
(1) Damage to oxide film
(2) Junction destruction
(Gate oxide failed)
(Junction Breakdown)
Failure Mode
(3) Melting of wiring film
(Wiring burn-out)
- Thermal destruction
- ESD (fine Al wiring is melted)
EOS (coarse Al wiring)
- Thin is easy
- Gate film is only 10nm
- Thin is easy
- Reverse bias
- Current concentration
- Shallow is easy
IC design trend:
1. Gate film is thinner
2. Junction is shallower
3. Al wiring is thinner
=> On-chip protection
internal ESD protection
Source: NEC information (1997, Guide to prevent damage for semiconductor devices by electrostatic discharge (ESD))
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Failure Mode
Structure/Property
Material
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Process
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