EN5322QI
Created on 2/27/2007 11:55:00 AM
2 A Voltage Mode Synchronous Buck PWM
DC-DC Converter with Integrated Inductor
RoHS Compliant
Halogen Free
General Description
Features
The EN5322 provides the benefits of high
switching frequency with the flexibility to optimize
the design for footprint or efficiency.
• Revolutionary Integrated Inductor
• Total Footprint as Small as 60 mm2
• 4 mm x 6 mm x 1.1 mm QFN Package
• 4 MHz Fixed Switching Frequency
• High Efficiency, up to 93 %
• 2% Initial VOUT Accuracy with VID Codes
• 2% Initial 0.6 V Feedback Voltage Accuracy
• 2.4 V to 5.5 V Input Voltage Range
• 2 A Output Current Capability
• Fast Transient Response
• Low Ripple Voltage; 8 mVP-P Typical
• Low Dropout Operation: 100 % Duty Cycle
• Power OK Signal with 5 mA Sink Capability
• Dynamic Voltage Scaling with VID Codes
• 17 μA Typical Shutdown Current
• Under Voltage Lockout, Over Current, Short
Circuit, and Thermal Protection
• RoHS Compliant; MSL 3 260 °C Reflow
The 4 MHz operation allows for the use of tiny
MLCC capacitors. It also enables a very wide
control loop bandwidth providing excellent
transient performance and reduced output
impedance. The internal compensation is
designed for unconditional stability.
Three VID output voltage select pins provide
seven pre-programmed output voltages along
with an option for external resistor divider.
Output voltage can be programmed on-the-fly to
provide fast, dynamic voltage scaling with
smooth transitions between programmed output
voltages.
Applications
•
•
•
•
•
•
•
•
Point of Load Regulation for Low Power
Processors, Network Processors, DSPs’
FPGAs and ASICs
Replacement of LDOs
Servers, Desktop Computers, Notebooks and
UMPC
Storage and Networking
Instrumentation
DSL, STB, DVR, DTV, and iPC
Computer Peripherals
Audio
Application Circuit
ENABLE
VIN
10 uF
CBYPASS
470 pF
VSENSE
PVIN
VS0
VS1
VOUT
VOUT
EN5322 POK
COUT
47 uF
VS2
PGND
AVIN
PGND
AGND
1 uF
Ordering Information
Part Number
EN5322QI-T
EN5322QI-E
CIN
Figure 1. Application Circuit
Temp Rating (°C)
Package
-40 to +85
24-pin QFN T&R
QFN Evaluation Board
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October 2007
EN5322QI
Absolute Maximum Ratings
CAUTION: Absolute maximum ratings are stress ratings only. Functional operation beyond recommended operating
conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Electrical Ratings
MIN
Voltages on: PVIN, AVIN, VOUT
Voltages on: VSENSE, VS0, VS1, VS2, ENABLE, POK
Voltage on: VFB
ESD Rating (Human Body Model)
ESD Rating (Charge Device Model)
MAX
-0.3 V
-0.3 V
-0.3 V
2 kV
500 V
6.5 V
VIN
2.7 V
-40 °C
-65 °C
+85 °C
+150 °C
+260 °C
Absolute Maximum Thermal Ratings
Ambient Operating Range
Storage Temperature Range
Reflow Peak Body Temperature MSL3 (10 s)
Thermal Characteristics
PARAMETER
Thermal Shutdown
Thermal Shutdown Hysteresis
Thermal Resistance: Junction to Case
Thermal Resistance: Junction to Ambient
SYMBOL
MIN
TSD
TSDH
θJC
θJA
TYP
155
15
6
36
MAX
UNITS
°C
°C
°C/W
°C/W
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
Input Voltage Range
VIN
2.4
Output Voltage Range
VOUT
0.6
Output Current
ILOAD
0
Operating Junction Temperature
TJ
0
Note: VDROPOUT is defined as (ILOAD x Dropout Resistance) including temperature effect.
VIN
MAX
5.5
- VDROPOUT
2
+125
UNITS
V
V
A
°C
Electrical Characteristics
VIN = 5 V and TA = 25 °C, unless otherwise noted.
Note 1: The tolerances with VID codes hold true only if VIN is greater than (VOUT + VDROPOUT).
Note 2: VFB, ENABLE, VS0-VS2 pin input current specification is guaranteed by design.
PARAMETER
Operating Input Voltage
Under Voltage Lockout
UVLO Hysteresis
Output Voltage with VID
Codes (Note 1)
VFB Voltage
SYMBOL
VIN
VUVLO
TEST CONDITIONS
VIN going low to high
VOUT
ILOAD = 100 mA
VS2 VS1 VS0 VOUT (V)
0
0
0
3.3
0
0
1
2.5
0
1
0
1.8
0
1
1
1.5
1
0
0
1.25
1
0
1
1.2
1
1
0
0.8
VFB
ILOAD = 100 mA, VS0 = VS1 = VS2 = 1
©Enpirion 2007 all rights reserved, E&OE
MIN
2.4
2
TYP
MAX
5.5
2.2
0.15
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
+2.0
-2.0
-2.0
-2.0
-2.0
-2.0
-2.0
-2.0
0.588
0.600
0.612
UNITS
V
V
V
%
V
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PARAMETER
Output Voltage with VID
Codes (Note 1)
VFB Voltage
Dynamic Voltage Slew Rate
Soft Start Slew Rate
Line Regulation
Load Regulation
VFB, ENABLE, VS0-VS2
Pin Input Current (Note 2)
ENABLE, VS0-VS2 Voltage
Threshold
POK Upper Threshold
POK Upper Threshold
POK Lower Threshold
POK Lower Threshold
POK Low Voltage
POK Pin VOH Leakage
Current
Shutdown Current
Quiescent Current
Quiescent Current
Current Limit Threshold
PFET On Resistance
NFET On Resistance
Dropout Resistance
Operating Frequency
Output Ripple Voltage
EN5322QI
SYMBOL
TEST CONDITIONS
VOUT
2.4 V ≤ VIN ≤ 5.5 V, ILOAD = 0 ~ 2 A, TA
= -40 ~ +85 °C
VS2 VS1 VS0 VOUT (V)
0
0
0
3.3
0
0
1
2.5
0
1
0
1.8
0
1
1
1.5
1
0
0
1.25
1
0
1
1.2
1
1
0
0.8
VFB
2.4 V ≤ VIN ≤ 5.5 V, ILOAD = 0 ~ 2 A,
VS0 = VS1 = VS2 = 1, TA = -40 ~ +85
°C
MIN
TYP
+3.0
+3.0
+3.0
+3.0
+3.0
+3.0
+3.0
-3.0
-3.0
-3.0
-3.0
-3.0
-3.0
-3.5
0.582
0.600
TA = -40 ~ +85 °C
0.0
1.4
111
102
92
90
0.15
POK High, TA = -40 ~ +85 °C
ENABLE Low
No Switching
Switching, VOUT = 1.2 V
2.4 V ≤ VIN ≤ 5.5 V
FOSC
VRIPPLE
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COUT = 2 x 22 μF 0805 X5R MLCC,
VOUT = 1.2 V, ILOAD = 2 A
3
0.618
1.5
1.5
0.033
0.13
2.4 V ≤ VIN ≤ 5.5 V, VOUT = 1.2 V
0 A ≤ ILOAD ≤ 2 A, , VOUT = 1.2 V
Logic Low
Logic High
VOUT Rising
VOUT Falling
VOUT Rising
VOUT Falling
ISINK = 5 mA, TA = -40 ~ +85 °C
MAX
UNITS
%
V
V/ms
V/ms
%/V
%/A
+/-40
nA
0.4
VIN
V
0.4
%
%
%
%
V
500
nA
160
60
200
4
μA
μA
mA
A
mΩ
mΩ
mΩ
MHz
8
mVP-P
17
800
15
2.1
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EN5322QI
Pin Configuration
NOTE: NC(SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they
must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
Figure 1. Pin Diagram, Top View.
Pin Description
PIN
NAME
1, 21-24
NC(SW)
2-3, 8-9
PGND
4-7
VOUT
10-12
VS2-0
13
VSENSE
14
VFB
15
AGND
16
AVIN
17
POK
18
ENABLE
19-20
PVIN
FUNCTION
No Connect. These pins are internally connected to the common drain output of the internal
MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or
voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result
in part malfunction or damage.
Input/Output Power Ground. Connect these pins to the ground electrode of the input and
output filter capacitors. Refer to Layout Considerations section for details.
Voltage and Power Output. Connect these pins to output capacitor(s).
Output Voltage Select. These pins set one of seven preset output voltages and the external
divider option (refer to Electrical Characteristics table for more details), and can be directly
pulled up to VIN or pulled down to GND.
Sense Pin for Internally Programmed Output Voltages with VID Codes. Connect this pin to the
last local output filter capacitor at all times for internal compensation.
Feedback Pin for External Voltage Divider Network. Connect a resistor divider to this pin to set
the output voltage. Use 340 kΩ, 1% or better for the upper resistor.
Analog Ground for the Controller Circuits
Analog Voltage Input for the Controller Circuits. Connect this pin to the input power supply.
Use a 1 μF bypass capacitor on this pin.
Power OK with an Open Drain Output. Refer to Power OK section.
Input Enable. A logic high signal on this pin enables the output and initiates a soft start. A
logic low signal disables the output and discharges the output to GND. This pin must not be
left floating.
Input Power Supply. Connect to input supply. Decouple with input capacitor(s) to PGND.
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EN5322QI
Functional Block Diagram
PVIN
POK
UVLO
POK
Thermal Limit
Current Limit
ENABLE
NC (SW)
Soft Start
P-Drive
Logic
(-)
VOUT
PWM
Comp
(+)
N-Drive
PGND
VSENSE
Sawtooth
Generator
Compensation
Network
(-)
Switch
VFB
Error
Amp
(+)
DAC
Voltage
Select
VREF
BIAS
Package Boundary
AVIN
AGND
VS0 VS1 VS2
Figure 3. Functional Block Diagram.
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EN5322QI
ENABLE
VS0
VS1
VS2
VIN
VS0
VS1
ENABLE
VSENSE
VS2
EN5322
PVIN
CIN-1
10 uF
10 V
0805
CIN-2
CIN-3
470 pF
1 uF
0603
VOUT
VOUT
AVIN
PGND
AGND
POK
COUT-1
COUT-2
22 uF
6.3 V
0805
22 uF
6.3 V
0805
RPOK*
100 k 5%
POK
* Leave RPOK open if the POK function is not used.
Figure 4. Typical Application Circuit with VID Codes.
Typical Performance Characteristics
Circuit of Figure 4, VIN = 5 V, VOUT = 1.2 V and TA = 25°C, unless otherwise noted.
Efficiency vs. Load Current (Vin = 3.3 V)
100
100
90
90
Efficiency (%)
Efficiency (%)
Efficiency vs. Load Current (Vin = 5 V)
80
70
60
50
80
70
60
50
40
40
30
30
0
0.4
0.8
1.2
1.6
0
2
0.8
1.2
1.6
2
Load Current (A)
Load Current (A)
Top to Bottom: VOUT = 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V,
0.8 V
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0.4
6
Top to Bottom: VIN = 2.5 V, 1.8 V, 1.5 V, 1.2 V, 0.8 V
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EN5322QI
Quiescent Current (Switching) vs.
Input Voltage
Quiescent Current (mA)
Quiescent Current (uA)
Quiescent Current (No Switching) vs.
Input Voltage
840
820
800
780
760
740
2
3
4
5
18
16
14
12
10
8
2
6
3
4
5
6
Input Voltage (V)
Input Voltage (V)
Output Voltage (V)
Load Regulation (Vin = 5 V)
1.202
1.200
1.198
1.196
1.194
1.192
1.190
0
0.4
0.8
1.2
1.6
2
Load Current (A)
Output Ripple at 2 A Load (VIN = 5 V )
CH2: VOUT
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Output Ripple at 2 A Load (VIN = 3.3 V )
CH2: VOUT
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EN5322QI
Transient Response at VIN = 5 V
(0-2 A Load Step)
CH2: VOUT, CH4: ILOAD
Transient Response at VIN = 3.3 V
(0-2 A Load Step)
CH2: VOUT, CH4: ILOAD
VOUT Scaling with VID Codes at VIN = 5 V
(VOUT = 1.2 V-2.5 V)
CH1: VS2, CH2: VOUT, CH3: POK
VOUT Scaling with VID Codes at VIN = 3.3 V
(VOUT = 1.2 V-2.5 V)
CH1: VS2, CH2: VOUT, CH3: POK
Power Up/Down at No Load
CH1: ENABLE, CH2: VOUT, CH3: POK, CH4: IINDUCTOR
Power Up/Down at 0.6 Ω Load
CH1: ENABLE, CH2: VOUT, CH3: POK, CH4: IINDUCTOR
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EN5322QI
Output Over Load at No Load
CH1: VOUT, CH2: VNC(SW), CH3: POK, CH4: IINDUCTOR
Output Over Load at 2 A Load
CH1: VOUT, CH2: VNC(SW), CH3: POK, CH4: IINDUCTOR
Output Over Load at No Load
CH1: VOUT, CH2: VNC(SW), CH3: POK, CH4: IINDUCTOR
Output Over Load at 2 A Load
CH1: VOUT, CH2: VNC(SW), CH3: POK, CH4: IINDUCTOR
Functional Description
The EN5322 leverages advanced CMOS
technology
to
provide
high
switching
frequency, while also maintaining high
efficiency.
The converter uses voltage mode control to
provide a high noise immunity, low output
impedance and excellent load transient
response.
No
external
compensation
components are needed.
Packaged in a 4 mm x 6 mm x 1.1 mm QFN,
the EN5322 provides a high degree of flexibility
in circuit design while maintaining a very small
footprint. High switching frequency allows for
the use of very small MLCC input and output
filter capacitors.
©Enpirion 2007 all rights reserved, E&OE
Output voltage is chosen from one of seven
preset values via a three-pin VID voltage select
scheme. An external divider option enables the
selection of any output voltage ≥ 0.6 V. The
VID pins can be toggled dynamically to
implement glitch-free dynamic voltage scaling.
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October 2007
POK monitors the output voltage and signals if
it is in regulation. Protection features include
under voltage lockout (UVLO), over current
protection, short circuit protection, and thermal
overload protection.
EN5322QI
voltage reaches sufficient level to ensure
proper operation. If the voltage drops below the
UVLO threshold the lockout circuitry will again
disable switching. Hysteresis is included to
prevent chattering between UVLO high and low
states.
Stability over Wide Range of Operating
Conditions
Enable
The EN5322 utilizes an internal compensation
network and is designed to provide stable
operation over a wide range of operating
conditions. One of the key features of this
device is the ability to add supplementary
capacitance to the output to improve transient
performance or reduce output voltage ripple
with dynamic loads. The EN5322 is stable with
up to 60 μF of output capacitance at the
VSENSE sense point. The high switching
frequency allows for a wide control loop
bandwidth.
The ENABLE pin provides means to shut down
the converter or initiate normal operation. A
logic high will enable the converter to go
through the soft start cycle and regulate the
output voltage to the desired value. A logic low
will allow the device to discharge the output
and go into shutdown mode for minimal power
consumption. When the output is discharged,
an auxiliary NFET turns on and limits the
discharge current to 300 mA or below. In
shutdown mode, the device typically drains as
little as 17 μA.
Soft Start
NOTE: The ENABLE pin must not be left
floating.
The internal soft start circuit limits inrush
current to negligible levels when the device
starts up from a power down condition or when
the ENABLE pin is asserted “high”. Digital
control circuitry sets the VOUT ramp rate to
minimize input voltage ripple and inrush current
to ensure a glitch-free start up. The soft start
ramp rate is nominally 1.5 V/ms.
Thermal Shutdown
When excessive power is dissipated in the
device, its junction temperature rises. Once the
junction temperature exceeds the thermal
shutdown temperature 155 °C, the thermal
shutdown circuit turns off the converter,
allowing the device to cool. When the junction
temperature drops 15 °C, the device will be reenabled and go through a normal startup
process.
Over Current/Short Circuit Protection
Current limit function is implemented by
sensing the current flowing through a sense
PFET which is then compared to a reference
current. When the sensed value exceeds the
reference current, the PFET is turned off and
the NFET is turned on at the next clock edge,
pulling VOUT low. This condition is maintained
for a period of 1.2 ms and then a normal soft
start cycle is initiated. If the over current
condition still persists, this cycle will repeat.
Power OK
The EN5322 provides an open drain output to
indicate if the output voltage stays within 92%
to 111% of the set value. Within this range, the
POK output is allowed to be pulled high.
Outside this range, POK remains low.
However, during transitions such as power up,
power down, and dynamic voltage scaling, the
POK output will not change state until the
transition is complete for enhanced noise
immunity.
Under Voltage Lockout
An under voltage lockout circuit will hold off
switching during initial power up until the input
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EN5322QI
used for minimal current consumption in
shutdown mode.
The POK has 5 mA sink capability for events
where it needs to feed a digital controller with
standard CMOS inputs. When POK is pulled
high, the pin leakage current is as low as 500
nA maximum over temperature. This allows a
large pull up resistor such as 100 kΩ to be
The POK output can also be conveniently used
as an ENABLE input of the next stage for
power sequencing of multiple converters.
ENABLE
VS0
VS1
VS2
VIN
VS0
VS1
VS2
ENABLE VSENSE
VOUT
PVIN
CIN-1
10 uF
10 V
0805
CIN-2
470 pF
CIN-3
EN5322
VFB
PGND
AGND
AVIN
1 uF
0603
340 k
1%
R1
COUT-1
VOUT
COUT-2
1%
R2
22 uF
6.3 V
0805
22 uF
6.3 V
0805
POK
RPOK*
100 k 5%
POK
* Leave RPOK open if the POK function is not used.
Figure 5. Typical Application Circuit with External Resistor Divider.
Application Information
Setting the Output Voltage
Input and Output Capacitor Selection
The output voltage can be set by programming
VS0-VS2 pins as shown in the Electrical
Characteristics table or by pulling all these VID
pins high and using an external voltage divider,
as shown in Figure 5. If the external voltage
divider option is chosen, use 340 kΩ, 1% or
better for the upper resistor R1. Then the value
of the bottom resistor R2 in kΩ is given as:
Low ESR MLCC capacitors with X5R or X7R or
equivalent dielectric should be used for input
and output capacitors. Y5V or equivalent
dielectrics lose capacitance with frequency, DC
bias, and temperature. Therefore, they are not
suitable for switch-mode DC-DC converter
filtering, and must be avoided.
A 10 μF, 10 V, 0805 ceramic capacitor with a
470 pF high frequency bypass capacitor is
required on PVIN for all applications. A 1 μF,
10 V, 0603 ceramic capacitor on AVIN is
generally sufficient for high frequency bypass
to ensure clean chip supply for optimal
performance.
204
R2 =
kΩ
VOUT − 0.6
where VOUT is the output voltage. R2 should
also be a 1% or better resistor.
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Two 22 μF, 6.3 V, 0805 ceramic capacitors are
recommended on the output for most
applications. The output capacitance before
the output voltage sense point can be
increased to 60 μF to improve load transient
response and output ripple.
3.
4.
POK Pull Up Resistor Selection
POK can be pulled up through a resistor to any
voltage source as high as VIN. The simplest
way is to connect POK to the power input of
the converter through a resistor. A 100 kΩ pull
up resistor is typically recommended for most
applications for minimal current drain from the
voltage source and reasonable noise immunity.
5.
6.
Layout Considerations
Proper layout and placement of external
components is critical to optimal functioning of
the converter and for minimizing radiated and
conducted noise.
7.
Following
these
layout
guidelines
as
demonstrated in the EN5322 customer eval
boards:
1. Input and output capacitors should be
placed on the same side of the PCB as
the EN5322 and immediately adjacent
to their respective pins on the package.
To minimize parasitic inductances, the
traces for making these connections
should be as short and wide as
possible.
2. A row of vias connecting these
capacitors’ ground pads to the PCB
GND plane should be placed along the
edge of the capacitor ground copper
closest to the positive capacitor pads.
These vias should start as close to the
©Enpirion 2007 all rights reserved, E&OE
12
EN5322QI
device as possible and continue
underneath the capacitors.
Avoid adding a test pin or test pad for
NC(SW) pins on the PCB. Doing so can
compromise the GND plane and result
in degradation of the performance.
There should be as many vias as
possible connecting the thermal pad
under the device to the PCB GND plane
for best thermal performance. Ideally,
the vias should have a drill diameter of
about 0.3 mm with at least 1 oz copper
plating in the barrel.
Keep the input and output current loops
separate from each other as much as
possible by putting a slit in the PGND
copper if necessary. Keep sensitive
signals on the PCB away from the
power supply circuit.
Connect the VSENSE trace to the last
local output capacitor. Make sure the
trace inductance between the output
capacitors and the sensing point is
minimized. The VSENSE trace should
also be kept away from noisy signals
that can contaminate it.
When using multiple converters on the
same PCB, try to minimize any crosstalk
between them:
- Keep the input circuit of any
converter away from the output
circuit of any other converter.
- Isolate the input circuits from
each other by connecting all the
inputs to a common point using a
start connection. Add a 2.2 μF
bypass capacitor at the start
connection if necessary.
- Add a SMT ferrite bead before
the input capacitor of each
converter, and a 2.2 μF or similar
bypass capacitor before the
ferrite bead.
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EN5322QI
Design Considerations for Lead-Frame Based Modules
Exposed Metal Pads on Package Bottom
QFN lead-frame based package technology utilizes exposed metal pads on the bottom of the
package that provide improved thermal dissipation and low package thermal resistance, smaller
package footprint and thickness, large lead size and pitch, and excellent lead co-planarity. As the
EN5322 package is a fully integrated module consisting of multiple internal devices, the lead-frame
provides circuit interconnection and mechanical support of these devices resulting in multiple
exposed metal pads on the package bottom.
Only the two large thermal pads and the perimeter leads are to be mechanically/electrically
connected to the PCB through a SMT soldering process. All other exposed metal is to remain free of
any interconnection to the PCB. Figure 6 shows the recommended PCB metal layout for the EN5322
package. A GND pad with a solder mask "bridge" to separate into two pads and 24 signal pads are to
be used to match the metal on the package. The PCB should be clear of any other metal, including
traces, vias, etc., under the package to avoid electrical shorting. Solder mask should cover the PCB
in all areas under the package.
Figure 6. Recommended Footprint for PCB.
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October 2007
EN5322QI
Package and Mechanical
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October 2007
EN5322QI
Additional Products
Part Number
EP5352QI
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EQ5352DI
EQ5362DI
EQ5382DI
EN5312QI
ER5312DI
EN5335QI
EN5336QI
EN5365QI
EN5366QI
Description
500 mA dc-dc with integrated inductor; 5 mm x 4 mm x 1.1 mm package
600 mA dc-dc with integrated inductor; 5 mm x 4 mm x 1.1 mm package
800 mA dc-dc with integrated inductor; 5 mm x 4 mm x 1.1 mm package
500 mA dc-dc regulator; tiny 3 mm x 2 mm x 0.9 mm DFN package
600 mA dc-dc regulator; tiny 3 mm x 2 mm x 0.9 mm DFN package
800 mA dc-dc regulator; tiny 3 mm x 2 mm x 0.9 mm DFN package
1 A dc-dc with integrated inductor; 5 mm x 4 mm x 1.1 mm package
1 A dc-dc regulator; tiny 3 mm x 2 mm x 0.9 mm DFN package
3 A dc-dc with integrated inductor; 10 mm x 7.5 mm x 1.85 mm QFN package
3-Pin VID VOUT programming
3 A dc-dc with integrated inductor; 10 mm x 7.5 mm x 1.85 mm QFN package
External resistor divider VOUT programming
6 A dc-dc with integrated inductor; 12 mm x 10 mm x 1.85 mm QFN package
3-Pin VID VOUT programming; Parallel capable
6 A dc-dc with integrated inductor; 12 mm x 10 mm x 1.85 mm QFN package
External resistor divider VOUT programming; Parallel capable
Contact Information
Enpirion, Inc.
685 Route 202/206
Suite 305
Bridgewater, NJ 08807
Phone: 908-575-7550
Fax: 908-575-0775
Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is
believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may
result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment
used in hazardous environment without the express written authority from Enpirion..
©Enpirion 2007 all rights reserved, E&OE
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www.enpirion.com