Preliminary
EN5364QI
Feature Rich 6A Voltage Mode
Synchronous Buck PWM DC-DC Converter
with Integrated Inductor
RoHS Compliant - Halogen Free
Description
Typical Application Circuit
The EN5364QI is a Power Supply on a Chip
(PwrSoC) DC to DC converter in a 68 pin QFN
module. It has a rich feature set to facilitate ease
of use in systems that are sensitive to beat
tones. The switching frequency can be
synchronized to an external clock or other
EN5364QIs with the added capability of phasing
multiple EN5364QIs as desired. Other features
include precision Enable threshold, pre-bias
monotonic start-up, margining and parallel
operation. During parallel operation, the phase of
switchers can be controlled to minimize ripple.
VIN
47µF
VOUT
47µF
XFB
SS
15nF
PGND
AGND
Figure 1: Simple Layout.
The Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity
by offering greatly simplified board design, layout
and manufacturing requirements.
•
All Enpirion products are RoHS compliant and
lead-free manufacturing environment compatible.
•
Temp Rating
Package
(°C)
-40 to +85
68-pin QFN T&R
QFN Evaluation Board
VOUT
AVIN
PGND
Features
Part Number
EN5364QI-T
EN5364QI-E
PVIN
ENABLE
EN5364QI is specifically designed to meet the
precise voltage and fast transient requirements
of present and future high-performance, lowpower processor, DSP, FPGA, ASIC, memory
boards and system level applications in a
distributed power architecture. Advanced circuit
techniques, ultra high switching frequency, and
very advanced, high-density, integrated circuit
and proprietary inductor technology deliver highquality, ultra compact, non-isolated DC-DC
conversion. Operating this converter requires
very few external components.
Ordering Information
1Ω
•
•
•
•
•
•
•
•
•
•
•
Integrated Inductor, MOSFETS, Controller in
a 8 x 11 x 1.85mm package
Wide input voltage range of 2.375V to 5.5V.
> 20W continuous output power.
High efficiency, up to 93%.
Output voltage margining
Master/slave configuration for paralleling
multiple EN5364QIs for greater power output.
Programmable phase delay between Master /
Slave and Slave / Slave devices for lower
output ripple.
5MHz operating frequency with ability to
synchronize to an external system clock or
other EN5364s. Multiple EN5364s on a
system board can be phase locked to
eliminate beat frequencies. Programmable
phase delays allow reduction of input ripple.
Monotonic output voltage ramp during startup with pre-bias loads.
Precision Enable pin for accurate sequencing
of power converters and Power OK signal.
Programmable soft-start time. Soft Shutdown.
Thermal shutdown, Over current, short circuit,
and under-voltage protection.
RoHS compliant, MSL level 3, 260C reflow
*Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success.
20090304
Preliminary
EN5364QI
Applications
•
•
•
•
•
•
Point of load regulation for low-power
processors, network processors, DSPs,
FPGAs, and ASICs
Low voltage, distributed power architectures
with 2.5V, 3.3V or 5V rails
Computing, broadband, networking,
LAN/WAN, optical, test & measurement
DSL, STB, DVR, DTV, Industrial PC
Beat frequency sensitive applications
•
•
Applications requiring monotonic start-up with
pre-bias
Ripple voltage sensitive applications
Noise sensitive applications
Pin Configuration
Below is a top view diagram of the EN5364QI package.
Figure 2: Top View of Package
NOTE: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or
damage.
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Preliminary
20090304
EN5364QI
Pin Descriptions
PIN
NAME
FUNCTION
1-4
PGND
5-13
VOUT
14-24
NC
25-26
27-33
SW
PGND
34-43
PVIN
44-46
NC
47
PGND
48
S_OUT
49
S_IN
50
M_S
51
EN_PB
52
ENABLE
53
AVIN
54
POK
55
AGND
56
XFB
57
EAOUT
58
NC
59
SS
60
S_DELAY
61-62
MAR[1:2]
63
VSENSE
64-68
PGND
Output power ground. Refer to layout section for specific layout requirements.
Regulated converter output. Decouple with output filter capacitor to PGND. Refer to
layout section for specific layout requirements
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground. One or more of these pins may be connected
internally.
Output Switching Waveform port
Output power ground. Refer to layout section for specific layout requirements.
Input power supply. Connect to input power supply. Decouple with input capacitor to
PGND. Refer to layout section for specific layout requirements
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground. One or more of these pins may be connected
internally.
Output power ground. Refer to layout section for specific layout requirements.
Digital Output. Depending on the mode, either a clock signal synchronous with the
internal switching frequency or the PWM signal is output on this pin. These signals
are delayed by a time that is related to the resistor connected between S_Delay and
AGND.
Digital Input. Depending on the mode, this pin accepts either a input clock to phase
lock the internal switching frequency to or a PWM input from another EN5364QI.
This is a Ternary Input put. Floating the pin disables parallel operation. A low level
configures the device as Master and a High level configures the device as a slave.
This is the Enable Pre-Bias Input. When this pin is pulled high, the Device will support
monotonic start-up under a pre-bias load.
This is the Device Enable pin. A high level enables the device while a low level
disables the device.
This is the Input voltage to the controller. A quiet supply!
Power OK is an open drain transistor for power system state indication. POK is a
logic high when VOUT is with -10% to +20% of VOUT nominal. Being a open drain
output several devices may be wired to logically AND the function. Size pull-up
resistor to limit current to 4mA when POK is low.
This is the quiet ground for the controller.
This is the External Feedback input pin. A resistor divider connects from the output to
AGND. The mid-point of the resistor divider is connected to XFB. The output voltage
regulates so as to make the XFB node voltage = 0.600volt.
Optional Error Amplifier output. Allows for customization of the control loop.
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground. One or more of these pins may be connected
internally.
A soft-start capacitor is connected between this pin to AGND. The value of the
capacitor controls the soft-start interval.
A resistor is connected between this pin and AGND. The value of the resistor controls
the delay in S_OUT.
These are 2 ternary input pins. Each pin can be a logical Lo, Logical Hi or Float
condition. 7 of the 9 states are used to modulate the output voltage by 0%, ±5%,
±10% or ±15%. The 8th state is used to by-pass the delay in S_OUT.
This pin senses the output voltage when the device is placed in the Back-feed (or
Pre-bias) mode.
Output power ground. Refer to layout section for specific layout requirements.
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Preliminary
20090304
EN5364QI
Block Diagram
S_OUT
M_S
PVIN
S_IN
To PLL
Digital I/O
UVLO
MAR1/2
Thermal Limit
Current Limit
Over Voltage
P-Drive
NC(SW)
VOUT
(-)
PWM
Comp
(+)
N-Drive
EAOUT
PLL / Sawtooth
Generator
PGND
Compensation
Network
(-)
XFB
Error
Amp
(+)
ENABLE
SS
Reference
Voltage
selector
Soft Start
EN_PB
EAOUT
MAR1
power
Good
Logic
POK
Bandgap
Reference
MAR2
Figure 3: System block diagram.
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Preliminary
20090304
EN5364QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond
recommended operating conditions is not implied. Stress beyond absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER
Input Supply Voltage
Voltages on: EN, EN_PB
Voltage on XFB
Voltages on: EAOUT
Voltages on: SS, PWM, S_IN, S_OUT, MAR[1:2]
Voltages on: POK
Storage Temperature Range
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
SYMBOL
MIN
MAX
UNITS
VIN
-0.5
-0.5
-0.5
-0.5
-0.5
-0.5
-65
7.0
VIN
2.5
2.5
3.0
VIN + 0.3
150
260
2000
V
V
V
V
V
V
°C
°C
V
TSTG
Recommended Operating Conditions
PARAMETER
Input Voltage Range
Output Voltage Range
Operating Ambient Temperature
Operating Junction Temperature
SYMBOL
MIN
MAX
UNITS
VIN
2.375
V
VOUT
0.60
TA
TJ
-40
-40
5.5
VIN –
0.1*ILOAD
+85
+125
V
°C
°C
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient (0 LFM) (Note 1)
Thermal Resistance: Junction to Case (0 LFM)
Thermal Overload Trip Point
Thermal Overload Trip Point Hysteresis
SYMBOL
TYP
UNITS
θJA
θJC
TJ-TP
20
1.5
+150
20
°C/W
°C/W
°C
°C
NOTES:
1. Based on a four-layer board and proper thermal design in line with JEDEC EIJ/JESD 51 Standards.
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Preliminary
20090304
EN5364QI
Electrical Characteristics
NOTE: VIN=5.5V over operating temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
SYMBOL
Input Voltage
Output Regulation
VIN
Feedback Pin
Voltage
VOUT
Feedback Pin
Voltage
VOUT
TEST CONDITIONS
MIN
TYP
2.375
2.375V ≤ VIN ≤ 5.5V,
ILOAD = 1A; TA = 25°C
2.375V ≤ VIN ≤ 5.5V,
0A ≤ ILOAD ≤ 6A
-40 ºC ≤ TA ≤ +85 ºC
Transient Response (IOUT = 0% to 100% or 100% to 0% of Rated Load)
VIN = 5V, 1.2V < VOUT < 3.3V
Peak Deviation
∆VOUT
COUT=50uF
Output Voltage Ripple
VIN = 5.0V, VOUT = 1.2V, IOUT = 6A,
Peak-to-peak
COUT = 5 x 10µF X5R or X7R
∆VOUT-PP
MLCC
Under Voltage Lockout
Under Voltage Lock
VIN Increasing
VUVLO
out threshold
VIN Decreasing
Switching Frequency
Switching
FSWITCH
Free Running frequency
Frequency
Phase-Lock Range (Note 3)
Phase-Lock
PLL Pull range about free running
FPLL
Frequency range
frequency
S_IN Duty Cycle
M_S Pin Float or Low
SYDC
for SYNC
S_IN Duty Cycle
M_S Pin High
SYDC
for PWM
Phase-Delay (Note 3)
Phase Delay
Phase delay programmable via
between S_IN and
resistor connected from S_Delay to
ΦDEL
S_OUT
AGND.
Phase Delay
Delay By-Pass Mode
between S_IN and
ΦDEL
S_OUT
Phase Delay
Accuracy
Phase Delay vs.
Delay in nsec / kΩ
S_Delay Resistor
ΦDEL
Delay in phase angle / kΩ value
@ 5MHz switching frequency
Load Characteristics
Maximum
IOUT
Continuous Output
(Note 1)
Current
Current Limit
The OCP Trip level
IOCP
Threshold
Supply Current
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MAX
UNITS
5.5
V
0.588
0.600
0.612
V
0.582
0.600
0.618
V
5
%
<20
mV
2.2
2.1
V
5
MHz
4.5
5.5
MHz
20
80
%
10
90
%
20
150
ns
10
ns
20
%
-20
2
3.5
6
ns
°
A
13.5
A
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Preliminary
20090304
Shut-Down Supply
Current
IS
EN5364QI
ENABLE=0V
µA
250
Precision Enable Operation
Disable Threshold
VDISABLE
Enable Threshold
Enable Pin Current
Thermal Shutdown
Thermal Shutdown
Hysteresis
Pre-Bias Start-Up
VENABLE
IEN
Pre-Bias Level
Non-Monotonicity
Power OK/GOOD
TSD
VPB
VPB_NM
Allowable Pre-Bias as a fraction of
programmed output voltage for
monotonic start up
Allowable non monotonicity
POK Deglitch Delay
VPOK Logic Low
level
VPOK Logic High
level
Parallel Mode Operation
∆IOUT
1.0
V
1.30
50
V
µA
150
20
°C
°C
1.10
Silicon junction temperature
Range of output voltage as a
fraction of programmed value
when POK is asserted. (Note 2)
Falling edge deglitch delay after
output crossing 90% level
VOUT Range for POK
= High
Current Balance
Max voltage to ensure the
converter is disabled
2.375V ≤ VIN ≤ 5.5V
VIN = 5.5V
20
85
50
mV
90
120
50
%
us
With 4mA current sink into POK pin
0.4
With 2 – 4 converters in parallel,
the difference between any 2 parts.
∆VIN < 50mV; RTRACE < 10mΩ.
%
V
VIN
V
+/-10
%
Output Rise Time
VOUT Rise Time
Accuracy
Logic Levels
Ternary Logic Low
Threshold
Ternary Logic High
Threshold
Binary Logic Low
Threshold
Binary Logic High
Threshold
Ternary pin Input
Current
∆TRISE
TRISE = Css* 65KΩ;
10nF ≤ CSS ≤30nF
-25
+25
%
0.4
V
2.7
V
(Notes 3, 4)
VT-Low
Threshold voltage for Logic Low
VT-High
Threshold voltage for Logic High
(internally pulled high; can be left
floating to achieve logic high)
2.0
0.8
VB-Low
1.8
VB-High
IITERN
The ternary pin has 100kΩ to
AGND and another 100kΩ to an
internal 2.5V supply. It is voltage
clamped to ~2V. If connecting to
VIN recommend using a series
resistor. See Figure-5
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See
Figure-5
µA
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Preliminary
20090304
EN5364QI
NOTES:
1. Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements.
2. POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing the
90% level, there is a 256 clock cycle (~50us) delay before POK is de-asserted. The 90% and 92% levels are nominal
values. Expect these thresholds to vary by ±3%.
3. Parameter not production tested but is guaranteed by design.
4. Rise time begins when AVIN > VUVLO and Enable=HIGH.
Features
•
•
Precision Enable Threshold: The Enable threshold is a precision Analog voltage rather
than a digital logic threshold. Precision threshold along with choice of soft-start capacitor helps
to accurately sequence multiple power supplies in a system.
Margining: The nominal output voltage can be increased / decreased by 5, 10 or 15% for
system compliance, reliability or other tests. The POK threshold voltages scale with the
margined output voltages. The following table provides truth table.
MAR-1
MAR-2
Float
Low
High
Low
High
Low
High
Float
Float
Float
Low
Low
High
High
Float
Float
High
Low
Output Modulation
Changes planned to
values listed below
0%
-5%
+5%
-10%
+10%
-15%
+15%
Delay By-Pass
Reserved
Table 1: Margining Truth Table
•
•
•
Pre-Bias Operation: When Device EN_PB is asserted, the device will support a monotonic
output voltage ramp with the output capacitor charged to a pre-bias level. Proprietary
circuit ensures the output voltage ramps monotonically from pre-bias voltage to the
programmed output voltage. Monotonic start-up is guaranteed for pre-bias voltages
between 20% and 85% of the programmed output voltage.
Phase-Lock Operation: With M_S pin floating or at a logical ‘0,’ the internal switching
clock of the DC/DC converter can be phase-locked to a clock signal applied to S_IN.
The clock logic levels are <0.4V and >2.0V. The clock frequency should be within ±10%
of the free running frequency. A delayed copy of the internal switching clock is available
at S_OUT. The magnitude of delay is controlled by the value of the resistor connected
between S_Delay and AGND pins. Multiple EN5364QI devices on a system board may
be daisy chained to reduce or eliminate input ripple as well as avoiding beat frequency
components.
Master / Slave Operation: Multiple EN5364QI devices may be connected in a Master /
Slave configuration to handle very large load currents. One Master device can directly
control up to 4 Slave devices or one Master device may control any number of Slave
devices in a daisy chain. The Master device’s switching clock may be phase-locked to
an external clock source or another EN5364QI. The device is set in Master mode by
pulling the M_S pin low or in Slave mode by pulling M_S pin high. When this pin is in
Float state, parallel operation is not possible. In master mode, the internal PWM signal
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Preliminary
20090304
•
•
•
•
•
•
EN5364QI
is output on the S_OUT pin. The PWM signal at S_OUT is delayed relative to the
Master device’s internal PWM signal. (The magnitude of delay is controlled by the value
of the resistor connected between S_Delay and AGND pins.) This PWM signal from the
Master can be fed to one or more Slave devices at its S_IN input. The Slave device acts
like an extension of the power FETs in the Master. The inductor in the slave prevents
crow-bar currents from Master to slave due to timing delays. The Slave device puts out
its own delayed PWM on S_OUT which could feed the next device in the daisy chain.
As a practical matter, paralleling more than 4 devices may be very difficult from the view
point of maintaining very low impedance in VIN and VOUT lines.
Phase Delay: When multiple EN5364QIs are used on a board, the phase delay function
may be used advantageously for reducing input / output ripple. The phase delay can be
used in two ways. First, the EN5364QIs can all be phase locked by feeding the S_OUT
of one device into the S_IN of the next device in a daisy chain. All the switchers are now
switching at a common frequency. However, the phase delay among the switching
waveforms may be controlled by an appropriate choice of a resistor that is connected
from the pin S_Delay to AGND. The magnitude of this delay is approximately 2ns/kΩ or
3.5°/kΩ (@5MHz) of resistance subject to a minimum / maximum delay as given in the
table of electrical characteristics. Second, when multiple EN5364QIs are used in parallel
to support a large load, one device acts as a master device whose PWM output is fed to
other EN5364QIs operating as slaves. Although all the devices are switching at the
same frequency and duty cycle, their phases can be controlled by an appropriate choice
for S_Delay resistor. The Master / Slave parallel mode operation is described in more
detail in a separate application note.
Over Current Protection: When the load current exceeds the over current protection
trip level the power FETs are placed in a high impedance state and the device enters a
hiccup mode. The output is disabled for 8192 clock cycles (~1.6ms) followed by a
normal soft-start. The device remains in hiccup mode as long as the fault persists.
Power OK / Good: Power good (POK) signal is asserted when the output voltage is
between 90% and 120% of the nominal. When VOUT is rising the POK threshold is
nominally at 92% of steady state VOUT. When VOUT is falling, the nominal threshold is
90% of steady state voltage. If VOUT exceeds 120% of programmed value, POK is deasserted and the power NFET is turned on. This event could cause the input power
supply to EN5364QI to enter a over current condition.
Soft-start circuit: to limit the in-rush current when the converter is powered up. The
soft-start interval is programmable through choice of Soft-start capacitance.
Thermal shutdown: When the device gets beyond the safe operating temperature, the
output is shutdown. Adequate hysteresis is provided to prevent chatter at trip point.
Under-voltage lockout: UVLO circuit disables the converter output when the input
voltage is less than approximately 2.2V to ensure that operation does not begin before
there is adequate voltage to properly bias all internal circuitry.
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Preliminary
20090304
EN5364QI
Output Voltage Setting / Phase-Lead Capacitor Details
VOUT
RA = 30, 000*Vin (value in Ω)
RA
CA
4.72*10−6
CA =
RA
(Cout & CA in Farads , RA in Ω )
XFB
RB
RB =
AGND
Figure 4:
Vref
Vout − Vref
RA
Output voltage resistor divider and phase-lead capacitor calculation. The above formulas ensure
optimum loop bandwidth for any Vin and Vout combination. The equations need to be followed in the
order written above.
2.5V
R1
100k
Maximum value of
Rext = (VIN -2)*67k
Rext
VIN
To Gates
100k
D1
Vf ~ 2V
R2
100k
Input pin current
= (VIN-2)/Rext
R3
7k
AGND
EN5364QI
Figure 5: Figure shows means to select Rext value to be used when connecting MAR-1, MAR-2 and / or M_S pins
to VIN.
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Preliminary
20090304
EN5364QI
Phasing Multiple EN5364QIs (An Example)
P/AVIN
R1
EN5364QI
S_IN
CO1
R3
S_OUT
VOUT2
XFB
C11
R11
EN5364QI
S_IN
CO2
R13
P/AVIN
S_D ELAY
C1
VOUT
S_D ELAY
XFB
P/AVIN
S_OUT
VOUT1
P/AGN D
P/AVIN
S_IN
VOUT
P/AGN D
(Optional)
S_D ELAY
XFB
EXT_CLK
X1_2
X1_1
VOUT
P/AGN D
X1
S_OUT
VOUT3
C21
R21
EN5364QI
CO3
R23
R2
R12
R22
P/AGND
Figure 6: Example of Synchronizing multiple EN5364QIs in a daisy chain with phase delay.
VDRAIN- 1
Delay ~ 140°
VDRAIN- 2
VDRAIN- 3
Delay ~ 120°
Figure 7: Example of a possible way to synchronize and use delays advantageously to minimize input ripple.
R3 ~ 39kΩ, R13 ~ 33kΩ. (Refer to Figure 6 for R3 and R13.)
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Preliminary
20090304
EN5364QI
Typical Performance Characteristics
Efficiency
Efficiency
95
90
90
85
E fficiency (% )
E fficiency (% )
95
1.2
2.5
80
75
85
1.2
80
2.5
75
3.3
70
65
60
70
0
1
2
3
4
5
0
6
1
2
3
4
5
6
Load (Amps)
Load (Amps)
Efficiency vs. Load: VIN = 3.3V; VOUT = 2.5, 1.2V
Efficiency vs. Load: VIN = 5.0V; VOUT = 3.3, 2.5, 1.2V
Start-up waveform: VIN = 5.5V, VOUT = 3.3V, Load = 6A
Ch.1 – Enable, Ch.2 – VOUT, Ch.3 - POK
Start-up waveform: VIN = 5.5V, VOUT = 1.2V, Load = 6A
Ch.1 – Enable, Ch.2 – VOUT, Ch.3 – POK
Output Ripple: VIN = 5.0V, VOUT = 1.2V, COUT = 1x47uF
(1206) + 1x10uF (0805)
Output Ripple: VIN = 3.3V, VOUT = 1.2V, COUT = 1x47uF
(1206) + 1x10uF (0805)
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Preliminary
20090304
EN5364QI
Load Transient: 0-6A Step. VIN = 5.0V, VOUT = 1.2V
Load Transient: 0-6A Step. VIN = 3.3V, VOUT = 1.2V
Start-up waveform in Back-feed (Pre-bias mode)
VBF = 400mV, VOUT = 2.5V
Start-up waveform in Back-feed (Pre-bias mode)
VBF = 1.9V, VOUT = 2.5V
Delay (ns)
Delay vs. S_Delay Resistance
180
160
140
120
100
80
60
40
20
0
Series1
0
20
40
60
80
100
S_Delar R (kohm)
Delay vs. S_Delay Resistance
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Preliminary
20090304
EN5364QI
Theory of Operation
Synchronous Buck Converter
The EN5364QI is a synchronous, programmable
power supply with integrated power MOSFET
switches and integrated inductor. The nominal
input voltage range is 2.375-5.5V. The output
voltage is programmed using an external resistor
divider network. The feedback control loop is a
type III, voltage-mode and the device uses a lownoise PWM topology. Up to 6A of continuous
output current can be drawn from this converter.
The 5MHz operating frequency enables the use
of small-size input and output capacitors.
The power supply has the following protection
features:
• Over-current protection with hiccup mode.
• Short Circuit protection.
• Thermal shutdown with hysteresis.
• Under-voltage lockout circuit to disable the
converter output when the input voltage is
less than approximately 2.2V
Output Voltage Programming
The EN5364 output voltage is programmed using
a simple resistor divider network. A phase lead
capacitor is required for stabilizing the loop.
Figure 4 shows the required components and the
equations to calculate their values.
Input Capacitor Selection
The EN5364QI requires between 40-80uF of
input capacitance. Low ESR ceramic capacitors
are required with X5R or X7R dielectric
formulation. Y5V or equivalent dielectric
formulations must not be used as these lose
capacitance with frequency, temperature and
bias voltage (please see Table 2).
In some applications, lower value ceramic
capacitors maybe needed in parallel with the
larger capacitors in order to provide high
frequency decoupling.
Output Capacitor Selection
The EN5364QI has been optimized for use with
output capacitance between 47µF and 150µF.
The phase lead capacitor value depends on the
the output capacitance as shown in Figure-4.
Low ESR ceramic capacitors are required with
X5R or X7R dielectric formulation. Y5V or
equivalent dielectric formulations must not be
used as these lose capacitance with frequency,
temperature and bias voltage (please see Table
3).
The EN5364 output voltage is determined by the
voltage presented at the XFB pin. This voltage is
set by way of a resistor divider between VOUT and
AGND with the midpoint going to XFB.
Description
MFG
P/N
47uF, 10V,
X5R, 1206
Taiyo Yuden
LMK316BJ476ML-T
22uF, 10V,
X5R, 1206
Taiyo Yuden
Murata
LMK316BJ226ML-T
GRM31CR61A226ME19L
Table 2: Recommended input capacitors.
©Enpirion 2009 all rights reserved, E&OE
Description
MFG
P/N
47uF, 10V,
X5R, 1206
Taiyo Yuden
LMK316BJ476ML-T
47uF, 6.3V,
X5R, 1206
Taiyo Yuden
Murata
JMK316BJ476ML-T
GRM31CR60J476ME19L
22uF, 6.3V,
X7R, 1206
Taiyo Yuden
Murata
JMK316B7226ML-T
GCM31CR70J226KE23L
10uF, 10V,
X7R, 0805
Taiyo Yuden
Murata
LMK212C106KG-T
GRM21BR71A106KE51L
Table 3: Recommended output capacitors.
Output ripple voltage is primarily determined by
the aggregate output capacitor impedance. At
the 5MHz switching frequency output impedance,
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Preliminary
denoted as Z, is comprised mainly of effective
series resistance, ESR, and effective series
inductance, ESL:
Z = ESR + ESL.
Placing multiple capacitors in parallel reduces
the impedance and hence will result in lower
ripple voltage.
1
Z Total
=
1
1
1
+
+ ... +
Z1 Z 2
Zn
Typical ripple versus capacitor arrangement is
given below:
Typical Output Ripple (mVp-p)
(as measured on EN5364QI
Evaluation Board)
1x47uF + 1x10uF
<30
5 x 10 uF
<20
Table 4. Output ripple vs capacitor configuration.
Output Capacitor
Configuration
Compensation
The EN5364 uses of a type III compensation
network. Most of this network is integrated.
However a phase lead capacitor is required in
parallel with upper resistor of the external
feedback network (see Figure 4). Total
compensation is optimized for use with a
minimum of 47µF output capacitance and will
result in a wide loop bandwidth and excellent
load transient performance for most applications.
The equations shown in Figure 4 are valid for
Cout up to 150µF at the voltage sensing point.
Additional capacitance may be placed beyond
the voltage sensing point outside the control
loop. Voltage mode operation provides high
noise immunity at light load. Further, Voltage
mode control provides superior impedance
matching to ICs processed in sub 90nm
technologies.
In exceptional cases modifications to the
compensation may be required. The EN5364QI
provides the capability to modify the control loop
response to allow for customization for specific
applications. For more information, contact
Enpirion Applications Engineering support.
©Enpirion 2009 all rights reserved, E&OE
EN5364QI
Enable Operation
The ENABLE pin provides a means to start
normal operation or to shut down the device. The
Enable threshold is precisely set by a voltage
reference. This allows precision sequencing of
multiple EN5364QIs. When the ENABLE pin is
asserted high, the device will undergo a normal
soft start. As the output voltage ramps up (ramp
rate controlled by choice of soft-start capacitor) a
second device may be Enabled using this ramp.
The second device will start up after a well
defined time given by the ramp rate and the
precise threshold level.
Soft-Start Operation
The SS pin in conjunction with a small external
capacitor between this pin and AGND provides
the soft start function to limit the in-rush current
during start-up. During start-up of the converter
the reference voltage to the error amplifier is
gradually increased to its final level by an internal
current source of typically 10uA charging the soft
start capacitor. The typical soft-start time for the
output to reach regulation voltage, from when
AVIN > VUVLO and Enable crosses its logic high
threshold, is given by:
TSS = CSS * 65KΩ (seconds)
Where the soft-start time TSS is in seconds and
the soft-start capacitance CSS is in Farads.
Typically, a capacitor of around 15nF is
recommended. A proper choice of SS
capacitance can be used advantageously for
power supply sequencing using the precision
Enable threshold.
During a soft-start cycle, when the soft-start
capacitor voltage reaches 0.60V, the output has
reached its programmed regulation range. Note
that the soft-start current source will continue to
charge the SS capacitor beyond 0.6V. During
normal operation, the soft-start capacitor will
charge to a final value of ~1.5V.
Soft Shutdown
When the Enable signal is de-asserted, the soft-
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Preliminary
start capacitor is discharged in a controlled
manner. Thus the output voltage ramps down
gradually. The internal circuits are kept active for
the duration of soft-shutdown, thereafter they are
deactivated.
POK Operation
The POK signal is an open drain signal from the
converter indicating the output voltage is within
the specified range. The POK signal is asserted
when the rising output voltage crosses 92%
(nominal) of the programmed output voltage.
POK is de-asserted ~50us (256 clock cycles)
after the falling output voltage crosses 90%
(nominal) of the programmed voltage. POK is
also de-asserted if the output voltage exceeds
120% of the programmed output. If the feedback
loop is broken, POK will remain de-asserted
(output < 92% of programmed value!) but the
output voltage will equal the input voltage. If
however, there is a short across the PFET, and
the feedback is in place, POK will be de-asserted
as a over voltage condition. Also, the power
NFET is turned on resulting in a large input
supply current. This is turn is expected to trip the
OCP of the power supply powering the
EN5364QI.
POK is an open drain output. It requires an
external pull up. Multiple EN5364QI’s POK pins
may be wired NOR with a single pull up. The
open drain NFET is designed to sink up to 4mA.
The pull-up resistor value should be chosen to
limit the current from exceeding this value when
POK is logic low.
Over-Voltage Protection
There is no over voltage protection caused by a
open at XFB node.
©Enpirion 2009 all rights reserved, E&OE
EN5364QI
Over-Current Protection
The current limit function is achieved by sensing
the current flowing through a sense P-FET.
When the sensed current exceeds the current
limit, both NFET and PFET switches are turned
off. If the over-current condition is removed, the
over-current protection circuit will re-enable the
PWM operation. If the over-current condition
persists, the circuit will continue to protect the
load.
The OCP trip point is nominally set to 225% of
maximum rated load. In the event the OCP circuit
trips, the device enters a hiccup mode. The
device is disabled for ~1.6msec and restarted
with a normal soft-start. This cycle can continue
indefinitely as long as the over current condition
persists.
Thermal Overload Protection
Thermal shutdown will disable operation when
the Junction temperature exceeds approximately
150ºC. Once the junction temperature drops by
approx 20ºC, the converter will re-start with a
normal soft-start.
Input Under-Voltage Lock-Out
When the input voltage is below a required
voltage level (VUVLO) for normal operation, the
converter switching is inhibited. The lock-out
threshold has hysteresis to prevent chatter.
Parallel Device Operation
The EN5364QI is capable of paralleling up to a
total of four converters to provide up to 24A of
continuous current. Please refer to the Parallel
Operation Application note, available on the
Enpirion website www.enpirion.com, for details
on parallel operation.
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20090304
EN5364QI
Layout Recommendations
Under Development
Figure 8: Layout of power and ground copper.
Figure 9: Use of thermal & noise suppression vias.
Recommendation 1: Input and output filter
capacitors should be placed as close to the
EN5364QI package as possible to reduce EMI
from input and output loop currents. This
reduces the physical area of the Input and
Output AC current loops.
These vias can be the same size as the
thermal vias discussed in recommendation 3.
Recommendation 5: The system ground
plane referred to in recommendations 3 and 4
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the
converter and the input/output capacitors
shown in figure 8.
Recommendation 2: Place a slit in the
input/output capacitor ground copper starting
just below the common connection point of the
device GND pins as shown in figures 8 and 9.
Recommendation 6: As with any switch-mode
DC/DC converter, do not run sensitive signal or
control lines underneath the converter
package.
Recommendation 3: The large thermal pad
underneath the component must be connected
to the system ground plane through as many
vias as possible. The drill diameter of the vias
should be less than 0.33mm, and the vias must
have at least 1 oz. copper plating on the inside
wall, making the finished hole size around
0.26mm. This connection provides the path for
heat dissipation from the converter. Please see
figures: 9, 10 and 11.
Please refer to the Gerber files and
summarized layout notes available on the
Enpirion website www.enpirion.com for more
layout details.
NOTE: Figures 8 and 9 show only the critical
components and traces for a minimum footprint
layout. ENABLE, Vout-programming, and
other small signal pins need to be connected
and routed according to the specific
application.
Recommendation 4: Multiple small vias
should be used to connect ground terminal of
the input capacitor and output capacitors to the
system ground plane as shown in figure 6.
©Enpirion 2009 all rights reserved, E&OE
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Preliminary
EN5364QI
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, ,
and in overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the
lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached.
This results in several small pads being exposed on the bottom of the package.
Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to
the PC board. The PCB top layer under the EN5364QI should be clear of any metal except for the
large thermal pad. The “grayed-out” area in Figure 7 represents the area that should be clear of any
metal (traces, vias, or planes), on the top layer of the PCB.
Figure 8 demonstrates the recommended PCB footprint for the EN5364QI. Figure 9 shows the shape
and location of the exposed metal pads as well as the mechanical dimension of the large thermal pad
and the pins.
Figure 10: Lead-Frame exposed metal. Grey area highlights exposed metal that is not to be mechanically or
electrically connected to the PCB.
©Enpirion 2009 all rights reserved, E&OE
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20090304
Preliminary
EN5364QI
Figure 11: Recommended footprint for PCB.
©Enpirion 2009 all rights reserved, E&OE
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Preliminary
EN5364QI
Package Dimensions
Figure 12. Package dimensions.
©Enpirion 2009 all rights reserved, E&OE
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Preliminary
EN5364QI
Contact Information
Enpirion, Inc.
685 Route 202/206
Suite 305
Bridgewater, NJ 08807
Phone: 908-575-7550
Fax: 908-575-0775
Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is
believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may
result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment
used in hazardous environment without the express written authority from Enpirion.
©Enpirion 2009 all rights reserved, E&OE
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