CADLINC INC.
Processor Specifications
Nu.ber:
Author:
Approved:
000014 Rev: A
. /. a /~.~.~­
~
~------- ------~~
Georse A. iewicz
p-~--~
Walter Siekierski
TABLE
1.
or
CONTENTS
Introduction •••••••••••••••••••••••••••••••••••••••••••••••••••• 1
2. Overview of Operation ••••••••••••••••••••••••••••••••••••••••••• 2
2.1. Central Processins Unit (CPU) ••••••••••••••••••••••••••••••••• 2
2.2.
"eaorw.I •••••• ~ •••••••••••••••••••••••••••••••••••••••• ••••••• 2
2.3.
Busei ••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 2
2.4.
InPUt - OutPut Devices •••••••••••••••••••••••••••••••••••••••• 3
2.5.
InterrUPts •••••••••••••••••••••••••••••••••••••••••••••••••••• 3
2.6.
Boot State •••••••••••••••••••••••••••••••••••••••••••••••••••• 3
2.7.
He.orv Hanase.ent ••••••••••••••••••••••••••••••••••••••••••••• 4
3. Theorv Of OPeration ••••••••••••••••••••••••••••••••••••••••••••• 5
3.1.
Introduction •••••••••••••••••••••••••••••••••••••••••••••••••• 5
3.2. Control Losic ••••••••••••••••••••••••••••••••••••••••••••••••• 5
3.2.1. Co••and Generation ••••••••••••••••••••••••••••••••••••••••• 16
3.2.1.1. Status Co..ands •••••••••••••••••••••••••••••••••••••••••• 19
3.2.1.2. Svste. Access Co••ands ••••••••••••••••••••••••••••••••••• 20
3.2.1.3. Hanased Access CO••ands •••••••••••••••••••••••••••••••••• 21
3.2.2. Reset Lo.ic •••••••••••••••••••••••••••••••••••••••••••••••• 22
3.2.3. Boot Lo.ic ••••••••••••••••••••••••••••••••••••••••••••••••• 23
3.2.4.
Interrupt Losic •••••••••••••••••••••••••••••••••••••••••••• 25
3.3. Heaorv H.na!e.ent •••••••••••••••••••••••••••••••••••••••••••• 27
3.3.1. Svste. Accesses •••••••••••••••••••••••••••••••••••••••••••• 27
3.3.1.1. Heaorv
"a~ •••••••••••••••••••••••••••••••••••••••••••••••
28
3.3.1.2. Context R•• ister ••••••••••••••••••••••••••••••••••••••••• 30
3.3.1.3. Proas •••••••••••••••••••••••••••••••••••••••••••••••••••• 32
3.3.1.4.
~D
9513 Ti.er ••••••••••••••••••••••••••••••••••••••••••• 33
3.3.1.4.1 •. Introduction ••••••••••••••••••••••••••••••••••••••••••• 33
3.3.1.4.2. Functional
Descri~tion
••••••••••••••••••••••••••••••••• 34
3.3.1.4.3. Ti.er Co•• ands ••••••••••••••••••••••••••••••••••••••••• 3S
3.3.1.4.4. Cadlinc OPeratint Hodes •••••••••••••••••••••••••••••••• 36
3.3.1.5. Intel 8274 UART •••••••••••••••••••••••••••••••••••••••••• 38
3.3.1.5.1.
Introduction ••••••••••••••••••••••••••••••••••••••••••• 38
3.3.1.5.2. Functional Description ••••••••••••••••••••••••••••••••• 38
3.3.1.5.3. UART Co ••ands •••• '.. • •••••• • •••••• •• • • • • • • • • •••• • • •• •••• 39
3.3.1.5.4. Cadlinc Operatins Hodes •••••••••••••••••••••••••••••••• 39
3.3.1.6. Parallel InPUt Port •••••••••••••••••••••••••••••••••••••• 41
3.3.1.7. Hardware VPA ••••••••••••••••••••••••••••••••••••••••••••• 41
3.3.2. Hanased Accesses ••••••••••••••••••••••••••••••••••••••••••• 42
3.3.2.1. Raa He.orv ••••••••••••••••••••••••••••••••••••••••••••••• 42
3.3.2.1.1. Locll He.orv ••••••••••••••••••••••••••••••••••••••••••• 43
3.3.2.1.2. Local Parity Lotic ••••••••••••••••••••••••••••••••••••• 44
3.3.2.1.3. HiShspeed Bus Interface •••••••••••••••••••••••••••••••• 46
3.3.2.2. Hultibus Interface ••••••••••••••••••••••••••••••••••••••• 47
3.3.2.2.1. Bus Haster Arbitration ••••••••• •i.
If ••••••••••••••••••••
47
3.3.2.2.2. He.orv Access •••••••••••••••••••••••••••••••••••••••••• 48
3.3.2.2.3.
r-o
Access ••••••••••••••••••••••••••••••••••••••••••••• 48
4. Bo.rd Kne.onies •••••••••••••••••••••••••••••••••••••••••••••••• 49
4 .1.
Buses'. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• S2
4.2. Ca..lnds ••••••••••••••••••••••••••••••••••••••••••••••••••••• 53
4.3. Co••unic.tians ••••••••••••••••••••••••••••••••••••••••••••••• S9
4.4. Hishspeed Bus •••••••••••••••••••••••••••••••••••••••••••••••• 61
4.5. Hultibus ••••••••••••••••••••••••••••••••••••••••••••••••••••• 63
4.6. Deyices •••••••••••••••••••••••••••••••••••••••••••••••••••••• 66
4.7. Heaorv Hanase.ent •••••••••••••••••••••••••••••••••••••••••••• 67
Appendix A - Ju.per Options ••••••••••••••••••••••••••••••••••••••••• 69
Appendix A.l
J81 •••••••••••••••••••••••••••••••••••••••••••••••••• 69
Appendix A.2
JB2 •••••••••••••••••••••••••••••••••••••••••••••••••• 70
Appendix A.l
J8l •••••••••••••••••••••••••••••••••••••••••••••••••• 71
Appendix A.4
JB4 •••••••••••••••••••••••••••••••••••••••••••••••••• 72
Appendix B
Initial He.orv Happins ••••••••••••••••••••••••••••••••• 73
Appendix C - Hultibus Bus Pin Assisnaents (Pl) •••••••••••••••••••••• 79
Appendix D -·Hishspeed Bus Pin Assisn.ents (P2) ••••••••••••••••••••• 80
Appendix E
Co••unications and Parallel Ports •••••••••••••••••••••• 81
Appendix F
Protection PRO" Code ••••••••••••••••••••••••••••••••••• 82
Appendix G
PAL Codes •••••••••••••••••••••••••••••••••••••••••••••• 84
Appendix G.l
PALPO •••••••••••••••••••••••••••••••••••••••••••••••• 85
Appendix G.2
PALP1 ••••••••••••••••••••••••• ·••••••••••••••••••••••• 86
Appendix G.l
PALP2 •••••••••••••••••••••••••••••••••••••••••••••••• 87
Appendix G.4
PAlPJ ••••••••••••••••••••••••••••••••••••••• i •••••••• 88
Appendix G.5 - PALP4 •••••••••••••••••••••••••••••••••••••••••••••••• 89
LIST OF TABLES
a
Table 1 -
S~5te.
Access State Flow •••••••••••••••••••••••••••••••••
Table 2
Hana~ed
Access State Flow tor Hishspeed Access ••••••••••• 11
Table 3 - Hanased Access State Flow tor Multibus Access •••••••••••• 14
Table 4 -
He.or~ Hana~e.ent
Table 5 -
Pa~e
Tlble 6
Context
Address Translation •••••••••••••••••••• 28
Hap Data Entries •••••••••••••••••••••••••••••••••••• 29
Re~ister
Data For.at ••••••••••••••••••••••••••••• 30
Table 7 - Multiplexed Ra. Addresses •••••••••••••••••••••••••••••••• 43
LIST OF ILLUSTRATIONS
Fi.ure 1
Control Lo.ic Block Di •• r •••••••••••••••••••••••••••••••• 6
Fi§ure 2
Svste. SPice Access Ti.in•••••••••••••••••••••••••••••••• 7
Ft.ur. 3
Ra••nd Hilhspeed Access Tl.in •••••••••••••••••••••••••• 10
Fi.ure 4
Hultlbus Access Ti.in••••••••••••••••••••••••••••••••••• 13
Fisur. 5
Clock State Generator Circuit ••••••••••••••••••••••••••• 17
Fifure 6
CO••and Generation •••••••••••••••••••••••••••••••••••••• 18
FilUre 7
Reset Circuit ••••••••••••••••••••••••••••••••••••••••••• 24
Fi.ure 8
Boot Circuit •••••••••••••••••••••••••••••••••••••••••••• 24
Fi.ure 9
Interrupt Control Circuit ••••••••••••••••••••••••••••••• 26
Fifure 10
Ti •• r Function Di •• r ••••••••••••••••••••••••••••••••••• 37
Fifure 11
UART Function Dia.r•••••••••••••••••••••••••••••••••••• 40
Fi.ure 12-- Parltv Lofic Block Di •• r ••••••••••••••••••••••••••••••• 45
1. Introduction
The CADLINC Series BOA Processor board consists of a Motorola
68000 central processins unit. RAM and PROM .e.or~, so.e 1/0 facilities, a local HIGHSPEED .e.or~ bus and an IEEE-796 MULTIDUS * intertaee. Onboard .e.or~ consists of 4 JEDEC st~le b~te-wide PROM sockets, and 2S6K b~tes of d~na.ic RAM. The 1/0 facilities are two serial
co••unications ports, a 16-bit bidirectional port and a S channel prosra•• able ti.er.
The Series BOA Processor can be used as a standalone s~ste. with
a power suppl~, backplane and serial ter.inal, or as part of a
fully inte~rated co.puter syste. that can include the CADLINC GRAPHICS
CONTROllER, ETHERNET board, MULTIFUNCTION board, DUAL PORT MEMORY
boards, FLOATING POINT Processor board, INTELLIGENT SERIAL CONTROLLER
board and .an~ other HULTIBUS cOIP3tible peripherals.
onl~
* HULTIBUS is a trade.ark of Intel Corp.
2. Overview
of
Operation
2.1. Central Processins Unit (CPU)
The Kotorola 68000 has a 16-bit data bus and a 23-bit address
bus. The internal resisters are 32-bits in lensth. It has 8 data and
7 address resisters. 2 stack pointers. a proSra. counter. plus a 16bit status word. Operations on data .ay be byte (8), word (16), or
Ions word (32 bits). Operations on addresses _ay be ot word or Ions
word lensth. All resisters .ay be used as indexes. The 68000 has 2
states of operation: Supervisor and User for enhanced syste. inteSritv
and security.
Onboard PROH consists ot 4 JEDEC stvle PROH sockets that can
accept 2732, 2764, 27128 or 27256 type ROHs (total capacity of 16K,
32K, 64K or 128K bytes respectively).
Onboard RAH cOllsists of 36 64K x 1 dYna.ic ra.s dvins a capacity
of 256K bytes with paritv. RAH refreshinS is done by a PROH .onitor
routine that executes 128 NOP instructions every 2 .illiseconds. The
prosra••able ti.er sene rates the Non-Haskable- Interrupt.
2.3. Buses
The CADLINC Series aOA Processor has 3 bus structures. The first
is the internal svnchronous bus for Svste. accessed 1/0 and Heaerv
Hanase.ent; the second is a proprietarY synchronous HIGHSPEED BUS on
the Auxiliary HULTIBUS connector for expanded DUAL PORT HEHORY, FLOATING POINT and ENHANCED SERIAL Processor boards; and the third is the
HUlTIBUS for expanded off-the-shelf peripherals. i.e. Disc controllers, ETHERNET, GRAPHICS CONTROllER, etc. Svste. I/O devicu and
onboard RAH do not reauire the use of the HUlTIBUS.
1.
Onboard ae.orv accesses are faster than the Hultibus.
2.
The HULTIBUS is then available for use by
other bus .asters without havins to contend
for priority very often.
3.
DUAL PORT HEMORY responds IS fast as onboard RAH
and is i ••ediately available to other bus .asters.
The Svste. 1/0 devices. onboard PROH and 2S6K bytes ot Local RAH
are not accessible to other bus .asters.
2.4.
Input - Output Devices
The Series BOA Processor board has a dual channel UART chip, S
prosraaaable ti.ers, and a 16-bit bidirectional port tor seneral purpose use. One of the UART's channels is contisured to coaaunicate
with a terainal or CADLINC keyboard dependins on the PROH aonitor supplied. The other channel can be Juapered with another coaputer or a
second terainal. The line drivers and receivers are RS-423 coapatible
and the connector pinouts are RS-232-C confisuration. Two at the tive
16~bit counter/tiaers are dedicated baud-rate Senerators for the U~RT
chip, one tiaer channel tor each serial channel. One tiaer is dedicated to Sene rate a 2-aillisecond interrupt to retresh dYnaaic RAH.
One of the two reaainins tiaers is aVlilable for user IPplications.
The other acts as a ·Watchdos· tiaer to auto.aticallY reset the systea
if the PROM .onitar proSra. has lost control. The 16-bit bidirectional port is desisned tor readins options selections froa a bank of
switches and to write status intoraation to a static displaY. .
2.5.
Interrupts
The 68000 has seven interrupt levels and I current interruPt
level .ask. An interrupt will be processed if its level is Sreater
than the current aask. Level 7, the hishest priority. is Non-Haskable
and will alwavs interrupt any task. This level is reserved for the
dyna.ic RAH refresh routine.
The standard HULTIBUS confisuration detines interrupt levels INTO
to INT7, with INTO beins the hishest priority. The CADLINC Series BOA
Processor defines priorities accord!ns to the Hotorola conventions
with INT1 as the hiShest. INTO, then, is not iapleaented and INTI is
the lowest prioritv.
PreassiSned interrupts on the.CADLINC Series
tallows:
INT7:
INT6:
INTS:
~
Processor are
IS
Refresh tiaer (Non-Haskable)
User prosra.aable ti.er
UART sene rated interrupts
Interrupts are processed by the 68000 in 'Auto-Vector' aode only.
Transter vectors are supplied troa an internal table, so the interruptins device need not supply a vector.
2.6.
Boot State
At power-on or whenever a hardware reset is done. the Processor
enters Boot State. In Boot State, the first onboard PROH pair overlavs
RAH start!ns at location O. All reads then coae froa PROH, but writes
can So to RAH. This enables the 6BOOO to fetch its initial proSraa
counter and svstea stack pointer froa PROH locations 0-3. RAH, then.
aay also be initialized. All interrupts, ineludins the Non-Maskable
INT7, are disabled bv hardware. When Boot State is exited, NonMaskable interrupt is enabled, but .askable interrupts will depend on
the current .ask level.
Boot State is terainated b~ one write to the
tion CLEARBOOT. See Device addresses.
S~stea
Access loca-
The Heeorv Hanaieaent s~stea has been desi~ned to support a
aulti-taskins operatini svstea. The concept, in short, is that ot
translatins, or aappins, Processor address bits A12-A21 (or A22) into
ph~sical
address bits HA12-HA23, alons with Protection, Address Space
Allocation and Pase Control inforaation about each Pa~e.
All accesses to local RAH and to HULTIBUS aeaorv Ind I/O are
translated and protected in the saae aanner.
Hanased Address access is initiated bv Processor address bit A23.
When it is ·on·, Heaorv Hanaseaent is disabled and indicates a Svste.
Access is to be perforaed. When it is ·off·, then the Processor
addresses A12-A21 (or A22) co.bine with pre-pro~raaaed Context bits to
for. a pointer into a 4K x 20 bit Arrav. The output of this Arrav contains the 12-bit Happed ph~sical address and B Protection arid allocation bits. The 12 HanaSed Addresses co.aine with the lower 11 Processor addresses to fora the 23-bit ph~sical address, ~ivins • full 16M
b~tes of phvsical space.
There are two aodes of coabinini Context bits with Processor
addresses: One· with 1 Context bit, hence 2 levels of Context; the
other with 2 Context bits havins 4 levels of Context. In the first
aode, Cont~xt bit CXO co.bines with Processor address bits A22 and A21
as the .ost sisnificant bits into the Arrav. 'In the second, Context
bits CX1, CXO and Processor address A21 are the aost sisnificant.
Hence, the first aode ~ields 2 Contexts of 8H bvtes .ach and the
second ~ields 4 Contexts of 4H bvtes each.
tion.
Context bits CXO and CXI are accessabl. vi.
See Device Addresses.
I
Svste. Access loca-
Durins a Svste. Access, hardware autoaaticallv swaps the upper
Processor address and Context bit(s) with lower Processor address bits
A2-A13. This allows a pro~raa in Supervisor state to access everv Context b~ aanipulation of Al2 and A13 durins a read or write to the Svstea Access Hap location.
3.
3.1.
Theor~
Of Operation
Introduction
The Processor divides UP its 16 Hb~tes of address space into two
8 Hb~te resions: S~ste. Space and Hanased Space. Systea space
coaprises the on-board PROHs, Tiaer, Uart, Parallel Port and Heaor~
Hanase.ent resisters. Hana~ed space consists at Local Heaor~, the
Hishspeed bus and Hultibus accesses.
Hanased space is divided into 2 (or 4) Contexts, each capable of
containins processes as lar~e as 8 Hb~tes (or 4 Hb~tes) in ph~sical
aeao~. The Heaor~ Hanase.ent Unit contains 4096 entries that filter
Virtual Processor addresses into Ph~sical addresse~ and supports the
full 16 Hb~tes of ph~sical space.
3.2. Control Losic
See scheaatic drawinss tSD29S014
See Appendices F and G for tir.ware codes.
See Fisure 1 Control Block Diasraa
The Series BOA Processor board aakes exten~ive use of Prosraa.able Arra~ Losic I.C.s to perfor. necessar~ co.aand ti.ins and direction control. Fisure 1 is an overall block diasra. that shows the
flow of input control and output co•• and sisnals.
The followins State Tables and Ti.ins Diasraas describe in Seneral the actions of the control losic. Reter to the PAL eQuations in
Appendix G.
After leavins Boot State, the control losic decides what SPace a
virtual address will stteaPt to access on evetv 68000 evcle by the
.a1n Address Strobe (as-) and the level of address bit 823. It 823 is
hiSh, a Svste. Access is reauested and, it the 68000 is in supervisor
state, then On-board devices, Heaory Hanase.ent raa and Boot clear
accesses are allowed. It a23 is low, then so.e Hanased Access is
reauested and different losic is enabled based on the state of Pase
Control bits (Bus I Local: b/l-, and 1/0 I Heaorv: 10/a-). The~ are
stored in the He.or~ Hanase.ent Raa alons with each pase at the
translated Virtual to Ph~sical addresses.
FIgure 1 - CadI Inc
Ser Jes 80A
Processor
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Decode
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Data and
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Connector
-
HIghspeed
r-----------i
I J2
-
Address
Buffers
Local
P2
256k byte
-
-
-
-
-
I
I
I
I
I
i
I
I
.J
L..
Data
-,
I
Commands
Command
Generat Jon
Address
68000
-,---,..-------r---r---r--..=!..
---------,
\.
I
I
I
I
Hult Ibus
Data
Buffers
.-1
CPU
r------
"1
I
7
Interrupt I I
Memory
I
LInes
LogIc
It
Management
I PI
I
L _ _ _ _ _ _ -'
I I
SID
IL..-------------'
I
Tlmer---'
IL _ _Refresh
I
_ _ _ _ _ .J
Hultlbus
Address
Latches
HuH Jbus
Commands
L
\
I
!
I
I
I
I
I
I
I
I
I
_ _ _ _ _ _ _ _ _ .J
1
clee
,
i: 5e
1
1
1
~: 51
1
1
V: 52 ~ 53 I
;~
I\~
kft7l
01: 23
0.-: Q)' 0
r - Ii~
, rI w-~
I
I~
'
: \. _ _ 60
54 \
55
I
56 \
57
I
58 \
59
I
51e \
511
I
512 ~ 513
;
1 ),
II
.
________________________________________
~ _ ~ _ ../
I
:L .
I
I
,
sysacc-
I
<
~----~------------------------------------------------------------------------~~:A--
xae:ll
____________________
(en.mapxwe.mapx- )
(devenabce.dev Jeesce.map- )
cs6
~
________________________
~
I
I
I
~~I---------------------------------------------------_r_4V
I
:,
'\~-~i-------------~~'.~------------_r---------------------------------------------------~---~:
I
, ~
,
I
________________________
I
I
/1 :
~------------------~-J
WrJie
de:15
Read
de:15
I
II
I
~---
N~,--..--..-------------,
--------..--~~{1\'-~
A
...
--------+----------------------/:
diac~-
I
I~l
AI
( Jorc- ------------------------~------------------;I ~
lowc- )
csle
I
~
~
:!t--0
cs3
>
,
:\~---\,
I ~I
( Jdsuds-)
r
I
I
ffi7
~LW-J
I· \ I
I
:,~,
14~_______________________'____~~~:~I:
--------------------------------------------------------------------------------------~~ :~
'--,~I
1
State --1I________________________________________________________
Description (See Figure 2)
1I__________
1I
f State o. 1
Processor addresses a1 thru a23 are negated ('1). I
1
1
r/w- is asserted to a Read ('6) at the end ot everY I
1
1 c~cle.
I
1____________1-I
1
__________________________________________________ 1
I State 1.
I
f
1--_____---__
State 2.
I
I
I
Processor addreses a1 thru a23 are asserted ('3). I
a23 is high indicatins a Systea access reauest. SyS- I
tea device address decodes.
1
1_--___--------------------------------------_-----_-----1
1
I
I
I
Processor strobes ('S- for all ~cles, lds:uds- tor
read c~cles) becoae valid ('5). sysacc is asserted
·hiSh·. ds senerated in a Read c~cle. For a Write
c~cle, r/w- is asserted (.6a).
____________11_____________________________ _..
I
I
1
1
____--1I
State 3. 1 cs3 asserted ('7). Processor drives Data Bus dO:d15 I
for a Write c~cle (U-U.
____________1I_____________________________________________________
--11
State~.
I
I
1
I
cs~
('7) asserted. Hultiplexed Addresses now switch
to upper Processor addresses (.ac).
lds:udsasserted on a Write cycle. ds sene rated in a Write
cycle.
I
I
1
1
I
I
____________1________________________________________________________1
State 5.
cs5 (17) asserted. a_csS- asserted (.ab) indicatinl I
l
Ith
e Hultiplexed Address Bus 'is valid.
1
____________
1---___________________________________________________
-1I
Table 1 - Systea Access State Flow
Note: Nuab,rs within
the Fisures.
I()'
reter to ballooned nuabers in
State
Description (See Fisure 2)
•1____________
1I ________________________________________________________
1I
1 State 6. 1 cs6 asserted. iorc- or iowc- Iccerted for access to 1
ith
e Ti.er or UART.
1l
____________
1 ________________________________________________________
11
State 7. 1----____________________________________________________
1 cs7 asserted. No action.
.11
1____________
1 State 8. I csS asserted. No action.
1
I
1
I
1______- 1 ______________________________1
cs9 asserted. Ho action.
State 9. 1--_____________________________________________________
1____________
-1
1 State 10. 1
1
1
1_____
cliO asserted. csl0 .enerates dtack- to the 68000.
-.1._________ ____________
No action.
1__________________________________
1
I
1
___
1 State
11. I
1__
__ __
_11
I State 12. I
1
I
1
I
1
I
Cvcle ter.inates. Ne.ate III strobes (.12). Hetate I
all Clock States (.ll). Slave keeps Data bus valid I
until til. Hetate Data Bus on a Write CYCle (.15).
I
I
• ____________1 ___________________ .. ___________________________________1
Table 1 - Svstea Access Stat.e Flow cont'd
Hate: Hu.o~rs within '()' refer to ballooned nu.ber. in
the Fi.ures.
os-
,
Ids: uds-
I ,
-' -' -! .~=--<!)
rlwm_rlw-
,
- --
01:23
mo12:23
I
, '-J,.',
I
,
I
'
cs3
m_preq-~__~~~~~~~======~~
cs_walt- ~!~
m_wa Itm_a0:7
____~~'1~~~~~
__
~~
cs4(mux)
cs5
(m_cs5- )
dtack-
___
--l:~
___
I
,
·1
access::
,
access:'
-,-I'r
~-~:~:
---------Jo..&-:4
I
'
'
i
I
I
~I--E®-=-H----~.:--"'--3~~
FIgure
3
®
Ram and HIghspeed Access Tim lng
State:
Description: (See Fi~ure 3)
1______________
1I______________________________________________________
1I
I State O.
I
I
I
I Processor addresses al thru a23 are ne~ated (t1).1
I Hi~hspeed Bus Hi~h Order Addresses are ne.ated (t2).1
I r/w- is asserted to a Read (.6) at the end of ever~1
I cvcle.
t
I
I
,
1______________1 ______________________________ . __________ ... _ _ _-1
, State 1.
I Processor addreses al thru a23 are asserted (t3).1
,
I Hi.hspeedHultiplexed Addresses __ aO:7 beco.e valid.'
I
I Hi.hspeed Bus Hi.h Order Addresses ._aaI7:23 beeo.el
t valid atter Heaorv Hana.eaent translation (.4). Pa.el
I
I Control bits b/l- and iol.- also beeo.e valid_______
(.4), 1I
1I______________1---_______________________________________
I State 2.
I
I
I
I
I
I
I
Processor strobes (as- for all eveles. Ids:uds- fori
read evcles) becoae valid (.5). Clock State senera-I
tor reset is deactivated. For Write evele. r/w- isl
ISserted (.6a).
I
1________ ___________________!I
I
I
1__________
I State J.
I esl asserted (.7). ._prea- and es_wai t- asserted I
I
I fro. es3 (.8). Processor drives Data Bus a_dO:dI5-1
I for a Write evele (.14).
1,______________1___________________________________
_-1I
I State Wait.
I
I
I
I
One Wait inserted auto.atieallv bv es_wait- follow-I
in. el00. Clock State .enerator skips one advance.1
For a Write evcle. strobes lds:uds- are asserted I
(.5). es_wait- is ne.ated to allow the next svste.1
clock ed.e to bu.p the .enerator.
I
I_______L______________
I
,
________
Table 2 - Hanased Access State Flow tor Hi.hspeed Access
Note: Nu.bers within 'C)' reter to ballooned nuabers in
the Fi!lures.
I
.1
1
'State:
Description: (See Fi~ure J)
1
_____________ 11______________________________________________________
1I
I State 4.
1
1
I
,
1
cs4 (17) asserted. Hultiplexed Addresses now I
switch to upper Processor addresses <Iec). I
cs_wait- disabled.
I
1____________ 1I ____________________________________________ 1I
I State 5.
I
cs5 (11) asserted. a_csS- asserted <lOb) indicat- I
I
I
in~
the Hult1plexedAddress Bus 1s valid. Proces- I
sor dtack- asserted.
,I____________1I________________________________________________
11
I State 6.
I
I
I
1___________
No action.
I
,
1____________ ____________________ .. ______ _1
Data Bus a_dO:15- captured on a Read c~cle
I
(110
&
111>.
1________________________ _ ______ ____________________1I
1 State 7.
I
1_____________ I
1 State O.
I
I
1
1
1
t ____________ I
1
C~cle terainates. Ne~ate strobes (112). Nesate all I
Clock States <11J). Ne~ate a_pres- (116). Nesate 1
Data Bus a_dO:15- on a Write cvcle (11S).
I
1________________________
Table 2 - Hanased Access State Flow for
Hi~hspeed
_1I
Access cont'd
Note: Nuabers within '()' refer to ballooned nuabers in
the Fi!lures;
osIds:uds·- .
r/w-
I
I
I I'
r---I-!J
I
I I
I
01:23
m012:23
cs3
bO$-
-..----.j-!..-.I~.
cs_wo dcs4 (mux)
cs5, cs6
b_ 00:02.3- ---...---4-~
oen- den- cen- _________~~~=P~~--~---r~
7
t c-,
I
(mr7 dc-, mw
I
I
I
I
I
I
~~~--l:__....JII
iorc-,
iowc- )
.:
1
I
II
1
1
I
b_ X 0 ck ~ ___---!-:_ _ _ _---«-t.$A-.'-t-:--JI""'-:--t=-F::
dto c k:
$ " \......
!-----,-1--1.
b_ d0: 15 -
1
I
Read access: 1
I
_--....:__---J$~®~10J'----<~'i__!_ _-.,-~~: '®
access::
I
~;6®~:~------~;~
Figure 4 -
Multibus Access Timing
----------------------------------------------------------------------1
State:
I Description: (See _
Filure
4)
1I_________________
1----______________
_____________________________
11
I State O.
1
I
1 Processor addresses al thru a23 are nelated (.1). I
I
I r/w- is asserted to a Read (.6) It the
I end at everV cvcle.
I
I _________________1-_____________________________
I
1
__________________1I
Processor addreses a1 thru a23 are asserted
Hanased hish order addresses .,12:23 beco.e
atter He.orv Hanale.ent translltion (14).
'Control bits b/l- and io/.- also beco.e
State 1.
(+3).1
validl
Pasel
valid'
1_________ _____ ____________
1_ _ _ _ _ • __ _ I <t4).
I State 2.
I
,
I
I Processor strobes ('5- for all eveles, Ids:uds-I
'for read cvcles) beco.e valid <.5). Clock Statel
, senerator reset is deactivated. For Write evcle,1
,
I r/w- is asserted (.6,).
.....1_____ _____ _____._ .____
I
1___________
,
I
I
I
I
,
!
csl Isserted (.n. bas- and cs_wait- Isserted fro. I
cs3 (.8). Bus arbitration bv the 8289 belun. Pro-I
cessor drives Data Bus dO:dlS- for a Write evclel
(.14). If .en- is asserted, then the Hultibusl
co
••and shift relister is_ _________________________
enabled.
______________________
1I
One Wait inserted auto.aticallY bv cs_wait- fol-I
lowins cl00. Clock State senerltor skips one I
advance. For I Write evele. strobes Ids:uds- arel
asserted (.5). cs_wait- is ne.atedto Illow thel
I.
next syste. clock edse to bu~ the Senerltor.
,
_________________1______
State 4
_____
I
I State 3.
I
1
I
I
I
I
I
1I_________________ 1I
State Wait.
1I
_ ___________ •••• _________
_ ______ _
I
1
+ Wait. , cs4 <.7) asserted. CI_wait- disabled. Ids- isl
I latched to produce aOO. If len- is asserted. then I
I the Hultibus Data bus b_dO:d15- is activated boJ'
, den-. Byte or Word transfers are deter.ined by thel
state ot aOO. Direction is deter.ined by r/w-. -1,
_________________ 1,_________________________________________________
Table 3 - Hanased Access State Flow for Hultibus Access
Note: Nu.bers within '()' refer to b.llooned nu.bers in
the Fisures.
I
St.te:
Description: (See Fiiure 4)
1I________________
11____________________________________________________
1I
I State 5 t Wait.1 cs5 (+7) asserted. Processor addresses aOl~all,1
I
I Hanaled addresses a.12~23 and the state at the .001
I
I latch are clocked into the Hultibus Address resis-I
I
I terse It aen- is asserted, the Addresses arel
I
I driven onto the Hultibus b_aO:a23-. cen- is also 1
I
I senerated and enables the Hultibus coa.and driYer.1
I ______________1__________________
I
1.
_______________________________1I
I State 6
I
I
+ Wait.1
A Hultibus coa.and (towe-, io~, awte- or arde-) I
I is lenerated and butfered to the Hultibusl
I (b_iowc-. b_iorc-, b_.wtc- or b_.rde-) it cen- isl
I asserted.
I
I All coa.and. data and address drivers and I
I receivers now re.ain active until b_xack- isl
___________________1_________________________
I received fro. the tars.t device.
______________________-1I
St.te Last -2. I
I
I
I
b_xack- is received fro. the Hultibus. Processor I
dtack- is asserted. Current evcle belins to ter-I
.inate. It the coaaand was lowc-, dtack- asserted I
will nesate it earlier than the other co••ands.
I
I
I
1
__________1________
. _________ . ______
Stat. Last -1. I No action.
I
_______________.1 ___________________________________________ ______--1
State Last.
I
I
I
I
I
Cycle ter.inates. Nesate'strobes (t12). 'Nesate alii
Clock States (+13). Nesate current co..and.1
Nesate bas- (+16) and Illow other Hultibus "astersl
to be sranted. Nesate Dlta Bus b_dO:15- on a Writel
cycle et15).
I
________1I ___ .. ________________________________ _ _1I
Table 3 - Hanased Access State Flow tor Hultibus Access. cont1d
Hot.: Nu.bers within
the Flsures.
I()I
ref.r to ballooned nu.b.rs in
3.2.1. Coaaand Generation
See Scheaatic .295014 Pages Sand 1 tor specific IC's ant their locations.
See Fisure 5 - Clock State Generator and fisure 6 - Coaaand Generation
for an overview of the losic.
See Appendices G.l throush G.5 tor detailed PAL codes.
The .ajor s~stea ClOCKS on the Processor board (cl00, c200 and
c400) are produced by dividing the Raw crYstal oscillator outPUt c50
(PS S IC El) b~ 2, 4 and a, respectivel~, b~ a fast tour-bit counter
(IC F2)
Coaaand Ti.ins relationships are s~nchronized bv the use of a
Clock State Generator <Ps S IC H2), which is a 745299 Octal Shift
Resister with controls. The clOCK into the Generator is c50 double
buffered, so that when shifts are enabled, their outputs will so to
the Ihish l state on each edse of the 68000 syste. clock cl00.
The outputs of the senerator are Clock State sisnals, labeled csl
to csl0. The 68000 drives its co•• ands, as-, lds- and uds-, relative
to Ihish' states of the systea clock cl00. A c~cle beSins at State 0
with negating the address bus and drives the co ••ands at State 2. The
first State after as- is asserted is always csl.
The reset input of the Clock State Generator is none other than
as- froa the 68000, inverted, thus enablins it on every 68000 CYCle.
The chip has two operatinS states once enabled, "Shift" and "Do
NothinS", controlled by cswait- froa PALPl (PS 5 IC F6). Svste.
Accesses do not reauire inihibitins the Clock State senerator, so onlv
Manased Accesses (those with address a2l low and Boot off) need control cswait-.
When cswait- is used, it .ust coae before cs4 is shifted in. csl
Sene rates RAS-, cs4 .ultiplexes the Dynaaic Raa address lines and csS
senerates CAS- on the bank selected by Manased Address aa17.
J
I
MuH lbus CJoeks
74S240
74S163
19.6608
Mhz
Osel/Jator
OA
DB
DC
OD
e50
e100
e200
e400
e800
carry
b_belk-
' - - System Clocks Generator
elk
74LS163
74S240
enabto-
(8 inary Counters)
n/e
n/e
n/e
nle
p.
TImeout Generator
~
>-+---IT
elk
~
e a r r y l - - - - t lmeout
mr
Clock States Generate
as-
74LS04
mr
1/00
1/01
1/02
j/03
1/04
j/05
1/06
j/07
es3
es4
es5
es6
cs7
es8
es9
es10
es_wa It----( holdoe
74S299
(Sh 1ft Reg ISler)
FIgure
5 - CJock State Generator C Jreu 1+
I\IV-
PA LP0
.nelS
oa-
68000
Clock
State
Generator
-- }
1.1.-, ada,.Iw-
.- -
cs3
cs4
cs5
cs6
)
System
Commands
HIghspeed and
Local Commands
...
cs10
Memory
Management
PALP3
'--- m_preqbas-
--
blIlolm-
-
m_waJt-: from
H19hspeed Bus
)
Managed
Commands
)
cswa It-: Clock
State Controls
Memory
} Management
Controls
PALP2
- - berrdtackCycle Acknowledge Inputs
Cycle Error Inputs
)
ds and bhen
Byte Access Controls
PALP!
Managed Addresses
Par lty Data & Enables
Hlghspeed and Local Commands
m_perr- from Hlghspeed Bus
~)
Par Ity Controls
~)
Onboard Rom
Control
I
F 'gure 6 - Command Generat Ion
3.2.1.1. Status Coaaands
See Appendices G.1 throu~h G.S tor detailed PAL codes.
See Fisure 6 - Coaaand Generation tor la~out of 10lical functions.
The Status ~oa.ands returned to the 68000 are reset-, halt-,
berr- and dtack-. halt- and reset- are discussed below.
To acknowledSe the 68000'5 data transfer to the various spaces,
dtack- is enabled bv two Clock States: csS ,lwavs and cs10 for S~ste.
Accesses and the special aode if an 1-0 Write to Hultibus.
Durins a Hanased Access, dtack- will latch itselt on if no error
is present (b~ berrx-). PaSe Control bits b/l- and io/.-, and Hultibus
response sisnals aen- and xack coaplete the necessa~ 101ic. The use
of cswait- will dela~ asserUnS csS (and csiO)
Durins a Svstea Access, berrx- is actuall~ asserted. but dtackis now Sene rated bv cs10 and is not latched.
Error silnals berr- (to the 68000) and berrx- (Extended berr-)
are Sene rated independentl~ but share the siae error conditions. The
berrx- sisnal is the siaPle ·or· of the four basic errors that can
happen: two (2) hardware faults - Tiaeout and Parity Error, and two
(2) Heaerv Hanaseaent faults - Protection Error (saaperr-) and Invalid
Pale attellPt.
Paritv Error aeans that soaethins is verv wrenl with Local or
HishsPeed Heaorv and should be investisated furiher. Ti.eaut, however,
can be useful in 10catinS what Hultibus devices and aeaorv Ire actuallv installed bv touchinl standard lacations and waitins far a
response.
The two Heaorv Hanaseaent faults keep the Operatins Svstea and
the User honest bv stoppins access to Virtual Addresses that are Protected or .apped Invalid. This sives the Processor bOlrd power for
coaplex Operation Svsteas to easilv aanase Heacrv Ind Devices.
When berr- occurs. the states af tiaeout, saaperr-, Plrerr- and
berrx- are latched into the Context Resister Ind can be valuable in
software when handlins the error. (See 3.3.1.2 for Context Resister
definitions. )
See Appendices G.4 and G.l for co.plete
lo~ic
eauations.
The .aJor S~ste. Access Co•• ands are initiated in two PAls, PALPJ
and PAlPO <Ps S IC F6, and P~ 1 IC FS, respectivelv). Svste. Access
Co••ands are those that control the access and direction of data for
On-board devices. Host are based on address a23 in the hish state and
decode the specific device with a22:a19.
Since access to On-board devices is privilaSed, the 68000'5 Function Code fc2 is sated to enable the co •• and onl~ when the 68000 is in
Supervisor state. The User, then, has access to these devices onlv
throush Svste. calls or Interrupts,
The current eauation for the sYsacc- and devenab- sisnals are
clarified as tallows:
s~sacc- will be low true (Hanased Access) when:
svsacc-
= as
* a23as- * boot * rw- * a23-
+ as- * boott
(Address Strobe off, no cvcle)
(Not in Bootstate and a23 low)
(1)
devenab- will be low true when:
deveanb-
=fc2 * ds * .23 * a22
+ fc2
(2)
* ds * a23- * a22- * a21- * a20- * 119- * booi * rw
Product line (1) enables a Hana~ed Acce'SS
to initialize On-board Dvnaaic Raa. This needs
Power-on Reset routines to setup valid aeaorv
area. Up to that point, subroutines could not
had to be in 68000 reSisters.
(3)
Write durins Booistate
to be done earlv in the
parity tor the Stack
be called and variables
Product line (2) enables for SUPervisor addresses startios It
OxCOOOOO, "
Product line (3) enables for Supervisor address OxO durins a
This branch forces access to PROM 0 as the 68000
Booistate Read.
besins to coae UP after Power-on or Resei.
3.2.1.3.
Hanated Access Co •• ands
The .aJorit~ of HanaSed Co •• ands are sene rated in PALP4 (Ps. 1
F4) and in PALP3 (Ps. 5 IC F6). These co •• ands include!
Ie
Control Clock States! ._wait-, cswait-.
Hultibus
He~or~
and 110 coe.ands;
erdc-,
.wtc-,
iorc-,
iowc-,
bas-.
Rae and Hishspeed: oe.raa-, we.rael;u-, __ preo-, onbrd-.
Pase Accesses: we •• apx-,
en.aapx~.
All of the above co.eands are enabled b~ the "low '
which in turn was enabled b~ the "low ' state of
address a23. The target bus is selected b~ bll- and iolaPaSe eap Raas ••preQ- and bas- are Sene rated b~ all of the
nals, except for the state of bll- (See PALP3).
s~acc-,
state of
the 68000
froa the
saae sis-
See Section 3.2.1 for discussion of cswait- and a_wait-.
Hultibus co.eands are not aade active until cs6 is asserted.
seQuence of events for a Hultibus acces are detailed in Table 3.
The
The 110 Write co•• and is a special case. There are aan~ devices
available for the Hultibus and have si.ilar coaaand response lotic for
He.or~, but 110 logic on soae var~ considerabl~ in their coepliance to
the Hultibus specification. When doing -an iowc- coe.and, b-xackasserted b~ the target board will cancel iowc- earl~. bas- and data
drivers will sta~ asserted until the noreal end at the c~cle (dtackasserted and as- negated two (2) hish clock states later).
we.ra.l:u- are directl~ buttered to the onboard Raes during all
valid Local or Hishspeed accesses. onbrd- discriainates between Local
and Highspeed accesses and controls generatins CAS- to the onboard
Raes. oe.ra.- enables the data bufters tor the Local Ra. and the
Hishspeed connector. a_prea- is the overall coe.and that starts soae
Local or Hishspeed access.
The PaSe Access coeaands allow the autoaatic updatins of the
"used" and the ·dirt~· status lines for the Pase beins updated. Ever~
ti.e a valid access to a Pate is eade, it is .arked as ·used". When
that Pate is written to, it is aarked "dirt~·so that the operatins
systea can keep track of aeaor~ allocations.
3.2.2. Reset Lo~ic
See Sche~atic t295014 PaSe 4.
See Figure 7 for la~out of Reset functions
In order to satisf~ the 68000 reauireaents for
reset- and halt- .ust be driven at the saae ti.e.
I
hard Reset, both
Hard Reset is senerated b~ "or-ins" several conditions tosether
to fora setinit- then buttered throush two open-collector drivers.
Conditions that sene rate setinit- are as tollows:
I
Reason:
Control:
1I_______________
1I______________________________________
___1I
~
Power On
I
I
I
I
,
IC D22 is a voltase coaparator that willi
trip its output when the aain Power Sup-I
pl~ voltase drops below 4.15 Volts. Rl
,
and C5 have the ettect ot slow ins the
I
turn-on tiae of the Suppl~.
,
External Reset'
,
,
External connections on the J2 Connector'
and, throush Juaper Block JB3, the Hul- ,
tibus b.init-.
,
,
,
,
,
Watchdos Tiaerl Prosra.aable Tiaer Channel 1. Usuall~ ,
/ setup to be soae larse count value that ,
I is restarted ever~ Retresh Interrupt. If/
/ the counter is allowed to count all the /
I wa~ down, then the Refresh function has ,
I so.ehow stopped, invalidatins .11 ot
/
I Local and Hlshspeed Heaor~.
_______________ 1_____________________________________
__lI
3.2.3. Boot Losic
See Sche.atic 1295014 PaSe 4.
See FiSfJre 8
At power-up or Reset to the 68000, the Processor board is in Boot
State. A hardware Reset condition (low-yolta~e cOIParator, external
Reset switch or Prosra•• able Watch-dos tiler output) is the si!nal
that sets the Boot flip-flop <Ps 4 Ie H4) and is also buffered to
drive reset- and halt- into the 68000, causin! a hard Reset. (This
does not affect the 68000 Reset instruction since reset- is then
driven b~ the 68000 itself.)
This is a te.pora~ condition that allows for loadins the initialization infornation into the 68000 at Virtual .elor~ address OxO.
Boot State makes the first Proa address enabled at OxO as well as its
noraal S~ste. Access address of OXCOOOOO. Once the Pro. lonitor loads
the initial startin! address <soaewhere above OxCOOOOO) then the 900t
flip-flop is reset and is onl~ re-entered by a hardware reset.
r--------------------------------,
+5
I
Voltage Comparator
+5
8211 V+
I
15K
100K
\,----4
~~--1
10uI
4.l5K
Power Level Log ic
tr Igger5 at +4.75V
hys
fhr
out
gnd
v-
r---------.l
745240
L. _ _ _ _ _ _ _ _ _ _ _ _ ~
,
7406 :
r---------------~
I
I
: c. tImer 1
: (from TJmer )
~
7406/505
In It
_______________ J
Figure
7 -
Reset
C!f'CU f-t
+5v
D S a
boot
In j'~
(from Reset
c frcu If above)
cfrboot(from PAlP0)
ClK
R
74S74
H4
F19ure 8 - Boot Clrcu ,.•
reset-
3.2.4.
Interrupt Losic
There are 7 allowable Interrupt levels into the 68000 cpu. The
hishest (Int 7) is reserved for executins the Refresh Routine ever~ 2
(or 4) .illiseconds. The next level Clnt 6) is a seneral purpose prosra.mable output of the AHD 9513 ti.er, as is the Refresh InterrYpt.
Level 5 Interrupts are defaulted to the UART for co ••unications.
Interrupt Levels 5 throush 1 are hardware wired to the Hultibusr
with Ju~pers available to add 6 and 7. All 7 Interrupt sisnals are
then latched into a resister CPs 5 IC K6) usins the 68000 s~ste. clock
clOO. These Latched sisnals so to a priorit~ encoder CPs 5 IC K7) to
provide a three-bit Interrupt code to the 68000 that is s~nchronous
with the s~ste. clock to avoid spurious traps.
Another function of Boot State is to disable all interrupts Just
after power-up or Reset. It's alwa~s possible for soae On-board device
or devices on the Hultibus to have an interrupt level active at
power-uP, and that can cause havoc if He.or~ has not ~et been initialized. The boot sisnal in the off state enables the Priorit~ Encoder
I.C. output.
Llni6Llni7b_lni5L Ini4L Ini3b_lni2L !nilL!nHJInt.510--!nt.! Imer2-
Ini6Int70--0 Ini50--0 Ini4c-o Ini30--01nt20-0 Inil0-0 Int0C
C
C
C
Interrupt
} Onboord
Seled Ion - J82
Int5Int6-
0-0
0-0
---l>- Int7-
c_re£resh
(from TImer)
741.374
Ocial Reg
,.f.,.
Int7Int6Int5Ini4Int3Int2Inil-
Int75Int65Ini55InH5Ini35Ini25Inil5CJ(
boot
Int7.
Int6s
iniSs
lni4s
Int3s
lni2s
Inils-
HuH Ibus Interrupt
Seled'lon - J84
All Interrupts
sync~rono.us wIth
Processor
Clock cl00
OE
IPI2-}
IpllIp10-
68000
Interrupt
PrlOr!ty
Levels
741.5148
p,.'O,.'tr
Encod.,.
FJgure 9 - Interrupt Control C Ircu It
The Series BOA Processor Helor~ Manaseaent unit consists of three
address lultiplexors, 5 fast 4096 x 4 static Ra.s, buffers tor High
and Low word access and a 512 x 4 PROH prosra.aed to decode Page
Access rights.
The processor is provided with a lap that can aap pases of 4K
an~where in the 16 "b~te address space.
During initialization,
the PROM Monitor sets UP the Pafe lap tables in a standard wa~ that
.akes all ae.or~ and I/O devices available to user prosrals. User
proSrals la~ change these ~aps as desired; however, page 0 and whatever pages are likel~ to contain the top ot the Supervisor Stack
should not be re.apped, otherwise .eao~ refresh .a~ tail.
b~tes
3.3.1.
S~ste.
Accesses
Ever~ 68000 bus c~cle
accesses soae Virtual .e.or~ location
within the 16 Hb~~e addressing ranse. When address bit a2l is "on", or
"hish", then the current c~cle is a S~ste. Access, hence occup~ing the
upper 8 "b~tes of available Virtual .e.or~.
--27--
The startin~ address for S~ste. Access to the He.or~ Hap is
OxSOOOOO. The sisnals ce •• ap- and we •• ap- are !enerated b~ PALPO (Ie
F5). When access into the He~or~ Hap Raas is reauested, the lower
address bus into those Raas is aultiplexed b~ the followins table:
Hanased
Access: I
Access: I
S~ste.
Translated Hapl
(a23 Low>
(a23 Hi!h)
Address:
__________________
1I ___________________
1I ________________
1I
cxO/cxl
a22/cxO
a21
a20
a19
a18
a17
a16
a15
a14
a13
a12
a13
a12
all
a10
a09
a08
a07
a06
a05
a04
a03
a02
xall
xa05
xa04
xaOO
xa01
xa02
xa03
xa07
xa06
xa08
xal0
xa09
I
I
1I __________________1 ___________________1 ________________1
Table 4 -
He.or~
Hanase.ent Address Translation
Initiall~, each pa!e of on-board RAH is aapped so that its ph~si­
cal and virtual addresses are identical. This' .eans that each se!.ent,
startins at sesaent 0, is full~ aapped (up to the li.it of available
.e.or~).
Pases are onl~ initialized for context O. Pase protection is
set so that both Supervisor and User aodes have Read, Write, and Execute access to e'ler~ ses.ent.
The enable control to the 4K x 4 is per.anentl~ active to allow
fast access durins a "anased c~cle. The Write co•• ands are separated
into Upper and Lower enables, dependins on address bit al (Sche. pg1>.
Writing to the Ra. that contains the four Pase Control infor.ais split into two conditions to !enerate we ••apx-: one for the
nor~al S~ste. access write (we.aapl-) and the other for
updatins the
used and dirt~ bits (en •• apx-).
tion
The preferred access to the
.oyes. This tor.at places the
word', or internal data 31-16,
Addresses in the "High word" or
o is located at address OxO, Hap
He.orv Hap is via Ions-word (32 bit)
Protection Code data bits in the 'Low
and the PaSe Control and Manased
internal data IS-0. ConseQuentl~, Hap
1 is at Ox4, etc.
--28--
The for.at at the data bus into the
Heaor~
Hap is as tollows:
I
Hap Entr~:
S~stea Data:1
1I___________________
11______________
1
Protection Code:
11__________________________________
11
1
I
1
PROT3
I
d19
I
1
PROT2
1
d18
I
PROT 1
I
d17
PROTO
d16
11______________
11
11___________________
I
1I __________________________________
11
Pa!e Control:
I
1
1
1
diS
1
I
I
d14
1
1
I
d13
1
1
(b/l-)
I
1
I
101 HeaorY
I
dl2
1
(io/.-)
1___________________
11______________11
1
used
dirty
buslloeal
Hanased Addresses:
1__________________________________
11
aa23
••22
.a21
a.20
.a19
dl1
dl0
d9
'd8_
d7
d6
.a18
.a17
d5
.a16
d4
aa15
d3
.•a14
d2
.a13
dl
.a12
dO
___________________
1______________
1
Table 5 - Pase Hap Data Entries
--29--
3.3.1.2.
Context
Re~ister
The starting address for a Svstea Access into the Context Resister is Ox880000.
The Context Resister is a one-word field whose bits reflect Yarious status inforaation about He_orv Hanaseaent integration, Refreshing
of dvna.ic aeaorv and Bus Error generation.
The for.at of data in the Context Register is as follows:
I
Data:
Function:
11_____________________________________________________
1I
11_______________
I
Read-Write:
I
I
1
I
I
,---------______1 __--___ ---------------------------------------_______1
dlS
I
,
I
I
d14
Refresh Enable - When "one", indicates to Slave
boards on the Hishspeed 8us to override Upper
Addre~s decoding to perait refreshing of
Dyna.ic
nas, if any.
I
1 Parity Enable - When 'one',
I
I
I
allows either Local
Parity Error detection or Hishspeed Parity Error
(a.perr-) to sene rate berr- to the 68000, indicating a bad Read has taken place.
I
d13
I Context bit cx1.
d12
Context bit cxO.
_______________
lI _____________________________
~
______________________1
Read Only:
I Latched Error:
1
I1-______________1I_____________________________________________________11
d8
S.8perr- (LON True). Indicates a Protection
Code violation.
d7
Parity Error Plrerr- (Low true).
d6
Tiaeout (Hish true). Too auch ti.e taken on a
Managed Access (Hultibus or 'Local' raa access).
dS
Bus Error extention berrx- (Low true). True on any
of the above three error conditions, but is also
valid alone when access to a Page aapped
"Invalid', that is, aspped as 'Local 1/0', has
been atteltPted.
_______________1_____________________________________________________
1
Table 6 - Context Relister Data Foraat
--30--
Context bits cxO and cxt provide latched address bits into the
Meaory Hap when a Hana~ed Access is initiated. This ~ives the ope ratin~ sYstem, like UNIX, the flexibility of switching Heaory Haps easily
between processes.
Hardware default enables one context bit, allowing 2 Contexts,
each 8M bytes per process. A second context bit, ex!, can be used to
provide 4 Contexts, each 4H bytes per process.
--31--
The tour 28-pin on-board PROH sockets support the JEDEC standard
pin assignments tor ROMs and EPROHs. The Ju.per block JBt (See Appendix A) selects address bits a14 and a1S to the sockets.
Default Ju.pers select 2732/2764 type 4K/SK EPROHs and allow
expansion upwards to 27128 (16K) and 27256 (32K) type devices.
Access to the first Logical PROH pair is allowed under two conditions: one, i~mediatelY after Reset, decodes the PROH 0 startins
address at OxOi the second decodes the PROH 0 address at OxCOOOOO.
The PROH 1 address is defaulted to OxCSOOOO at all ti.es.
--32--
3.3.1.4. AHD 9513 Ti.er
See 'The Aa9S13 S~ste. Ti.ins Controller Handbook' fro. Advanced Micro
Devices for a co.pleat description of all of the functions of the
chip.
See Fi~ure 10 for AHD's Function Diasra. of the 9513 Ti.er.
3.3.1.4.1.
Introduction
This discussion sives a Quick overview of the functions of the
chip that the Series 80A Processor Board aakes use of.
The 9513 isa support device for processor oriented s~ste.s that
is desisned ~o enhance the available capabilit~ with respect to countins and ti~ins operations. It provides the capabilit~ for prosra••able freQuenc~ s~nthesis, hish resolution proSra •• able dut~ c~cle
wavefor.s, retrisserable disitial ti.ins functions. tiae-of-da~ clockins, coincidence alarms, cOIPlex pulse seneration, hish resolution
baud rate seneration, freQuenc~ shift ke~ins, stop-watch tilinS, event
count accumulation and .an~ lore. A variet~ of prosra •• able operation
modes and control features allow the 9513 to be personalized for particular applications as well as d~na.icall~ reconfisured under prosraa
control.
--33--
3.3.1.4.2. Functional Description
See Fisure 10 for AHD's Function Diasrae of the 9513 Tiaer.
The oscillator's freauencs is controlled at the Xl and X2 interface pins b~ the S~ste. Clock divided b~ 2, sivins a reference freauencs of 4.9152 Hhz. The internal oscillator's output is devided b~
the Freauencs Scalar to provide several sub-freauencies.
The 9513 is addressed b~ the external syste. as two locations: a
Control port and a Data port. the Control port provides direct access
to the Status and Co~aand Resisters, as well as allowins the user to
update the Data Pointer reSister. The Data port is used to co••unicate
with all other addressable internal locations. The Data Pointer reSister controls the Data port addressins.
A.ons the reSisters accessible throush the Data port are the Haster Hode resister and five (5) Counter Hode reSisters. one for each
counter. The Haster Hode resister controls the prosra~aable options
that are not controlled by the Counter Hode resisters.
Each of the five seneral-purpose counters is 16-bits Ions and is
controlled b~ the Counter Hode resister. Throush this
resister, a user· can software select one of 16 sources as the counter
input, a variet~ of satins and repetition eodes. UP or down counting
in binars or SCD and active-hish or active-low input and output polarities.
independantl~
Associated with each counter are a Load resister and a Hold
resister, both accessible throush the Data port. The Load reSister is
used to autoeaticalls reload the counter to an~ predefined value, thus
controllins the effective count period. The Hold resister is used to
save the count values without disturbing the count process. peraittins
the host Processor to read interaediate counts.
All five counters have the saae basic control losic and control
resisters. Counters 1 and 2 have additional Alara resisters and co aparators associated with thea, plus the extra losic necessar~ for
operatiin! in a 24-hour ti.e-ot-da~ .ode.
Each seneral counter has a sinsle dedicated outpin. It .a~ be
turned off when the output is not of interest or aa~ be confisured in
a variet~ of wa~s to drive interrupt controllers, bufters, etc.
--34--
A powerful co ••and structure siaplifies user interaction with the
counters.
A counter aust be araed b~ onedf the ARH coa.ands before countine can co•• ence. Once araed, the countins process .a~ be further
enabled or disabled usins hardware Satins facilities. (The Series BOA
Processor necessarilv ties all Gates and Sources to one unchansins
state. Sorr~.) The ARH and DISARH coaaands permit software satins of
the count process in so~e.odes.
The LOAD co•• and causes the counter to be reloaded with the value
in either the associated Load resister or the associated Hold reSister. It can often be used as a software retrisser.
The
hardware
co •• and,
mav be
usins an
DISARM co.mand disables further count ins independent of an~
satins. A disarmed counter .a~ be reloaded usins the LOAD
aa~ be incre.ented or decre.ented usins the STEP co ••and
and
read usins the SAVE coaaand. A count process .a~ be resuaed
ARM comaand.
The SAVE co•• and transfers the contents of a counter to its associated Hold reSister. This co •• and will overwrite an~ previous Hold
resister contents. TheSAVE co•• and is desisned to allow an accuaulated
count to be preserved so that it can be read b~ the-host Processor at
a later ti.e.
Two combinations ot basic co •• ands exist to either LOAD AND ARH
or to DISARM AND SAVE an~ combination of cou~ters.
Additional co •• ands are provided to: step an individual counter
bv one count; set and clear an output tossle; issue a software Reset;
clear and set special bits in the Haster Hode reSister; and load the
Data Pointer reSister.
--35--
3.3.1.4.4.
CadI inc
Operatin~
Hodes
The 9513 has been hardware confisured to provide a variety of
services on the Series 80A Processor board. Two (2) of the channels
are dedicated Baud rate generators, using Haster Hode D, and do not
!!enerate interr~,pts.
Two (2) other channels 'Jse Hode A to toggle
their associated outputs and provide interrupts to the 68000 at level
7 (for refreshins D~na.ic Rams) and level 6 (user program.able). The
interrupt routines aust set the output inactive and leave the count
run free to interrupt again at the proper rate (ever~ 2 .illi-seconds
for INT 7~ for exa~ple).
The fifth channel can be confisured to pulse the 68000 Reset
whenever the count reaches zero. This is called the Watchdog Tiaer
function. It is aeant to be used in an operating s~ste. that .onitors
the Refresh counter inte~rupts and reloads the Count into the Watchdog
Tiaer. If the operating s~ste. hangs and no longer services these,
then the Board will auto.aticall~ Resets.
Channel 2 of the 9513 is the onl~ one buffered to a Juaper allowing connection to an~thing. Its default is to level 6 interrupt.
Channel 1 is the Watchdos Tiller; channel 3 is the Refresh Ti.er
connected to level 7 interrupt. Channels 4 and 5 are the Baud rate
generators.
--36--
5/
57
Soure e }-5
Go Ie 1-5
,-
•
-
Xl
(Not Connect ed) .
X2
/
16-8!I' Counter
~.
Frequency Scaler
Osc I!lator
"
Cpunter 5 Lagle Group
OUT 5
Counter 4 Log'c Group
OUT 4
Counter 3 Log!c Group
OUT 3
(e20 0)FOUl.
(Noi Usod)
--
4-bl'l Counter
FOUT D,.. ,del'
8-8 It Command
R09 !st er
8
.--
d0-d7~
,
d8-d15--r:8
f--
t
Input Select
LogIC
6'-8! I Data .--- 8-8!1 ,Status
Po Inter
RegJsi er
8
v
8us Buffer
and Mu;(
16
L
/
~
16-8 It Mas'ler
Mode Reg !s'ler
Counter 2 Lagle Group
16 v
r-
8us
Int·erfoce
Control
OUT 2
t
t
lor c-low c-ee_ tIme r-01 (el d- ) -
t
Gnd
Power On
Reset
1---1
Vee
FIsure 10 - TImer Fund Ion DIagram
Counter 1 Lagle Group
t
OUT 1
3.3.1.5. Intel 8274 UART
See specification sheets on the Intel 8274 or NEC 7201 for a co.pleat
description of all of the functions of the chip.
See Fi~ure 11 for UART Block Diagra ••
3.3.1.5.1.
Introduction
This discussion gives a Quick overview of the functions of the
chip that the Series BOA Processor Board .akes use of.
The Dual-Channel UART chip suPPorts As~schronous (Start-Stop),
Byte Synchronous (Honosync, IBM Bisync), and Bit Synchronous (ISO's
HDLC, IBH's SDlC) protocols. The Cadi inc Series BOA Processor configures the UART to use only the Asynchronous, Polled or Interrupt driven
and non-DHA features.
3.3.1.5.2.
Functional Description
The SYsteM interface to the host Processor consists of B ports or
buffers:
I'
1
'a21
all1 ___________________
Read Operation 11__________________________
Write Operation
1___1 ____
1I
1
,
, 0'
1
0'
ChI
I l ' 0 1 Chi
, 0 1 1 1 ChI
, l ' l ' ChI
I
1
A Data Read , Ch.A Data Write
A Status Read' ChI A Co•• and-Para.eter
8 Data Read I Ch.B Data Write
B Status Read' ChI 8 Co•• and-Paraaeter
,
I
I
I
, ___1I____ 11___________________11__________________________11
1
Data buffers are addresed
b~
82
a
0, and Coa.and ports by a2
= 1.
Co•• and, status and para.eter inforaation is held in 22 resisters
within the UART (8 Write register and 3 Read registers for each channel).
An internal pointer register selects which of the co •• and or
status resisters will be read or written during a co •• and-status
access to a channel.
After Reset, the contents of the pointer register are zero.
The
first write to a co •• and re~ister causes the data to be loaded into
Write Register 0 (WRO). The three least significant data bits of WRO
are loadad into the Co •• and Status Pointer. The next Read or Write
operation accesses the read or write register selected by the pointer.
This pointer is reset after the operation is coapleted.
--38--
3.3.1.5.3.
UART
Coa~ands
For operating in the As~nchronous lode, the UARY lust be initialized with the following inforft'lation: character lensth (WR3; d7, d6 and
WR5; db, d5), clock rate (WR4; d7, db), nUMber of stop bits (WR4; d3,
d2), odd, even or no parit~ (WR4; d1, dO), interrupt .ode (WR1, WR2),
and receiver (WR3; dO) or tranaitter (URS; d3) enable. When loading
these paraMeters into the UART, WR4 inforMation aust be written before
the WR1, WR3, WRS para.eters-co.aands.
3.3.1.5.4.
CadI inc Operating Hodes
The Processor board does not enable an!:l [IliA f'Jnctions of the
UART. Both channels are allowed to use Polled and Interrupt operating
..odes. InterrlJPts for all serial comMunications, includins lultiple
/1ultifuction boards, are handled via INT 5.
Both channels trans~it and receive using RS-423 cOMPatible
drivers and receivers, translllitting at +5 V to -5 V level and able to
receive standard RS-232 levels of +12 V to -12 V. The receiver device
is a two-input balanced level cOIliParator that has the t input grounded
and the - input connected to the active signal. The transaitter device
drives a single line per input.
Channel A is reserved for the Console ter.inal (either a Cadlinc
Ke!:looard and CRT aonitor or a duab terainal) and does not use an~
hardware to enable lode. controls. This port can then be used in a
siaple three-wire co ••unication scheme (TxD, RxD, ground).
Channel B allows the use of these lodell control
RTS, CTS, and DCD.
--39--
signals:
['TR,
Daio Bus
- 1 -8- - '
J9:d7
a2--~
b/ac/d-
J8:dl5
a1
lorclowcce1lmerc400
r8se1-
----.I
rdwrcselk
reset-
c.p!
from Timer
TxCa
RxCa
c.p2
from Timer
TxCb
RxCb
. ----,
: Channel:
I
I
I
I
I
I
:
,
A
RxO
Txd
I
I
I ~--<
I
I 1-------'1-d
I
1------
:
OTR:
RTS I
CTS I
OeD:
I
I
I
I
I
I
I
I
I
I
I
I
B
RxO
Txd
L
t
L
t
t-
r----'
: Channel:
J1.p1.rxd
nc
1.----.1
t-
74LS~4
Inverters
26LS32
ReceIvers
OTR: I - - - - - - ' - - l l
I
RTS I t------4--d
I
CTS I~-<~--~~~
I
I
lOCO I ~-<'1+----
I
I
I
&._---~
Intel 8274
or NEe 7201
FIgure 11 - UART Block DIagram
Slew Rate
Control
26LS29
TransmItters
I
I
I
I ~---,<"'1-----I
I I----I-d
I
:
J1.p1.txd
p2.rxd
p2.txd
Jl.p2.dtr
J1.p2.rts
J1.p2.cts
Jl.p2.dcd
3.3.1.6. Parallel
In~ut
Port
The Parallel Port currently reads 16 extern.l switches fro. which
the PRO" "onitor interprets Boot devices and Console conti~uration.
The default access address for oe.port- is Ox900000.
Control si~nals a5-, r/w- and oe.port- are buttered throu~h Open
Collectored drivers for interrace handshakin~. The halt- si!nal is
also buffered to drive an external LED.
The Parallel Port receives set.init- fro. an external Reset
switch and is then wire-ored to !enerate the 68000 reset- si~nal.
3.3.1.7. Hardware VPA
The sisna! ypa- is a Syste. Access address at OxF80000. It is
onlv used durins the 68000'5 Autovector Interrupt handlin~. When an
Interrupt occurs and is accepted, the 68000 sets the Hisher Order
address bits to ·one·. The sisna! ypa- is received by the 68000 as
Valid Peripheral Address.
__ "f __
3.3.2. Manased Accesses
Refer to Scheaatic drawins t295014 paSes 1 and 5
When a Hanased Access is reauested, the used and dirty bits at
the PaSe Control Static raa aust be uPdated to show that a particular
pase was accessed (used) and it was written to (dirtv). These sisnals
are .ultiplexed by r/w and aultiplexor chip (IC H7) is enabled by
en.aapx- fro. PALPJ (IC 6). If there is a paSe fault on the c~cle,
i.e. Protected froa Read, Write or Execute, then the write is not
done, leavins the status unchansed tor further processins. It the
cycle is okay by cs6 tiae, then b/l- and io/.- are·unchansed, used is
always written as ·one· and dirty is chansed to ·one· durin. a write
only.
The static Raas write on the trailins edse at its write-enable
input. To resolYe the PaSe Control updates, en ••apx- is delaved froa
soins active until cs6. This allows the Bus error losic tiae to
decide that the Hanased ~cle is sood.
Raa Heaorv accesses iaplv either Local RAM data located on-boa~
the Processor, or Hishspeed accesses located on Dual-Ported Heaory
boards, the Floatins Point board or other devices respondins to
Hishspeed bus reGuests.
3.3.2.1.1.
local
Me.or~
The local Rae unit consists of 36 K 64Kbit D~na.ic Ra. devices
. (P~ 2) ~ivin~ a total of 262,144 bytes of Parity checked .e.or~. The
MUltiplexed addresses and Data driven into the RailS are also directl~
connected to the Hi~hspeed bus. This .akes the Hishspeed bus a functional extension of the local Ram.
The Rail c~cle besins when cs3 is buffered (PS 1 - IC F03 and Ps
2- IC E14) to drive ras- to all the Ra.s. At cs4, the Lower Address
driver (PS 2- Ie A14) is shut off, and the Upper Address driver (Ps 2IC C14) is enabled. At· csS, casO- or casl- is selected and driven
(pa~e 2- ICs K14 and E14) to the appropriate bank ot 18 RailS.
The addresses into the Ra.s are not a strai~ht-forward swap at
address bits. The followins table details the address translation:
I
I Bus Addressl
At cs3 1
At csS
(ras-) 1-___________
I
(cas-) 1I
1I ____________1I ____________
I lI_aO
I lI_al
1 11_12
I 11_13
, lI_a4
I 11_.5
1 11_.6
a4
I
I
1
al
,6
I
17
,
al
a2
I
I
I
19' I
.a15
I
•• 14
I
I
I
I
I
I
.10
.,12
,
I
I
11116'
1
'S
.11
I
I La7
I
a8
. "'ll
,I____________ 11________----1I____________11
Table 7 - Multiplexed Ra. Addresses
--A~--
3.3.2.1.2. Local Parity Lo~ic
See Sche.atic 1295014 Pase S
See Fi~ure 12 tor Local Parity Block Diasraa.
The 256K b~tes of On-board dvnaaic ra. is provided with Parit~
checkin! on everv b~te. A Parity bit is senerated on a write bv
resolvin! the even pari tv of the bvte with two 82562 Parity
Generator/Checkers (IC DIS and B17), with the r/w- line as the ninth
bit of both bvtes. The output of this lo~ic soes to the data-in of the
Parit~
D~na.ic
Raa, and is written with the rest of aeMOr~. When a
Read is done, the data-out of the Paritv raa now becoaes the ninth
bit, and the output at the lo!ic should indicate correct Parity.
When an error does occur, PALPI (IC 819) provides the input to a
flip-flop, enlperr-, that will be clocked on the trailin~ edse of asfro. the 68000 to Senerate Iperr-.
The sisnal used to sene rate berr- to the 68000. parerr-, is
enabled in PAlPl bv the Context Resister bit prtvenab, lperr- froa the
Local Parity loSie and bv a.perr- frca the Hishspeed bus.
The parerr- sisna! will actuallv be seen on the cvele after the
occurance of the error. Software hand!in! of bus errors aust be able
to tell Parity Errors froa everv other error to recover control. The
Cadlinc Pro. Monitor resident on the board prints an error .essaSe any
tiae a berr- occurs and stops the process. Other errors indicate violation ot various Protection or Allocation rishts, but Parity Error is
always si!nificant.
--44--
Processor
Doio 8us
Output from
Upper Par !iy Ram
I
ffi_OOU
dIS
d14
d13
dl2
dll
dl0
d9
d8
odd
even
poru
uds-
w/r-
m_do!
Output from
Lower Par tty Rom
d7
dS
dS
d4
d3
d2
dl
d0
parI
fds-
E
m_dlum_perronbrdprtyenab
Iperr-
PALPI
porerrenlperrIperr-
even
odd
E
m_dd,...
'-.,,;-"
Input io
ParIty Rams
82562 Parity
Generator
and Checker
FI5ure 12 - Parity Logic Block DIagram
3.3.2.1.3.
Hishspeed Bus Interface
The CadI inc Hishspeed Bus allows the Processor to access lore
fast .e.or~ than ph~sicall~ resides on the CPU board. The Hishspeed
Bus is meant to respond 8S fast as the On-board .e.or~ and to respond
to control sisnals as it it were an extention ot the D~na.ic Raa
melo~ chips. This sives the Processor a full 16 Hbytes of hishspeed
.elor~ on one b'JS while tree ins the Hultibus for other Haster devices.
Cadi inc Dual-Ported He.or~ boards are an intesral part of the hishpertormance s~ste. for their aeeessibilit~ b~ both this Hishspeed bus
and b~ the Hultibus.
When the current 68000 address cycle selects 'Local' .e.or~
throush He.or~ HanaSelent, i. e., the ._prea- COI.and is asserted, the
hish-order Hanased Address bits 1_la23 throush 1_la17 specif~ lelor~
somewhere out on the Hishspeed bus. It a board has responded to the
address ranse, then it will drive or receive data on the Hishspeed
bus, on a write or a read, respectivel~.
There is no explicit 'acknowledse' of the c~ele b~ the slave
board on the Hishspeed bus, Just as there is no explicit aeknowledse
of an On-board .e.o~ reauest when the addresses there happen to co.pare. The Hishspeed bus interface relies on I_wait- trol the slave
board to indicate whether it is read~ to accept the Multiplexed Ra.
addresses. I_wait- direetl~ controls the Clock state senerator b~ seneratins cswait- in PALP3 (Ps 5 - ICF6), thereb~ preventins the shift
resister froa advaneins until it Soes awa~, s~nchronous with the 68000
clock cl00. If there happens to be no slave board to respond to the
address, then no I_wait- would be senerated and the ~cle terainates
noraall~ without data beinS transfered or error.
The slave board will usuall~ sene rate a_wait- when it is beins
accessed on the other bus it is connected to, e.S., Hultibus for
Dual-Port He.o~ or the 8086 processor on the Floatins-Point board.
Also, for boards with D~na.ic Raa devices, IS opposed to Static Raas,
a period of tine after the actual bus access ends lust be inserted to
.aintain the Ra.s' 'precharse' reauire.ents.
When all delavs on the slave board are resolved, it will be~in to
drive its local addresses based on the Multiplexed Ral addresses, now
in the low Address state. I_wait- will be nesated at this tiae and the
next hish state of cl00 effectivel~ lets the Clock State senerator
advance, drivins the new Hish Address states onto the bus.
Froa that point. the ~cle terainates
further control fro. the slave board.
--4&--
normall~
without
an~
3.3.2.2.
Multious Interface
When the current 68000 c~cle selects a 'Bus' access through
Hanase.ent, the Control logic generates bas-, ~hich is used to
as the reQuest to start Hultibus arbitration. The particular co•• and
to be driven out to the Hultibus is dependant on the how the Heaor~
Hap for that page was setup.
He.or~
3.3.2.2.1.
Bus Haster Arbitration
See Scheaatic t295014 Pase 3
The Arbitration logic uses an 8289-tvpe Bus Arbitor (IC K3). The
chip is used in a siaple aode, where there is one input (bas-) and one
output (aen-) actuallv used b~ the Processor board.
The Status line InPuts are all tied to bas-, therebv soin! idle
when the 68000 c~cle ends and allowinS another Bus Haster access
throush it. It is intended the Processor .ake the aost use of faster
local and Hi!hspeed Heaories so that the bulk of Hultibus accesses are
done bv other standard devices.
The b.prn- (Prioritv In) sisnal into the 8289 is selectabl~ to
allow the Processor board HiShest Prioritv tor access to the Hultibus,
or to receive the b.pro- (Priority Out) troa the board iaaediatelv
above it in the card case. In both cases, the 8289 drives its own
b.pro- to the board baediateh below the Processor. This scheae also
allows tor hisher speed Parallel Arbitration that can accoaodate as
aanv as 8 Hasters on the Bus.
All the rest of the Hultibus Arbitration sisnals (b.init-,
b.brea-, b.b'Js~-, and b.crea-) are used internaltv by the 8289 to
satisfv the Intel reauire.ents.
Once control of the Hultibus is established, aen- Soes active and
stays on until another Bus Haster reauest takes control awa~. The
Address Bus is directlv enabled b~ len-, and the Data and Coa.and
driver delays are enabled by bas- and aen-. When bas- and aen- are
both asserted, a shift register (IC K1) is enabled and is clocked by
the 20HHZ base clock. The second shifted output enables the Data
drivers (den-), the third shift enables the Coaaand drivers (cen-).
The Processor board suPPorts Hultibus b~te accesses b~ latchins
in the state of the 68000'5 Ids- line at cs4 tiee, Seneratins Hultibus
address baO, and providinS a local bhen (Byte Hi!h Enable) froa both
Ids- and uds- in PAlP2 <Ps - S IeF1). These two lines are latched
alons with the HanaSed Address bus (aa23:aa12) and the lower 68000
address bus (all:al) at csS tiee to provide the full 24 bits at Hultibus accesses. All tour at the Hultibus caa.ands <ardc-, .wtc-,
iorc-, iowc-) are then ~ated, in PAlP4 (P~ 1 - IC F4), to besin at cs6
thle.
All 24 bits of the Hultibu5 Address bus are driven tor either
He.ary or I-O accesses.
When b.~ack- is driven by the target board as the acknowledse,
dtack- is generated in PALP2 (IC Fl). dtack- then latches itself
asserted until the end of the 68000 cvcle.
PALP4 (Ie F4) decodes .rdc- and .wtc- on the proper state of
b/l-, io/.- and r/w-.
3.3.2.2.3.
Han~
addresses.
1-0 Access
Kulitbus products use either 16 or B bits to decode 1-0
The Processor board drives all 24.
PALP4 (IC F4) decodes iorc- and iowe- on the proper states of
b/l-, io/.- and r/w-. There is I special .ode for ter.inatin~ the
iowc- co •• and early. When b.xack- is returned and dtack- is asserted,
the iowc- co••and is terainated, but the 68000 cvcle still has 2+
clock states of Kultibus control.
This was done to acco••odate Hultibus boards that return b.xacki •• edlatelv after receiving the iowc- co•• and, allowin~ a wide .,r~in
of data hold tiae on the bus.
--4A--
4.
Board Hne.onies
(Note: Schelatic drawinss and the printed forlat at the wirelist
slishtly different in notation. Hnelonic "b.init\" on the
sche.atic corresponds to "b_init-" on the wirelist, etc. This is
because UNIX editors, throuth which these doculents were
prepared, differ slishtly in their handlins of special characters, i.e. "\", "." and "_". In Seneral, then, "_" or "." in a
ane.onic siSnify an off-board connection, and "_" or "\" as the
last character at the ane.onic lean it is "low" true.)
are
--49--
----------------------------------------------------------------------
1_____________________________________________________________________
Processor Board Si~nal Ha~es:
11
I
I
I
I
I
I
t
1
I
t
I
(Hu) -12vdc
(Mu) -5vdc
(Mu) 12vdc
(Bu) aO
(Bu) 11'a23
(Bu) 81(Hu) aen
(Mu) aen(Co) as
(Co) as(Hu) b_aO:23(Mu) b..bclk(Hu) b_bhen(Mu) b_bprn(Hu) b_bpro(Hu) b_brea(Mu) b_busY(Mu) b_cbra(Mu) b_ce1k(Mu) b_dO:15(Hu) b_inhl(Mu) b_inh2(Mu) b_init(Mu) b_intOI7(Mu) b_int.(Mu) b_iorc(Hu) b_iowc(Hu) b_ardc(Mu) b_awte(Mu) b_xack(Mu) bu(Hu) belk(Co) blu'r(Co) berrx-
I
I
I
I
I
I
bhen
(Co) boot
(HH) btl(Co) clOO
(Co) c200
(Co) c400
(Co) c50
(Co) c50(Co) c50-(Co) c800
(Ca) c.pl:2
(Co) c_refresh
CCo) c_tiaert:2
(Co) carMI
(Co) easO:1(Hu) ee1kCHu) ce_byte(HH) ce_apCHH) ce_8aplfHH) ee_aapy(Ov) ce_proaO:1(Oy) ee_5io(Dv) ce_Uaer(Hu) ee_word(Hu) cen(Hu) eenl(Co) ekberr
CCO) e1rboot(Co) es3
(Co) <:s3(Co) cs4
CCO) <:s4(Co) es5
(Co) cs6
(Mu)
(Co) cs7
(Co) cs8
(Co) c:s9
(Co) cslO
(Co) c:swait(Ca) ctsb(HH) exOU
(Bu) dO:!5
(Mu) dben
(Mu) d2aen
Ufu) d3aen
(Ca) dc:db(Hu) den(Ov) devenab(HH) dirty
(Co) ds
(Co) dtack(Ca) dtrb(Ca) dtrb-(tfM) en_aapx(Co) enabto
(Co) enabto(Co) enlperr(Co) fcO:2
(Hu) snd
(Co) hilt
(Co) halt(Co) hardreset
(Co) hardreset(Co) hYst
(Co) init
(Co) init(Co) intO:7(Co) intis:7s-
_____________________1________________________1-_____________________1
Svabols tned:
Bu - Buses
C. - Coaaunications
Co - Coulnds
By - Devices
Hs - HiShspeed
HH - Heaory Hana.eaent
Hu - Hult.lbus
Processor Board Sisnal Haaes cont'd!
1I_____________________________________________________________________
1I
I
I
/
/
I
I
I
(Co)
(Co)
(Co)
(Oy)
(Dy)
(HH)
(Co)
(Ca)
(Ca)
(Ca)
(Ca)
(Ca)
(Ca)
(C.)
(C.)
(BY)
(Bu)
(Bu)
<Bu)
(Co)
(Co)
(Hs)
(Hs)
(H5)
(Co)
(Co)
(Co)
(Co)
(H5)
(Hs)
(Hs)
(Hs)
(Hs)
int_sioint_sio--int_tiaer2ioreioweio/.ipl0:2JLpl_rxd
Jl_pl_txd
Jl-P2..cts
Jl-P2_dcd
Jl-P2_dt.r
JLp2..rts
J1_p2_rxdltxd
J1_p2..t.xdlrxd
J2..as
J2_halt
J2..inOU5
J2..r-lw1
Idslperra_aO:7
a_C5Sa_dO: 15la_dila_diuLdola_douLld5._.. 17:23
a_perra-preaa_rtenab
I
I
I
I
I
I
I
I
I
I
I
I
________________________1I____
(Hs) a_uds(Hs) a_wait(HH) aa12:23
(Co) aeasO:t(Co) aras(Hu) arde(Co) IIwera.l(Co) aweraltu(Hu) IIwte(Co) nc
(HH) oe_cx(Oy) oe_port(Co) oe_raa(Co) onbrd(Ca) p2_rxd
(Ca) p2_txd
(Co) parerr(Co) parerrl
(Co) parerru
(Co) parl(Co) paru(HtO 'protO::S
(Co) prt.Yenab
(Co) r-Iw
(Co) reset.
(Co) reset(Co) rtenab
(Ca) rtsb(C.) rt.sb(C.) rxda
(Ca) rxdb
(Co) rlw(C.) sa:d
~
SYliools Used:
Bu - Buses
C.. - Cd....unications
Co - COIII.ands
Oy - DeYices
Hs - Hishspeed
HM - Heaorv Han.~eaent.
Hu - Hultibu5
__ Itt __
I
I
I
I
I
I
I
I
I
I
OtH)
(Co)
(Co)
(Co)
(ell)
(C.)
(Co)
(MH)
<ttu)
(Bu)
(Bu)
(Co)
(HH)
(HH)
(HH)
(HH)
(HH)
(Co)
(Co)
(Co)
(HH)
(Hu)
(Ca)
saaperrsysaccthr
tiaeout
txda:b
txda:budsused
yec
ycclal4
ycclalS
vpawe_cxwe_IIapwe__ aplwe_aapuwe_aapxwe_raalwe_raauwlrxaO:11
xllck
xca:b
I
I
I
_______________1 ____________________1I
4.1. Buses
The tollowins naae. are or.anized to describe onboard 'bus' si.nals. Hultib"s ~nd Hishspeed Bus na.es are described in separate sections.
General Bus Haaes:
1________________________________________________________________
1I
I
aO
Produced by latchins lds- with
al-
Inverted 68000 al, for Hap Lon. words.
I
al:a23
68000 Address Bus.
t
I
I
dO:1S
68000 Data Bus.
t
j2-as
68000 Address Strobe. Hi true coa.and
cs~.
1
I
tor parallel Port
j2-halt
Sisnal tor LED Halt indicator
Hi true data bus tor Parallel Port
Rea~
(low) Write (Hi) coaaand tor Parallel Port
Chip Enable tor the Parallel Port
ycctal~
ycclalS
Select Hish Address 14 tor PROMS.
Select Hish Address 15 tor PROMS.
___________1-_____ ._____________________________________________1
4.2.
Coa.ands
The tollowinS naaes describe the aaJority ot Coaaand and Control
sisnals used by the 68000 and by all other lo~ic onboard.
Co..-and Naaes:
1, _________________________________________________________________
11
1
I
as
, as-
68000 Address Strobe
I
I
Bus Error to the 68000
, berr,, berrx, boot
Bus Error Extention
1 c100
, c200
, c400
, c800
Systea Clock at 10 Mhz
Tiaer Clock at 5 Mhz
UART Clock at 2.5 Mhz
1.25 Mhz Clock
1
,
c50
Raw CrYstal outPUt at 19.6608 Mhz
cSOc50--
Inverted and delayed CrYstal
Inverted and delayed Crystal
Tiaer outPUt producins INT7
Watchdos Tiaer outPUt produces Reset when low
User Prosraaaible Tiaer output produces INT6
carry
Carry froa Svstea Clock counter
CI50:1-
Coluan Address Strobe for Onboard Ria
ckberr
Clock Bus Error. Invertec berr-
clrboot-
Clelr Boot. See PALPO.
c53:10
Clock States e13, es4, ••• cs10
cs3-
Inverted csl. Produces RAS to local Raa5.
cs4-
Inverted c54. Multiplex control for Ria Addreses.
____________1 ____________________________________________________1
__ III:'T_
Co•• and Ha.es cont'd:
1I______________________________________________________________
1I
I
I
cswait-
Clock State Wait. Hakes the Clock State ~eneratorl
wait before c54 ~et5 ~enerated. See PALP3 forI
e005.
1
ds
Data Strobe (Hish true). Produced by lds- OR uds-.I
dtack-
Data Transfer Ack. to the 68000. See PAlP2 fori
eons.
I
enabto
enabto-
Enable Tiaeout Generator. See PALP3 for eons.
1
I
I
I
1
-I
enlperr-I
Enable Latched Parity Error. If 'low' when 15-1
1 soes away, then a Parity Error in Onboard Raa has
I occured. See PAlPl for eouns.
fcO:2
I
I
I
68000 Function Codes:
210
I o 0 0 Undefined
I o 0 1 User Data
I o 1 0 User Prosraa
I o 1 1 Undefined
I 1 0 0 Undefined
I 1 0 1 SuPervisor Data
I 1 1 0 Supervisor Prosraa
I 1 1 1 Interrupt Ack
1
--____---1--_--__-------------------------------------_____---1
1_________________________________________________________________
Co•• and Ha.es cont I d
1
11
1
1 halt
1 haltI hardreset.
I hard reset.I
68000 halt sisnal
Power level
h~st.
h~sterises
init.
initint.O:7-
Interrupts allowed to be latched
intls:7s-
latched Interrupt.s to encoded to the 68000
int_sioint._sio-int._sio---
OtC interrupt. tro. t.he UART
Butfered
Select UART Int.errupt. to IHT5
int_tiaer2-J
Select c_tiaer2 to IHT6
I
iplO:2-
J
J
68000 Interrupt
Priorit~
bits
_____J.__________ _____________________1
--55--
;
Coaaand Haes cont' d:
1______________________________________________________________________
11
1
I
I
I
lds-
68000 Lower Oata Strobe
lperr-
Latched Parity Error. Latched when enlperr- was assertedl
on an Onboard R.a access, indicatin~ a Parity Error. Thisl
si~nal will be ~.ted with the Parity enable line in PALPI
to Sene rate parerr-.
a_dil8_diua_dol,a_dou-
Lower
Upper
Lower
Upper
acas0:1-1
Byte
Byte
Byte
Byte
Parity
Parity
Parity
Parity
I
I
inPut
input
output
output
Buttered cBsO:l- to drive Onboard Raa CAS pin.
I
aras-
1 Buttered cs3- to drive Onboard R.a RAS pin.
I
...er.al-1 Butfered wer.al- to drive Onboard R•• WRITE Low Byte pin •
IWeralu-1 Buttered weraau- to drive Onboard Raa WRITE Hish Bvte pin.'
1
I No Connect.
I
oe_r••- I DeYice Select tor
1
1
1
nc
I
enablin~
Onbaord.R•• data drivers.
onbrd- 1 Onboard Access Enabled. See PALPl for eans.
1
____-.1 __________ .. _________ ..
I
_______________
1
I
I
1
..1
----------------------------------------------------------------
I_______________________________________________________________
Co•• and Ha.es cont'd:
1I
I
parerr-
Parit~
parerrl
parerru
Output of Low B~te Parit~ checker. Hish true
Output of Hish B~te Parit~ checker. Hish true
parl-
9th bit into Low Parit~ seneratorlchecker.
Low when writins, follows a_dol
(inverted) when readins.
9th bit into Hish Parit~ seneratorlchecker.
Alwa~s Low when writins, tollows a_dou
(inverted) when readins.
Error. See PALP! for eons. Generates berr-I
when either an Onboard Ra. access or Hishspeed busl
access has reported a Parit~ Error. See PALP2 fori
its use.
Alwa~s
paru-
prtYenabl Parit~ Error Enable bit in the Context Resister.
I When low, PALP1 disables parerr- tro. soins active.1
_________1I _____________________________________________________1I
--------------------~------------------------------------------
1______________________________________________________________
Coaaand Haaes cont'd:
1
1I
I
I r-Iw
I
I
I
I
Inverted 68000 rlw- tor PROHs direction
I
I
I
I reset 1
I
I
I reset- I 68000 hardware Reset
I
1
I
I rfenab I Refresh Enable bit in the Context Resister. But-I
I fered
I
to the Hishspeed bus, this allows al
I
1 Hishspeed bus tarset board to override Address I
I
I coapare with the intention ot refreshins D~naaicf
1
I Ra.s through the s~stea. Boards with Static Raasl
I as their Dual Ported .eaories can isnore this.
I
I
I
I
1 rlwI
I
I
I setinitI
I
I
I
I
s~sacc­
68000 Read (low) Write (high) coaaand signal
I
1
1
Clock boot and issue hardware Reset.
1
I
Systea Access. See PALPO tor eons. When Hish, a
Syste. Access is reauested, aostlv when 68000
address a23 is high.
When low. a Hanased Access is reouested.
I
I
I thr
I
I
I
I
Power Level threshold
tiaeout
Cvcle Ti.eout Error.
uds-
68000 Upper Data Strobe
vpa-
Valid Peripheral Address - Interrupt ack only
1
I
1
I we_raal-I
I we_raau-I Local Raa write enable. See PRLP4.
I
f
I wlr1 Inverted 68000 rlw-. Used for Hultibus data
1I _________1I ____________________________________________________1
The tollowins na.es are related to serial co••unications onboard.
Co••unication Sisnals:
1__________________________________________________________________
-11
Baud rate Clocks tor Port
It
ctsb-
Clear to Send Port B
dcdb-
Carrier Detect Port B
dtrbdtrb--
Data Terain81 Ready Port B
J1Jl_rxd
JLpl_txd
Port It Receive
Port It X.it
Jl_p2_cts
J1J2-dcd
JLp2_dtr
Jl_p2_rts
Jl_p2-rxdltxdl
J1J2-txdlrxdl
Port
Port
Port
Port
Port
Port
and B
B Clear to Send
B Carrier Detect
B Data Ter.inal Readv
8 Reauest to Send
B (Receive) or X.it
8 (X.lt) or Receive
I
---------__--_1_,____-------.------------------------------_________________1
-59--
1_____________________________________________________________
Co••unication Sisnals cont1d:
11
1
I
I
1 p2_rxd
1 p2_txd
I
Selected Port B Receive
Selected Port B X.it
I
I
,
I rtsbrtsb--
Reouest to Send Port B
I
,
'rxda:b
Receive Data Port A and B
I
X.it chip slew rate inputs
1
I
X.it Data Port A and B
I
I
I
I
I
I
I sa:d
I·
1
I txda:b
I txda:b-I
1I ________11___________________________________________________ -1I
4.4.
Hishs~eed
The
Bus
followin~
na.es describe the
Hi9hs~eed
Bus.
1________________________________________________________________
Hi~hspeed Bus Sisnals:
11
__ aO:7
I
I
Multiplexed
D~na.ic
Raa Addresses. See Table 7.
1
a_csS-
I
._dO:1S-
I
I
I
a_Ids-
r
Butfered Clock State 5 for valid CAS address.
Data Bus. Connected
Ra.s data lines.
directl~
the the onboard
1 Buftered 68000 ldsI
__ aa17:23 1 Buttered Upper Hanased Addresses
a-perr__prea-
I
1
I
Parit~
Error
Processor Reauest. This sianal indicates to the
Tarset board that D_Da17:23 are valid to enabler
I respondins. See PALP3 for eons.
1
I
I
___________1I _________________________________ -----______________1I
Hi~hspeed Bus Si~nals cont'd:
1I________________________________________________________________
1I
I
a_rfenab
Buftered Refresh Enable. Indicates that the Tar~etl
board should override the Upper Hana~ed Addressl
coapare and start respondin~. This is to allowl
the refreshin~ of D~na.ic Ra.s out on thel
Hi!hspeed Bus at the sa.e tiMe that the Local Raal
is refr.shins.
I
I
Butfered 68000 rlw-
I
I
Buttered 68000 uds-
I
I
HiShspeed Wait. Indicates to the Processor boardl
that the Tar!et board is not read~ to have thel
Hultiplexed Ra. addresses __ aO:1 switch to thel
upper address bits. This stops the Clock Statel
senerator fro. advancins b~ extendin! cswait-.I
&-wait- is not an acknowledse of valid addressl
co.pare, but a co •• and to wait until the Tar~etl
board can CAS the upper address bits. See PAlP31
tor its use in creatins cswait-.
I
I
1_________--1__________________________________------------------1
4.5.
"ult.ibus
The followins na.es describe the Hultibus Co •• and, Address,
Data lines as well as onboard si~nals that support thc~.
and
1________________________________________________________________
Hultibus Si~nals:
11
I
1 -12vdc
I -5vdc
1
Power SUPplies
I 12vdc
I
24 bit Address bus
Bus Arbitor Clock
B\lte
Hi~h
Enable
Bus Priority In
b..bPl'o-
Bus Priority Out
b..breGb_busgb_cbrG-
Hultibus Haster arbitration handshakins sisnals.
Used only b\l It A3 (8289).
See chip specifications.
1
Constant Clock
1
Data bus
1
I
I
t
I
1
Not Used
I
1
Reset
I
1
I
__-----_--_1______----------------------------------------____--1
Hulttbus Stsnals cont'd:
1______________________________________________________________________
11
I
b_intO:7- I
b_intab_iorcb_iowcb__ rde-
I
I
I
I
10
I
I
I
Heaor~
b_awtc-
I
I
b_xaek-
I
I
I
I
I
I
aen
am-
Interrupts
I
I
I
I
I
I
I
I
Not used
Co ••ends
Co••ands
.1
Co..and
I
I
I
Ae~~owledse
Address Enable froa 8289 arbitor (Hish true).
I
Address Enable froa 8289 Arbitor (Low true).
I
I
I
bas-
Bus Address Strobe. This is the reauest to the 82891
arbitor to becoae the Hultibus Haster. Generated throushl
PAlP3, it corresponds to __ prea- but bll- is now in thel
·bus· state.
belk-
Bus Arbitor Cloek into the 8289 ehip.
bhen
Byte Hish Enable. Generated by Ids- and uds- both true,
that is, when a word Iccess is reGuested.
eclk-
Constant Clock. Buttered 68000
S~stea
Cloek el00.
Enable Byte and Enable Word.
___________. ___ _________________,___________________________-------____-----1
~
Hultibus Signals cont'd:
1I ________________________________________________________________
1I
I
I cenI
I
I
Coaaand Enable
dela~
to sate on one of 4 Co •• snds I
I
cenl-
output enable for the four (4) Hultibusl
coa.ands. cen1 won't be gated 00 until aen- fro.1
the 8289 arbitor is true.
I
Ph~sical
I
I
I
I
I d11en
I d2aen
dlaen
aen Dela~s 1, 2, and 3. Part of the Address,
Data and ea••and deia~ resister for the Hultibus.
These are the inputs to the ne>:t resister eleaent,
trolll the previous elelllents' outPIJt.
densnd
Power
iorciowcardcawtc:-
Co.asnds to butter to the Hultibus.
vce
Suppl~
sround
I
I
I
I Power
Suppl~
+5 Volts •.
t
I Buftered Hultibus Coa.and Acknowledge
xack
_________
. _______1I ____________________________________________________1
4.6.
Devices
The tollowin~ naaes describe CO.Dand Enables and related direction control lines for onboard devices.
I ______________________________________________________________________
Device Sillnal Na.es:
1
1I
I
I
ce_proaO:l-1 Chip enable tor the onboard PROM sockets. ce_proal-1
corresponds to Virtual address oxcaoooo. ce_~ro.O-,1
however, corresponds to two (2) address: OXO durin!1
Boot State onlv. and OxCOOOOO when not in Boot State.
ce_sio-
Chip Enable tor the UART, address OxDOOOOO.
ce_tiaer-
Chip enable for the Tiaer, address OxD90000
devenab-
Enables the 1-9 decoder to drive the
five (5) Device addresses.
iorc:-
Used bv the UART and the TIMER as well as the Hultibus
as the Read co.aand.
1
I
I
I
I
1
I
iowc:-
Used bv the UART and the TIMER is well as the Hultibus
the Write co•• and.
IS
1
Chip Enable tor the Parallel Port, address Ox900000.
I
I1_______ L ________________ .. ______..:.._______________________1
4.7. Heaorv Hanaseaent
The tollowins naaes describe
trol sisnals.
Heaor~
Hanaseaent Coamand and Con-
Heaorv Hanaseaent Sisnlls:
__________________________________________________________________
1,
bllce-aapce-aaPIce_llapu-
cxO:l
dirty
I
'Bus (Hish) or Local (Low) tas of the current PaSe
I
I
I
I
I
I
Chip Enable for Hap Raas. address Ox800000
Chip enable for Upper and Lower Pase Hap words.
I Context bits latched in the Context Resister
Indicates Pase has been written to.
Enable Hap Extention. Allows IC H7 (aultiplexor)
to over-write PaSe HIP Status bits used and dirt~.
See PALPJ tor eans.
10 (HiSh) or Heaorv (low) tas at the current PaSe
Hanased Addresses. Output of the Pase Hap Raas. See
Table 5 tor translation to data bus scheae.
Output Enable for Context Resister, address 0x8800001
I
Protection Code entries into the PaSe Hap Ria.. See I
Table 5 tor translation to data bus scheae. and I
APpendix F for code that sene rates s.aperr-.
I
1
_ _ _ _-40 _ _ _ _•_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
--1..,--
-----_. -,------------------------------Sisnals cont'd
I
Heaor~ Hana~eaent
1____ _
1
__ -----------------------------------______1
I
Hap Error. See APpendix F for code.
I
1
I
Indicates PaSe has been accessed successtull~.
I
saaperrused
we_cx-
Write coaDand for Context ReSister, address OxSSOOOO
Write Enable for Hap Raas, address OxSOOOOO
Write enables for Upper and lower Pase Hap words.
Write Hap ExtenUon. The write control to the
PaSe HaP Raa haldlnS the four p'ase status bits.
See PALPl for eans.
..
Pa~e
xaO:U
Raas phYsical addresses. See Table 4.
~
I ___________ ______________________.____________..______________-----_---1
The tollowi~ t.bles describe onbo.rd Options .vailable. The
defaults (etched in on the circuit card) are shawn as -en) --- (nfl)-.
Appendix A.l - JBl
This
Ju~er
block allows selection of:
1)
Serial Part 8 Trans.it and Receive pins on connector J1
2)
Extended Addresses tor the Proa sockets •
-I. -----------------------------------------------JBt:
______________
..._---1.I
1
I
•
p2.rxd
•1 J1.p2.txdlrxd
I
(1) -- (2) I J1.p2.rxd/txdl
(3)
(4) 1 p2.txd
I
1
I
1
vcc
(5)
(6)
•1
114
(7)
(8)
I
1
I
vec
a15
(9)
(11)
•
•1
1
,
- f - vcc/a14'
_I
I
(10) 1 ---+- vec/ a151
(12) 1 __ I
1
_ _ _ _ _ 1I
••
______-1.•
The eo.aunications default ultiaatelv selects pin 3 of the RS-232
connector IS Receive. and pin 2 as Transait.
To swap Port 8 Trans.it and Receive:
1)
Cut
2)
Juaper (1) to (3) and (3) to (4).
(1) fro. (2) and (3) fro. (4).
The Pro. addresses are defaulted for 2764 (8192 x 8) JEDEC devic.s.
To select 27128's:
To select 27256'5:
1)
Cut (5) fro. (6) Ind
2)
Cut (9) fro. (10) Ind Juaper (11) to (12)
Ju~er
(7) to (8) tosether.
__1.0__
to~ether.
APpendix A.2 - JB2
JuaPer J82 sets the Interrupt level ot the UART at INT 5 and sets
the Tiaer Channel 2 to INT 6.
J82:
1_________________________________
--11
1
1
1 int.sio--- I
I int.ttaer2- I
1I _
I
1
(2)1
(3) --- (4)1
(1) ---
1
int5-1
int6-1
________ !1_______ !I
~endix
A.l - J8l
Ju.per J83 selects vlrious Hultibus coaaands and controls.
J8l:
.- - - - - - - I
b.init-
-+-1
I_I
I
b.bdk.- I
I
b.l:)pm- I
I
b.cclk.- I
• _______...1I
--
I
I
initI
(l) -- (4) I set.init-I
I
I
(S) - - (6) I bdk
I
I
I
(7)
(8) I tround
I
I
I
I
(9) --- (10)1 cdk.
I
I
(1)
(2) I
I
I ............
1____
The top 2 pairs select the source tor the Hultibus Reset ,isnal
b-init-. The default 15 for set.init- to drive it. This Illows lets
the external Reset Switch, Uatchdos Tiaer and Power Level Co.parator
to reset the Kultibus. The other option is to cut (3) froa (4) and
connect (1) to (2) tosether to source init- to the Hultibus. This
option will add the 68000'5 Reset instruction to the first three.
The third pair defaults the source of the Hulttbus Bus Arbitor
elock b-bclk- to eoae fraa the Proeessor itself. If another device on
the Hultibus is seleeted to drive this sisnalr then YOU aust cut (5)
fro. (6) ~ ~.
'
The fourth pair default is Hultibus Haster Priority not at the
Hi.hest level. This option assuaes one of the tollowinS:
1)
There is .,Hisher Priority Bus Haster in one slot above the Pro':Cessor board in a Serial Priority scheae.
2)
There is I Parallel Priority Scheae. one whose Arbitration is
deterained bv lotte on the Hultibus aotherboard.
For a Sinsle Board eontituration, or one that has the Processor
as the Hi!!hest Priority Hasterr then YOU aust Ju.,er (1) to (8)
totether •
. The fifth Plir defaults the source of the Hultibus Constant Clock
'b_cclk- as .the Processor itselt. This clock is used by other Cadi inc
Board produets to svnchronize Hultibus Ind Hishspeed bus tiains with
the Processor board and should not be cut. However, when aore than one
Proeesor board is plutsed into one card--cate (tor various reasons),
" then the Haster Processor (the one that drives the Hishs,eed bus)
should hive this line intaet and all of the others aust cut (9) froa
UO) •..
-11-
Ap~endix
A.4 - JB4
Ju.~er JB4 selects Interrupts froa the Hultibus. (Note that int.6and int7- are out of seQuence at the top o~ the block.)
JB4:
1I_i---____________________________
;
lI
t ;
I
t btint.6- 1 (1)
1 b.int7- 1 en
I b.int.5- I
(5) --1 b.int4- 1 (7) --1 b.int3- f (9) --I b.int2- 1 (11) --1 b.int.l- 1 (13) --1
1_.
t
I
(2) 1
(4) 1
(6) I
(8) I
(10)1
(12)1
(14) 1
int6-1
int7-t
int5-1
int4-1
int3-1
int2-1
int.1-1
I
_
I
I
_ _ 1_ ••• ____ --1_--1
Interrupts int6- and int7- are not. defaulted throush because
t.hose levels on the Processor have predefined funct.ions that should
not ehan~. If theY are enabled, then the User aust take eare in handli~ the Refresh
routines (int7-) and the Prosra•• ableInterrupt
(int.6-) so as not to eonflict with the Processor.
-_
."
Appendix B - Initial He.orv Happins
.'P.
The CADLINC BASIC HONITOR will establish the tollowins .e.orv
The Pa~e .ap preserves v4rtual addresses in all contexts, and
allows III Iccess tvpes to all users tor all addresses except the onbond RAH holdiM the 4014 uulator, whic!l is protected a!ainst all
use~tate accesses but allows all supervisor-state accesses.
Virtual
Low Addr
llvtes
000000
256
000100
256
000200
512
000400
3k
001000
I
I
I
__ 1
I
I
I
I
I
I
I
I
I
252K
orl
.ore, less I
eaulator tol
ux ot604K I
I
Top at HS
tal·
ra.
097FFF
f
I
1_
I
I
I
I
I
Happed I Phvsicall Noraal Contents
tot
I Address I
-
.. ____1-_____________________
I
I
HS busl 000000
Pre-defined vectors
I
HS busl 000100
RAH refresh routine
I
HS busl 000200
Global data, rastopO
I
HS bust 000400
Supervisor stack
I
HS busl 001000
-
I
I
I
I
I
I
I
I
-
All installed hi!lhspeedl
I
bus Raa
Invalid
Initi.l Processor He.orv HaP cont'd
-73-
I
I
I
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
.L
I
Virtual I B~tesl Happed I Ph~sical
'Noraal Contents
I
Low
Addr'
,
t
o
:
'
Address
II
_ _ _.....1_ _--1.._
1 - -__ .
_ 1 ________________1
1
I
09BOOO I 32k
,
HS
1
I
I
1
OAOOOO
I
,
bus' (top
oft 4014 e.ulator.code
, inshlled' 1
1 hiShspeed. 1
1 bus RAM) 1 32k
I
64k
,
,
I
I
,
,
HB 1-01 0000
SHD Disk controllers. 1
followed
b~
Ethernet I
. aodules. extra serial I/O 1
ports. tiaers. etc.
1
I
1
1
I
,
OBoooo
64k
HB aeal
FDOOOO
3Coa ethernet aodules
,
OCOOOO
12Bk
HB aeal
FEOOOO
Raster
,
OEoooo
12Bk
HS busl
7EOOOO
Floatins Point Hodule
I
I
_ _ _....L-_--1_
I
1_
Initial Processor
_ __ 1
Heao~v
Displa~
Hodule
,
,
I'
,
__ . _______--1
Hap cont/d
1 Virtual 1 Bvtes
I1______
Low Addrl1
Happed I Phvstcall
to:
I AddresS" I
Noraal Contents
I
I
_ _ _____11
880000
1 __ •• ,
1_ _____,_______
1
I
I
I
Re.aini~ hishspeed bus RAH
I
5H
I HS bus I.. 098000
I
1
I
I
Hultibus RAH, etc.
HB aeal 000000
2H or 1920k
I
I
HltFunct board 0 proas, HVRAHI
HB aea I FAOOOO
128k
I
I
Pase Hap Resisters
1
512k
I I .'
I
Context Resister
I
512k
I -
900000
512k
100000
600000
7EOOOO
800000
1
I
I
I
Initial
P~ocesso~
Parallel 110 Resisters
.,1 __
He.orv Hap cont'd
_ _ a,
, __ . . . _ _ _ _ _
,.
I
I
-l
J
J Virtual
J low Addr
Happed 1 PhYsical I Nor.al Contents
.1
I
to:
I
Address
1
I
__1 - - - - 1 _ _
J _ _ _ _ _ _ _ _ _ _ _ _ _--1
B~tesl
980000
512k
Clear Boot State
COOOOO
512k
PROH 0
C80000
S12k
PROH 1
000000
512k
On-board UARTs
080000
512k
On-board n.er
F80000
512k
I
_____....1_______'1..._
----:..1 __ _ . _
VPA (not used by pro~ra.s)
.. _ _ _ _--1
L _____ _
Initial Processor He.orv Hap cont1d
The standard phYsical address settings used
b~
Cadi inc are as follows:
1
I Address RansR 1I______
S~ace'
Hodule
I
1____
.
I..
__________________1
1 000000 - OlFFFFI Local busl
I 040000 - FDfFFFI HS bus I
,
,
I
I FEOOOO - FFFFFFI HS bus I
,
1_
I
• _____ 1
On-board raa
I
Dual-ported
raa,1
hish-speed bus Iccess'
Floating Point Hodulel
I
I
___-1-_______________1
--------------------------------I
I
Sp.ace I Int. I Hodule
I Level I
Address Ranse
1__ ..
I
-
I
79FFFFI HB aeal
,
000000
(HaxiJaU.>
I
top
to
next' HB lell
aodule
I
liB aell
FBOOOO - F9FFFF
I
tiD ... 1
f80000 - f8FFFF
-
,.ell ,
fAOOOO - FBFFFF
tiD
FAOOoo - FAFFFf
HB lell
I
tiD .eal 2
-
fDOOOO - FD1FFf
HB aea'
2
I
FD4000 - FD5FFF
FD6oo0 - FD7fFF
HB aeal 2
I
HB leal 2
fEOOOO - FFFFFF
HB aeal
I
_L
Standard
n*
L•••
Phvsi~.l
I
I
Dual-POrted
raa,
I
aulI tibus access
I Hul tibus ral
I
I HltFunct 1 ,2764's
I
I
I
Hltfunct 1 ,2732's
I Hltfunct. 0 , 2764's
I
I HltFunct. 0 ,2732's
I
I
,
leal ethernet. aodule 01
I
I
fD2000 - fD1FFF
1 _ - - -_____ .
I
___ --1I
I lCo. ethernet aodule 11
I
I
I
I
lCoa et.hemet. aodul. 21
I
1 leol ethernet aodule 11
1
I
Rast.er
Displ.v
Hodule
I
_1 _______ . _________ --1I
Addresses -
He.o~
Hate that .11 of the floatios Point Hodule is aapped; floatios
point operations are nor.all~ initiated in the 10Sicai processor partition at virt.ual address. Of0000. Due to ladul. constrlints, t.here is
alwavs a p.rtition at this address.
I
Address ran~e lInt
Hodule
1I _________________
___________ 1I ____________
________________________!I
!~
OODO
__ EO
__ EB
--FO
__F4
OOFa
OOFC
01_0
0200
8000
8200
rFOO
_ 00D1 .
- --E1 .
- __ EF
- __ F3
- .__F7
- OOFB
- OOFF
- 01_6
- 025F
- 801F
- 821F
- FF7F
I
I
______
~
~
3
3 or 4
3 or 4
4
4
4
4
2**
1
5
5
1
CPC Tape.aster tape cntrl
DTC-510A/DTC-86 disk cntrl 0
DTC-510A/DTC-86 disk cntrl 1
Interphase S"D-2180 disk cntrl 0
Interphase SHD-2180 disk cntrl 1
Interphase SHD-2181 disk cntrl 0
Interphase 5HD-2181 disk cntrl 1
3 Hbit Ethernet Module
Antt-aliased Raster Display Hodule
HI tFunct board 0 ilo ports
HltFunct bond 1 ilo ports
Dual-ported aeDOrY aultibus parity
tla~sltault
_ _ _ _ _1 ___________________
__1I
Standard Physical Addresses - Hultibus 1-0
-** - These interrupt
-- -levels
-are
,
user-pr~ra•• able.
not
Juaper selected' these are the default levels used.
Appendix C - Hultibus Bus Pin Assi9n.ents (P1)
-------------------------------------------I
I
I Hneaonie I Pin II Pin I' Hneaonie
(Solder Side)1
(IC Side)..J.I____1I______1I __________
I1____
,-_1
,
I
1
3
S
7
I Snd
I vcc
I vee
1 12vde
1 -Svdc
I tnd
I b-bclkI b-bprnb_busvb-ardeb_ioreb-xlekne
b_bhenb-ebrab_cclkb_intab_int6b_inUb_int2b-intob_a14b-a12b_a10b_a8b_a6b-a4b_a2b-Iob_d14b_d12b_d10b_d8b_d6b_d4b_d2b_dolind
>
13
15
17
19
21
23
25
27
,,
29
f
31
33
35
I
I
I
I
I
I
I
'l7
I
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67 t
69
71
73 I
75 I
,,
nc
n
-l2vdc
79
81
83
85
I vee
'vcc
I lind
I
I
9
11
I
I
I
I
I
I
I
I
I
I
I
I
I
I
f
I
I
I
2 I 9nd
4 I vee
6 I vee
8 I 12vde
10 I -Svdc
12 I tnd
14 f b_init16 1 b-bpro18 I b_breCl20 I b_awte22 I b_iowc24 I b_inh1b_inh226
b_11628
b_a1730
b_al832
b_a19J.i
b_int736
b_int538
b_int340
b_int142
b_atS44
b_a1346
b_illl48
b_a950
b_a752
b_a554
b_a356
b_a1S8
b_d1560
b_d1362
b_dll64
b_d966
b_d768
b_d570
b_d372
b_d174
tnd
76
78
nc
-12vde
80
82
vee
84
86
vee
__ -'0--
~d
Appendix D - Hi.hspeed Bus Pin ASli!lnaents (P2)
-------------
. ----------,
I
1
1
1 Hnellanie 1 Pin ., Pin .1
1
I
1 <Ie Side) 1
' _ _ _ 1.
_1_
11
I
2 1
1 1
~rea4 1
3 1
Llla20
lI_r/w6
5 1
8
7 1
L8a19
9 1 10
Luds12
11
Lrfenab
14
13
ne
16
15
II-Perr17
18
Ldl20
19
Ld322
21
ne
24
23
Ld426
25
nc:28
27
La3
30
29
Ld732
31
nc:
34
33
ne
36
lI_d835
38
37
La7
40
39
Inc:
42
41
Ldl044
43
lind
46
45
ftc:
48
47
Ld1249
50
nc:51
52
nc:54
53
Ld14b_a2255
56
58
b_a2057
60
59
ftc:
I
----
1.
SVllbals used:
nc:- • No Connection
!lnd • Ground
Hn..onie
,
(Solder
_ _ Side)1
_ _1
lI_waitlI_aa23
LIIa21
1I_8a22
LldsLCI5LIIa18
lI-IIa17
LdoLd2LaO
ne
II_ciSftc:
Ld6La!
La6
Ld9-.
ftc:
La2
Ldll!Ind·
La4
Ld13ftc:
II_aS
Ld15b-a23b_a21nc:
1____ .1 ___
. _ _ _1
Appendix E - Co ••unieations and Parallel Ports
----------------------------------------
J2 Parallel Port:
J1 Co••unieatton Port:
1
1I ___________________________
1I
I ___________________________________
1
I
1
J1.pl.txd 3
J1.p1.rxd 5
7
9
11
snd 13
15
17
19
21
23
25
27
29
31
33
35
37
J1.p2.dtr 39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28 J1.p2.txdlrxd
JO J1.p2.rxdltxd
32 J2.p2.rts
34 J2.p2.cts
36
38 !lnd
40
42
44
46
48
50
J2.inO
J2.inl
J2.in2
J2.in3
J2.1n4
J2.in5
J2.1n6
J2.in7
J2.in8
J2.in9
J2.in10
J2.in11
J2.1n12
J2.in13
J2.1n14
J2.in15
oe.pol't-
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
w/r- 41
J2.as 43
set.init- 45
J2.halt- 47
'ICC 49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
snd
SM
snd
snd
snd
snd
snd
!lnd
snd
*,d
!lnd
!lnd
!lnd
snd
!lnd
and
!lnd
!lnd
!lnd
snd
!lnd
snd
snd
Ind
!lnd
• ___1
__ At_
Appendix F - Pfotection PRO" Code
1* Protection Pro. for Enhanced Processor *1
1* 2l-JAH-8l Geof.e Kiewic%
Chansed state of
.define
.define
'define
'detine
.define
tdefine
.define
'define
'detine
prott
Pfot2
protl
protO
s~slee_i
a2
a8
a1
10
87
s~sacc_i
fel
teO
read al
tc2
a5
84
a6
'define prot (protO*dO + protl*dl + Pfot2*d2
tdefine s~s-access (s~slcc_i)
'define execute_~cle (fel 'I !feO II read)
tdefine read_c~le
(!tel II feO II read)
tdefine write_~ele
(!rel II teO 'I tread)
char protcodeC16][7l •
-(
I
0
____ I,
t I--X_I,
11"___ 1,
'2..
"3
t{
~
h
7
~
q
a~
~
C
c1
~
)0
J
-~
-92-
11"_X___ I,
Irw____ I,
Irwx __ I,
11"_1"_1,
Irw_r__ ',
11'__ N_ I.
Irw_rw_',
'fW_I"-XI,
Irw_rwx',
11'-XI"_XI,
I l'WX r_x I ,
IrwX-X ' ,
'fwxrwx'
+ Pfotl*dl)
*1
sa.perr(add)
tnt add;
{
int res - 0;
res I- (te2 " read-cvele " (protcodeCprotJCOl == 'r'»?1:0;
res Iz ( fc2 " write.evcle " (protcodeCprotlCll == 'w'»?1:0;
res I- (tc2 " execute.cvcle " (protcodeCprotJC2J == 'x'»?1:0;
res I- (ltc2 II read.cvcle U (protcadeCprotJC3l == 'r'»?1:0;
res I- (Itc2 " write.evcle 'I (protcode[protJC4J == 'w'»?1:0;
res I- (Itc2 " execute.cvcl~ " (protcadeCprotlC5J == 'x'»?1:0;
res - (res " !svs.access)11:0f
return(res);
a.in()
{
5ize(512);
proaCd4,O)J
proa(d5,0) ,
proa(d6,saaperrCadd»'
proaCd7,lsaaperr(add»'
prolotblasti
·-83-
APpendix G - PAL Codes
The Series BOA Processor aakes extensive use of PALs (Pro~raa.­
Arra~ Losic
I.C.) to perforl lost of the necessar~ discrete
lo~ic. Each PAL is coded to use its inputs as ele~ents of a lo~ic
eauation, in either '1' state or '0' state, losicall~ 'anded' into
·product· lines that can be 'ored' with as aan~ as 6 more 'product'
lines. The tri-state output can be controlled b~ an 8th 'product'
line. Six of the ei~ht outputs can be ted-back into the internal
aatrix and used as aore input ele.ents. Two pins are then dedicated as
outputs onl~, and ten as inputs onl~.
able
PALs ~iye the Processor sreat flexibilit~ b~ e1iainatin~ a Sreat
aanw discrete I.C.s and consolidatins their functions into a s.a11
nu.ber of prosra•• able chips. Board la~out is aided bv the lostl~
arbitrarv pin assi~naent structure, Which can be better aanipulated b~
fir.ware than b~ artwork.
The followins pa~es are the lo~ic eauations tor the individual
PALs on board the Series 80A Processor. The for.at here is as the
Structured Desi~n 5D20/24 PAL proSraamer reauires, called PALASH.
Sale ane.onics have been abbreviated for clarit~ and all are in
upper-case letters.
One tvPe at PAL chip is used for all 5 Processor PALS, the
PAL16L8-A. and pro~ra •• ed with individual code. All eauations are
evaluated to yield 'low true' results. This reduces the reauire.ent
tor extra losic inverters since lost IC's with control si~nals are
'low true' anvwav. A tew anelonics, e.S. DS. SYSACC and BHEN, are
written tor a 'hish true' output, so their losic eauations tend not to
be as strai~htforward as the others. The losic sVlbols used are:
./.
•••
'f'
'a'
When ane.onic is low true. otherwise hish true.
Lasical AND.
Losical OR.
When Risht side of eauation is true. aake the Lett ane.onic low.
--84--
Appendix G.l - PAlPO
PA116l8
p.rod 3
rev 0.0
!ieorSe kiewicz
s~ste. control pal
cadlinc, inc.; 55 park st.;
rw
IS
troY, aieh
48083
tc2 boot a23 a22 a21 a20 ds !ind
a19 clrboot oecx devenab ce.ap oeport weaap weex sysace vec
*
* * *
Ice.ap=fc2 * ds * a23 *la22 *la21 * la20 * la19
Iwe.ap=tc2 * ds * a23 * la22 *la21 * la20 * la19 * Irw * las
loecx=fc2 * ds * a23 * la22 * la21 * la20 * a19 * rw
Iwecx=fc2 * ds * a23 * la22 * la21 * la20 * 819 * Irw * las
loeport=fc2 * ds * a23 * la22 * la21 * a20 * la19
Iclrboot=fc2 * ds * a23 * la22 * la21 * 820 * a19 * Irw * las~
Idevenab=fc2 * ds * a2l * a22
tfc2 * ds * la23 * la22 * la21 * la20 *la19*boot*rw
Isysacc=as f las Iboot * la23
f/as boot Irw 1;23
description
18-apr-83 charuiins -oeport-to read-write, and chansins -clrbootaddress to Ox980000.
svsacc chansed to hish tor syste., low tor .anated 20-Jan-83
s~ste.
800000
880000
900000
980000
cOOOOO
c80000
dOOOOO
d80000
f80000
addresses:
- pase.ap resisters
- context resister
- parallel port
- clear boot
- pro. 0
- pro. 1
- uart
- tiaer
- hardware vpa
r-w
r-w
r-w
w
r
r
r-w
r-w
not used by software
--es--
A,.~endix
G.2 - PAlPl
PAL16L8
pal pi prod 5
rey 0.0
seorse kiewic%
parity control
cadlinc inc, 55 park st., troY" .ich. 48083
oera. bl .a20 .a22 .a19 .,.err prtYenab parerru parerrl snd
lperr enlperr parerr onbrd aa18 rw ma21 .a23 wr vec
lonbrd
=l.a18
* l.al9 * l_a20 * l.a21 * l.a22 *l.a23 * loera.
Iwr • rw
len!perr • lonbrd
+ lonbrd
Iparerr • 11perr
+ I.perr
* loera.
* loeraa
* parerru * rw
* parerrl * rw
*prtvenab
* prtvenab
description
version 2 of paritv i.ple.entation.
version 4 of parity stuff tor the box (sorrv, don). trvins bl in
seneratins lonbrd to ayoid ~ettin~ Icas durin~ .ultibus access.
.
16-.ar-83
version 5 ~ettins rid of Ibl in lonbrd ad teplacins with loera••
18-.ar-83
--86--
Appendix G.3 - PALP2
PAL16LB
p;1p2
.. rod 5
.,k.
bus status
cadlinc, inc., 55 ..ark. st., troy .ich
48083
bl parerr sa...err Ids ti.eout uds sysace aen CIS
csl0 bhen xaek ds berrx ioa dtack fc2 berr vee
* *
*
* *
*
*
~nd
Iberr • CIS ds sysacc Ifc2
+ cs5 ds Iparerr
+ csS ds Isysacc IS.,Perr
+ ds * ttaeout
+ csS ds Isysacc 10. Ibl
* *
* *
lberrx
*
=
tiaeout
+ Iparerr
+ Isa...err
+ io. Ibl
* * ds
Idtaek = esS * sysace * csl0
+ esS * Isysacc * lioa * Ibl * berrx
+ csS * Isysacc * bl * ioa * laen * xack *berrx * cs10
+.csS * Isysacc * bl * 110. * lien * xack * berrx
+ esS * Idtack * berrx
Ids • Ids
* uds
Ibhen • lds
+ uds
description
l1-aav-83 aualifv -dtack- with -csl0- dUrin~ a aultibus io access
only. aultibus aeaorv is unchan.ed.
28-a.r-~3
latched dtack with csS. also insert berrx into dtaack.
lenerate bus controls dtack and berr tor the 68000
on clockstate csS, sysacc, and error info •
• lso produce data strobe -ds- and aultibus bvte hilh enable -bhenlroa 68000 data strobes -lds- ad -uds-•
•
svsacc sense chanted. hilh for svstea, law tor
--81--
.anl~ed.
20-Jan-83.
Appendix
G.~
- PALPl
PAL16LB
palp3
prod 6
ieorse kiewicz
reQuest and wait Senerators
cadlinc, inc., SS park st.,
troY, aich
48083
bl as saaperr cs6 cl00 weaplaen csl cs4 ind
await aprea bas weapx enablto cswait boot a23 enpx vcc
* las
* saaperr * las
lenpx = cs6 * saaperr
Iweapx
=Iweapl
+ cs6
Icswait
=las· * la23 * Icl00 * Ics4 * Iboot
* /a23 * Ibl * Ilwait * Ics4 * Iboot
+ las
+ las
*la23 * bl * aen * esl * Ics4 * Iboot
lenablto = las * la23 * Ibl
+ las * laen * bl * la23
laprea = las * la23 * Ibl * /boot * es3
Ibas =csl * la23 * bl * Iboot
description
23-asy-B3 re.ove -es3- fro. -cswait eQuation. this allows for a
sloppier -as- to synchronize back to Sene rate -cs3- on a low
state of -cl00-. initially to fix fluke inability to access
dual port aeaorY, this will .lso clean any .ar~inal 68000 parts
whose tiainss are at the lon~ end of the spec.
12-aav-83
add -aen- and -bl- into eauation for -cswait- to SQueeze out
• bit aore tiae for aultibus accesses.
produce hiShspeed bus reQuest -aprea- and aultibus
reQuest -bas- only durins a aanased access (/a23),
Sene rate -cswait- to insert a wait when the hishspeed bus
is not ready <await).
4-aar iaprove -enabto- ieneration on aanased reQuest to aultibus
--88--
Appendix G.5 - PALP4
PAL16L8
palp4
prod 4
sak
lultibus. local ril and io read-write controls
eadline
s~sace iOI bl rw berrx es6 Ids uds eesio snd
eetiler Iwte dtaek weralu oeraa weraal iowe iore .rde vee
Ilwtc
=esc * Irw * bl * liol * berrx * Is~saee * lIds
+ esc */rw * bl * /101 * berrx * Is~saee * Iuds
** rwrw **blbl **liol
* berrx *
* lIds
liol * berrx *
* IIJds
liore • csc * rw * bl * iOI * berrx *
* lIds
+ es6 * rw * bl *iol * berrx *
* Iuds
+ esc * rw *
* leetimer * lIds
+ cSc * rw *
*
Icetiler * Iuds
t es6 * rw *
* leesio *Iuds
liowe =esc * Irw * bl * io. * berrx *
* Ilds * dtack
+ esc * Irw * bl * iOI * berrx *
*
Iuds * dtaeK
+ csc * Irw * svsacc * Icetiaer * lIds
+ esc * Irw *
* Icetiaer * Iuds
+ esc * Irw *
* leesio * Iuds
loeraa = Ibl * liol * berrx *
* lIds
+ Ibl * liol * berrx *
* Iuds
Is~saee
Is~sacc
Ilrde • esc
+ es6
Is~saec
Is~sacc
s~saec
s~saec
s~saee
Is~sacc
Is~sacc
s~saee
s~sacc
Is~sace
Is~sacc
* Ibl * liol * berrx * Isvsacc * Iuds
=Irw * Ibl * liol * berrx * Is~sace * Ilds
Iweralu • Irw
Iweraal
description
28-aar-83 added dtaek to lultibus writes to turn com.and off.
also swapped pins 12 and 13 to .ake roo. for dtack.
s~aec sense chansed to hish for s~ste •• low for .anased.
--A9--
READER'S COHHENTS FORM
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Please be sure to include the docuGent Title and Number when returning
this fora.
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ized? Please lake suggestions for ilProveGent:
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specif~
organ-
the error
NAME ____________________________________________ DATE _________ _
ORGANIZATION ___________________________________________________ _
STREET _________________________________________________________ _
CITY _____________________________ STATE _______ ZIP __________ _
Hail to:
CADLINC Inc.
55 Park. St.
Troy, HI 48083
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