Workshop Novel materials, devices and technologies for high performance
on‐chip RF applications
ESSDERC 2012
Friday, September 21, 2012
Bordeaux
France
Digitally Tuning capacitor: from RF to
Millimeter Wave applications in
advanced CMOS Technologies
Yvan Morandini1,3, Daniel Gloria2, Thomas Quemerais2,
Frederic Gianesello2, Florence Sonnerat2
1 IBM, SRDC, 850 rue Jean Monnet 38926 Cedex Crolles, FRANCE
2 STMICROELECTRONICS, T R&D, 850 rue Jean Monnet 38926 Cedex Crolles, FRANCE
3 DOLPHIN INTEGRATION, 39 avenue du Granier, 38942 Cedex Meylan, FRANCE
1
Overview
• Context & Motivation
•
•
•
•
•
Agility Topic
Front end module challenges
RF Transceiver Digitally assisted (RF) challenge
Millimeter Wave applications challenge
Tunable Capacitor: needs and specifications
• Digitally Tunable Capacitors solutions
•
•
•
•
•
Tunable Capacitor : State of the art
Which DTC type for which applications : choice of Architecture?
Measurements Methodology
Modeling Methodology
Automated Design
• Example of circuit applications
• Conclusion and perspectives
2
Agility Topic
Agile System
Antenna tuning
Beamforming
Phase Shifting
Matching
Agility
Filtering
VCO
Agile Function
Phase Locking
Duplexing
Powering
Front-end module : Challenges (1/2)
Antenna Tuner Challenge
Bezooijen, IMS2012
Kelly, IMS2010
Gianesello, SOI conf 2011
4
Front-end module : Challenges (2/2)
• 4G/LTE standards introduce a large number of new bands of
frequencies to be supported.
• This multiplication of frequencies dramatically complicate the Front
End Module of world phones, particularly the filtering part.
• Current architectures tends to add a new physical filtering path for
each frequency that need to be supported, creating routing issues and
consuming a lot of area.
• Agile filtering would allow to greatly reduce both complexity and cost
of the FEM of world phones.
To adress antenna tuner and agile duplexing :
High Power and high Tuning range tunable
Capacitor
5
Digitally Assisted RF : scaling down
• Scaling down of CMOS technology and reduction in supply voltage :
complexity to implementate RF circuits
• Use of digitally-assisted involves RF circuit implementation
Staszweski IMS2012
6
Digitally Assisted RF : DPLL & DCO
• All-digital phase-locked loop (ADPLL) : adapted to PVT variations and ease of portability to
different processes
• Fine frequency resolution : minimum device size
• Wide-tuning : digitally bank control
Start Frequency Locking
PVT Calibration Mode
Broad frequency range : ΔfPmax
Coarse frequency steps :ΔfP
Acquisition Mode
Medium frequency range : ΔfAmax
Medium frequency steps :ΔfA
Tracking Mode
Narrow frequency range : ΔfTmax
Fine frequency steps :ΔfT
Operating Mode DCO
Frequency steps versus capacitance steps
7
DCO : state of the Art
DCO
Technology
ΔCmin [aF]
Δf
Frequency
[1]
130nm
38
23 kHz
2.4 GHz
[2]
90nm
50
24 kHz
900 MHz
[3]
65nm
55
1.03 MHz
10.5 GHz
[4]
90nm
10
2 MHz
5.3 GHz
[6]
180nm
4
14 kHz
5.8 GHz
[7]
65nm
16
20kHz
5.8 GHz
Debroucke, PhD Defense 2011
Very Agressive Specifications in term of
Capacitance step to address DCO function
8
MMW applications
• Wireless MMW Markets
• Wireless Video 60 GHz
• Automotive Radar 77 GHz
• Medical Imaging 120 GHz
Natarajan, JSSC2012
• In Situ MMW Characterization Fully-integrated 60-GHz phased-array receiver architecture and frequency plan
• Noise Parameters extraction based on the use of impedance synthesizer
(Tuner) up to 220 GHz
• Power available efficiency based on the use of impedance synthesizer up to
200 GHz.
• Off-Wafer tuner is limited by the frequency range and generate high losses
between this external tuner and the device under test
• In situ tuner is required
9
MMW Agile function : Phase shifter
• Phase shifter localization in an receiver module for beamforming
Aim : Antenna
phased controlled to
steer the beam
• Phase shifter performances are based on agility of variable load (tunable
component)
• Phase shifter specifications:
• Phase shift step commonly used to achieved a full 0-360°:22.5°, 45°,90°and
180°
• Fine phase control : 10°
• W-HDMI band : 57 – 66GHz
• Low phase variation
MMW tunable capacitor with high tuning
range to address MMW circuit
10
Tunable Capacitor Needs
Front End Module
Circuits
RF transmitter
Circuits
MMW applications
High Power
Tunable Capacitor
High precision
Tunable Capacitor
High Frequency
Tunable Capacitor
Capacitance range
500fF to 20pF
10aF to 2pF
10fF to 500fF
Step Capacitance
100fF to 10pF
10aF to 20fF
100aF to 20fF
Tuning Range
>10
<5
>4
Power Handling
>30dBm
10dBm
10dBm
Operating Frequency
2GHz
10GHz
>30GHz
11
Overview
• Context & Motivation
•
•
•
•
•
Agility Topic
Front end module challenges
RF Transceiver Digitally assisted (RF) challenge
Millimeter Wave applications challenge
Tunable Capacitor: needs and specifications
• Digitally Tunable Capacitor solutions
•
•
•
•
•
Tunable Capacitor : State of the art
Which DTC type for which applications : choice of Architecture?
Measurements Methodology
Modeling Methodology
Automated Design
• Example of circuit applications
• Conclusion and perspectives
12
Technology Benchmark on high power variable capacitor
Silicon
Key
Parameters
Figure of Merit
DTC
Varactor
SOI/SOS MOS/diode
Wide
Medium
Tuning Range
III/V
MEMS
BST
Wide
Wide
Narrow
Implementation
Quality factor
+
+
++
+++
+++
Bias Voltage
++
++
+
--
--
Power
Handling
+
--
+
+++
++
++
++
++
-
Not
enough
results
Cost
++
++
+
-
--
Packaging Size
Small
Small
Small
Big
Big
Reliability
DTC SOI is the best compromise
between performances and technologies implementation
to offer high power tunable capacitor
13
High precision and MMW tunable capacitor : varactor vs DTC
Varactor approach
Non linear behavior
versus voltage
Technology Impact
Layout/parasitic Impact
Limited fine tuning
Limited Tuning Range
Limited Tuning Range
Capacitance step limited
to the input voltage
precision
Limited Capacitance Range
DTC approach
Linear behavior
versus control
High precision
capacitance step
No technology Impact
Dedicated to high
Tuning Range
Architecture Impact
Poor Quality Factor
Developp specific DTC architecture
to propose High precision and MMW tunable capacitor
14
DTC : Operating Principle
• Simplified model of digitally tunable capacitor bank is composed of 2N-1 identical
elementary cells
b0
b1
bN-1
b2
• Each elementary cell is controlled by a digital word (bn-1,..., b2,b1,b0) and the total
capacitance can be represented as :


Ctotal  2 N  1 C0  b0  C  2  b1  C  ...  bN 1  2 N 1  C
• C0 and ∆C represent the initial capacitance of the elementary and the offset
cell, respectively
Specific Architecture to be developped
15
DTC power Concept : Stacked Transistor
• Problem to solve : Power Handling > 30dBm with Tuning Range>10
• Technology Solution: HRSOI technology
• Architecture Solution : Stacked serial transistor with good isolation
ON
RF Group 28/09/2012
OFF
16
16
High precision DTC : scaling down
• Problems to solve : make capacitance step of the order of attofarad value
• Constraints to be fulfilled:
• Propose a solution with digital control
• Propose a solution with limited impact on process variation
• Limited sensitivity to matching in matrix configuration
• Technological Solution: Advanced CMOS technology
output
T1
R
T2
L=30nm
W=80nm
Nfing=1
Mult=1
Ground
R
L=30nm
W=80nm + ΔW
ΔW=10nm
Nfing=1
Mult=1
Ground
inversor
Vctrl
Embodidment of 2
MOS transistor
with 1 bulk
connection and
proximity of 2
MOS
transistors
DTC aF
Unit cell : digital inversor + N LVT RFMOSFET
T1
DC/RF decoupling
resistor
T2
DC/RF decoupling
resistor
Layout of high precision DTC implemented
on CMOS 28nm CMOS Technology
17
MMW DTC concept : Travelling Wave
• Problem to solve : Operating Frequency >30GHz with Tuning Range>4
• Architecture Solution : Travelling Wave Concept
• Technology Solution : CMOS/BiCMOS Technology with high performance BEOL
• DTC Travelling Wave Architecture
• Transmission line is periodically loaded by MOSFETs switches
18
DTC Measurement Methodology
High Power
Tunable Capacitor
High precision
Tunable Capacitor
S-parameters measurements
until 67 GHZ
S-parameters measurements
until 67 GHZ on macro bank
Small Signal
Modeling extraction
Small Signal
Modeling extraction
Load-Pull Measurements
Non direct Methodology with LC Tank
frequency measurements
High power Characterization
aF capacitance step
extraction
High Frequency
Tunable Capacitor
S-parameters measurements
until 220 GHZ on macro bank
Small Signal
Modeling extraction
Load-Pull Measurements
until 220 GHZ
aF capacitance step
extraction
Large Signal Networks Analyzer
(LSNA) or NVNA
Non linear Modeling
behaviour (X-parameters)
19
Power DTC : Electrical results
LB DTC
Capa.
C1
4
Cmin (pF)
1
Cmax (pF)
12
ΔC (pF)
0.733 pF
C (pF)
Bit (state)
Capacitance vs. binary word
Frequency (Hz]
Capacitance vs. frequency
High Impact of parasitics (and then of Layout)
20
Fine tuning DTC : CMOS 28nm technology
Implementation (1/2)
30 bits control
1.83mm
4.38mm
DTC fF
unit cell :MoM + N LVT RFMOSFET
DTC aF
Unit cell : digital inversor + N LVT RFMOSFET
21
Fine tuning DTC : CMOS 28nm technology
Implementation (2/2)
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
20.1fF
1.67fF
120aF
7aF
1aF
Number of bits 6 bits
6 bits
6 bits
6bits
6bits
64 states 64 states 64 states 64 states
5E-14
1.078E-14
5E-18
1.80E-12
1.60E-12
4.5E-14
4E-14
1.077E-14
1.076E-14
4E-18
1.40E-12
1.20E-12
3.5E-14
3E-14
1.075E-14
1.074E-14
3E-18
1.00E-12
8.00E-13
2.5E-14
2E-14
1.073E-14
1.072E-14
2E-18
6.00E-13
4.00E-13
1.5E-14
1E-14
1.071E-14
1.070E-14
1E-18
2.00E-13
0.00E+00
5E-15
0
0
10
20
30
40
50
60
Cdtc (F)
2.00E-12
deltaCdtc (F)
Cdtc (F)
64 states
1.069E-14
1.068E-14
DeltaCdtc (F)
ΔC
0
0
10
20
30
40
Command
Command
Bank1
Bank5
50
60
22
High Precision DTC
B1
B2
DC commandW mos1
B1 to B6
W mos2
0.09um
Lmos1&2
0.08um
30nm
Nfing1&2
Mult1&2
1
1
B3
RFMOSFET 1 and 2
B4
B5
B6
∆Cmin_simu @5GHz
∆Cmin_mes @5GHz
1 aF
63aF
Vdd
inv
DTC capcitance (F)
DeltaC capcitance (F)
All simulation results are obtained with RFMOSFET model limited to metal 1.
The parasitic effects due to Metal 1 to 4 stack are not taken into account
Measurement Capacitance versus frequency
Measurement
Small Step capacitance versus frequency
23
High resolution LC tank
All DTC bank layout
30 bits DC command configuration
DTC capcitance (F)
Insertion losses (dB)
All DTC bank layout
Capacitance versus frequency
Fsim
Fmes
5GHz
4.81GHZ
LC operating Frequency
24
MMW DTC Characterization
• Travelling Wave DTC implemented on BiCMOS9MW technology
DTC1
DTC2
Debroucke, RFIC2011
Capacitance vs. frequency
High Performance TW DTC
TR>10
P1dBm@94GHz = 10dBm
Power measurement results at 94GHz for DTC1 and 2
25
Modeling Strategy
MOSFET Transistor
Available Library Model
Unit Cell Parasitic
Modeling
MIM or MoM capacitor
Available Library Model
Elementary Unit
Transmission Line
Access Modeling
b0
b1
b2
bN-1
Scalable DTC
Models
26
DTC modeling : parasitic of unit cells
Lacc
Cgd
Cdgnd
Racc
2 scale factors to be used:
• multiplicity (M) :
number of unit MOS
• number of fingers (N)
Cds
Cggn
d
Cgs
Racc
Lacc
Scalable model based on
analytical equations
 possibility to generate a
wide range of Cmin
Csgnd
2 fixed dimensions:
• finger width (2um)
• length (280nm)
Elementary cell parasitic Modeling + Transmission Line :
entire DTC Modeling
RF Group 28/09/2012
27
27
Modeling Results
• Problem to solve : Operating Frequency >30GHz with Tuning Range>4
Model
C DTC(pF)
Measurements
Model without parasitics
+50%
CMAX (pF)
CMIN (pF)
numéro état
fréquence (Hz)
fréquence (Hz)
28
Automatic Design
DTC input:
Cmin, Cmax, nb
bit, power, freq
Model
parameter
extraction
TCL/TK programm
Matlab:
Optimization
step for fitting
tcl routine:
Seed values for
empirical
analytical model
Initial
analytic
model
.lib Eldo file
Call .tcl routine :
input Cmin,Cmax,nb
bit, frequency
Power Handling
Specification :
number of
stacked MOS
Results: Mmos,
Nmos, Cmim
ADS Agilent + Matlab Program
Netlist + simulation
ELDO Simulator
DTC electrical results output
29
Overview
• Context & Motivation
•
•
•
•
•
Agility Topic
Front end module challenges
RF Transceiver Digitally assisted (RF) challenge
Millimeter Wave applications challenge
Tunable Capacitor: needs and specifications
• Digitally Tuning Capacitor solutions
•
•
•
•
•
Tunable Capacitor : State of the art
Which DTC type for which applications : choice of Architecture?
Measurements Methodology
Modeling Methodology
Automated Design
• Example of circuit applications
• Conclusion and perspectives
30
Antenna Tuner (1/2)
• Peregrine : CMOS 180nm SOS technology
Power Delivered to Antenna vs. Frequency
Kelly, IMS 2010
3rd Harmonic [dBm]
Capacitance vs. frequency
Input Power [dBm]
3rd Harmonic vs. Input Power
Fully Integrated
Antenna Tuner
Concept
Multiple DTCs and mixed-signal control can
be combined to create real-time ANT VSWR
correction
Whatley, RFIC 2011
31
Antenna Tuner (2/2)
• STMicroelectronics : 130nm CMOS SOI technology
• Leveraging SOI antenna switches experience, the development of high
power (and highly linear) Digitally Tuned Capacitor (DTC) is on its way.
• The tuner should benefit from a co-design with the antenna
Sonnerat, SiRF 2012
S11(dB) and S21 (dB) versus frequency of the measured tuner, for 12
phase states, for VSWRantenna=5:1 on the [400 MHz – 6 GHz]
band with a focus on the band 7: [2.5-2.69 GHz].
SOI CMOS DTC component, could play a
key role in the development of tunable FEM
32
High Resolution 60GHz DCO
• Mm-wave digitally-controlled oscillators (DCOs) with reconfigurable passive
resonators are proposed and achieved: wide tuning range (>10%) and fine
frequency resolution better than 160kHz
60 GHz ADPLL and RF frontend test chip block diagram
(a) Schematic of the proposed 60-GHz L-DCO
(b) inductor-based fine-tuning
(c) reconfigurable TL as coarse- and mid-coarsetuning
Wu, RFIC 2012
High Z Characterization create an opportunity to go
even further in the development of ultra fine coarse
variable capacitance
33
Millimeter Wave Characterization
• Noise Characterization : Si/SiGe HBT on B5T STMicroelectronics Technology
Comparison of the measured and
simulated tuner output impedances
between 56 GHz and 94 GHz
In-situ tuner schematic
Quemerais, RFIC 2012
NFmin vs Frequency
NPN Si/SiGe:C HBT transistor
Tuner micro-photography
1 emitter of Wemitter=0.18 ìm and Lemitter=5 ìm
VBE=0.85V, VCE=1.5V with IC=4 mA
34
Conclusion and perspective
• Digitally Tunable Capacitance enable to:
• Propose alternative solution for agile devices addressing wireless Market challenges
• Develop innovative and competitive offer versus analog capacitances
• DTC development need to have a global solution from layout to model
capability :
• Specific methodologies have been developed and qualified for testability and modeling
• DTCs enable to address the need of the wireless industry leveraging
technology scaling (More Moore) down to 28nm CMOS technology (and
below)
• But DTCs also create some additional opportunities with SOI technology
to propose added value through a « More than Moore » approach.
DTC Solution address wireless business needs leveraging both
Advanced bulk CMOS and SOI derivative Technologies
35
Acknowledgment
• Thanks to :
• Alin Ratiu for modeling work on DTC during internship
• Romain Debroucke for his collaboration to MMW DTC
development
• Cédric Durand and Jean-Christophe Ricard for their
collaboration on tunable duplexer development
Thank you !
37