Polliwog Product Lineup
Basic Suites
Manufacturing
Verification
PollEx PCB
Metal Mask Manager
PollEx DFM
For generating standard metal masks and verifying
masking rules
For detecting manufacturing defects in PCB designs
Mounting Emulator
For validating component mounting process
For detecting manufacturing/assembly defects in
PCB designs
Mounter-Machine Data Export
PollEx DFE
For exporting mounting data in machine-dependent
mounter formats
For detecting electrical defects in PCB designs
For checking discrepancies among PCB, schematic
and BOM and comparing two versions of PCB or
schematic designs
Gerber to PCB
For detecting electrical defects in schematic designs
PollEx CAM
Router Machine JIG Generator
For reviewing ECAD Designs
PollEx Logic
For reviewing schematic designs
PollEx BOM
For importing MS/Excel format BOMs and intelligently reading in ASCII BOMs
PollEx CP (CrossProbe)
PollEx Logic DFE
For extracting intelligent design data from Gerber/
ODB++ data
For reviewing 274D and 274X format Gerber data
For extracting router machine JIG data
PollEx Design Closure
Block JIG Generator
Validation
PollEx SI
For board level signal integrity analysis
For closing PCB designs with integrated design
and validation
For extracting block JIG data
UPMS
For extracting soldering pallet data
For managing unified part library data
PollEx DFA
PollEx SI Explorer
For pre-design interactive signal integrity analysis
Solder-Pallet Data Extractor
PollEx PI
Solder Quantity Calculator
For board level power integrity analysis
For calculating solder quantity from metal mask or
solder mask data
PollEx Thermal
For board level thermal analysis
PollEx PCB is linked to other POLLIWOG product family
Schematic
Design
Layout
Design
Manufacturing
CAE (Analysis)
Mount
Part Creation / Review
Design Review / Change
Analysis Engine
Soldering
Assembly
Test
UPMS / UPViewer
UDVS / PollEx PCB
PollEx CAM / PollEx Logic
PollEx PCB / PollEx Design Closure
PollEx SI
PollEx PI
PollEx Thermal
SI Explorer
PollEx PM / PollEx CE / Gerber to PCB
Utility
PollEx MagicNet
CAE Extractors
PollEx CP / PollEx BOM
Rule-Based Verification
Logic DFE
Work Sheet Planner
Mount SIM
PollEx DFE
PollEx DFM
Metal Mask
Manager
Block Design
PollEx DFM
PollEx DFS
PollEx DFA
PollEx DFM
PollEx PCB
Viewing ECAD Design Data
PollEx PCB
Do you want to see any design data? PollEx PCB is a good partner for your work!
While PCB Design tools are mostly reserved for PCB design engineers, frequently other engineering disciplines also need to access the design data
throughout the PCB design and manufacturing process for reviewing and analyzing the design.
PollEx PCB allows users to view all PCB design objects in detail. PollEx PCB quickly reads entire PCB design data and provides users with convenient
ways to explore the design details. Its flexible and intuitive GUIs allow users to easily view and modify ECAD files in various formats.
Its many features include query, measure, finding objects, and various reporting. This module is the basis of other PollEx suite of tools such as PollEx CP,
PollEx DFM, and PollEx DFE.
Supports All Major ECAD Formats
Vendor
Product
PCAD / Protel
Allegro
Spectra Quest
OrCAD Layout
Board Station / Neutral File
Expedition
PADS
ODB ++
CADSTAR
CR5000 Board Designer
CR5000 PWS
CR8000 Design Force
Features
Picking(Query)
Mouse click and figure out all properties of objects.
PCB Explorer(Search)
Easily search objects and object-linked structures on layout.
Can easily add new features requested by users
Supports customization services.
Extends to other optional products (DFM, DFE, SI or Thermal).
Supports various API (Application Program Interface).
Mark-up Function
Make comments on design, keep status and share them with other
engineers.
Restricted PDBB
Clear security problem with optimized layout saving.
PollEx PCB
Viewing ECAD Design Data
Data Group Features
Net Group Features
PCB Data Extractor
Net 2D/3D Viewer
Help users easily document objects on PCBs.
Component Arrangement Plan
Help users easily arrange components on PCB based on the placement
state.
Show routed nets in 3D structure and provide object searching.
Net Topology Viewer
Show net topologies of routed nets.
Net Analyzer
Attribute Finder
Analyze routed nets and report detailed net structure including routed
layers and lengths between pins, vias, and branching points.
Using component properties, help users find components and document them.
Real PCB Assembly Viewer
De-Cap Extractor
Find decoupling capacitors among capacitors on PCB and report them.
Using 3D package data, provide full 3D view of
PCB assembly.
PollEx CP (Cross Probe)
PollEx Logic
Comparing 3 Points and Revised Design Data
Viewing of Schematic Design Data
PollEx CP
PollEx Logic
Optimum solution for engineer without time loss
Simple easy reading of any schematic design format
PollEx CP compares physical, logic, and table-driven design data each
other. It can also check differences between two versions of physical
design, schematic design, and BOM.
PollEx CP uses data files of PollEx PCB, PollEx Logic, and PollEx BOM. Its
powerful features include easy-to-use, robust reporting, and graphical
display. Aditionally PollEx CP can be employed for checking and comparing attributes of design data from different vendors.
PollEx Logic is a schematic design viewer which reads in the design data
from various schematic design tools. It shows schematic objects, logic
symbols, net connections, and other related objects in individual design
sheets.
By combining objects users can easily identify the location in the sheet
and attributes of the objects. Users can also extract BOM files from the
schematic design data.
PollEx Logic is the basis of PollEx CP. With the use of PollEx CP users can
link and search all objects between physical design data and schematic
design sheets.
Features
Comparing 3 Points-PCB / Schematic / BOM
Detects a point of difference among PCB, Schematic and BOM in few
seconds.
Corrects problems caused by human errors before manufacturing stage.
Supported ECAD Formats
Vendor
[Revision Management / 3 Points Compare / Powerful Link & Search]
Application
EDA Format
PCAD - Schematic
OrCAD Capture
DxDesigner
PADS Logic
Comparing Revisions of Same Data Type - PCB to PCB, Schematic to Schematic
Detects a point of difference between PCB and PCB or Schematic and
Schematic.
Reduces time of engineers in finding a point of changed information
(Parts, Components and Nets).
EDIF
System Designer
Features
[PCB to PCB]
[Logic to Logic]
Imports multiple ECAD vendors formats.
Exports multiple vendors netlists.
Compact data saved in binary.
Encryption for binary save database.
Object Query/Search.
Object wired link and search.
Easy mark-up and save.
Symbol and net topology librarians.
Usage environment for setup and save.
Making a result as MS-Excel report.
Can get a report for each compared result.
[Export to MS-Excel report]
[Logic Data Extractor]
[Can paste to all Windows application]
PollEx BOM
PollEx CAM
Easy Matching of BOM Data of Any Format
Viewing Gerber Files of 274D & 274X Formats
PollEx BOM
PollEx CAM
Smart solution for making BOMs of any format
Verifying the manufacturing data in Gerber files.
After reading in physical design data PollEx BOM can generate ASCII BOM
files or table-driven MS-Excel format BOM files.
Wise Marker in PollEx BOM can easily import BOM data in ASCII unformatted BOM files.
PollEx BOM is linked to PollEx CP to allow users to compare the BOM
data with physical and schematic design data.
PollEx CAM is a viewer for 274D and 274X format Gerber files. Users can
automatically load an aperture file for 274D format Gerber files. Powerful
features of PollEx CAM include easy dragging and dropping for controlling
layer and checking difference between two different Gerber data.
Combined with PollEx PCB, users can compare physical designs with their
Gerber data.
Features
MS-Excel
PollEx BOM
Unformatted
ASCII BOM
PollEx PCB
Automatically detects format of 274D and 274X.
Automatically searches and reads aperture file for 274D.
Can import square hole data.
Capable of reading another Gerber data continuously after one Gerber
data.
Compares and marks up different shapes for two different layers.
Detects overlapped hole data for single layer and multiple layers.
Exports to 274X.
[To make BOM data and link with PollEx CP]
G-274X
Features
G-274D
Easily imports and handles unformatted BOM with Wise Marker feature.
Makes structure of MS-Excel data using Wise Marker for setting each
column.
Easily exports to a customized BOM format from PollEx PCB (pdbb file)
format.
Linked to PollEx Cross Probe for comparing 3 Points.
Aperture
HOLE
Drill
[Importing structure of PollEx CAM]
1
Usage of PollEx CAM
Compare two layers from different Gerber data.
Find overlapped objects in one or multiple layers.
2
3
Show Data Fill and Un-Fill modes.
1 Reading MS-Excel format BOM.
2 Reading from PollEx PCB file.
3 Reading unformatted ASCII BOM.
[User customized BOM format]
PollEx DFM
Detecting Manufacturing Defects in PCB Designs
PollEx DFM
Design for Manufacturing System
PollEx DFM is a rule-based PCB verification software for manufacturing engineers. Using PollEx PCB as its basis PollEx DFM supports PCB design data
in various ECAD formats. It allows users to detect design errors which result in costly manufacturing defects.
Reduces Time and Cost of Design to Manufacturing Process
Its features allow users to reduce expense and loss of time occurring in a mass production cycle. Numerous manufacturing defect items are checked
against the PCB design data, and any design errors are reported at the point of error so that they are easily identified and corrected. Consequently
employing PollEx DFM results in significant reduction of manufacturing defects.
Division 1
Corporate Manufacturing
Rule Management System
Division 2
Division 3
Classification for
each object
Common Rules
Re-use for next job
Generate reports in a DFM result file or MS-Excel file format.
Checking with
Standard Rule
Features
Overseas
Branch A
Overseas
Branch B
Overseas
Branch C
[Running structure of PollEx DFM]
User-optimized environment for setting multiple rules.
Uses entire intelligent ECAD design data available in PollEx PCB.
Verification of assembly and fabrication against conceptual and physical
designs.
Provides customized functions of reflecting requirements of field engineers.
Can manage checking history as report with screenshots of real error
points.
Efficient use of Running Core and Pre/Post Processors.
Major checking items
Over 147 Items
Component spacing optimization
Considering condition of Pin Pad
Component Spacing (basic), Component Spacing 2 (considering placed direction),
Reverse Placement Spacing, Clinch Spacing, Min Pad Spacing in Component
Hole Through Pad, Silk On Pad, Dummy Pad, Via Spacing, Teardrop, Via S/R Spacing,
SR Pad, Remove Copper, Thermal Pad, Copper Connected Pad, Minimum Via Land
Size, Via Over Stack, Multi-Pattern Connection, Metal Mask, PSR Covered Via
Presence of marks for manufacturing equipment
First Pin Mark, IC Visual Mark, Center Mark, Polarity Mark, Pin Count Mark, Fiducial Mark, PCB Mark, SMT Direction Mark, Wave Mark
Adequate condition for manufacturing environment
Prefix Check, Pair Component, Silk to Silk, Reference Name Silk, Reference Name
Ordering, Pin Arrangement, Silk Print Between Two Pins, Variant Pad Shape, Edge
Pin Size, OSP, Nearest Comp Silk, Specific Area, Pad Size by Pin Pitch, U Name
Overlap, U Name Angle, BGA, Pad Size
Annular ring optimization
Dip Annular Ring, Via Annular Ring
Placement optimization
Component Count, Component On Component, Component Placement, Prohibited Component, Placement At Reverse Side, Standard Component, Component
Placement Angle, Mark Placement, Placement Keep-out
Tooling
Screw, Pin Mark Match Check, Hole Mark Match Check, Pad Match Check, Board
Outline Match Check, Silk Match Check, Placement Mark
Drill condition
Drill Size of Hole, Drill Size of Pin, Drill Size of Via, Under Hole/Via, Hole Distance,
Gas Hole, Drill Scan, Similar Hole Size
Considering condition of PCB space
Board Spacing, PCB Outline Spacing, Guide Hole, Guide Line, Cutting Region, PCB
Outline Sharp Angle, Array Board Size Check, Label Box, Missing Hole, Min Silk
Width, Jig Hole, Routing Slit, SM Violate, Dummy PCB, Board Origin Offset, V-Cut,
Sub Board MisArrangement, Data Existence, Sub-Board Placement, PCB Outline
Width, Ground Wall
Net verification
Connected Pad, Lines Between Two Pins, Net to Net, Min Width, Pad to Net, 1Pin
Nets, Crack Pattern, Object to Object, Unrouted Net, Keep Out pattern, Intermediate Pattern, Void Coverage, Mechanical Short, Connected Pattern Direction,
Copper Boundary Width, Silver Paste TH PCB, Test Point
FPCB
Bending Area, Stiffener, Round Pattern, Bonding Pad, Silver Paste, Min Via Spacing,
Manufacturing Process, Coverlay, Bonding Area, Silk-covered Via, Coverlay Open
Via, Meshed Copper, Silk Keep-out Area
Miscellaneous for specific product
LED, Text Existence, Key Pad, Dome Sheet Guide Hole, TCP Bonding Mark, TCP
Dummy Pad, TCP Pad, TCP Align Hole, FPC Dummy Pad
Considering BGA component
Spacing from other object, Underfill
“PollEx DFM, easy-to-use suite of tools designed to help engineers and designers verify PCB designs
with design and manufacturing rules.”
PollEx DFA
Detecting Manufacturing/Assembly Defects in PCB Designs with 3D Package Data
PollEx DFA
Design for Assembly System
PollEx DFA is a rule-based PCB verification software for manufacturing engineers. It consists of Pre-Processor, Running Core, and Post-Processor. PreProcessor is used for setting input parameters. Users can define rules or classify and register groups or classes for components. Running Core checks
the rules against PCB design data. Finally Post-Processor is employed for reviewing the checked results.
Reduces Design Iterations Caused in Assembly Process
While footprint library is used for PCB designs, physical devices are used for real PCB assembly process. The differences between footprints and physical
packages result in various types of failures during assembly process. Using footprint data alone, the assembly defects cannot be fully detected as using
real 3D package pins and body data. With the use of real 3D package body and pin data, PollEx DFA checks various manufacturing issues including
soldering, design stability, assembly, and BGA bonding. Upon importing PCB designs in PollEx PCB, 3D package data can be easily loaded for individual
components by linking a 3D package library managed by UPMS (Unified Part Management System).
Features
Customized and optimized environmental settings for multiple rules.
Supported by all intelligent information from ECAD database using
PollEx PCB.
Supported by fully-integrated 3D package librarian, UPMS(Unified Part
Management System).
Provides customized functions, reflecting requirements of manufacturing engineers.
Can manage checking history as report with screenshots of real error
points.
Efficient use of Running Core and Pre/Post Processors.
Easy-to-use documentation.
Major checking items
Over 20 Items
Assembly
Soldering
Shield-CAN, Heat-Sink, Component Deflection, Component height Keep-out,
Alternative component
Shadow region check, Toe and heel check between footprint pad and package
pin, Solderability, Solder quantity calculation, S/M to component clearance
Stability
BGA
Radial-type component placement around Heat-Sink or High-voltage device
BGA under-fill region check
“PollEx DFA detects manufacturing/assembly defects in PCB designs with the use of 3D package
and pin shapes.”
PollEx DFE
Detecting Electrical Defects in PCB Designs
PollEx DFE
Design for Electrical Performance Checking System
PollEx DFE is a rule-based PCB verification software for electrical engineers. It consists of Pre-Processor, Running Core, and Post-Processor. Pre-Processor
is used for setting input parameters. Users can define rules and classify and register groups/classes for nets and components. Running Core checks
PCB designs with the pre-defined rules. Then Post-Processor is employed for reviewing the checked results.
Based on Accumulated Electrical Analysis Knowledge, Makes Rules and Verifies the Design
PollEx DFE allows users to spend less for performing difficult and time-consuming electrical analysis on PCB designs. Numerous electrical defect items
are checked in early design stage, and design errors are reported for easy identifications and corrections. Employing PollEx DFE significantly reduces
costly design iterations.
Result Viewer
- Synchronize result tab and display window.
- Export to MS-Excel or ASCII text.
- Generate documents and attached error images.
O S C ILLO S C O P E
Des ign file: CA B LE _HD-P V R_DQ S _03.TLN
B oardS im /LineS im , Hy perLy nx
Des igner: us er
4500. 0
Pr obe 1: U( A1) . DQ0
Pr obe 5: U( E 1)
Pr obe 1: U( A1) . DQ0
Pr obe 5: U( E 1)
4000. 0
3500. 0
3000. 0
2500. 0
V ol t ag e -mV -
2000. 0
1500. 0
1000. 0
Re-usable Rule
500. 0
0. 000
- 500. 0
0. 000
2. 000
4. 000
6. 000
8. 000
10. 000
T ime (ns)
12. 000
14. 000
16. 000
18. 000
20. 000
Date: Thurs day A ug. 19, 2004 Tim e: 10:17:20
S how Lates t W aveform = Y E S , S how P revious W aveform = Y E S
Co-relation
CAE (SI/PI)
Generalization
Physical Design +
Classification Info + ...
ECAD
Individual Knowledge
[Running structure of PollEx DFE]
Features
Optimizes environmental setting for multiple rules.
Uses entire intelligent ECAD design data available in PollEx PCB.
Detects electrical problems in PCB designs without employing analysis
tools.
Provides customized functions, reflecting requirements of field engineers.
Can manage checking history as report with real image screenshots.
Efficient usage of Running Core and Pre/Post Processors.
Major checking items
Over 61 Items
High Speed
Power
AGND/Power-Net Clearance, Approach GND VIA, Approach Prohibition VIA, Complete Shield, Copper Cross Over Detect, Routing Area Ratio, Return Path
Differential Pair Nets
Antenna Ground, Connected VIA, Decap, Decap2, Ground Coverage, Inductance,
Power-Net to Net, Parallel Jumper, Potential Difference, Power-Width, Stability
Copper, Supplementary Pattern, VIA Option
Diff-Complete Shield, Differential Pair Net, Differential Pair Net2, Length & Width
Filter
Net
Allowed Pattern Width, Antenna VIA, Bus, Bus2, Component to Net Clearance,
Confirm Net Group, Connected Comp, Connected Circuit, Copper Area Ratio,
DC Resistance, GND Isolation, Length, Limit Approach Net, Net Group Shield, Net
Isolation, Net to Net, Pattern Sharp Angle, Prohibit Connected Comp, Serpentine,
Star Connection, Stub, Test Point, VIA Quantity, Width
Bead
Component
Approach Pair Comp, Component Direction, Component Position, Component
Shield, Comp-Connected Circuit, Keep off Pair Comp, NC Pin, Pin Connected
Width, Polarity
Board
Board to Component Clearance, Board to Net Clearance, Groundwall of VIA
“PollEx DFE detects complex electrical defects in PCB designs.”
PollEx Logic DFE
Detecting Electrical Defects in Schematic Designs
PollEx Logic DFE
Design for Electrical Performance Checking System
PollEx Logic DFE is a rule-based schematic design verification software for electrical engineers. It consists of Pre-Processor, Running Core and PostProcessor. Pre-Processor is used for setting rule-parameters. Users can define rules and classify and register groups/classes for nets and components.
Running Core checks schematic designs with the pre-defined rules. Then using Post-Processor, users can easily review failed items.
Detects Design Errors and Guides Users for Better Net Naming at Logic Design Stage
A well arranged schematic design results in a good quality PCB layout. Correctly chosen net names make PCB designers easily route the board.
PollEx Logic DFE also allows users to set standard net naming convention.
Features
Optimized environments for setting multiple rules.
Provides customized functions of reflecting requirements of field engineers.
Can manage checking history as report with screenshots of real error
points.
Efficient usage of Running Core and Pre/Post Processors.
Makes standard net naming convention.
S-Return Path Viewer
Viewing of Signal Current Return Path
S-Retrun Path Viewer
Signal Current Return Path Viewer
PollEx PCB Signal Return Path Viewer finds current return paths of entire signal nets in PCB designs. Users can easily obtain analytical results and graphical display of dominant or major paths.
Finds Current Return Paths and Graphically Displays Them
As digital data rates in electronic systems continue to increase,
the demands on test professionals and on hardware escalate
over the full range of PCB mechanisms. And the importance
of getting current return path is increasing. Return current has
various paths depending on frequency. PollEx PCB Signal Return Path Viewer provides current return plot for user-selected
driver and receiver ports.
Manufacturing
Generating Manufacturing Data Files
Mount SIM
Metal Mask Manager
Using 3D Package and Layout Data, Generates MachineDependent Component Mounting Instruction
Checks Metal Mask Data of PCB Layout against Standard Metal Masks
Metal Mask
Gerber
Gerber to PCB
Block JIG Generator
Creates PCB Designs from Gerber or ODB++ Files
Extracts Block JIG Files from PCB Layout
Block JIG
Data
Mounter-Machine Data Export Router Machine JIG Generator
Extracts Machine-Dependent Mounter Input Files
Machine
Defendent
Part Data
Extracts Router JIG Files from PCB Layout
Router JIG
Data
Solder Quantity Calculator
Solder-Pallet Data Extractor
Calculates Solder Quantity from Solder Mask or Metal
Mask Data
Extracts Solder Pallet Files from PCB Layout
Soldering
Pallet Data
PollEx Design Closure
Closing PCB Designs with Integrated Design and Validation
PollEx Design Closure
Using Unified Part Data and Integrated Design and
Validation, Completes Design/Validation Process
PollEx Design Closure allows users to create or change PCB designs, perform various
analyses, and output the final design in Gerber and IPC2581 data files. By correcting
design errors found in PollEx DFM, DFE and DFA and instantly validating design changes
with embedded thermal, signal integrity and power integrity analyzers, PollEX Design
Closure can quickly close the design and validation process.
Logic Design
PCB Layout
PollEx
Design Closure
PollEx PCB
IPC-2581
Drastically Reduces Design Iterations with Common
Application Used by Multiple Engineering Disciplines
CAE
Verification
Design Correction
Verification
Validation
Prototype
Build
Frequently electrical, thermal and manufacturing engineers want to fix simple design
GERBER
problems by themselves. However, complexity of design tools and design flow prevents
them from making changes on the design.
PollEx Design Closure is designed to be commonly used by multiple engineering disciplines for detecting and correcting design
problems through real-time collaboration. The completed design can be output in Gerber files for manufacturing or in IPC2581
files for back-annotating to original ECAD system.
SMT
TEST
UPMS
Unified Part Management System
UPMS
Keeps Logic Symbol, Footprint, 3D Package, Mounting, and Electrical and Thermal Model Data
in Single Database
Unified part library data managed by UPMS are widely used in PollEx suite of tools. PollEx Design Closure uses UPMS parts for the PCB layout and
running thermal, signal integrity, and power integrity analyses. PollEx DFA and Real PCB Assembly Viewer use the 3D package data for checking design
errors and displaying PCB assembly in 3D, respectively. Analysis programs such as PollEx SI, PI and Thermal use the electrical and thermal models of the
UPMS parts, while the mount data is used for Mounter-Machine Data Export.
Ultimate EDA Part Data Management System
Different part data librarians are employed in design process, which disrupts design-to-manufacturing flow. Only different parts of manufacturer-specific
part data are managed by such part librarians. Typically corporate part libraries do not maintain data needed for electrical and thermal analyses. Using
a different library at each design process makes collaboration among multiple engineering disciplines more difficult. UPMS employs new method of
managing unified part library data which supports various design and analysis applications and can be commonly used by various engineering disciplines.
UP Viewer is used for reviewing unified part library data created by UPMS.
Conceptual Design
mechanical data
- STEP
- Wizard Created
Schematic Design
Layout Design
CAE (SI, PI, Thermal)
various schematic tools
- Cadence Concept
- Mentor LMS
- Zuken SD, LCDB
various PCB design tools
- Cadence Allegro DB
- Mentor LMS
- Zuken BD, CDB
different analysis format
- SPICE
- IBIS
- Linear
- Thermal models
PollEx Tool Set
UPMS
UP Viewer
PollEx SI
SI Explorer
Board Level Signal Integrity Analysis System
Pre-Design Signal Integrity Analysis System
PollEx SI / SI Explorer
Performs Comprehensive Time and Frequency Domain Signal Integrity Analysis
PollEx SI (Signal Integrity) is a fast, accurate, and easy-to-use signal integrity validation program for analyzing PCB designs. It allows users to detect
and correct signal integrity problems during design stage so that costly design iterations are eliminated or significantly reduced.
O S C ILLO S C O P E
Des ign file: CA B LE _HD-P V R_DQ S _03.TLN
B oardS im /LineS im , Hy perLy nx
Des igner: us er
4500. 0
Pr obe 1: U( A1) . DQ0
Pr obe 5: U( E 1)
Pr obe 1: U( A1) . DQ0
Pr obe 5: U( E 1)
4000. 0
3500. 0
3000. 0
2500. 0
V ol t ag e -mV -
2000. 0
1500. 0
1000. 0
500. 0
0. 000
- 500. 0
0. 000
2. 000
4. 000
6. 000
8. 000
10. 000
T ime (ns)
12. 000
14. 000
16. 000
18. 000
20. 000
Date: Thurs day A ug. 19, 2004 Tim e: 10:17:20
S how Lates t W aveform = Y E S , S how P revious W aveform = Y E S
PollEx PCB
Various Types of ECADs
ECAD Type A
Input Setup
Timing Analysis
- Delay
- Over / Under Shoot
- Reflection
- CrossTalk
ECAD Type B
ECAD Type C
ECAD Type ...
PollEx SI
PollEx SI Explorer
Features
[Running structure of PollEx SI]
Signal integrity validation capabilities are tightly integrated into PollEx PCB which is interfaced with various PCB design tools.
Complete signal integrity solutions are provided throughout the PCB design stages including the pre-design and post-layout stages.
Time-domain analysis capabilities include wave propagation delay, reflection, crosstalk, and eye diagram analyses.
Frequency-domain analysis capabilities include the calculation of scattering, admittance and impedance parameter matrices.
Fully automated built-in analysis features include layer stack-up optimization, net topology analysis and post-route signal integrity validation.
Both transistor level SPICE models and behavioral SPICE and IBIS models can be used for the driver / receiver / terminator device models.
Various IC package pin parasitic models such as lumped RLC, distributed RLC, SPICE netlist, and S-parameters can be used for the signal integrity
analysis.
Built-in Polliwog SPICE is employed for accurate simulation.
Built-in electromagnetic integral equation solver using method of moments calculates accurate frequency-dependent RLCG matrices for coupled
loss dispersive transmission lines and generates equivalent broad-band SPICE netlists using network synthesis methods.
Built-in 3-D electro-dynamic finite element solver extracts S-parameters of coupled vias and generates equivalent broad-band SPICE netlists using
network synthesis methods.
Built-in part and material editors allow user to easily generate I/O buffer models, package parasitic models, and material data and construct part
and material libraries for repetitive uses.
Composite nets are automatically identified, and the
Waveform
Parasitic Model
connecting passives can be modeled as RLC, SPICE netlist, and S-parameters for the composite net analysis.
Differential net pairs are automatically identified, and
analyses are performed for the differential pairs.
PollEx SI modules have been designed for common use
by multiple engineering disciplines so that design project
members can quickly validate the designs and design changes throughout the design process.
X-talk
Diff-Pair
Major Benefits
No need for interfaces or data transfer between the PCB design and signal integrity analysis tools.
No need for purchasing and maintaining expensive stand-alone signal integrity tools.
Signal integrity experts can oversee much more designs since most built-in signal integrity validation features can be effectively used by electrical
engineers, PCB designers, and manufacturing engineers.
Close collaboration among design project members allows better designs in reduced design time.
PollEx PI
Board Level Power Integrity Analysis System
PollEx PI
Performs Pre & Post Route Frequency and Time Domain Power Integrity Analysis
PollEx PI (Power Integrity) is a fast, accurate, and easy-to-use power integrity validation program for analyzing complex, multi-layer, multi-reference
power delivery networks (PDNs) in PCB designs. It allows users to detect and correct power integrity problems during design stage so that costly design
iterations are eliminated or significantly reduced.
Features
Power integrity validation capabilities are tightly integrated into PollEx PCB
which is interfaced with various PCB design tools.
Accurate full-wave electromagnetic analysis is performed on PDNs using powerful
frequency-domain finite element formulation together with method of moment.
Frequency-domain analysis capabilities include calculation of multi-port scattering,
admittance, and impedance parameter matrices of PDN structures and finding
resonance frequencies.
Time-domain analysis capabilities include simultaneous switching noise (SSN)
analysis on multiple signal nets.
Pre-design analysis allows users to optimize decoupling capacitor selections by
easily constructing multiple decap assignment cases.
Accurately analyzes coupling across power/ground planes and overlay dielectrics
above or below power/ground planes.
Accurately analyzes plane edge discontinuity, accounting for edge radiations, as well as split plane edge discontinuity.
Supports skin effect losses and dielectric losses.
Full-wave 3D finite element modeling of via discontinuities with edge effects included.
Built-in meshing engine allows automatic mesh generation for PDNs and passive components.
PollEx Thermal
Board Level Finite Element Thermal Analysis System
PollEx Thermal
Calculates Board Surface and Component Surface and Junction Temperatures
PollEx Thermal is a fast, accurate, and easy-to-use finite element thermal validation
program for analyzing PCB designs. It allows users to detect and correct thermal
problems during design stage so that costly design iterations are eliminated or
significantly reduced.
Features
PollEx PCB
Various Types of ECADs
ECAD Type A
ECAD Type B
ECAD Type C
ECAD Type ...
Tightly integrated into PollEx PCB which is interfaced with various PCB design
tools.
Performs accurate 3-D finite element steady-state thermal analysis.
Analyzes any shape or size of PCB.
Analyzes any type of PCB construction and material.
Manual input for all
Analyzes any type of cooling scheme.
thermal components.
Models convection, radiation, and conduction boundary conditions.
Get Thermal
component information.
Models any locally varying thermal boundary condition.
PollEx Thermal
Models any component package type.
Provides easy and convenient ways of thermal characterization of components.
Input thermal
Uses component and material libraries for repetitive uses.
UPMS Part Librarian
analysis constraints.
Analyzes any type of component heat sink.
Automatically generates a large scale finite element model including the PCB, components, and the interface between the components and PCB.
Outputs temperatures at the junction and surfaces of components as well as the surfaces and mid-plane of PCB.
PCAD is a trademark of Altium Limited.
Protel is a trademark of Altium Limited.
Allegro is a trademark of Cadence Design Systems, Inc.
OrCAD is a trademark of Cadence Design Systems, Inc.
OrCAD Capture is a trademark of Cadence Design Systems, Inc.
Spectra is a trademark of Cadence Design Systems, Inc.
Board Station is a trademark of Mentor Graphics Corporation.
DxDesigner is a trademark of Mentor Graphics Corporation.
Expedition is a trademark of Mentor Graphics Corporation.
PADS Layout is a trademark of Mentor Graphics Corporation.
PADS Logic is a trademark of Mentor Graphics Corporation.
PowerPCB is a trademark of Mentor Graphics Corporation.
Genesis is a trademark of Mentor Graphics Corporation.
CADSTAR is a trademark of ZUKEN Inc.
CR5000 BoardDesigner is a trademark of ZUKEN Inc.
CR5000 PWS is a trademark of ZUKEN Inc.
CR8000 Design Force is a trademark of ZUKEN Inc.
PostScript is a trademark of Adobe Systems Incorporated.
Excel is a trademark of Microsoft Corporation.
PollEx PCB is a trademark of Polliwog Corporation.
http://www.polliwogeda.com
Copyright POLLIWOG Corporation. All rights reserved.
POLLIWOG, the POLLIWOG logo and PollExTM are either registered trademarks
or trademarks of POLLIWOG Corporation in the Republic of Korea.