Design a Forward
CONVERTER
Gorge Hsieh
Technical Marketing
George_hsieh@techmosa.com.tw
Tel :02-8226-7698 ext.3001
Cellular phone : 0935041907
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AGENDA
•Forward converter v.s Buck converter vs. Flyback converter
•Features of Forward converter
•Operation of Forward Coverter
Operation
Current waveforms
Magnetics of forward converter
Reset schemes
Synchronous forward converter
•Design Procedures
Design a transformer
Measure the magnetic inductance & leakage inductance of transformer
Mosfet
Secondary rectifier
Output inductor
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AGENDA --- cont.
•Design Procedures --- cont.
Output Capacitor
Loop compensation
Active Clamp Forward converter --- LM5025
ZVS --- zero voltage switching
Operation
Decide the Cr
•Other Topologies
Double end Forward
Half bridge
Full bridge
Phase-shift Full bridge
Current double forward
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Buck vs. Forward vs. Flyback
Buck
Converter
n=
Np
Ns
12VinÆ3.3V, duty=27.5%
Forward
Converter
Vo
Vin
Flyback
Converter
Vo
=D
Vin
48VinÆ3.3V, duty=6.87%
Vo D
=
Vin n
Vo
D
=
Vin N(1 − D)
Q
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The features of Forward Converter
A. For larger Vin to Vo step ex. Vin=48, Vo=3.3V
B. Isolation
C. Lower ripple & noise --- compare to Flyback converter
D. Smaller transformer --- compare to Flyback converter
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Operation
Mode 1: Q 1 on , D1(Forward diode) on, D2(free wheel diode) off
T1
D1
L
D2
Q1
Mode 2: Q 1 off , D1 off, D2 on --- Free wheel
T1
D1
Note : Work like buck
converter, L maintain
the output current
continuous. T1,
transformer, step down
the input voltage by
Np/Ns turn ratio.
L
D2
Q1
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Operation of Forward converter
(1)
IL
I D1
Vin
Vs
Q1
Vg
D1
D2
I D2
Vg
Vs
I D1
I D2
IL
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Operation of Forward converter
(2)
IL
I D1
Vg
Vin •
Vin
Vs
Q1
Vg
D1
D2
Vs
Ns
Np
I D1
I D2
IL
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Operation of Forward converter
(3)
IL
I D1
Vg
Vin •
Vin
Vs
Q1
Vg
D1
D2
I D2
Vs
Ns
Np
I D1
I D2
IL
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Operation of Forward converter
(4)
IL
I D1
Vg
Vin •
Vs
Q1
Vg
D1
D2
Vs
Ns
Np
I D1
I D2
IL
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Operation of Forward converter
(5)
IL
I D1
Vg
Vin •
Vs
Q1
Vg
D1
D2
I D2
Vs
Ns
Np
I D1
I D2
Io
IL
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Model of Forward Transformer
Np : Ns
Lm
D2
Im
Overhead of forward transformer
Q1
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Current waveforms
Magnetizing current
: ripple current
ΔI
Lm
Im
Io
D2
Q1
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ΔI
Magnetics of Forward converter
Np : Ns
+
Lm
Im
D2
V1
-
T
Overhead of forward transformer
Flux Density B = ∫0
(Gauss)
V
dt
N • Ae
V1
t1
Q1
dΦ
=V
dt
dB • Ae
N
=V
dt
N
B=∫
V
dt
N • Ae
N • Im
H=
l
Magnetic Force
(A/m)
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Magnetics of Forward converter
Flux need be reset in every cycle
Np : Ns
+
Lm
D2
Im V1
-
T
Overhead of forward transformer
Flux Density B = ∫0
(Gauss)
V
dt
N • Ae
V1
t2
0
t1
Q1
dΦ
=V
dt
dB • Ae
N
=V
dt
N
B=∫
V
dt
N • Ae
N • Im
H=
l
Saturated
Magnetic Force
(A/m)
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Magnetics of Forward converter
Need a nagative voltage in the rest of time to reset the flux
Np : Ns
Lm
-
D2
Im V2
+
T
T
Overhead of forward transformer
Flux Density B = ∫0
(Gauss)
V
dt
N • Ae
V1
t2
0
t1
V2
V1*t1=V2*t2
VT balance
Q1
dΦ
=V
dt
dB • Ae
N
=V
dt
N
V
B=∫
dt
N • Ae
H=
N • Im
l
Magnetic Force
(A/m)
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Magnetics of Forward converter
Then the transformer can work again
Np : Ns
Lm
+
D2
ImV
T
T
Overhead of forward transformer
Flux Density B = ∫0
(Gauss)
V
dt
N • Ae
V1
t2
0
t1
V2
V1*t1=V2*t2
VT balance
Q1
dΦ
=V
dt
dB • Ae
N
=V
dt
N
B=∫
V
dt
N • Ae
N • Im
H=
l
Magnetic Force
(A/m)
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Unfortunately, Forward converter inherent no rest path
Mode 1: Q 1 on , D1(Forward diode) on, D2(free wheel diode) off
D1
T1
+
-
+
-
L
D2
Q1
Mode 2: Q 1 off , D1 off, D2 on --- Free wheel
T1
D1
L
D2
+ +
- -
In this case, there is no negative current path
Q1
In order to make the magnetic current continuous,
transformer will induce a very high voltage thus destroy
the Mosfet, Q1
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Flyback has inherent rest path
D
-
+
RL
-
+
T
Q
-
+
-
+
RL
T
Q
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Reset schemes
Reset winding
+
-
-
-
+
+
RCD clamp
Active Clamp
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Cost effective solution for magnetic reset
Disadvantage --- higher Vds, but may be lower switching
loss while Mosfet turned on
f =
1
2π Lm • Cs
Larger Cs
smaller Cs
higher switching loss
Vin
Lower switching loss
Vds
Vg
Cs
Vin
Vds
Vg
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Synchronous Forward Converter
+-
+-
Q3
+-
+Q2
Q1
Q1 on, Q2, On, Q3 off
Q1 off, Q2, Off, Q3 on
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DESIGN Procedure
Vi: Input voltage
Ii : Input current
Vo : output voltage
Ro : Output load resistance
Vr : Output voltage ripple
D : duty cycle
Fs : Switching frequency
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A.
Design a transformer
a. Select a magnetic core
100W
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b. Pick Ae --- effective core area & Al
Al : induc tan ce
per turns 2 nH / T
+ / − 25%
L = N 2 • Al
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c. Calculate Np --- Primary tunns
Np =
Vi • Dmax
• 1010
ΔB • Ae • Fs
Vi : volt
B : gauss
Ae : mm 2
Fs : Hz
Vi : Maximum input volatge
Dmax : Maximum duty cycle
Ae : effect core area
ΔB: delta
flux density
Fs : Switching
Frequency
Lm = N p • AL
2
Note : ≈ 2000 gauss
Lm : the larger is the better
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d. Calculate Turn ratio:
n=
Np
Ns
≤
Vi (min) • Dmax
Vo + Vd
You must decide maximum duty
cycle(<50%)
e. Calculate wire diameter:
Criterion : cross area/current
I = 4 D 2 ⇒ φ = 0.5 0mm
for 1A
⇒ ≈ 400 circul mil / A
I = 6 D 2 ⇒ φ = 0.41 mm
for 1A
⇒ ≈ 256 circul mil / A
I = 8 D 2 ⇒ φ = 0.35 mm
for 1A
⇒ ≈ 190 circul mil / A
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Create a specification for the transformer
Schematic
1
ψ=2* 0.6mm, 12Ts
Np
2
4
ψ= 0.16mm, 8Ts
9,10
Pin 9~6 / ψ= 0.6mm x 4, 2Ts
Ns Pin 10~7 / ψ= 0.6mm x 4, 2Ts
Nb
5
6,7
Electrical Specification
Converter Type : Forward
Vin,min : 32V,
Vin,max : 60V
Duty,max : 0.45
Frequency : 250KHz
Vo : 3.3V
Io : 10A
.
.
1. Magnetic Core:
EFD30
3. Wire diameter
2.Np:
Leakage
Pin 1-2
+/-x210%
Pin1~2 Inductance:
/
ψ=0.5uH
0.6mm
Ns: Pin9,10~6,7 /
ψ= 0.6mm x 8
Nb: Pin4~5 /
ψ= 0.16mm
Np2
Ns
Np1
Insulate tape
4. Winding sequence
I.
Np 6 Turns, 加TAPE
II.
Ns 2 Turns, 加TAPE
III.
Nb 8 Turns, 加TAPE
IV.
Np 6 Turns, 加TAPE
5. High pot
1500V
1,4
6,7
1500V
1,4,6,7
CORE
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Planar transformer
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Core Losses
Core loss = hssteresis loss+eddy current loss
= K (ΔB ) m f n
m = 2-2.5
n = 1.1-1.5
Ferrite : <2MHz
Powder core : <1MHz
Alloy : <200KHz
Amorphous : <300KHz
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How to measure Lm & leakage inductance?
a. Measure Lm
LCR meter
Ll
Secondary
open
Lm
b. Measure Leakage inductance Ll
LCR meter
Ll
Lm
Secondary
short
Lm >> Ll
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Power Stage
1.
Components
A.
Power Mosfet
Vds : >2*Vin, max, it is dependent on the reset capacitor Cs (refer to page
Ids :
Rds(on)
Ciss
Coss
Tfall (fall time)
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)
B. Output Diode
Vr : reverse voltage
If(average) : Forward current
If(peak) : Io +
Vd :
Vr > [Vinmax •
N ⎤
NS
, Vo + Vreset • S ⎥
Np
N p ⎥⎦
1
ΔI
2
Cj :
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Output inductor
L
di
=V
dt
L=
dt = (1 − Dvin @ max ) • Ts
dt
(Vo + Vd )
di
Dvin @ max = n *
Ts =
di=0.2*Io,max(A)
VD + Vo
Vin ,max
n=
Np
Ns
1
Fs
VL
Vs
Vd
+
Q1
+
Δ I L @ Q1off
Vo
-
Maximum ripple happen when Vin@max
Vs
Vg
ΔI L
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Output capacitance
1. Consider transient response
1
1
(ΔI ) 2 L = (ΔV ) 2 C
2
2
ΔI : transient load
ΔV : accepted
overshoot
2. Consider ripple voltage
ESR ≤
Vr
ΔI L
ΔI L : inductor ripple current
Vr : Ripple voltage
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Comparison with high value capacitors
– variety of capacitors
Multilayer ceramic capacitor
Ni based electrodes
(TAIYO)
OS-CON (SANYO)
Al electrolytic capacitor
Ta electrolytic capacitor
SP Cap (Panasonic)
POS CAP (SANYO)
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Polarity
Derating
Ripple Current
Limit
Solder Heat
Resistance
Anti
-solvent
Loading
Test
MLCC
No
◎
◎
◎
◎
◎
Ta cap
Yes
×
△
×
△
×
AE cap
Yes
×
×
△
×
△
* Layout
* Require * Must consider
issue
70 to 50% allowable ripple
* Mounting of rated
current when
issue
Voltage.
determine cap
* Reverse
value.
Problem
* Heat generation
voltage
will lower the
reliability.
◎ is Excellent
△ is Limited
* Limited
condition
when
reflow is
used.
*Solvent
penetration
into
capacitor
body.
× is Bad
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Comparison of Capacitor’s Self Heat Generation
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Impedance vs. Frequency
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MLCC vs. OS-CON
Impedance and ESR versus
Frequency characteristics
100
Impedance, ESR (ohms)
10
R
22uF OS-CON
Z
R
22uF MLCC
Z
1
22uF OS-CON
0.1
0.01
22uF MLCC
0.001
1K
10K
100K
1M
10M
Frequency (Hz)
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The ripple current of 47uF MLCC is about 2.5A
Temperature Rise Versus Ripple Current
Temperature Rise (°C)
100
10
1
47uF MLCC
47uF Ta Cap
100uF POSCAP
0.1
0
0.5
1
1.5
2
2.5
3
3.5
4
Ripple Current (A rms)
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DC Bias Characteristic
DC Bias characteristic
10
0
-20
DC/C [%]
ΔC/C [%]
0
-40
-60
-80
-100
0
2
4
6
8
-30
-50
10
0
NPO vs. X7R vs. Y5V
Temperature Characteristic
20
-55~125
-55~125
10~85
+/-30 ppm
+/- 15%
+22%~-56%
2
1
3
4
5
6
7
125
150
DC Bias voltage [V]
Temperature Characteristic
20
10
DC/C [%]
0
ΔC/C [%]
-20
-40
DC Bias Voltage [V]
-20
-40
-60
0
-10
-20
-30
-80
-100
-10
-40
-50
-25
0
25
50
75
Temperature [degrees C]
100
-50
-75
-50
-25
0 25
50
75
Temperature [degree C]
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100
Sense resistor
1
I O + ΔI L
2
Io
0
I D1
I D1
IL
Np:Ns
Q1
Vg
1
I O + ΔI L
2
n
CS
680pF
IP
n=Np/Ns
2K +
VCS
-
Rs
Rs =
VCS
1
I o + ΔI L
2
n
V
Loss = CS
Rs
2
VCS = 0.5 ~ 0.8V
0.82
6.4W =
0.1Ω
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Loss = I 2 • DCR
Current transformer
0.1A
+
+
10A
1V 10Ω
1V
0.1Ω
10A
-
1V 2
loss =
= 0.1W
10Ω
loss =
1V 2
= 10W
0.1Ω
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Reset capacitor --- Cs
Vin
Lm
1 1
•
2 f
Vin
Vds
Vg
Cs
Vg
f =
1
2π Lm • Cs
Fs
1
≥
2π Lm • Cs 2 • (1 − Dmax )
1 1 1 − Dmax
• ≤
Fs
2 f
1 − Dmax 2
(
)
π • FS
CS ≤
Lm
f ≥
Fs
2 • (1 − Dmax )
,for reference
Cs ≈ 100 pF ~ 1000 pF
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Output diode snubber
R
C
Ll
fr
Vin
Vg
Cs
1
fr =
2π Ll • C j
R=
C≅
Ll : leakage induc tan ce
C j : diode
junction capaci tan ce
Ll
1
=
C j 2π • f r • C j
2~5 times of Cj
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Control Loop
Open loop
L
Vin
Vo
C
Resr
RL
Ip
Current Mode Controller
Vg
Cs
ns
Rs
S
Q
5V
+
_ Ve
R
Id
Vo
cathode
+
Comparator
R5
R4
_
COMP
FB
_
Vref
Ic
+
TL431
Vref
FB
Anode
OP AMP
Vo ↑ FB ↑ Id ↑ Ic ↑ Ve(comp) ↓ Ip ↓ Vo ↓
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Photo Coupler --- For isolation
Photo Coupler provide signal transfer, the Idea is a DC gain
Vcomp = Vcc − R5 * Ic = Vcc − R5 * (
ΔVcomp = ΔVe *
1.
Vo − Ve
Ic
* CTR ( ))
R4
Id
R5
* CTR
R4
CTR : Current Transfer Ratio
80%-----150%
2.
Bandwidth --- must > cross over frequency
of flyback converter (1/10 of switching
frequency)
3.
Popular solution: PC817 --- Sharp
TLP521 --- Toshiba
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With Photo Coupler
Vcc
Gain
R5
Vo
1nF
R4
10K
47nF
_
0db
0.91K
Ic
9.9Hz
142Hz
+
f
33KHz
s
Vo R1
wz
=
*
Ve R 2 1 + s
wp
1+
10K
= 10.9
0.91K
0db
Close over frequency
Close loop Gain(
+
)
w Z ≅ 338Hz
w P ≅ 79KHz
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With Photo Coupler
Vcc
Gain
Vo
R2
0db
Ic
9.9Hz
142Hz
f
33KHz
cathode
ref
+
_
Vref
Anode
0db
TL431
Close over frequency
Close loop Gain(
+
)
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TL431--- Shunt regulator
Vin
IKA =
RL
Vin − Vo
RL
Io,max = IKA
Vo
cathode
ref
+
_
Shunt Current
Vref
Anode
TL431
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Band gap reference of 431
Vin
I1 = 10I2
R
VBE( Q1) ≠ VBE( Q 2 ) Q I1 = 10I2
R1
I1
R2
Ref
I2
I2 =
VBE( Q1) − VBE( Q 2 )
R3
VREF = VBE( Q 3 ) + ( VBE( Q1) − VBE( Q 2 ) )
Q1
Q2
Q3
R3
KT I1
ln
q I2
T
T
= Vgo (1 −
) + VBEO ( )
To
To
R2
R3
VBE( Q1) − VBE( Q 2 ) =
VBE( Q 3 )
Vgo = band − gap
Vgo
V
dVREF
R 2 K I1
VBEO + BEO +
=−
ln
dt
To
To R 3 q 12
R 2 I1
q
If,
ln = ( Vgo − VBEO( Q 3 ) )
R 3 12
KTo
dVREF
= 0 Vgo = 1.22V
dt
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Control Loop
a. Open loop --- Similar to current mode Buck converter
A. DC gain :
B. Low frequency Pole :
C. ESR zero :
D. Double Pole :
n•
Ro
Note
Rs
Ro: load resistance
n : main transformer turn ratio, Ns/Np
1
2π • C • RL
1
2π • C • Resr
Fs
2
Gain
Note:
DCgain =
0db
I o • Ro I o • Ro N p • Ro
=
=
R
N S • Fi
Ve
I in • s
ns
Fp
Fz
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Fs
2
f
Loop Compensation
5V Vo
1. Lower fz more phase margin, stable but slow response
2. Lower fp less phase margin, but noise immunity
3. DC gain & crossover frequency is limited by 431 &
photo couple
Vo
SR3C1 + 1
SR1 R2C1 ( SR3C2 + 1)
R5
4.R 4 =
R4
comp
Vo − Vd − VK
IK
fz =
R1
C2
I K ≅ 3 − 6mA VK ≅ 1.24V
1
1
fp =
2πR3C1
2πR3C 2
R3
R1 R 2
C1
R3
Gain
cathode
0db
FB
+
_
Vref
431
R2
Anode
Fp
Fz
Crossover frequency
Fs
2
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f
Vcc Bias
Vin
R,large
High power dissipation
Nb
Vcc
Vin
R l arg e
Long start up time
Vin
Np
Simple
Ns
Vin
R,small
R,large
High power dissipation
Nb
zener
Vcc
short start up time
Vin
Ns
Complex
Np
Vin
Vin
R l arg e
Lower power dissipation
Vcc
Nb
short start up time
LDO
Vin
Internal Vcc
Ns
Simple
Np
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Design Example
Vin,min
Vin,max
Duty, max
Vo
Vs
Io
eff
In
Fs
Vbias
n(Np/Ns)
Trnsformer section
Magnetic Core
Delta B
Ae
Al
Np
Lm
Ns
Nb
Winding
Skin depth(mm)
Maximum Diameter of wire
Dim, pri,total
wire # (primary)
Dim,pri, per wire
Dim, sec
wire # (secondary)
Dim,sec, per wire
=Vo+Vd
Vo*Io/Vin*eff
n=
Vin, min × Dmax
36
78
0.55
3.3
3.4
30
0.85
3.33
240000
12
5.824
Vo + V D
EFD 30
(mm^2)
nH
Np =
Vin × Dmax
×1010
ΔB × Ae × FS
3.61E-04
2.2
7.9
Np/n
NS ×
Vbias
Vo + V D
s=
72
Fs
(mm)
2*s
sqrt(Iin/8), unit: mm
sqrt(Io/8), unit: mm
unit: mm
2000
69
2150
13.0
0.15
0.29
0.65
4
0.32
1.94
8
0.68
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Secondary section
Output Inductor
DeltaIL
D@vin,max
L
IL
Output capacitor
Vripple
I,transient
V,overshot
C
ESR
0.2* Io, max
(Vo+Vd)*n/Vin,max
L=
Io +
(Vo + VD ) * (1 − D@ vin, max )
6.0
0.3
1.8E-06
FS * ΔI
1
ΔI L
2
accepted ripple voltage
transinet current
accepted overshoot in transinet response
I2
C=L 2
V
33
0.05
10
0.1
1.8E-02
0.0083
Vripple
ΔI L
Sense resistor
Vs,max
Rs
Reset capacitor
Lm
Cs
Maximum current sensing voltage
VCS
Rs =
1
I o + ΔI L
2
n
1 − Dmax 2
)
π • FS
CS ≤
Lm
(
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0.6
0.106
0.00036
9.9E-10
Loop compensation
RL
C
ESR
DC gain
Vo/Io
Ro
Rs
N •
Cross over frequency
First pole
1
2π • C • RL
1
ESR zero
2π • C • Resr
open loopGain at cross over DC gain - loss
R3/R*
R*
R3
1
C1
C1 =
C2
C
2
2π R 3 f Z
1
=
2π R 3 f P
0.11
0.0009
0.0040 17mOHM for 47uF ceramic
31
10000
1675
46075
16
0.16
2000
319
2.98E-07
1.08E-08
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Schematic
3
C1
L147uH
1
C2
D1
R1
1
T1
2
C12
2.2uF
2.2uF
6
6
MMBTA42
Q1
2
E
B
D3
12V
2
1
1
C13
1uF
2
0.1uF
1
2
C14
Q3
5
RT/CT
COMP Output
D4
K
2
1K
1N4148
A
T2
6
6
R8
8.2
3
R9
R10
1K
7
AZ3843
0
4
1
PGND I Sense
R12
1
4
CT
2
1
C15
2.2nF
Q4
1
IRF640
1
C19
470pF
2
R14
6.34K
C20
R15
330OHM
330nF
C21
10nF
U2
TLP521
2
2
680pF
10
1
3
C18
1
R13
1
2
1
4
2
0.1uF
3
C16
2
C
2
C17
2.2uF
MMBT2907
1
VFB
8
3
E
2
1
VREF
8
10K
Vc
2
2
2
B
R5
1K
U1
7
1
1
R6
1K
R7
U3
AZ432
R16
3.09K
C22
3300pF
A Reliable business Partner
68uF
68uF
C6
330uF
+
68uF
+
C8
C11
2.2uF
R2
470
C7
C10
10
11
T12
C3
1nF
C 2
2
2.2uF
10
11
12
C5
1
C9
32CTQ030
1
4
1
1
1
1
R3
10
VCC3V3
D2
330uF
1
4
L35.6uH
L2
2uF 10A
3
2
VCC
1
9
8
7
9
8
7
Vin = 48V
470
1nF
C4
3
2
3
R4
68K
2
BAV70
2
1uF
Thanks
Gorge Hsieh
Technical Marketing
George_hsieh@techmosa.com.tw
Tel :02-8226-7698 ext.3001
Cellular phone : 0935041907
A Reliable business Partner