™
TECHNOLOGY ORGANIZATION, INC.
Bulletin No. 8310PD9601
March 1997
Raleigh, NC, USA
ASIC2B Data Sheet
CONTENTS
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
ASIC2B FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
APPLICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
USER WARNING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Important User Warning Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SYSTEM OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Sync and Clock Loss Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Input Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Input Signal Selection and Data Echo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Output Control and Debouncing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Bus Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Reset Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Mode/Sync Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Input and Output Shift Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Multiplex Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
EEPROM and Programming Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Vcc (Power) and Vss (Common) – Pins 2 and 16 . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Clock – Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Data In – Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Data Driver – Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Inputs A and B – Pins 5 and 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Outputs A, B, and C – Pins 13, 14, and 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Cosc – Pin 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Vdd (+9 V Reference) – Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Mode/Sync – Pin 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Shift Clock In and Out – Pins 9 and 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Multiplex Clock – Pin 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
ELECTRICAL SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Vcc (Power Input Voltage) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Vdd (Regulated Output Voltage Reference) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Clock and Data In Inputs (Bus Interface Signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Data Driver Output (Bus Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Inputs A and B (External Input Signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Vin Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Outputs A, B, and C (External Output Signals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Mode/Sync, Multiplex Clock, Shift Clock In, Shift Clock Out (Logic Outputs) . . . . . . .24
Sync Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Clock Loss Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Cosc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
EEPROM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Program Mode Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
SIGNAL TIMING DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
1
ASIC2B Data Sheet
Contents
2
Bulletin No. 8310PD9601
March 1997
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
INTRODUCTION
ASIC2B Data Sheet
Introduction
The SERIPLEX ASIC2B (Catalog No. SPX SP2562B) is an application-specific IC which
provides a simple, small, and inexpensive means to implement communication among
control devices through the SERIPLEX control bus. The ASIC2B completely
implements SERIPLEX protocol in hardware, so that control device designers do not
need any knowledge of the protocol.
The ASIC2B supports transmission of up to two discrete input signals to the control
bus, and two discrete output signals from the control bus. The ASIC2B provides a third
discrete output signal, which may be programmed as any of eight logical combinations
of the two bus output signals. These signals are physically transmitted to and from the
control device circuitry through individual logic-level pins.
Designers of simple discrete devices such as photo sensors, limit switches, and valves
can use the ASIC2B to obtain SERIPLEX connectivity with a minimum of circuitry,
printed wiring board space, design time, and expense. The ASIC may also be used to
exchange analog signals and other multi-bit values through the SERIPLEX bus through
the use of simple peripheral circuitry. No microprocessor, firmware, or complex logic
devices are needed in order to use the ASIC within discrete or analog control devices.
The control bus is a component-level network which provides a simple, inexpensive,
fast, and deterministic means of exchanging data among control devices. These devices
include sensors such as photo switches, proximity sensors, and push buttons; actuators
such as valves and contactors; and controllers such as programmable logic controllers
(PLCs) and personal computers. All control devices are networked together by a single
4-conductor cable, saving the considerable installation cost of traditional hard-wired
control and I/O systems.
SERIPLEX control bus technology is “open” and available to any control vendor. For
information about the control bus, as well as guidelines and suggestions for the
application of the ASIC2B, contact:
SERIPLEX Technology Organization
PO Box 27446
Raleigh, NC 27611
1-800-SPLX-INC
ASIC2B FEATURES
•
Complete SERIPLEX protocol implementation for discrete input and output devices
•
Exchanges signals between external circuitry and SERIPLEX bus
— Two external inputs transmitted to bus
— Two bus outputs transmitted to external outputs
— Third external output is a programmable logical combination of the two bus
output signals
•
All configuration data is stored in on-board non-volatile EEPROM (Electronically
Erasable Programmable Read-Only Memory) memory
— Signal addresses, mode, logic functions, digital debounce length, data echo
— No requirement for external DIP switches, thumbwheels, or other circuitry
— Configured by standard SERIPLEX Set-up Tool (available from Square D Co.)
•
16-pin narrow SOIC package is small and inexpensive
•
Built-in Bus Fault Detection
•
Selectable digital debouncing for output signals
•
Selectable Data Echo feature confirms correct receipt of output data to host controller
•
Polarity selection for all external input and output signals
•
CMOS technology for low power consumption & wide operating voltage range
•
Built-in voltage regulator for internal signal stability; reference available for
external use
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
3
ASIC2B Data Sheet
Applications
APPLICATIONS
Bulletin No. 8310PD9601
March 1997
•
Shift Clock outputs simplify external circuitry required to exchange multi-bit
values with SERIPLEX bus
•
Selectable 5 or 9 V input signal logic thresholds
•
Multiplex Address Clock output simplifies external circuitry required to decode
SERIPLEX bus multiplex channel address
•
Mode/Sync output signal indicates both selected bus operating mode (master/
slave or peer-to-peer) and detection of bus Sync pulse
The SERIPLEX control bus generally performs the same purpose as ordinary discrete
I/O wiring, and is suitable for use in a wide variety of control applications, in many
different markets and industries. Some popular applications are:
•
Industrial control and automation—discrete, batch, and continuous process
•
Material handling
•
Building control and automation
•
Data Acquisition
•
Monitoring/alarm systems
•
Lighting control
In turn, the SERIPLEX ASIC2B may be embedded in a wide variety of control and
monitoring devices, such as:
•
Discrete sensors:
— Proximity switches
— Photo detectors
— Limit switches
— Push buttons and selector switches
— Pressure switches
•
Discrete actuators
— Valves
— Relays and contactors
— Lamps
•
Analog sensors
— Temperature sensors
— Flow meters
— Level indicators
— Resolvers and encoders
•
Analog actuators and control devices
— Motor drives
— Proportional valves
— Circuit breakers
•
Monitoring and indicating devices
— Panel meters
— Operator-interface terminals
•
Multi-point input and output devices
— General-purpose I/O blocks or multiplexers
— Sensor concentrators or manifolds
— Pushbutton panels
Because it does not supply the SERIPLEX bus Clock signal, the ASIC2B is generally not
used for controllers such as computer or PLC interfaces. However, it can be embedded
into simple control devices which both read and write control data, such as data-entry
terminals, if the bus Clock signal is provided by another source such as a Clock module.
4
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
ASIC2B Data Sheet
User Warning Information
The SERIPLEX control bus was designed to provide users of devices implementing the
SERIPLEX technology with deterministic, real-time control systems providing
significant installed cost savings. The use of the SERIPLEX ASIC requires appropriate
electronic circuitry to adapt the ASIC to the manufacturer’s devices.
USER WARNING
INFORMATION
To make proper use of the SERIPLEX control bus, application designers and installers
must understand the operation, capabilities, and limitations of the SERIPLEX bus and
of the devices which connect to it. SERIPLEX bus device manufacturers and vendors
must provide their users with sufficient information so that they can design their
applications to work as intended and in compliance with all applicable laws,
performance, and safety requirements, regulations, codes, and standards. In addition
to product specifications, dimensions, and methods of use and installation, this
information must include all appropriate warning or caution messages, including the
information listed below.
Important User Warning
Information
It is possible that corrupted information in the control system described in this
document can report an incorrect input or incorrectly operate an output. If used where
personnel and/or equipment hazards exist appropriate interlocking must be
employed. Those responsible for the application, implementation, and use have the
responsibility to see that the necessary design considerations have been incorporated
into each application to ensure complete adherence to applicable laws, performance
and safety requirements, regulations, codes, and standards. This system offers
significant advantages in communication throughput, I/O number and distance.
Proper application will result in a reliable, high performance control system.
! WARNING
HAZARD OF UNEXPECTED OUTPUT ACTUATION
When used where personnel and/or equipment hazards exist hard-wired safety
interlocks must be employed.
Failure to observe this instruction can result in death or serious injury.
PIN ASSIGNMENT
Pin No.
1
16 Vcc
Vdd 1
Vss 2
SP256-2B
15 OA
Symbol
Type
Name
Vdd
Output
9 V Reference
2
Vss
Power
Common (0 V)
3
DI
Input
SERIPLEX Bus Data Input
4
B_CK
Input
SERIPLEX Bus Clock Signal
5
IA
Input
Input A
DI 3
14 OB
B_CK 4
13 OC
6
IB
Input
Input B
12 Cosc
7
D_Drv
Output
SERIPLEX Bus Data Output Drive Control
11 Mux_C
8
M/S
Output
Mode/Sync
10 S_C_I
9
S_C_O
Output
Shift Clock Out
IA 5
IB 6
D_Drv 7
M/S 8
9
S_C_O
Figure 1: Pin Assignment
10
S_C_I
Output
Shift Clock In
11
Mux_C
Output
Multiplex Clock
12
Cosc
Input
Oscillator Control
13
OC
Output
Output C
14
OB
Output
Output B
15
OA
Output
Output A
16
Vcc
Power
Power (+12/24 VDC)
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
5
ASIC2B Data Sheet
System Overview
SYSTEM OVERVIEW
Bulletin No. 8310PD9601
March 1997
The control bus is a commponent-level network which provides a simple, fast,
inexpensive, and deterministic means of exchanging data among control devices. These
devices include sensors such as photo switches, proximity sensors, and push buttons;
actuators such as valves and contactors; and controllers such as PLCs and personal
computers. Control devices are networked together by a single 4-conductor cable, saving
the considerable installation cost of traditional hard-wired control and I/O systems.
The SERIPLEX cable includes four wires: two for power (normally +24 VDC), one
Clock signal, and one Data signal. Each data transmission frame is defined by a series
of pulses on the Clock line, bounded by a Sync pulse during which the Clock line
remains inactive for 8 clock periods. Each device on the network counts the Clock
pulses, and the state of the Data line during a particular Clock period defines the value
of a corresponding Data signal bit. (Refer to Figure 2.)
Frame Length = Number of Addresses
Clock
0
1
2
3
4
Addresses or
Pulse Numbers
253 254 255
Sync Period
Sync Period
Data
Sampled
Here
+12 VDC
Data
3
0 VDC
Figure 2: Peer-to-Peer Timing Diagram
Each discrete input or output device on the bus is assigned an address. In the peer-topeer bus mode, this signal address corresponds directly to the sequence of the Clock
pulses. For example, input device 3 asserts its signal value on the Data line during
Clock pulse 3. Correspondingly, output device 3 monitors the Data line during Clock
pulse 3 to determine whether it should be on or off until the next time its signal is
presented to the bus. In this way, input devices can directly control output devices
without intervention by a host controller such as a computer or PLC.
Devices may be assigned multiple consecutive signal addresses in order to form a
multi-bit signal value. For instance, 16 consecutive bits could be assigned to an analog
input device such as a flow meter; these bits would then represent a 16-bit binary
number which could be read and used by another device.
In the master/slave bus mode, there are two clock pulses per signal address instead of
one in the peer-to-peer mode (Figure 3). During the first clock pulse for each address,
input data is transmitted from a remote device to a host controller such as a computer
or PLC. During the second clock pulse, the host controller transmits output data to
remote devices. This logically separates input signals from output signals at the same
address, and allows the host controller to make all control decisions and to have
exclusive control over the state of all bus output signals. In this mode, the ASIC writes
input signals and reads output signals to and from the bus, but does not read input
signals from or write output signals to the bus.
6
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
ASIC2B Data Sheet
System Overview
Frame Length = Number of Addresses
0
Address
+12 VDC
Clock
Line
0V
Pulse
Number
0
2
1
1
2
Sync Period
3
in
Input
1
Data +12 VDC
Line
3
254
4
5
6
7
out
in
Data
sampled
here
out
in
out
255
8
510 511
Sync
Period
Output
2
0V
Figure 3: Master/Slave Timing Diagram
The maximum number of signal bits which may be transmitted within a single data
frame is 255 in peer-to-peer mode and 510 in master/slave mode (Address 0 is not
used). However, the peer-to-peer mode still supports 510 I/O devices because each
signal acts as both an input and an output signal. Signal capacity may be increased by
multiplexing, in which multiple devices are assigned the same signal addresses. This is
accomplished by using Output signals 1 through 4 as a binary number which indicates
a “multiplex channel” between 0 and 15. A single multiplex channel is scanned in each
data frame. Remote I/O devices may be assigned to an individual multiplex channel.
These devices monitor the multiplex channel indication to determine whether to assert
or receive their signals within a particular data frame.
Non-Multiplexed Data
0
16
Bits 1–4
Channel
Decode
32
Multiplexed Data
48
0000 = 0
0001 = 1
0010 = 2
...
1111 = 15
64
80
240
Channel
0
1
2
15
Figure 4: Multiplex Channel
SERIPLEX signal update time depends on the length of the data frame (from 16 to 256
addresses), the bus Clock rate (16 to 200 kHz), and the number of multiplex channels
scanned (1 to 16). Refer to SERIPLEX system documentation for methods of calculating
signal update times.
The ASIC supports elementary logic which allows for more complex control in peer-topeer mode systems. Each input and output state may be logically inverted by making
individual selections during the ASIC set-up process. In addition, the ASIC contains a
single logic gate which produces a third physical output (Output C) as any of eight
logical combinations of the two bus output signals (Outputs A and B). This logical
combination can in turn be sent to the bus as an input signal through use of the Data
Echo feature.
The SERIPLEX bus Clock and Data signal amplitude is 12 VDC nominal, while the bus
power can be either 12 or 24 VDC nominal. The Data signal is low true, meaning that a
low logic level corresponds to a value of 1, with high corresponding to 0. In its “resting”
state, the Data line is pulled high by the source of the Clock signal (either a clock
module or host controller). Any device asserts its input signals by either pulling the
Data line low during the proper Clock pulse to indicate a 1, or by leaving the Data line
high to indicate a 0.
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
7
ASIC2B Data Sheet
System Overview
Bulletin No. 8310PD9601
March 1997
With this method, “wire-OR” logic may be used—that is, multiple devices may be
assigned to a given input signal and any of them may assert a 1 to override the 0’s
asserted by other duplicate devices. Similarly, multiple output devices may be assigned
to the same address, and all respond to the same output signal value. In this way the
I/O capacity of the bus may be increased to more than 510 devices per data frame.
The SERIPLEX ASIC is embedded into control devices to allow these devices to
communicate through the bus. The ASIC connects directly to the bus and completely
implements the SERIPLEX protocol according to standards, so that this protocol is
transparent to device designers. The ASIC may be used for both discrete (single-bit)
and analog (multi-bit) devices to interface input signals, output signals, or both.
Because it does not supply the bus Clock signal, the ASIC2B would generally not be
used for controllers such as computers or PLC interfaces.
8
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
ASIC2B Data Sheet
Theory of Operation
THEORY OF OPERATION
Bus Interface
Data Driver Data In Clock
7
3
4
Data In
Vcc
10
EEPROM
Read/Write
Controller
Osc
Clock
Clock
Inhibit
Data In
EEPROM
Data
Shift
Clock
Generator
Clock
Inhibit
Osc
Address
Decoder
Read/
Write
Control
Bus
Input
Signals
Signal
Addresses
Bus
Output
Signals
Clock
Sync and
Clock Loss
Detector
Bus Mode
9
Multiplex
Clock
Generator
11
Mode/Sync
Signal
Generator
8
Circuit
Interface
Shift
Clock In
Shift
Clock Out
Multiplex
Clock
Mode/
Sync
Inhibit
Output C Logic
Selections
Output
Polarities
EEPROM
Debounce
Selections
Data Echo
Selections
Input
Threshold
Input
Polarities
Output
Controller
Input
Signal
Selector
Bus Fault
Detector
Data In
Inhibit
Inhibit
Reset
Delay
Inhibit
Input
Controller
Osc
Vcc
Power
Interface
16 Vcc
(Power)
Cosc
12
Internal
Power
Oscillator
Voltage
Regulator
2 Vss
(Common)
1 Vdd
(9 V Ref.)
Osc
5
A
6
B
15 14 13
A B C
Inputs
Outputs
Signal Interface
Figure 5: ASIC2B Block Diagram
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
9
ASIC2B Data Sheet
Theory of Operation
Overview
Bulletin No. 8310PD9601
March 1997
The primary function of the SERIPLEX ASIC2B is to transmit 2 discrete input signals
from external circuitry to the SERIPLEX control bus, and to transmit 2 discrete output
signals from the SERIPLEX bus to external circuitry. In addition, the ASIC provides:
•
A third physical output as a logical combination of the two bus output signals
•
Bus Fault Detection to prevent invalid output signals from reaching external
circuitry
•
Clock Loss Detection to ensure that input and output signals assume a known
state in the event that the SERIPLEX bus stops running
•
Shift clocks which may be used by external circuitry to shift multi-bit signals (such
as analog values) to and from the SERIPLEX bus
•
Multiplex Clock output which may be used by external circuitry to decode the
currently active multiplex channel number
•
Mode/Sync output which indicates to external circuitry both the selected
SERIPLEX bus mode (master/slave or peer-to-peer) and the timing of the
SERIPLEX bus Sync pulse
•
A 9 VDC reference signal which may be used by external circuitry to create a
stable power supply for use by external signal-processing circuitry
•
A means to store ASIC configuration data (signal addresses, logic settings, etc.) in
non-volatile memory so that it can be retrieved for use by internal ASIC circuitry
The block diagram in Figure 5 shows the general signal flow and functional circuitry
which the SERIPLEX ASIC2B uses to accomplish its functions. This section gives a brief
overview of the ASIC operation; more detailed explanations of each function within the
ASIC are given in the following sections.
The ASIC is powered from the SERIPLEX bus power supply. This voltage is internally
regulated by the ASIC to provide signal stability, as well as an external reference
voltage.
The ASIC2B communicates with the SERIPLEX bus by means of the Clock, Data In, and
Data Driver signals. The Clock and Data In signals are connected directly to the
SERIPLEX bus Clock and Data lines, whereas the Data Driver signal is intended to
drive an external transistor which in turn would be directly connected to the SERIPLEX
bus Data line.
The Address Decoder counts SERIPLEX bus Clock pulses to determine when to
transmit input and output signals to and from the bus, based on the programmed A
and B signal addresses. The Sync and Clock Loss Detector resets the Address Decoder
at the end of each bus data frame.
Input signals flow through the Input Controller, where they are inverted if so
programmed, and on to the Input Signal Selector, which determines whether to
combine the input signals with output signals according to Data Echo programming
selections. The processed input signals are then made available to the Address Decoder
for transmission to the SERIPLEX bus.
Output signals flow from the Address Decoder both to the Output C logic and directly
to the Output Controller. The Output C Logic combines Output A and B signals to form
the Output C signal. The Output Controller inverts the Output signals if programmed
and then sends them to the Output pins if allowed by the Sync and Clock Loss Detector
and by the Bus Fault Detector.
The Shift Clock In, Shift Clock Out, and Multiplex Clock signals use the Address
Decoder and the Clock signal to create clock signals for use by external circuitry. The
Shift Clock signals facilitate exchange of multi-bit signals with the SERIPLEX bus (such
as analog signal values), and the Multiplex Clock facilitates decoding of the currently
active multiplex channel.
10
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
ASIC2B Data Sheet
Theory of Operation
The EEPROM Read/Write Controller performs reading and writing to the ASIC’s onboard EEPROM non-volatile memory, which is used to store ASIC2B configuration
data such as signal addresses and logic selections.
The Oscillator provides an internal clock signal which is used to control and
synchronize timing of signals within the ASIC2B.
Address Decoding
The ASIC2B is assigned two different signal addresses during ASIC programming—
Address A and Address B. Each signal address is shared by both an input signal and
an output signal. In the peer-to-peer mode, input and output signals sharing the same
signal address are identical since they are present on the bus at the same time. In
master/slave mode, the input and output signals are logically separate, since they are
transmitted during different Clock pulses.
The Address Decoder counts pulses of the Clock signal to determine the current signal
address to be transmitted over the bus. When the address decoded from the clock
pulses is the same as the ASIC’s A or B programmed signal address, then the
appropriate input signal is transmitted to the Data Driver pin, and/or the output signal
is transmitted from the Data In pin to the Output Controller and the Output C logic.
In the peer-to-peer bus mode, each clock pulse corresponds to a signal address, so that
the Clock pulse count equals the signal address. In the master/slave mode, there are
two clock pulses per address, with the first clock pulse being for input signals and the
second for output signals. Therefore in master/slave mode the Address Decoder
divides the Clock pulse count by 2 to determine the signal addresses.
Clock pulses are counted at the negative (high-to-low) transition of the Clock signal.
The address decoder makes SERIPLEX bus input data available to the Data Driver pin
immediately following the positive (low-to-high) transition of the Clock pulse
corresponding to that input signal address, so that it may be sampled at the next
negative transition. The ASIC samples SERIPLEX bus output data at the appropriate
negative transition of the Clock signal. In peer-to-peer mode, the ASIC both transmits
and receives data during the same Clock pulse, whereas in master/slave mode, input
data is sampled and output data is transmitted during separate Clock pulses.
The Address Decoder recognizes and decodes signal addresses from 1 through 255.
Signal addresses greater than 255 are effectively ignored by the ASIC2B. The Address
Decoder is reset at the end of each data frame by the Sync and Clock Loss Detector,
whereupon it starts counting again at 0.
When power is applied to the ASIC2B following a power-loss condition, the Address
Decoder is reset to 0.
Sync and Clock Loss
Detection
SERIPLEX bus data frames are defined by a series of pulses on the bus Clock line,
bounded by a Sync period of approximately 8 Clock cycles during which the Clock line
remains in the high logic state. This Sync period is used to synchronize all SERIPLEX
bus devices’ address-decoding mechanisms. If the Clock line remains inactive for an
extended period of time, as when the bus is not operating, the ASIC2B detects a Clock
Loss condition. Upon Clock Loss, output signals are disabled and the ASIC is placed in
its default state.
The Sync and Clock Loss Detector continually monitors the Clock signal. If no negative
(high-to-low) transition of the Clock signal is detected for 10 cycles of the internal
oscillator (Cosc), a Sync period is detected. In a typical application circuit, this period
is approximately 67 µs, which is slightly longer than half the 100 µs period of the
SERIPLEX minimum-frequency 10 kHz Clock signal. The Sync and Clock Loss
Detector notifies the Address Decoder, the Bus Fault Detector, and the Mode/Sync
Signal Generator of the presence of the Sync period.
If negative transition of the Clock signal is not detected for 256 cycles of Cosc, Clock
Loss is detected. In a typical application circuit, this period is approximately 1.7 ms.
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
11
ASIC2B Data Sheet
Theory of Operation
Bulletin No. 8310PD9601
March 1997
The Sync and Clock Loss Detector notifies the Address Decoder, the Output Controller,
the Input Controller, and the Shift Clock Generator of the Clock Loss condition.
Both Sync Period and Clock Loss conditions are ended upon the first negative
transition of the Clock signal following the Sync detection.
Input Control
External input signals are received from the Input A and Input B pins by the Input
Controller. These pins are low-true; that is, a low logic level corresponds to a signal
value of 1, and a high level corresponds to 0. The logic thresholds of these signals are
determined by the Input Threshold selection during ASIC programming, which may
be set to either 0 to 5 VDC, or 0 to 9 VDC.
The Input Controller uses a low-bandpass filter to reject noise on the input signals.
Each input signal must remain stable for approximately 5 cycles of the internal
oscillator (Cosc) in order for the ASIC2B to detect a change in logic state; typically this
period is approximately 33 µs. The external circuitry which connects the input signals
to the ASIC2B must include a 390 K resistor in series with each input, which acts with
internal ASIC circuitry to create an anti-aliasing filter.
If selected during ASIC programming, the Input Controller inverts the logical state of
either input signal. The conditioned input signals are then transmitted to the Input
Signal Selector.
Input Signal Selection and
Data Echo
The Input Signal Selector determines whether to transmit the conditioned input signals
directly to the Address Decoder, or to transmit output signals as SERIPLEX bus inputs,
depending upon the Data Echo options selected during ASIC programming.
If no Data Echo options are selected during ASIC programming, the Input Signal
Selector simply passes the conditioned input signals from the Input Controller directly
to the Address Decoder.
If the selection to echo Output A to Input B is made, the Input Selector logically OR’s
the Output A signal from the Output Controller with the Input B signal from the Input
Controller, and then transmits this combined signal to the Address Decoder. In most
cases when the Data Echo option is selected, the external Input B signal is not used, so
that the SERIPLEX bus Input B signal is logically equivalent to the ASIC2B’s external
Output A signal.
Similarly, Output B or Output C may be echoed to Input A. This selection is made in
two steps—first, the selection is made as to whether any output signal will be echoed
to Input A, and then the selection is made as to whether the signal to be echoed will be
Output B or Output C. Again, the Input Signal Selector logically OR’s the echoed
output signal with the conditioned Input A signal from the Input Controller.
The Echo Output C to Input A feature may be used to report a logical combination of
SERIPLEX bus output signals back to the SERIPLEX bus, although care must be taken
to ensure that this does not cause unintentional signal feedback at Address A.
The Input Signal Selector clears the bus input signal values to 0 whenever the Inhibit
signal is asserted by the Reset Delay circuit. This ensures that no input data is presented
to the SERIPLEX bus during a power loss, Bus Fault, or Clock Loss condition, and for
4 bus data frames following the removal of all of these conditions.
12
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
Output Control and
Debouncing
ASIC2B Data Sheet
Theory of Operation
The Address Decoder sends Output A and Output B signals directly from the SERIPLEX
bus to the Output Controller. If selected through ASIC programming, the Output
Controller debounces Output signals A and B. This feature may be used to filter output
signals in noisy applications, as well as to compensate for “bouncy” control devices such
as mechanical switches. Debouncing is accomplished by comparing the present output
signal value from the bus to the value received in the last 1 or 2 data frames. The Output
Controller changes the state of the output signal between 1 and 0 if and only if all the
compared signal values agree—that is, if the output signal has remained stable for the
required debounce period. For each of the ASIC2B’s bus output signals, the Digital
Debounce feature may be disabled, or a debounce length of either 2 or 3 data samples
(current value + 1 or 2 previous values) may be selected during programming.
The Output Controller produces the Output C signal by combining the debounced
Output A and Output B signals through a logical OR gate according to the truth table
below. Selection of Outputs A and B signal polarity for the Output C logic gate does not
affect the logical state of the external Output A and Output B pins. Conversely, logical
inversion of the external Output A and Output B pins does not affect operation of the
Output C logic.
Table 1:
Invert
A→C
N
N
N
N
Y
Y
Y
Y
Output Control
Invert
B→C
N
N
Y
Y
N
N
Y
Y
Invert
Output C
Logic
Equation
N
C=A+B
C’=A’*B’
Y
N
Y
N
Y
N
Y
C’=A+B
C=A’*B’
C=A+B’
C’=A’*B
C’=A+B’
C=A’*B
C=A’+B
C’=A*B’
C’=A’+B
C=A*B’
C=A’+B’
C’=A*B
C’=A’+B’
C=A*B
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Output A
Signal
Output B
Signal
Output C
Signal
0
0
0
0
1
1
1
0
1
1
1
1
0
0
1
0
1
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
0
0
0
1
0
1
0
1
1
1
0
0
0
1
0
1
1
1
0
1
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
13
ASIC2B Data Sheet
Theory of Operation
Bulletin No. 8310PD9601
March 1997
The Output Controller inverts the logical state of individual output signals if selected
through ASIC programming. The processed output signals are then latched onto the
ASIC’s Output A, Output B, and Output C pins at the end of the SERIPLEX bus Sync
period following the bus data frame during which the output signals were received.
Note that there is a fixed delay between reception of an output signal and its
availability to the ASIC2B’s output pin; this delay is determined by the bus Clock
frequency, frame size, and the output signal address.
The Output controller clears the Output signal values to 0 and turns off the Output pins
(that is, the pins become open-circuit) whenever the Inhibit signal is asserted by the
Reset Delay circuit. This ensures that no output data is presented to the external
circuitry during a power loss, Bus Fault, or Clock Loss condition, and for five bus data
frames following the removal of all of these conditions. In the event of a Bus Fault, the
outputs will be inhibited at the same time that the latest data would be clocked to the
Output pins; this behavior should prevent invalid data caused by a Bus Fault condition
from reaching the external circuitry.
Following any condition which produces the Inhibit signal, all external output pins
remain disabled until the debounce conditions for both Output A and Output B have
been satisfied.
Bus Fault Detection
During the Sync period following each SERIPLEX bus data frame, ASIC2B-compatible
SERIPLEX controllers (such as Clock Modules and controller cards) produce a pulse on
the bus Data line. Proper reception of this pulse by both the controller and the remote
devices indicates to each device that the Data line is not open, shorted high (to Power),
or shorted low (to Common). This also indirectly indicates that bus Power is present,
and that the bus Clock signal is operating properly since a valid Sync period has been
detected.
The Bus Fault Detector monitors the Data In signal following detection of a SERIPLEX
bus Sync period. If it detects a negative (high-to-low) transition of the Data line before
the Sync period is terminated by a negative transition of the Clock line, the bus is
presumed to be operating normally, and the Output Controller is allowed to operate
normally.
If the Bus Fault Detector does not detect a negative transition of the Data line within
the Sync period, it asserts a Bus Fault signal to the Reset Delay circuit. This inhibits the
external output signals and the Data Shift Clock outputs, turning them off.
Oscillator
The Oscillator produces an internal clock signal which is used by several ASIC2B
internal circuits to synchronize and control timing within the ASIC2B. The frequency
of this clock signal is determined by the value of the external resistor connected to the
Cosc pin.
The oscillator signal is used by the following circuits within the ASIC2B:
•
Sync and Clock Loss Detector
•
Input Controller (for low-bandpass signal filter)
•
EEPROM Read/Write Controller
A Cosc frequency of 150 kHz is recommended for device operation over the SERIPLEX
bus frequency range of 10 to 200 kHz. This may be accomplished by connecting a
54.9 kΩ resistor between the Cosc pin and Vss.
At a Cosc frequency of 150 kHz, the ASIC2B will detect a Sync period in approximately
67 µs. This is longer than one-half Clock period at the minimum bus Clock rate of
10 kHz; that is, during data transmission the bus Clock signal would not remain at a
logic high level for more than 50 µs. However, the 67 µs Sync-detect time is still less
than the minimum Sync period duration of 80 µs, which is used at bus Clock rates from
100 to 200 kHz.
14
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
Voltage Regulator
ASIC2B Data Sheet
Theory of Operation
The ASIC is powered by the SERIPLEX bus power source, which may be either 12 or
24 VDC nominal. The internal Voltage Regulator provides the ASIC internal circuitry
with a stable power supply, so that signal levels, thresholds, and timing remain
constant throughout the external power source’s voltage range.
The Voltage Regulator also provides a stable 9 VDC reference signal through the Vdd
pin. This reference voltage may be used by external circuitry to create a stable power
supply for use by external signal-processing circuitry. Note that the 9 VDC reference
signal is valid at SERIPLEX bus voltages above 12.0 VDC; below this value the 9 VDC
reference may fall below its specified voltage level.
Reset Delay
The Reset Delay circuit prevents the ASIC2B from transmitting SERIPLEX bus input
and output signals during abnormal operating conditions. These conditions include:
•
Power Loss
•
Bus Fault
•
Clock Loss
•
EEPROM Program/Verify mode
When the Reset Delay circuit detects a loss of ASIC power from the Vcc pin, or is
notified of any of the listed conditions by other circuits within the ASIC, it asserts an
Inhibit signal. This Inhibit signal is used by internal ASIC circuitry as follows:
•
The Output Controller disables external output signals and resets its debounce
circuitry.
•
The Input Signal Selector clears input signals and disables their transmission to
the SERIPLEX bus.
•
The Shift Clock Generator disables transmission of the shift clock signals.
•
The Address Decoder reinitializes its address counter and output signal values.
•
The Mode/Sync Signal Generator disables transmission of the Sync pulse signal.
The Inhibit signal is released from the Input Signal Selector and the Mode/Sync Signal
Generator upon the fourth SERIPLEX bus Sync period following removal of all of the
listed conditions. The Inhibit signal is released from the Output Controller, Shift Clock
Generator, and the Address Decoder upon the fifth Sync period or upon satisfaction of
both the A and B output debounce conditions, whichever occurs later following
removal of all of the listed conditions. This allows time for SERIPLEX bus and ASIC2B
internal signals to stabilize before normal operation resumes.
Mode/Sync Generation
The Mode/Sync Signal Generator produces the Mode/Sync signal, whose normal state
indicates whether the ASIC2B has been programmed to operate in master/slave or
peer-to-peer mode. This circuit produces a short pulse on the Mode/Sync signal at the
time that a SERIPLEX bus Sync period is detected by the Sync and Clock Loss Detector.
If peer-to-peer mode is selected through ASIC2B programming, the Mode/Sync pin is
normally set to a low logic state. When the Sync and Clock Loss Detector detects a Sync
period, the Mode/Sync Signal Generator sets the Mode/Sync pin to a high logic state
for the duration of one cycle of the internal Cosc oscillator (typically 6.7 µs), and then
returns the pin to a low logic state.
If master/slave mode is selected through ASIC programming the Mode/Sync pin is
normally set to a high logic state. When the Sync and Clock Loss Detector detects a
Sync period, the Mode/Sync Signal Generator sets the Mode/Sync pin to a low logic
state for the duration of one cycle of the internal Cosc oscillator (typically 6.7 µs), and
then returns the pin to a high logic state.
In most cases, it is possible for external circuitry which monitors the Mode/Sync signal
for Sync timing to look for only the positive transition or only the negative transition
of this signal, regardless of whether master/slave or peer-to-peer mode is selected.
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
15
ASIC2B Data Sheet
Theory of Operation
Bulletin No. 8310PD9601
March 1997
These edges will be skewed by approximately one Cosc cycle (typically 6.7 µs) between
the two modes, but this time is relatively insignificant compared to a SERIPLEX data
frame period, so it probably has little effect on the operation of external circuitry.
The Mode/Sync Signal Generator does not produce the Sync pulse whenever the
Inhibit signal is asserted by the Reset Delay circuit. However, the SERIPLEX bus mode
indication is still valid at all times while the ASIC2B is properly powered.
Input and Output Shift
Clock Generation
The Shift Clock Generator produces clock signals which may be used by external
circuitry to shift multi-bit signals (such as analog values) between external shift
registers and the SERIPLEX bus. The shift clock signals are generated from the time
that Address A is detected until the time that Address B is detected on the SERIPLEX
bus, and are timed so that input and output signals may be read from and written to
the bus Data line in accordance with SERIPLEX protocol standards. Both a Shift Clock
Out and an Shift Clock In are provided because SERIPLEX bus timing is different for
input and output signals in the master/slave mode.
The Shift Clock In signal is used to shift SERIPLEX Bus output data from the bus into
external shift register circuitry. It normally rests at a high logic state. It is timed so that
it produces negative (high-to-low) transitions at the same time that the SERIPLEX bus
Clock signal is undergoing negative transitions at which bus output data signals are
sampled. The first cycle of the Shift Clock In signal begins during the SERIPLEX bus
Clock cycle corresponding to the ASIC’s Output A signal address, and the last cycle
corresponds to the ASIC’s Output B signal address.
The Shift Clock Out signal is used to shift SERIPLEX Bus input data out of external shift
register circuitry and onto the SERIPLEX bus. It normally rests at a high logic state. It is
timed so that it produces negative transitions at the same time that the SERIPLEX bus
Clock signal is undergoing positive transitions which indicate that bus input data should
be placed on the bus Data line to be sampled. The first cycle of the Shift Clock Out signal
occurs during the SERIPLEX bus Clock cycle corresponding to the ASIC’s Input A signal
address, and the last cycle corresponds to the ASIC’s Input B signal address.
Note that the period of the Shift Clock In and Shift Clock Out signals is twice as long in
master/slave mode operation as it is for peer-to-peer mode operation at the same
SERIPLEX bus Clock frequency, due to the presence of separate input and output clock
pulses in master/slave mode. The duration of the negative Shift Clock In negative
pulse is 0.5 SERIPLEX bus Clock cycles for both bus operating modes. The duration of
the Shift Clock Out negative pulse is 0.5 bus Clock cycles in peer-to-peer mode and 1
full bus Clock cycle in master/slave mode.
The Shift Clock Generator holds both Shift Clocks in the high logic state at all times
while the Inhibit signal is asserted by the ASIC2B’s Reset Delay circuit. The Shift Clock
outputs are re-enabled following the fifth Sync period after all conditions which
produce the Inhibit signal are removed.
Multiplex Clock Generation
The Multiplex Clock Generator produces a Multiplex Clock signal, timed to allow
external circuitry to read Output signals 1 through 4 from the SERIPLEX bus. These
signals may be decoded by the external circuitry to determine the multiplex channel
currently being scanned on the SERIPLEX bus. This facilitates the design of devices
which provide multiple different signals on different multiplex channels, as well as
devices which produce a single signal on an individual multiplex channel.
The Multiplex Clock signal normally rests at a high logic state. It is timed to produce
negative (high-to-low) transitions at the same time that the SERIPLEX bus Clock signal
is undergoing negative transitions at which bus output data is sampled. The first
negative transition occurs during the bus Clock cycle corresponding to Output 0, in
order to give the external circuitry time to prepare to receive the multiplex channel
indication bits. The Multiplex Clock continues to cycle during Outputs 1 through 4,
and then returns to its resting state.
16
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
ASIC2B Data Sheet
Theory of Operation
The period of the Multiplex Clock signal is equal to 1 bus Clock cycle in the peer-topeer mode, and 2 bus Clock cycles in the master/slave mode, due to the presence of
separate input and output clock pulses in master/slave mode. The duration of the
negative Multiplex Clock pulse is 0.5 bus clock cycles in both bus operating modes.
External circuitry which makes use of the Multiplex Clock signal must connect directly
to the SERIPLEX bus Data line. The SERIPLEX bus output data cannot be shifted
through the ASIC2B’s output pins.
The operation of the Multiplex Clock Signal Generator is not affected by the Inhibit
signal produced by the ASIC2B’s Reset Delay circuit.
EEPROM and Programming
Control
The EEPROM provides storage for ASIC configuration data such as signal addresses
and logic settings. Because this memory is “non-volatile”, the configuration data is
retained even while the ASIC is not powered. Individual EEPROM memory locations
are used by the ASIC’s internal circuits to determine the operation of the ASIC.
The EEPROM Read/Write Controller monitors the Clock and Data In signals to
determine when an EEPROM Read/Write or read request is being received. If a proper
programming request sequence is detected and the power input (Vcc) is within the
allowable range, the EEPROM Read/Write Controller generates the proper internal
logic signals to allow data transfer between the EEPROM and the programming device.
The EEPROM contains 32 bits of information to store the necessary configuration data
for the ASIC2B’s programmable features, as shown in Table 2.
Table 2:
EEPROM Information
No. of Bits
Function
8
Signal Address A
8
Signal Address B
2
Input Signal Polarity (external input signals A and B)
3
Output Signal Polarity (external output signals A, B, and C)
2
Output C Logic Selections (polarity of bus output signals A and B into Output C logic)
1
SERIPLEX Bus mode (master/slave vs. peer-to-peer)
4
Output Signal Debounce Selections:
• Debounce Enable for bus output signals A and B
• Debounce Length (2 vs. 3 data samples) for bus output signals A and B
1
External Input Signal Thresholds (0 to 5 vs. 0 to 9 VDC)
Both input signal thresholds are controlled by the same selection bit
3
Data Echo Selections:
• Echo external output signal A to bus input signal B
• Echo either external output signal A or C to bus input signal A
• Select external output signal B vs. C for echo to bus input signal A
! WARNING
UNINTENTIONAL EQUIPMENT OPERATION
The SERIPLEX ASIC2B’s EEPROM memory must be programmed and read exactly as
described in this bulletin. Design of circuits using the ASIC2B and of programming
devices for the ASIC2B must ensure compliance with these guidelines. Failure to do so
can result in incorrect and/or unstable data within the EEPROM memory. Depending
upon the circuit and its application, an improperly programmed ASIC2B can cause
unintentional operation of control devices.
Failure to observe this instruction can result in death, serious injury, or
equipment damage.
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
17
ASIC2B Data Sheet
Theory of Operation
Bulletin No. 8310PD9601
March 1997
The EEPROM data is written and read serially through the ASIC2B’s SERIPLEX bus
interface pins. The following conditions must be present in order for the EEPROM
Read/Write Controller to enable EEPROM reading and/or writing:
•
The ASIC power (Vcc–Vss) must be within the EEPROM programming voltage
range of 15 to 16.5 VDC.
•
The Clock signal must remain idle for at least 6,144 cycles of Cosc (approximately
40.5 ms at 150 kHz) while power is applied to the ASIC.
•
The EEPROM Read/Write Controller must detect 15 positive (low-to-high)
transitions of the Data In signal while the Clock signal is held at the high logic
state, following the 40.5 ms waiting period.
EEPROM programming must be accomplished within the specified programming
voltage range. Programming at too low a voltage may reduce the data retention time
of the EEPROM, resulting in EEPROM cell “1” values changing to “0”. Programming
at a voltage above the threshold may result in damage to the EEPROM memory, which
can result in both incorrect data values and inability to reprogram the memory.
Once the EEPROM Read/Write Controller has detected a valid Program Mode
sequence, it checks the condition of the Data In signal during the first negative
transition of the Clock signal. If the Data In signal is in a low logic state this indicates a
Write cycle, and the EEPROM Read/Write Controller shifts data from the Data In pin
into the EEPROM during the following 32 Clock cycles. If the Data In signal is high
during the first Clock transition to indicate a Read cycle, the Controller shifts data out
of the EEPROM onto the Data Driver pin during the following 32 Clock cycles.
One bit of EEPROM data is shifted to or from the SERIPLEX bus Data line during each
Clock cycle, with the bit being placed on the Data line at the positive transition of the
Clock line, and the data being sampled at the negative transition of the Clock line. Data
to be written to the ASIC2B is high-true (high logic state = 1, low = 0), but data read
from the ASIC2B is low-true (low = 1, high = 0).
EEPROM data is presented in Table 3 for both Read and Write operations:
Table 3:
Bit No.(s)
18
EEPROM Data for Read/Write Operations
EEPROM Data Element
Possible Values
1-8
Signal Address A
8-bit binary value between 0 and 255
Transmitted least-significant bit first
(0 is invalid, but is not prevented)
9-16
Signal Address B
8-bit binary value between 0 and 255
Transmitted least-significant bit first
(0 is invalid, but is not prevented)
17
Input A Polarity
0 = Non-inverted
1 = Inverted
18
Input B Polarity
0 = Non-inverted
1 = Inverted
19
Output A Polarity
0 = Non-inverted
1 = Inverted
20
Output B Polarity
0 = Non-inverted
1 = Inverted
21
Output C Polarity
0 = Non-inverted
1 = Inverted
22
Output A Logic Polarity
(Input to Output C Logic)
0 = Non-inverted
1 = Inverted
23
Output B Logic Polarity
(Input to Output C Logic)
0 = Non-inverted
1 = Inverted
24
SERIPLEX Bus Mode
0 = Peer-to-peer mode (mode 1)
1 = Master/slave mode (mode 2)
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
ASIC2B Data Sheet
Theory of Operation
Table 3:
EEPROM Data for Read/Write Operations (Continued)
Bit No.(s)
EEPROM Data Element
Possible Values
25
Debounce Output A
0 = No Output A debounce
1 = Debounce bus Output A signal
26
Output A Debounce Length
0 = 2 Output A Debounce data samples
1 = 3 Output A Debounce data samples
27
Debounce Output B
0 = No Output B debounce
1 = Debounce bus Output B signal
28
Output B Debounce Length
0 = 2 Output B Debounce data samples
1 = 3 Output B Debounce data samples
29
Input Logic Threshold
0 = 0 to 5 VDC Input A and B logic threshold
1 = 0 to 9 VDC Input A and B logic threshold
30
Echo Output A to Input B
0 = No data echo Output A to Input B
1 = Echo Output A to Input B
31
Echo B or C to Input A
0 = No data echo Output B or C to Input A
1 = Echo Output B or C to Input A
32
Echo B vs. C to Input A
0 = Echo Output B to Input A
1 = Echo Output C to Input A
Voltage levels for the Clock and Data In signals must swing between bus common (Vcc)
and at least the Vdd reference of the IC being programmed (typically 9 VDC); a high
logic signal level of +12 VDC is recommended with 100 kΩ series resistance. It is
recommended that the clock frequency be between 31 and 41 kHz.
If the EEPROM data has been successfully received during an EEPROM Write cycle, the
Data Driver output of the ASIC2B becomes active indicating that the EEPROM
Programming Cycle is active. The Data Driver signal remains active until EEPROM
programming is complete. The bus Clock input of the ASIC must continue to toggle
until the Data Driver signal becomes inactive. After the Write data shifts into the
ASIC2B, the EEPROM Read/Write Controller erases the existing EEPROM data, and
then writes the new data into the EEPROM. This entire operation requires about 500 ms.
At the end of an EEPROM Read or Write cycle, the ASIC2B exits the EEPROM
Programming mode, and is ready for normal operation. The power voltage should be
moved out of the programming voltage range at this time.
0
1
2
3
29 30 31 32
Clock
1
Data
In
Data
Driver
Program
Mode
Reset
Time
2
3
4
14 15
R/WR
Program Mode
Pulses
Set-up
Time
EEPROM Data
Programming
Busy
Idle
Figure 6: EEPROM Read/Write Cycle Timing Diagram
EEPROM Programming Mode Reset Time: Before the ASIC2B is allowed to enter
EEPROM Programming Mode, the Clock line must remain at a high logic state for at
least 6,144 cycles of Cosc (40.5 ms at Cosc = 150 kHz).
EEPROM Programming Mode Pulses: Following the Program Mode Reset Time the
ASIC2B must sense 15 positive (low-to-high) transitions of the Data In signal while the
Clock signal remains high and Vcc (power) is between 15 and 16.5 VDC. The ASIC2B
enters programming mode immediately upon sensing the 15th positive transition.
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
19
ASIC2B Data Sheet
Theory of Operation
Bulletin No. 8310PD9601
March 1997
Set-up Time: The time required by the programming device to set up the Data In signal
before initiating the first Clock signal transition. This time is not limited by the ASIC2B.
Read/Write Signal: The ASIC2B monitors the state of the Data In signal during the first
negative (high-to-low) transition of the Clock signal to determine whether this is a
Read or a Write cycle. If the Data In signal is in a high logic state, this indicates a Read
cycle and the following 32 Clock pulses are used to shift data out of the EEPROM onto
the Data Out pin. If the Data In signal is low, this is a Write cycle and data is shifted into
the EEPROM from the Data In pin.
EEPROM Data: For the next 32 Clock signal pulses, one bit of EEPROM data is placed
onto the Data In and/or Data Driver pins (depending on whether this is a Read or
Write cycle) at each positive transition of the Clock signal. This data is then sampled by
the receiving device at the next negative transition of the Clock signal. The received
Write data at the Data In pin is high-true. The transmitted Read data at the Data Driver
pin is also high-true, so that after being inverted through an external drive transistor it
appears on the SERIPLEX Data line as low-true.
Programming Time: During a Write Cycle, the ASIC2B asserts a Programming Busy
signal by driving the Data Driver line high while completing the EEPROM erase and
program cycle. This appears as a low logic signal after passing through the external
Data Drive transistor.
The Clock signal must pulse during this period or the EEPROM programming
operation will terminate and the EEPROM data will be indeterminate. When EEPROM
programming is complete, the Data Driver output turns off, and the programming
device returns the Clock signal to its logic-high resting state. The ASIC2B exits EEPROM
Programming Mode and is ready for normal operation. The power voltage should be
moved out of the programming voltage range after the Busy signal is released.
The Programming Control Circuit counts 6,144 bus Clock pulses to erase the EEPROM,
followed by 6,144 Clock pulses to program the EEPROM with new data. These times
must fall within the Erase and Programming Cycle times specified within this
document. Programming for too short a time may reduce the data retention time of the
EEPROM, resulting in EEPROM cell “1” values changing to “0”. Programming for too
long may result in damage to the EEPROM memory, which can result in both incorrect
data values and inability to reprogram the memory.
Idle Time: Following completion of a Read cycle, the programming device should
continue to supply power to the ASIC2B with the Clock signal high for at least 0.1 s, to
ensure that the ASIC2B properly exits EEPROM Programming Mode.
20
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
PIN DESCRIPTIONS
Vcc (Power) and Vss
(Common) – Pins 2 and 16
ASIC2B Data Sheet
Pin Descriptions
Power is applied to the ASIC2B between the Vcc and Vss pins. Ordinarily this power
is obtained directly from the SERIPLEX bus. This power is nominally 24 VDC for
normal bus operation (12 VDC for ASIC1-compatible systems), and 15.5 VDC for
ASIC2B EEPROM reading and writing. A buffer resistor of 300 Ω should be placed in
series between the SERIPLEX bus power line and the ASIC2B’s Vcc pin. The voltage
loss across this resistor is approximately 0.4 VDC; the supply voltage must compensate
for this loss in both normal operation and ASIC programming.
Clock – Pin 4
The Clock pin is a logic input which receives the SERIPLEX bus Clock signal directly.
The input is current-sinking, so that external circuitry must supply positive voltage
and current in order to drive the input to a high logic state. A 100 kΩ series resistor
between this pin and the SERIPLEX bus Clock line is recommended to protect this
input from transient voltages on the bus. The Clock input uses 4.5 V hysteresis (based
on minimum 9 V signals) and a low pass filter with a breakpoint of 225 kHz (based on
100 kΩ series resistance). The filter roll-off is 6 dB/octave or greater.
Data In – Pin 3
The Data In pin is a logic input which receives the SERIPLEX bus Data signal directly. A
100 kΩ series resistor between this pin and the SERIPLEX bus Data line is recommended
to protect this input from transient voltages on the bus. The Data In input uses 4.5 V
hysteresis (based on minimum 9 V signals) and a low-pass filter with a breakpoint of
225 kHz (based on 100 kΩ series resistance). Filter roll-off is 6 dB/octave or greater.
Data Driver – Pin 7
The Data Driver output is a “totem-pole” dual-FET output intended to drive a FET
transistor which in turn drives the SERIPLEX bus Data line directly; refer to “Data
Driver Output (Active)” for specifications. The Data Driver output is high-true (high
logic level = 1, low = 0), which is inverted from the SERIPLEX bus Data line low-true
levels, so that it can drive the Data line properly through an open-drain FET or bipolar
NPN transistor. A pull-down resistor between the Data Driver pin and Vss (Common)
is required to turn off the external transistor if ASIC power is lost.
Inputs A and B – Pins 5 and 6
Input A and Input B are logic inputs which receive discrete (binary) input signals from
external circuitry connected to the ASIC2B. The inputs are current-sinking, so that
external circuitry must supply positive voltage and current in order to drive the inputs
to a high logic state. The inputs are low-true, so that a low logic state corresponds to a
signal value of 1, and a high state to 0. Input logic thresholds may be selected for
compatibility with either 0 to 5 VDC logic circuitry or 0 to 9 VDC logic. This selection
is made through ASIC2B EEPROM programming. The inputs use a low-bandpass filter
with a breakpoint of about 15 kHz and roll-off of 6 dB/octave, based on a Cosc
frequency of 150 kHz and 390 kΩ series resistance.
Outputs A, B, and C –
Pins 13, 14, and 15
Outputs A, B, and C are open-drain FET outputs intended to drive external circuitry to
perform logical control based on SERIPLEX bus output signals. The outputs are lowtrue, so that a low logic level corresponds to a signal value of 1, and a high state to 0. A
pull-up resistor is required between each output pin and Vcc (bus Power) in order for
the pins to achieve a high logic state.
These outputs are disabled (that is, off-state or open-circuit) whenever the ASIC2B has
detected a loss of the SERIPLEX bus Clock signal or a SERIPLEX Bus Fault, as well as
during ASIC2B programming and for a period of at least 5 SERIPLEX bus data frames
until all output debounce conditions have been satisfied following power-up or any
fault condition.
Cosc – Pin 12
The Cosc input is used to control the frequency of the ASIC2B’s internal Cosc clock,
based on the value of an external resistor connected between the Cosc pin and Vss
(Common). This signal controls and synchronizes timing of signals within the ASIC2B.
A Cosc frequency of 150 kHz (R = 54.9 kΩ) is recommended for operation over
SERIPLEX bus Clock frequencies from 10 to 200 kHz.
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
21
ASIC2B Data Sheet
Pin Descriptions
Bulletin No. 8310PD9601
March 1997
Vdd (+9 V Reference) – Pin 1
The Vcc pin is a low-current precision voltage source with a nominal output of +9 VDC
as referenced to Vss (Common). This reference voltage may be used by external
circuitry to create a stable power supply for use by external signal-processing circuitry.
Note that the 9 VDC reference signal is valid at SERIPLEX bus voltages above 12.0
VDC; below this value the 9 VDC reference may fall below its specified voltage level.
Mode/Sync – Pin 8
The Mode/Sync pin is a logic output whose normal state indicates whether the ASIC2B
has been programmed to operate in master/slave or peer-to-peer mode. In addition,
this circuit produces a short pulse on the Mode/Sync signal at the time that a
SERIPLEX bus Sync period is detected by the Sync and Clock Loss Detector. This
output is driven by an open-drain FET, so that an external pull-up resistor is required
between the Mode/Sync pin and Vcc (bus Power) in order for the output to achieve a
high logic state.
The Mode/Sync output is active at all times while the ASIC2B is powered. If this pin’s
steady-state output level is at a low logic state, peer-to-peer mode operation has been
programmed; a high state indicates master/slave mode operation. In addition, a pulse
of opposite polarity is superimposed on the steady-state signal for one cycle of Cosc at
the time that a SERIPLEX bus Sync period is detected by the ASIC2B.
Shift Clock In and Out –
Pins 9 and 10
The Shift Clock In and Shift Clock Out pins are open-drain FET outputs which may be
used by external circuitry to shift multi-bit signals (such as analog values) between
external shift registers and the SERIPLEX bus. An external pull-up resistor is required
between each Shift Clock pin and Vcc (bus Power) in order for these outputs to achieve
a high logic state.
The shift clock signals are generated from the time that Address A is detected until the
time that Address B is detected on the SERIPLEX bus, and are timed so that input and
output signals may be read from and written to the bus Data line in accordance with
SERIPLEX protocol standards.
Multiplex Clock – Pin 11
The Multiplex Clock pin is an open-drain FET output which may be used by external
circuitry to decode the multiplex channel number currently being scanned on the
SERIPLEX bus. An external pull-up resistor is required between the Multiplex Clock
pin and Vcc (bus Power) in order for this output to achieve a high logic state.
The Multiplex Clock signal normally rests at a high logic state. It is timed to produce
negative (high-to-low) transitions at the same time that the SERIPLEX bus Clock signal
is undergoing the negative transitions at which bus Output signals 0 through 4 are
sampled. This allows external circuitry to read Output signals 1 through 4 from the
SERIPLEX bus, and in turn to decode the current multiplex channel number.
22
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
ASIC2B Data Sheet
Absolute Maximum Ratings
ABSOLUTE MAXIMUM
RATINGS
Applied voltage (Vdd - Vss):
Power dissipation:
Operating temperature:
Storage temperature:
Maximum input voltage:
Minimum input voltage:
EEPROM programming cycles:
ELECTRICAL
SPECIFICATIONS
Unless noted otherwise, the following conditions apply to electrical specifications:
Vcc (Power Input Voltage)
•
36 VDC
Maximum 235 mW
-20 to +85 °C
-40 to +125 °C
Vdd +0.5 V
Vss - 0.5 V
1,000
Vcc between 12 and 32 V as referenced to Vss
•
Clock and Data signals at 9 V peak as referenced to Vss
•
Ambient temperature between -40 and +85 °C.
•
Clock and Data lines operate from 0 to +12 VDC with 100 kΩ buffer resistor.
Max input voltage:
Min input voltage:
Operating current draw:
30.0 VDC
9.0 VDC (Note: Internal regulator disabled below 10 VDC.)
1.3 mA typical, 2 mA max at 24 VDC, + Vdd output current and
Data Driver output current
Maximum 2 mA, + Vdd output current and Data Driver output
current
Programming current draw:
9 VDC ± 0.3 VDC
Maximum 5 mA
100 mA with 300 Ω resistor in series with Vcc input
Vdd (Regulated Output
Voltage Reference)
Voltage output:
Current output:
Short circuit current:
Clock and Data In Inputs
(Bus Interface Signals)
Clock and Data In inputs are low true and current sinking.
Max input current:
(between Vss & Vdd)
1 µA
Max input clamp current:
(beyond Vss & Vdd)
24 mA
Vin Hysteresis:
High trip point 7.50 VDC ± 10%
Low trip point 3.00 VDC ± 10%
Low-pass filter 3dB breakpoint:
225 kHz (Assume 100 kΩ 1% external series resistor)
Data Driver Output
(Bus Interface)
The Data Driver output is high true and current sourcing.
Inputs A and B
(External Input
Signals)
All external inputs are low true and current sinking.
Vin Hysteresis
Max output voltage (no load):
Max output current:
Max off-state leakage current:
Vdd
2.5 mA at 0.7 VDC
1 µA
Max input current draw:
1 µA at Vdd
Max input clamp current:
(Vin > Vss or Vin < Vdd)
24 mA
Low-pass filter breakpoint:
15 kHz at Cosc = 150 kHz
(Assume 100 kΩ 1% external series resistor)
Logic Threshold
5V
9V
Symbol
Description
Minimum
Nominal
Maximum
Vih
High trip point
3.0 VDC
3.75 VDC
4.2 VDC
Vil
Low trip point
0.95 VDC
1.25 VDC
1.4 VDC
Vih
High trip point
6.0 VDC
7.0 VDC
7.85 VDC
Vil
Low trip point
1.75 VDC
2.0 VDC
2.55 VDC
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
23
ASIC2B Data Sheet
Electrical Specifications
Bulletin No. 8310PD9601
March 1997
Outputs A, B, and C
(External Output Signals)
All external outputs are low true and driven by open-drain FETs.
Mode/Sync, Multiplex Clock,
Shift Clock In, Shift Clock
Out (Logic Outputs)
All logic outputs are low true and driven by open-drain FETs.
Max output voltage:
Max on-state sink current:
Max on-state voltage:
Max off-state leakage current:
0.7 VDC above Vdd
2.5 mA at 0.5 VDC
0.5 VDC
1 µA
Sync Detection
Sync Detection time:
10 cycles of Cosc with clock held high
Typically 67 µs at Cosc = 150 kHz
Clock Loss Detection
Clock Loss Detection time:
256 cycles of Cosc
Typically 1.7 ms at Cosc = 150 kHz
Cosc
Frequency range:
Max error:
Resistor range:
50 to 400 kHz
±15% with a 1%, 100 ppm Cosc resistor
25 to 110 kΩ
EEPROM Memory
Programming Temperature
Data retention time:
Max read/write cycles:
Programming voltage:
Erase cycle time:
Programming cycle time:
0 – 70 °C
10 years at 85 °C
1,000 cycles
15.0 – 16.5 VDC
100 – 200 msec
100 – 200 msec
Program Mode Detection
Program Mode Detection Time:
6,144 cycles of Cosc
Typically 40.5 ms at Cosc = 150 kHz
24
Max voltage:
Max continuous voltage:
Max on-state sink current:
Max on-state voltage:
Max short-circuit current:
Max off-state leakage current:
36 VDC
32 VDC
5 mA at 1.25 VDC
1.25 VDC
100 mA
1 µA
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
ASIC2B Data Sheet
Signal Timing Diagram
The timing diagram shown below depicts the general timing of ASIC2B signals in
relation to the SERIPLEX bus Clock and Data lines.
SIGNAL TIMING
DIAGRAM
Peer-to-Peer Mode
Assume
Address A = 16
5
0
1
2
3
4
Assume
Address B = 31
14 15 16 17 18
29 30 31 32 33
255
SYNC
0
1
CLOCK
MUX_C
S_C_O (to data bus)
S_C_I (from data bus)
4
DATA
OUTPUT A
(previously off)
OUTPUT B
(previously off)
1
1
I/O Sample Point
I/O Sample Point
4
3
3
INPUT A
INPUT B
MODE/SYNC
7
7
Master/Slave Mode
Assume
Address A = 16
6
0
1
2
3
4
5
6
15
16
Assume
Address B = 31
17
18
29 30
31
32
33
34 255
SYNC
0
1
BUS CLOCK
MUX_C
S_C_O (to data bus)
A
B
A
B
S_C_I (from data bus)
DATA
1
4
2
1
2
4
OUTPUT A
(previously off)
3
OUTPUT B
(previously off)
3
MODE/SYNC
7
7
Notes:
A Bus input sample point (Master/Slave Mode)
B Bus output sample point (Master/Slave Mode)
1 If input is active the data line will be ≤ 2.75 VDC during the first half of address window.
If input is not active the data line will be ≥ 8.25 VDC.
2 If an output is activated by the host the data line will be ≤ 2.7 VDC during the second
half of address window. If not activated the data line will be ≥ 8.25 VDC.
3 Outputs A & B may turn on at this point if bus fault test is passed.
4 Bus fault detection pulse—originates in host controller or clock module.
5 Clock cycle 15 to 255 depending on selected frame size in Mode 1.
6 Clock cycle 30 to 510 depending on selected frame size in Mode 2.
7 Pulse width equals approximately one Cosc cycle (normally 6.7 µs).
Figure 7: Signal Timing Diagram
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
25
ASIC2B Data Sheet
Dimensions
Bulletin No. 8310PD9601
March 1997
The ASIC2B is available in a 16-pin, narrow-body small outline package (SOIC).
Dimensions are shown in Figure 8.
DIMENSIONS
3
2
1
Top
View
H
h x 45°
End
View
C
A2
16
E
See Detail A
Bottom
View
Parting
Line
Detail A
∝
F
L
B
Side
View
A
D
A1
Seating
Plane
Figure 8: SOIC Dimensions
Table 4:
Symbol
26
SOIC Reference Dimensions1
Common Dimensions — in (mm)
Min
Nom
Max
A
0.061 (1.5494)
0.064 (1.6256)
0.068 (1.7272)
A1
0.004 (0.1016)
0.006 (0.1524)
0.0098 (0.24892)
A2
0.055 (1.397)
0.058 (1.4732)
0.061 (1.5494)
B
0.0138 (0.3505)
0.016 (0.4064)
0.0192 (0.48768)
C
0.0075 (0.1905)
0.008 (0.2032)
0.0098 (0.24892)
D
0.386 (9.8044)
0.391 (9.9314)
0.393 (9.9822)
E
0.150 (3.81)
0.155 (3.937)
0.157 (3.9878)
F
—
0.050 (1.27)
—
H
0.230 (5.842)
0.236 (5.9944)
0.244 (6.1976)
h
0.010 (0.254)
0.013 (0.3302)
0.016 (0.4064)
∝
0°
5°
8°
Note
2
3
1
Dimensioning and tolerances per ANSI.Y14.5M—1982.
2
Reference datums “D” and “E” do not include mold flash or protrusions, but do include mold mismatch and are
measured at the mold parting line. Mold flash or protrusions shall not exceed 0.006 in. (0.1524 mm) per side.
3
Formed leads shall be planar with respect to one another within 0.003 in. (0.0762 mm) at seating plane.
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
Bulletin No. 8310PD9601
March 1997
ASIC2B Data Sheet
Notes
NOTES
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved
27
ASIC2B Data Sheet
Bulletin No. 8310PD9601
March 1997
SERIPLEX is a registered trademark of Square D Company.
This product contains SERIPLEX technology and conforms to the latest version of the SERIPLEX standard.
Electrical equipment should be serviced only by qualified electrical maintenance personnel. No responsibility is
assumed by Square D for any consequences arising out of the use of this material.
For more information regarding the use of SERIPLEX technology or to incorporate the ASIC in your products, contact
the SERIPLEX Technology Organization, Inc., (STO) at 1-800-SPLXINC (1-800-775-9462).
28
© 1996 Seriplex Technology Organization, Inc. All Rights Reserved