US 20020121995A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2002/0121995 A1 (43) Pub. Date: Tabler (54) APPARATUS AND METHOD FOR DIGITAL TO ANALOG CONVERSION Sep. 5, 2002 Publication Classi?cation (51) Int. Cl.7 . (52) US. Cl. ............................................................ .. 341/145 H03M 1/66 (75) Inventor: John A. Tabler, San Jose, CA (US) (57) ABSTRACT Correspondence Address: FERNANDEZ & ASSOCIATES LLP _ _ _ _ _ 1047 EL CAMINO REAL The invention includes a segmented digital-to-analog con SUITE 201 verter (DAC) processing an N-bit input digital signal. A ?rst segrnent converter processes the most signi?cant bits and subsequent segrnent converters process the least signi?cant bits of the N-bit input digital signal. The ?rst segment converter includes ballast resistors that nullify the effect of MENLO PARK, CA 94025 (73) Assignee; SUMMIT MICROELECTRONICS, [NC any imbalance of the resistance of the ?rst segrnent DAC versus the sum of the resistances in the remaining segment (21) App1_ NO_; 09/752,226 DACs. The ?rst segment may be a 2, 4, 6, 8 or higher bit (22) Filed: Dec. 29, 2000 larly be 2, 4, 6, 8, or higher bit DACs. DAC While the second or subsequent segrnents rnay sirni 74 72 " RH] SPST31 ‘ L1 N91 4 /‘ \ QPDT“ ‘ B3 L-*'—J > R1 RD/UNB sPsT21 RTAP3 C3g/l/wt/wjmz ./‘ I NC4 N 3 L—_" JNCZO spsrao i“ NC?” ! / SPDT2 RDUM2 :50, ~ Ncs Nc11 sPsT20 A/w/ 'NC12 . B2 RTAP2 J i \ |—' SPSTlI R3 j 7,833“ Q B1, i i RDUM. ‘AA/V‘ ./° N07 l—l NCM N018 I N“ /' N313 RTAPI s1>sr01 i 101s R4 i NC8 : '—' VOH SPSTlO / 1 NC9 SPSTOO G1 NC16 [7! '—' RlJOW N010 VOL ; Patent Application Publication Sep. 5, 2002 Sheet 1 0f 4 VOUT 68 VOH 56 RHI 5O RSHI 65 54 First DAC D-LSB 60 ———-> Segment 64 Second DAC Segment DB-LSB 62 —————> RLOW 52 US 2002/0121995 A1 VOL 58 ———————> D-MSB 70 FIGURE 1 RSLOW 66 Patent Application Publication Sep. 5, 2002 Sheet 3 0f 4 US 2002/0121995 A1 ‘r ‘r o: o: M.mgb w Sep. 5, 2002 US 2002/0121995 A1 APPARATUS AND METHOD FOR DIGITAL TO ANALOG CONVERSION subsequent segments may be 2, 4, 6, 8, or higher bit DACs and the principles and approach of the architecture Would apply. BACKGROUND OF INVENTION [0001] BRIEF DESCRIPTION OF DRAWINGS 1. Field of Invention [0010] FIG. 1 is general schematic diagram of a seg [0002] Invention relates to digital-to-analog converters (DACs) and more particularly to digital-to-analog convert ers With cascading segments. mented digital-to-analog converter according to one embodiment of the present invention. [0003] 2. Description of Related Art [0011] FIG. 2 is a more detailed circuit diagram of a ?rst segment of a digital-to-analog converter according to one [0004] DACs are presently available to produce an analog voltage output by selectively tapping a resistor string con nected betWeen the high voltage reference and ground or the embodiment of the present invention. loW voltage reference. HoWever, once the resolution of the DAC is over siX or eight bits, the number of components [0012] FIG. 3 is a How chart of the process in the digital-to-analog conversion according to one embodiment of the present invention. required is fairly high. For example, a 10-bit DAC of this topology Would require 1024 resistors, 1024 sWitches, and 1024 logic drive lines. A DAC design that does not require [0013] FIG. 4 is an architectural diagram of a dual 10-Bit non-volatile digital-to-analog converter according to one embodiment of the present invention. the high number of elements is desirable as the silicon area needed for the circuit Would be reduced Which in turn Would DETAILED DESCRIPTION OF PREFERRED loWer manufacturing costs. [0005] Several DAC architectures have concentrated on cascading segments Where a ?rst segment includes a resistor string that produces a ?rst voltage corresponding to the most signi?cant bits (MSB) and the second segment includes a resistor string that produces a voltage corresponding to the least signi?cant bits (LSB). The second segment uses the output voltage of the ?rst segment of the DAC such that the second segment effectively interpolates the selected ?rst segment voltage to correspond With the LSBs. One such device is described in US. Pat. No. 3,997,892. [0006] Other prior art approaches for cascaded segment converters suffer from linearity problems and other perfor mance characteristics When applied to higher resolution DACs. Thus, there is a need for a DAC architecture that reduces the number of circuit components While achieving satisfactory linearity characteristics. SUMMARY OF INVENTION [0007] Invention resides in a cascading DAC design that achieves the reduction of number of circuit components and maintains good performance characteristics. The present invention includes a segmented DAC architecture Where the ?rst segment DAC processes N1 most signi?cant bits of an N-Bit DAC and the subsequent segment DACs process the EMBODIMENT(S) [0014] FIG. 1 is general schematic diagram of a voltage output segmented digital-to-analog converter (DAC) according to one embodiment of the present invention. A high voltage reference RHI 50 and a loW voltage reference RLOW 52 are input to the ?rst DAC segment 54. The most signi?cant bits (MSB) of the input signal is selected by a decoder, (not shoWn), and comes in through D-MSB 70 into the ?rst DAC segment 54. D-MSB 70 is used by ?rst DAC segment 54 to activate the sWitches based on the values of the MSB. A high voltage output VOH 56 and a loW voltage output VOL 58 comes out of the ?rst DAC segment 54 and connect into the high input reference voltage RSHI 65 and the loW input reference voltage RSLOW 66, respectively, of the second DAC segment 64. It should be noted that this segmented DAC architecture does not require a buffer ampli?er betWeen the ?rst DAC segment and subsequent DAC segments. The least signi?cant bits (LSB) of the input digital signal selected by the decoder becomes digital input to the second DAC segment 64 as input D-LSB 60 and DB-LSB 62. D-LSB 60 and DB-LSB 62 are used by the second DAC segment 64 to activate the sWitches based on the values of the LSB. The output voltage of the DAC is VOUT 68, Which may go through a buffer ampli?er, (not shoWn), before being used by an application. balance of the bits, (N—N1), of the N-bit input digital signal. [0015] The DAC architecture includes ballast resistors that nullify DAC segment processing of a tWo-segment DAC according the effect of any imbalance of the resistance on the ?rst segment DAC versus the sum of the resistance in the to one embodiment of the present invention. This diagram is for the ?rst segment of a 10-Bit segmented DAC, the ?rst remaining segment DACs. segment being a 2-Bit DAC processing the MSB coupled to a second segment 8-Bit DAC processing the LSB. The ?rst segment 2-Bit DAC processes bits 8 and 9 of the input [0008] One embodiment involves a tWo-segment cascad ing design for a 10-Bit DAC Where the ?rst segment processes the tWo MSBs and the second segment processes the eight LSBs. In one application of the present invention, tWo 10-Bit DACs, With their associated circuits comprising a 10-Bit volatile data latch, a 10-Bit nonvolatile data regis ter, and a unity gain operational ampli?er, are integrated With a con?guration register and a standard tWo-Wire serial interface. [0009] The present invention may have a ?rst segment that is a 2, 4, 6, 8 or higher bit DAC While the second or FIG. 2 is a more detailed circuit diagram of the ?rst digital signal and comprises a string of resistors, tap points for the output high voltage VOH, tap points for the output loW voltage VOL, tWo sWitching netWorks, 72 and 78, and three ballast resistors, RDUMl, RDUM2, and RDUM3, for rectifying a mismatch betWeen the resistance of the ?rst segment DAC versus the resistance of the second segment DAC. The tWo sWitching netWorks are the sWitching net Work 72 controlling a set of single-pole-double-throW sWitches determining the path for the ballast resistors and the sWitching netWork 74 controlling single-pole-single Sep. 5, 2002 US 2002/0121995 A1 throw switches determining the paths for the taps of the output high voltage VOH and for the taps of the output loW voltage VOL. The series string of resistors that decrements the reference high voltage RHI to the output high voltage VOH and output loW voltage VOL consists of R1, R2, R3, and R4, With equal resistance values. The ballast resistors, consisting of RDUM1, RDUM2, and RDUM3, have equal resistance values. The resistance value of each of the ballast resistors RDUM1, RDUM2, or RDUM3 is equal to the sum of the resistors in the second segment DAC, expressed by the folloWing formula: RDUML1=RDUM2=RDUM3=EResistance second segment DAC. of the [0016] For eXample, in the 8-Bit second segment DAC, each of the ballast resistors Would be equal to the sum of the resistance of the 256 resistors of the 8-Bit second segment DAC. In practice, the value of each of the ballast resistors is slightly higher to account for the small circuit connection resistance encountered in the second segment DAC. Table 1 traces the circuit path for the output high voltage VOH, output loW voltage VOL, and the ballast resistors for MSB bits (8,9) values of (1,1), (1,0), (0,1), and (0,0). For eXample, When the input digital value the MSB bits (8,9) is (1, 1), the tap for VOH is created by sWitching netWork 74 closing single-pole-single-throW sWitch SPST31 and the tap for tapped and relayed to the neXt segment DAC, repeating the process until the output high and loW signal is input into the LSB segment DAC 130. The voltage output from the LSB segment DAC is tapped for further processing 140. [0021] FIG. 4 is an architectural diagram of a serial input, voltage output dual 10-Bit DAC according to one embodi ment of the present invention. The 10-Bit DAC consists of a 2-Bit DAC segment processing the MSB, (bits 8 and 9), coupled to an 8-Bit DAC processing the LSB, (bits 0-7), of the input 10-bit digital signal. The design of the 10-Bit DAC includes a serial interface and control logic 20 for initial processing of input data for the con?guration register 32, for the non-volatile registers 26, 28, and for processing the input 10-bit digital signal. The serial interface and control logic 20 is an industry standard 2-Wire serial interface With coupling for a serial clock 12 and serial data in/out 14. The top 10-Bit DAC 30 has a 10-Bit nonvolatile register 22, a 10-Bit volatile control register 26, and a buffer ampli?er 36. The bottom 10-Bit DAC 34 has a 10-Bit nonvolatile register 24, a 10-Bit volatile control register 28, and a buffer ampli?er 38. The con?guration register 32 is programmable to set the poWer-on options to recall a full-scale value, a Zero scale value, a mid-scale value, or a nonvolatile register value. VOL is created by sWitching netWork 74 closing the single pole-single-throW sWitch SPST30. The output loW voltage VOL is tapped after the signal passes through the series resistor R1. Similarly, When the input digital value of MSB bits (8,9) is (1,1), the circuit path for the ballast resistors is determined by sWitch netWork 72 activating single-pole volatile register that holds the current digital value. In double-throW sWitches SPDT1, SPDT2, and SPDT3 as listed in Table 1. by the serial interface and control logic 20; commanded to [0017] The output voltage of the 10-bit DAC is calculated by the folloWing formula: Each of the 10-Bit DACs has the 10-Bit nonvolatile register that can hold a value that can be recalled Whenever the device is poWered on, based on the setting of the con?gu ration register 32. Each of the 10-Bit DACs has the 10-Bit addition, the 10-Bit volatile register can be set to any value load the poWer-on Zero scale, mid-scale, or full scale value; or commanded to recall a preset value stored in the 10-Bit nonvolatile register. The high and loW reference voltages for the top 10-Bit DAC are labeled as VREFH 24 and VREFL 25 [0018] Where VOUT is the output voltage of the entire DAC, RHI is the high reference voltage, RLOW is the loW reference voltage, N is the number of bits of the input digital signal, and DINPUT is the decimal value of the input digital signal. For example, if the decimal value of the input digital signal of in a 10-Bit DAC is 25, (binary 00000 11001), and (RHI-RLOW) is equal to 5.0000 volts, then VOUT is equal to 0.1221 volts. respectively, While the output voltage is VOUT26. The high and loW reference voltages for the bottom 10-Bit DAC are labeled as VREFHlll and VREFL110 respectively, While the output voltage is VOUT19. The dual 10-Bit DACs can be operated independently or in tandem. [0022] Other embodiments of the present invention includes other con?gurations Where the ?rst segment DAC processes N1 most signi?cant bits of an N-Bit DAC and the [0019] The ?rst DAC segment can be a 2, 4, 6, 8, 10 or higher MSB segment DAC. Similarly, the second segment subsequent segment DACs process the balance of the bits, (N—N1), of the N-bit input digital signal. The ballast resistors DAC can be a 2, 4, 6, 8, 10, or higher LSB segment DAC of any design and the principles and architecture of the present invention Would still apply. Would function in the same manner to nullify the effect of any imbalance of the resistance on ?rst segment DAC versus [0020] FIG. 3 is a How chart of the process for an N-bit DAC according to one embodiment of the present invention. [0023] Foregoing described embodiments of the invention The N-bit input digital signal is decoded and the decoded output signals are routed to the appropriate segment DAC sWitching netWorks 100. The sWitches of the MSB segment the sum of the resistance in the remaining segment DACs. are provided as illustrations and descriptions. They are not intended to limit the invention to precise form described. In particular, it is contemplated that functional implementation DAC are activated based on the value of the decoded MSB of invention described herein may be implemented equiva of the N-Bit input digital signal 110. Concurrently, sWitches lently in hardWare, softWare, ?rmWare, and/or other avail of the neXt segment DAC are activated based on the value able functional components or building blocks. of the decoded neXt set of bits of the N-Bit input digital signal 111. This process is repeated until the sWitches of the LSB segment DAC are activated based on the value of the decoded LSB of the N-Bit input digital signal 119. The output high and loW signal from the MSB segment DAC is [0024] Other variations and embodiments are possible in light of above teachings, and it is thus intended that the scope of invention not be limited by this Detailed Descrip tion, but rather by claims folloWing. Sep. 5, 2002 US 2002/0121995 A1 ment converter connect to the second input high TABLE 1 reference voltage and the second input low reference voltage respectively of the second digital-to-analog PATH OF VOLTAGE OUTPUT HIGH, VOLTAGE OUTPUT LOW & BALLAST RESISTORS FOR THE FIRST SEGMENT CONVERTER INPUT DIGITAL BIT (9, s) VALUES PATH SWITCHES, TAPS, RESISTORS" 1, 1 VOH RHI, Nc1 sPsT31, Nc4, NC7, NC8, VOH voL RHI, L1, Nc1, R1, RTAP3, sPsT30, NCS, NC6, NC9, Nc10, voL BALLAST RHI, L1, Nc1, R1, RTAP3, Nc2, RDUM3, sPDT3, B3, NC17, Nc11, Nc12, RDUM2, SPDTZ, c2, NC15, RDUMl, SPDT1, c1, G1, RLoW 1, 0 VOH RHI, L1, Nc1, R1, RTAP3, sPsT21, Nc4, voL NC7, NC8, VOH RHI, L1, Nc1, R1, RTAP3, Nc2, Nc20, R2, BALLAST 0, 1 VOH voL VOH BALLAST segment converter is an 8-Bit digital-to-analog converter. 3. The segmented digital-to-analog converter of claim 1, wherein the input N-Bit digital signal is a 12-bit digital Nc10, voL segment converter is an 8-Bit digital-to-analog converter. RHI, L1, c3, sPDT3, RDUM3, Nc2, Nc20, R2, Nc11, Nc12, RDUM2, sPDT2, c2, NC18, RDUM1, SPDT1, c1, G1, RLoW RHI, L1, Nc1, R1, RTAP3, Nc2, Nc20, R2, Nc11, Nc12, RTAP2, Nc13, SPST11, NC7, NC8, VOH RHI, L1, Nc1, R1, RTAP3, Nc2, Nc20, R2, sPsT10, NC9, NC10, voL RHI, L1, c3, sPDT3, RDUM3, B2, sPDT2, Nc2, Nc20, RDUM2, Nc12, RTAP2, R3, Nc14, NC18, RDUM1, SPDT1, c1, G1, RHI, L1, Nc1, R1, RTAP3, Nc2, Nc20, R2, NC11, Nc12, RTAP2, R3, NC14, RTAP1, voL to-analog segment converter. 2. The segmented digital-to-analog converter of claim 1, wherein the input N-Bit digital signal is a 10-bit digital signal, the ?rst digital-to-analog segment converter is a 2-Bit digital-to-analog converter and the second digital-to-analog signal, the ?rst digital-to-analog segment converter is a 4-Bit digital-to-analog converter and the second digital-to-analog RLoW 0, 0 equal to the sum of the resistance values of the second set of series resistors of the second digital Nc12, RTAP2, Nc13, sPsT20, NC6, NC9, Nc12, RTAP2, R3, RTAP1, NC15, BALLAST segment converter and each ballast resistor of the plurality of ballast resistors of the ?rst digital-to analog segment converter having a resistance value NC15, SPSTOl, NCS, VOH RHI, L1, Nc1, R1, RTAP3, Nc2, Nc20, R2, Nc11, Nc12, RTAP2, R3, Nc14, RTAP1, R4, NC16, SPSTOO, Nc10, voL RHI, L1, Nc3, sPDT3, RDUM3, B2, sPDT2, RDUM2, Nc12/Nc11, NC17, B1, SPDT1, RDUMl, NC18, R4, NC16, G1, RLOW *Origination points, resistors, and termination points are in bold charac ters. What is claimed is: 1. A segmented digital-to-analog converter for processing an N-Bit input digital signal comprising: a decoder for decoding an input N-bit digital signal into a most-signi?cant-bits set and a least-signi?cant-bits set; a ?rst digital-to-analog segment converter including a ?rst set of series resistors, a plurality of ballast resistors, a ?rst set of switching networks for activating the appro priate switches corresponding to the value of the most signi?cant-bits set, and a ?rst voltage output high and a ?rst voltage output low; a second digital-to-analog segment converter including a second set of series resistors, a second set of switching networks for activating the appropriate switches corre sponding to the value of the least-signi?cant-bits set, a second input high reference voltage and a second input low reference voltage, and a second voltage output; and a high reference voltage source and a low reference voltage source; wherein the ?rst voltage output high and the ?rst voltage output low of the ?rst digital-to-analog seg 4. The segmented digital-to-analog converter of claim 1, wherein there is no buffer ampli?er between the ?rst digital to-analog segment converter and the second digital-to-ana log segment converter. 5. A method of segmented conversion of an N-Bit digital signal to an analog signal, the method comprising: decoding an input N-Bit digital signal into a most-sig ni?cant-bits set and a least-signi?cant-bits set; routing the most-signi?cant-bits set into a ?rst digital-to analog segment converter and the least-signi?cant-bits set to a second digital-to-analog segment converter; activating a ?rst set of switches of a switching network of the ?rst digital-to-analog segment converter, the ?rst set of switches being activated corresponding to the value of the most-signi?cant-bits set of the input N-Bit digital signal; activating a second set of switches of a switching network of the second digital-to-analog segment converter, the second set of switches being activated corresponding to the value of the least-signi?cant-bits set of the input N-Bit digital signal; tapping an output analog signal at the output voltage tap point of the second digital-to-analog segment con verter; wherein the ?rst digital-to-analog segment converter includes a plurality of ballast resistors, each ballast resistor of the plurality of ballast resistors having a resistance value equaling the sum of the resistance values of all series resistors in the second digital-to analog segment converter and the ?rst digital-to analog segment converter having a ?rst high voltage output and a ?rst low voltage output connecting to a second input high reference voltage and a second input low reference voltage of the second digital-to analog segment converter, respectively. 6. The segmented digital-to-analog conversion method of claim 4, wherein the ?rst digital-to-analog segment con verter is a 2-Bit digital-to-analog converter and the second digital-to-analog segment converter is an 8-Bit digital-to analog converter. 7. The segmented digital-to-analog conversion method of claim 4, wherein the ?rst digital-to-analog segment con Sep. 5, 2002 US 2002/0121995 A1 verter is a 4-Bit digital-to-analog converter and the second activating the appropriate sWitches corresponding to digital-to-analog segment converter is an 8-Bit digital-to analog converter. 8. The segmented digital-to-analog conversion method of claim 4, Wherein there is no buffer ampli?er betWeen the ?rst digital-to-analog segment converter and the second digital the value of the least-signi?cant-bits set, a second to-analog segment converter. 9. A dual cascading digital-to-analog converter for pro cessing an N-bit digital signal comprising: a ?rst cascading digital-to-analog converter including a ?rst cascading decoder for decoding an input N-bit digital signal into a most-signi?cant-bits set and a least-signi?cant-bits set, a ?rst cascading primary seg ment converter, and a ?rst cascading ?nal segment converter; the ?rst cascading primary segment con verter including a ?rst cascading primary segment set of series resistors, a plurality of ?rst cascading ballast resistors, a ?rst cascading primary segment set of cascading ?nal segment input high reference voltage and a second cascading ?nal segment input loW refer ence voltage, and a second cascading ?nal segment voltage output; the second cascading primary segment voltage output high and the second cascading primary segment voltage output loW of the second cascading primary segment converter connecting to the second cascading ?nal segment input high reference voltage and the second cascading ?nal segment input loW reference voltage respectively of the second cascading ?nal segment converter and each ballast resistor of the plurality of second cascading ballast resistors of the second cascading primary segment converter having a resistance value equal to the sum of the resistance sWitching netWorks for activating the appropriate values of the second cascading ?nal segment set of series resistors of the second cascading ?nal segment converter; sWitches corresponding to the value of the most-sig ni?cant-bits set, and a ?rst cascading primary segment an interface and control logic unit for initial processing of input data for the con?guration register, for the non voltage output high and a ?rst cascading primary segment voltage output loW; the ?rst cascading ?nal volatile registers, and for the input N-bit digital signal, segment converter including a ?rst cascading ?nal segment set of series resistors, a ?rst cascading ?nal segment set of sWitching netWorks for activating the appropriate sWitches corresponding to the value of the least-signi?cant-bits set, a ?rst cascading ?nal segment input high reference voltage and a ?rst cascading ?nal segment input loW reference voltage, and a ?rst cas cading ?nal segment voltage output; the ?rst cascading primary segment voltage output high and the ?rst cascading primary segment voltage output loW of the ?rst cascading primary segment converter connecting to the ?rst cascading ?nal segment input high reference voltage and the ?rst cascading ?nal segment input loW reference voltage respectively of the ?rst cascading ?nal segment converter and each ballast resistor of the plurality of ?rst cascading ballast resistors of the ?rst cascading primary segment converter having a resis tance value equal to the sum of the resistance values of the ?rst cascading ?nal segment set of series resistors of the ?rst cascading ?nal segment converter; a second cascading digital-to-analog converter including a second cascading decoder for decoding the input N-bit digital signal into a most-signi?cant-bits set and a least-signi?cant-bits set, a second cascading primary segment converter, and a second cascading ?nal seg ment converter; the second cascading primary segment converter including a second cascading primary seg ment set of series resistors, a plurality of second cascading ballast resistors, a second cascading primary segment set of sWitching netWorks for activating the appropriate sWitches corresponding to the value of the most-signi?cant-bits set, and a second cascading pri mary segment voltage output high and a second cas cading primary segment voltage output loW; the second cascading ?nal segment converter including a second cascading ?nal segment set of series resistors, a second cascading ?nal segment set of sWitching netWorks for a serial data connection coupled to the interface and control logic unit; a serial clock connection coupled to the interface and control logic unit; a ?rst cascading nonvolatile register for storing a ?rst cascading value that can be recalled and a second cascading nonvolatile register for storing a second cascading value that can be recalled; a ?rst cascading volatile register for holding the current digital value or receiving a value as determined by the serial interface and control logic for use in the ?rst cascading digital-to-analog converter and a second cascading volatile register for holding the current digi tal value or receiving a value as determined by the serial interface and control logic for use in the second cascading digital-to-analog converter; a con?guration register for setting options for the dual cascading digital-to-analog converter, including poWer on options; Wherein the input N-Bit digital signal is processed by either the ?rst cascading digital-to-analog converter creating the ?rst cascading ?nal segment voltage output or by the second cascading digital-to-analog converter creating the second cascading ?nal seg ment voltage output. 10. The dual cascading digital-to-analog converter of claim 8, Wherein the poWer-on options comprise recalling a full scale poWer-on value, recalling a Zero scale poWer-on value, recalling a mid-scale poWer-on value, or recalling the ?rst cascading nonvolatile register value if the ?rst cascad ing digital-to-analog converter is being used or the second cascading nonvolatile register value if the second cascading digital-to-analog converter is being used.