International Journal of Electronics and Computer Science Engineering
Available Online at www.ijecse.org
1640
ISSN- 2277-1956
Design of Current steering DAC using 250nm CMOS
Technology
2
3
Vineet Tiwari 1, Prof.Sanjeev Ranjan ,Dr.(Prof) Vijaynath
12
Department of Electronics and Telecommunication Engineering
12
Disha Institute of Management & Technology,Raipur,India
3
Department of Electronics & Communication,Bit Mesra,Ranchi,India
1
vineettiwaris@gmail.com,2sanjeev.ranjan@dishamail.com,3vijaynath@bitmesra.ac.in
Abstract- To build a digital to analog converter, that only receives digital signal that can only receives digital signal and
produces only analog signal. A converter in which digital input signals are changed to essentially proportional analog
signals. Abbreviated DAC a device for converting information in the forms of combination of discrete(usually binary)
states or signal to information in the form of combinations of discrete(usually binary) states or signal to information in
the form of value or magnitude of some characteristics of signal, in relation to standard or reference signal. Digital-toanalog (D/A) converters (sometimes called DACs) are used to present the results of digital computation, storage, or
transmission, typically for graphical display or for the control of devices that operate with continuously varying
quantities. D/A converter circuits are also used in the design of analog-to-digital converters that employ feedback
techniques, such as successive-approximation and counter-comparator types. In such applications, the D/A converter may
not necessarily appear as a separately identifiable entity. The fundamental circuit of most D/A converters involves a
voltage or current reference; a resistive “ladder network” that derives weighted currents or voltages, usually as discrete
fractions of the reference; and a set of switches, operated by the digital input, that determines which currents or voltages
will be summed to constitute the output. The output of the D/A converter is proportional to the product of the digital
input value and the reference. In many applications, the reference is fixed, and the output bears a fixed proportion to the
digital input. In other applications, the reference, as well as the digital input, can vary; a D/A converter that is used in
these applications is thus called a multiplying D/A converter. It is principally used for imparting a digitally controlled
scale factor, or “gain,” to an analog input signal applied at the reference terminal. Analog to digital converter performs
the reverse operation. It has many era of operations in audio and Video form and whiffletree electromagnetic device uses
DAC linkage in typewriter. It describes the 3.3 volt, 65 MHz 8 bit CMOS digital to analog converter, includes two stage
current cell matrix. This paper describes a 1v CMOS 8 bit DAC with two stage current cell matrix architecture which
consists of 4 MSB and 4 LSB current matrix stage. The symmetric two stage current cell matrix architecture allows the
designed DAC to reduce not only the complexity of decoding logic, but also the no of high swing current mirrors. The
designed DAC with a by 90 nm nwell CMOS standard process. The experiment is based on settling time, Integrity, or
non linearity. The designed DAC is fully operational for power supply down to 1 volt such that DAC is suitable for low
voltage and low power applications.
Keywords— current cell matrix, DAC, high swing cascade current mirror, low power, current steering DAC.
I. INTRODUCTION
As VLSI is more progressing as day by days. Many different types of mixes signal circuits have been implemented
on a single chip is used including data conversion techniques. Recently many high speed utilizing a single stage
current cell matrix. The DAC architecture with a single stage is able to achieve a fast settling time. It requires a
complex logic and because of large power dissipation and large area taking, due to that other option for high speed
dac is using resistor string with voltage follower drives low resistances load. But it also lags with high power
dissipation and large area. Thus for low power and small area taking DAC uses a simplified circuit having 4 MSB
current cell matrix and 4 LSB current cell matrix. It is simple circuit uses less number of current source as compared
to single stage matrix DAC. High speed segmented converter architecture is shown below, binary weighting is used.
In figure below as a combination of 3 bit segmented current network with a 6 bit Binary weighted network is shown.
In this segmented current network part all transistors are equal. The size of transistors concerning current weighting
must equal to 64I.With
I = (VREF/R1)
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Design of Current steering DAC using 250nm CMOS Technology
Figure 1. Segmented architecture
Segmentation is more needed when minimize glitches and nonlinearity. The decoding to drive 256 current network
consists of 4 bit (16 bit elements)row decoder combined with 4 bit(16 elements)column decoder. For time delay 2
LSB use extra decoder. Clock buffer is required for good timing accuracy. Segmented architecture of one quarter
8x8 matrixes is shown. There are two types of cells dummy cells and active cells.
Figure 2. Matrix architecture
Current cell:-The current cell consists of Digital and analog part. The digital part consists of the decoding logic
with the clocked pass transistors to control switches and analog part consisting of cascaded current sources with the
differential switch pair M1 and M2.The output current of all cells are summed and total current will be supplied to
load resistors R1 and R2 converting into the output voltage.
DAC architecture with two stage current cell matrix:-The proposed circuit diagram shown in figure, input digital
bits are decoded by row decoder and column decoder is used to select any column element. In this DAC current
source is selected at left circuitry by MSB inputs according to row and column operation .The decoded data
(R2i,R2i+1,Cj) pass through the matrix switching decoder to generate VO,i,j. The Vo,i,j signal produced by the matrix
circuit generates two current components IOUT,i,j and Iout,I,j.
In order to a number of current cells and complexity of design, the two stage current cell matrix is
Referred. The resultant output current IOUT and resultant output voltage VOUT is calculated by equation (1) and(3).
Where IMSB,ILSB and bi are MSB current and LSB current and ith input digital bit respectively.
I OUT =IMSB (23b7 +22b6 +21b5 +20b4 ) + ILBS (23b3 +22b2 +21b1 +20b0 )
(1)
I MSB= 16ILBS
(2)
Where IMSB,ILSB and bi are MSB current and LSB current and ith input digital bit respectively.
VOUT = VOUT RLOAD, where RLOAD is the load resistance.
Proposed DAC requires a simple decoding logic without latch circuit to synchronize time delays .for generating
identical time delay, latches are not required. The output voltage VO,i,j of the matrix switching decoder as in figure is
given by
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II.PROPERTIES OF DAC ARCHITECTURE
The importance of Digital- to-Analog converters (DACs) is a direct consequence of the utilization of digital
electronics. In many applications, digital circuits can only be utilized providing an appropriate translation i.e.
conversion, of their digital output information into the analog world. The function of this translation is realized
through DACs.. Depending on the specific applications, there are various specifications that a D/A conversion
should satisfy. These specifications can be realized through different ways, i.e. algorithms. These algorithms can be
implemented through various circuit solutions, e.g. current-based circuits, resistor-based circuits, capacitor-based
circuits.DACs are the interface between the analog and digital worlds in electrical engineering. The progress
achieved during the last decade in computing and data processing is closely related to these chips. Four major DAC
topologies can be distinguished: Binary Weighted DACs: These DACs consist of either current sources or resistors
for each bit. These elements are connected to a summing point which provides the output,
A. R2R Ladder DAC This DAC consist of a structure of resistor values which can be closely matched this topology
is binary weighted and can provide a higher resolution compared to its purely binary weighted counterpart.
B. Delta-Sigma DAC: This DAC are relatively new and they rely on Pulse density and noise shaping techniques
which allow for the use of a lower resolution DAC in the forward path (usually 1 bit).
C .Segmented DAC: This DAC are a hybrid between the binary Weighted and the thermometer decoded topologies.
This mix proved to be the fastest and most precise topology, at the expense of die area.
III FUNCTIONALITY AND SPECIFICATIONS
Digital-to-Analog Converters (DACs) implement a Digital-to-Analog (D/ A) con-version function, see Fig.1.1. The
arguments of this function are digital data, reference clock and reference amplitude (unit) .The output of the D/A
function is the DAC analog output signal. The input signal is discrete in time and quantized in amplitude, coded in
digital bits. The time-reference for the DAC is provided by its input clock signal. In most cases, the DACs are
synchronized, requiring a separate clock input. However, there are some cases of asynchronous DACs, which
interpret the time-reference through the change of the input digital data. In both cases, the output analog signal is
continuous in time with quantized amplitude. The quantization of the output signal amplitude depends on the
resolution of the digital input signal and that of the DAC. The D/A function can also be considered as a translation
of the abstract level of digital information to concrete analog entities, such as currents, voltages, and power. Such a
translation implies an analog characterization of the output of the DAC.
A. Static Characterization For a static characterization, the main representation of the D/A function is given by the D/A transfer
characteristic. Figure.1.2 illustrates a D/A transfer characteristic which is derived from real test-chip measurements
with magnified non-linearity by a factor of 150. The plot provides the static relation between the DAC input codes
(x axis) and the DAC output analog value (y axis, representing the DAC differential output voltage). The x axis is
discrete and is only defined around the possible digital input codes, represented as bins in a plot. The number of bins
is usually determined by the DAC resolution. The example of Fig. 1.2 shows a 12 bit DAC. The y axis is
continuous. The maximal value of the D/A function on the y axis represents the DAC full-scale (FS) range.
Figure 3 the DAC as black box: input-to-output transformation
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Figure 4.Three D/A functions for a DAC, as designed (straight line), empirical ideally linear
(Dashed line), and empirical (non-linear graph, derived from measurements with
Non-linearity magnified by a factor of 150)
The difference between the empirical ideal linear line and the empirical D/A transfer characteristic shows
the DAC non-linearity. For a proper reading of the DAC non-linearity, usually it is normalized to the LSB step of
the DAC output. In such a way the DAC INL (Integrated Non-Linearity), shown in Fig. 4, is defined. The straight
line in Fig. 4 is the nominally expected D/A transfer characteristic. It describes the ideal linear relation between the
digital input and analog output. Several specifications can be defined, e.g. offset, gain, FS range. The non-linear
graph is the actual, e.g. measured, D/A transfer characteristic. For the example of Fig. 4, it is based on real
measurement results of a 12 bit DAC with a magnified non-linearity by a factor of 150. The offset, gain and FS
specification need to be defined based on the real measurement data. There are a number of ways to define these
specifications. These depend on the way the empirical linear equivalent of the actual D/A transfer characteristic is
defined. Without loss of generality, in this book the line connecting the initial and final points of the actual D/A
transfer characteristic is used.
LSB step of the DAC output. In such a way the DAC INL (Integrated Non-Linearity), shown in Fig. 5, is
used.
Figure 5.12bit DAC INL
B. DAC DNL The evaluation of the INL usually includes two main properties: the global shape of
The graph and its deviation from the straight line. The shape of the graph indicates the dominant order of the DAC
non-linearity. For example, the shape shown in Fig.5would suggests a strong second-order non-linearity. The
deviation from the straight line indicates how strong the non-linearity is and hence how linear the DAC is. For
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example, the deviation shown in Fig.5 is about−500 LSB, which suggests a linearity that is 10 bit less than the
resolution, i.e. 2 bit DAC linearity.
For many DAC applications, e.g. control and self-calibration as shown further in the book, the local
behavior of the INL graph is important, i.e. the linearity between successive DAC code transitions. This can be
characterized by the DAC DNL (Differential-Non-Linearity). The DNL characterizes the non-linearity for each LSB
step. The DNL at code k equals the difference between the two code-consecutive INL values at codes k + 1 and k:
DNLk = INLk+1 − INLk
(1.1)
Figure6 shows the corresponding DNL characteristic of the D/A transfer characteristic of Fig.4 and the INL
characteristic of Fig 5. The DAC DNL is usually used to indicate DAC local errors. For example a large deviation
for a given DAC analog unit is directly indicated as a spike in the graph. Another commonly used criterion is the
DAC monotonicity. A DAC is monotonic if DNLk −1 for all k.
Figure6.12 bit DAC DNL
The opposite, the non-monotonicity, is a strongly non-linear condition of the D/A transfer characteristic featuring a
local gain with opposite sign. That is to say that an input digital code x1 x2 is converted to DAC output y(x1)
y(x2), while the overall DAC gain is positive.
C.Dynamic Characterization For the dynamic DAC characterization, many figures are widely used, depending on the DAC application
and its requirements. For example, audio and video applications require strict specifications for glitch energy
between the code transitions; radio-frequency (RF) communication applications require strict specifications for
DAC dynamic linearity; digital communication applications require strict specifications on FS high-speed
specifications eye patterns. This considers the DAC dynamic linearity group of figures, since they are very
important in the RF communication applications. Figure 6 shows an exemplary spectrum of a DAC sine wave output
signal.SFDR (Spurious-Free-Dynamic Range), HD (Harmonic Distortion), and IMD (Inter-Modulation Distortion)
are the most important parameter. The most popular implementations include switched-capacitor DACs, resistorbased DACs and current- steering DACs. The charge-redistribution DAC is a switched-capacitor (SC) circuit,
implementing DA conversion in the charge domain [6], [3], [13]. Usually, charges stored on a number of capacitors
are used to perform the required conversion. Figure shows an example of a differential charge-redistribution DAC.
Its output signal is generated by an amplifier, the speed and the linearity of which are usually the main performance
limitations. Furthermore, the performance of these converters is also constrained in accuracy due to the finite
matching of the capacitors. The R-2R ladder is a simple approach to implement DACs. Its basic principles are
outlined. When a voltage is applied to node 6 in the circuit, a binary voltage scale builds up along the upper nodes.
The same applies to the currents flowing in the vertical resistances 2R. The binary weighted currents flowing
through the vertical resistances 2R can be selected and combined
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Figure 6. A block diagram of a Current-Steering DAC, with binary LSB—unary MSB
Algorithmic segmentation, exemplary circuit implementations, and an optional
Exemplary calibration engine.
In a common node and consequently converted to voltage, for example as shown in Fig. 1. Switches, which are
controlled by the input digital word, Bn, pass the binary weighted currents to the summing node or redirect them to
ground. The summing node in the example, Fig. below, is the virtual ground at the negative input of the amplifier.
Today, The R2R ladder approach is rarely encountered in state-of-the-art DACs
The current-steering DAC is the most popular implementation, mainly because of its high speed. It is the
implementation that is considered in this book. The main building blocks of current-steering DACs are discussed.
Figure 7.R 2R ladder DAC
IV.Current-Steering DAC Architecture
The current-steering DAC implementation provides high-speeds and high-accuracies with respect to the
other main implementation alternatives. The basic analog entity is current and hence the DAC output is usually
current. The output DAC current can quickly charge parasitic capacitances at the output and hence achieve high
speeds. Matching of currents is a well elaborated topic and many techniques exist to achieve higher accuracy and
matching of currents than what is possible and reasonable with the other possible alternatives. Figure7 shows a
block diagram of a representative current-steering DAC implementation. Usually, the input of the DAC complies
with the LVDS (low-voltage- differential signal) standard, which provides high digital input data rate. Thus, the
LVDS input buffers are the first circuits that process the input signals. Further, the N bit differential signal is split
into B bits LSB and (N − B) bits MSB parts, if the algorithmic segmentation requires this. The MSB bits are
encoded into 2(N−B) – 1 Bits of thermometer (unary) code by a binary-to-thermometer decoder. The LSB bits are
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delayed by a series of buffers with an approximately equal delay to that of the decoder. Equalizing the moments
when the information appears at the inputs of the flip-flops is important, since the slowest time difference between
the fastest and the slowest bits would limit the maximal possible sampling rate. The decoder usually works
asynchronously. Thus, the information needs to be again synchronized after it. The advantage of such an approach is
that the implementation of the decoder is decoupled from the implementation of the flip-flops, e.g. the type of logic
(CMOS, Differential-NMOS, Current-Steering, etc.). A is advantage is that an asynchronous decoder always allows
slower speeds than a synchronous one. Next, after the binary-to-thermometer decoder, the signals are directed to
flipflops, usually implemented as Master-Slave latches. These flip-flops are referred to as “analog”, because of their
sensitivity and importance to the quality of the generated converter output. Thus, all physical processes should be
considered at a very low, analog level.
Figure 7. A block diagram of a Current-Steering DAC, with binary LSB—unary MSB
Algorithmic segmentation, exemplary circuit implementations, and an optional
Exemplary calibration engine
The electrical signals of the carried digital information are of significant importance. The Master-Slave Latches
synchronize the data and shape their physical signals in a proper way for the next block—the current switching cells.
The main task of the current switching cells is to combine the appropriate currents, generating the analog current
output for the input digital word being converted. The currents, or the analog elements, which are used to generate
the analog output current, are placed in the block “Pool of (unit) current sources”. The currents generated by this
block may be optionally corrected by currents coming from the Array of CALDACs (calibrating DACs). The
calibrated currents are passed to the current switching cells to generate the output of the converter. Next to the above
described core of the DAC, there are optional components, needed for example to perform calibration, like
comparators and references. With respect to the operation, the DAC sub-blocks can be classified as dynamic and
static blocks. The dynamic circuits are those which process dynamic signals, i.e. data and clock signals. The static
circuits are those which operate with static analog values (currents and voltages) during the normal operation of the
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converter. The dynamic group includes input LVDS buffers, decoder and LSB delay line, flip-flops, and current
switches. The static group includes the pool of current sources, the optional array of CALDACs, and biasing circuits
(not shown).
V.DAC Circuit Design Techniques
Despite the array of digital-to-analog converter topologies available, it was relatively simple to pick which topology
to use for this project. Process tolerances and area considerations rule out resistor-ladder and charge division
architectures, and there are uniformity issues with current division topologies. This leaves the obvious choice of
current steering architectures, which was in fact chosen for the transmitter implementation. This section discusses
design decisions made once the architecture choice was finalized, with emphasis placed on low power and
technology scaling issues. Figure 8 shows the 100%-segmented (i.e. entirely unit-element) DAC architecture chosen
for this design.
The first block the digital input signal encounters is a four-to-one multiplexor, which converts a 32-bit wide 50
MHz digital input signal into an 8-bit 200 MHz signal. This block is strictly for testing purposes; after examining
waveforms generated by the Hewlett-Packard logic analyzer, it was ascertained that the signal produced at 200 MHz
was more or less a sine wave. Compounding the poor signal generator quality at extremely high clock rates is the
difficulty in getting a signal that fast onto the board. To allay these fears, the multiplexor was added to reduce the
input signal’s clock rate to 50 MHz. Of course, once the digital backend circuits are complete, they will generate the
200 MHz signal on-chip and thus the multiplexor block can be removed. After the multiplexor, the 8-bit digital
signal undergoes binary-to-thermometer decoding. The four most significant bits drive the column decoder, while
the four least significant bits drive the row decoder. After decoding, there are 16 row and 16 column bits, which act
as control signals for the current source blocks. The number of current sources active at a given time is determined
by the value of the input signal; for a digital input of 00000000, there will be zero current in IOUT and 255*IREF
flowing in node OUT I . For an input of 11111111 the situation is reversed, and turning on the correct number of
current sources can represent all digital values between these two extremes.
Figure 8 Block diagram of current-switched segmented DAC architecture used.
The current source blocks are seen in the 16 by 16 matrix, and the circuitry included in each is shown in
Figure 9. Each current source contains digital decoding circuit that determines whether to turn on IOUT or OUT I
based on the row and column signals. The analog part of the cell consists of a cascoded current source and a
differential switch; the current source is biased with a standard high-swing biasing scheme. PMOS devices were
used in the current source because they reduce crosstalk. Previous designers had tried both NMOS and PMOS for
the current sources and found that the crosstalk from digital portions of the chip is much less in the P-type devices.
This makes logical sense as the PMOS devices are built in an n-well and therefore is shielded from the substrate.
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Figure 9. Current source cell.
A. Analog Aspects Having decided on the 100% segmented topology, the majority of time spent on the design dealt with the analog
aspects of the current source cell. Decisions were made on the amount of current each source should generate and
how small the transistors could be and still meet matching requirements. Each area will be explored in detail
B. Power Consumption The dominant source of power consumption in the digital-to-analog converter is the analog portion of the current
source matrix. Since the design is differential, each element is sourcing the reference current regardless of the output
value. Thus a rough estimate of total power consumption (excluding power consumed by the digital blocks, which is
almost negligible due to the dynamic nature of the CMOS standard cells) is easy: simply multiply the number of
current sources by the reference current by the supply voltage:
C. .Matching requirements From the previous discussion, it is apparent that ideally the reference current should be as low as possible.
Unfortunately, there are several constraints that provide a minimum value for the reference current, including
matching requirements, signal-to-noise ratio, and speed considerations. Matching requirements will be analyzed
first. As defined by Pelgrom, mismatch “is the process that causes time-independent random variations in physical
quantities of identically designed devices.” [7] Essentially, this means that each current source in the matrix
generates a current that varies slightly from the desired current, IREF. Therefore the current sources have to be
designed in such a way that random variations do not degrade the performance of the circuit below its specifications.
Pelgrom’s paper has become the de facto standard for analysis of transistor matching, and thus his formula for the
standard deviation of saturation current for two identically sized devices was used for the design. This formula is:
D. Signal-to-Noise Ratio To maintain an accuracy of at lea st 8 bits of resolution, it was imperative that the signal-to-noise ratio of the DAC
remained above 48 dB. To provide a sufficient safety margin, the design aimed for a signal-to-noise ratio of 60 dB.
The signal power was easily calculated: it was simply a function of the chosen output reference current.
E. Speed Requirements This was a relatively high-speed digital-to-analog converter, and thus the output current needed to charge the
capacitor load of the subsequent filter stage was significant. For this stage, working closely with the designer of the
filter stage proved profitable; he estimated the output capacitance the DAC would have to drive at around 5
picofarads. To determine the amount of current necessary to charge this capacitor fast enough, the standard formula
for charging a cap was used:
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F. Digital Aspects Clearly, the design time for a digital-to-analog converter is dominated by the analog components. However,
given its digital interface to the world, standard digital cells play a role as well. In this section the digital
components of the DAC will be briefly discussed. All the digital blocks were implemented with standard cells, with
the exception of the decoder.
Figure 10. 32-to-8 bit multiplexor setup. This allows 32-bit, 50 MHz input signals to be seen as 8-bit, 200
Mhz signals to the DAC.
G. 1 4-to-1 Multiplexor
The 4-to-1 multiplexor is not an integral component to the DAC; in fact, when the digital backend circuitry
is completed and placed on the same chip as the analog components, the mux will not be necessary at all. However,
our pattern generating system here at the BWRC only produces clean signals up to about 50 MHz. Therefore to
ensure that the DAC is testable at its specified speed of 200 MHz, a 4-to-1 mux was added, as shown in Figure
4.4.The operation is simple. There are eight 4-to-1 multiplexors, one for each digital input bit. The two flip-flops are
wired as a two-bit counter, and the Q_BAR outputs of the flip-flops are used as the select signal inputs to the eight
muxes. The digital inputs change every 20 ns, while during each clock cycle the multiplexors choose one of the four
input signals. This results in each 8-bit input being fed to the DAC at 5 ns intervals, resulting in the desired 200
MHz input signal.
H.Binary-to-Thermometer Decoding Logic
Once the 200 MHz 8-bit digital input stream is established, it must be converted from binary encoding to
thermometer encoding. To control the 256 current sources, the eight bits are divided into the 4 rows and 4 columns,
each of which is fed to a binary –to thermometer decoder block. The logic operation that each decoder performs is
shown below in Table 3.1 (note that the table shown is only for a 3 -bit decoder; the reader can easily extrapolate the
table to understand how a 4-bit decoder would work!). The decoder is implemented in the same fashion as the
multiplexor, with standard
I. Current Source Decoder
Once the input is translated into thermometer code, the last remaining digital aspect is the decoding logic
contained in each current source cell. The goal of this logic is very simple: the number of current sources that turn
on (i.e. the positive output terminal enabled) should be equal to the value of the thermometer input code. The best
way to describe the logic that implements this functionality is as follows. If the previous row is high and either the
current column strobe or the current row strobe is high, then the current source should source current through the
positive output terminal. Rewritten in logical fashion, OUT = ROWN- 1 AND (ROWN OR COLN).
After decoding the three input signals, the cell latches the result with a simple inverter pair. The two nodes formed
by the latch control the analog switches, thereby passing the current through either OUT or OUT bar.
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Figure11.example illustrating the functionality of current source logic
An example illustrating the implementation and functionality of the current source decoding logic. The filled-in
squares represent the current sources that are funneling current through the positive output terminal. Provides an
example of the decoder logic functionality for a given binary input. The eight input bits are separated into the four
MSBs and LSBs and passed to the thermometer-decoding row and column controller blocks. These blocks translate
the binary input into thermometer code and pass the values into the current source array. Each current source cell
then decodes the three inputs and latches the output, using the value stored to control which terminal is enabled.
S.No
Year
Resolution
INL(LSB)
DNL(LSB)
Sampling
Rate
SFDR/Input
frequency
Power
/Area
VI.SUMMARY TABLE
250nm Technology
2006-2008
10bit
+-.5
+-.3
250MHz
60Db/122.5MHz
22mw/.35mm2
V. CONCLUSION
This paper covers mainly the design of Current steering DAC. From the result we can say the following points. It is
fast data converter with low power supply, so it can be useful for below given power supply, It reduces complexity
and fastest speed. There are various constraints that affect the design like signal to noise ratio and power
consumption. There are also many operating many factors depending upon design.It is more easier and compatible.
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[2] Chi-Hung Lin and Klaas Bult “A 10-b 500-MSample/s CMOS DAC in 0.6mm2," IEEE JOURNAL OFSOLID-STATE CIRCUITS, VOL.33,
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[3] Jurgen Deveugele, Michiel Steyaert " A 10b 250 MS/s Binary- Weighted Current-Steering DAC," IEEEInternational Solid-State Circuit
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[4] Mercer, D., Singer, L.“12-b 125 MSPS CMOS D/A Designed For Spectral Performance”; ISLPED1996 Digest of Technical Papers, Pages
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[5] Schofield, W., Mercer, D., St.Onge,L., “A 16b 400MS/s DAC with <-80dBc IMD to 300MHz and <-160dBm/Hz noise power spectral
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