A 14-bit MOS DAC with Current Sources free from
Power-Line Voltage Drop and with Output Circuits free
from Code-dependent Variable Time Constant
Toru Sai and Yasuhiro Sugimoto*
Department of Electrical, Electronic, and Communication Engineering, Chuo University
1-13-27, Kasuga, Bunkyo-ku, 112-8551, Tokyo, Japan
E-mail: sai@comp.elect.chuo-u.ac.jp, *sugimoto@elect.chuo-u.ac.jp
designs, all the output of the current sources was tied to one
output terminal where a load resistor is connected. However,
the number of currents that tie to the output terminal depends
on the digital input code of the DAC. Therefore, the number
of parasitic capacitances, each of which is associated with a
specific current source and current switch connected to the
output terminal of the DAC, changes depending on the digital
input code. This is one of the major reasons that highfrequency reconstructed waveforms of DACs have large
harmonic distortions [5].
In this paper, we have designed a DAC that realizes 14-bit
resolution without calibrating the unit current sources in a
matrix, and have also designed output circuits for the DAC
that do not have a time-constant change even when the digital
input code changes.
Abstract-A 14-bit MOS DAC is described that has current
sources that are free from the non-linear current mismatch
caused by ground-line voltage drop and output circuits that do
not suffer from time-constant change at the output terminal
when the input digital code changes. Base current sources are
locally classified into two groups with two different values, and
the unit current source is constructed by adding one base
current source from one group and another base current source
from the other group. Eight buffer amplifiers are distributed
between the output terminal and current switches to stabilize the
voltage at the node where several outputs of unit current sources
are tied together and to eliminate the influence of stray
capacitances associated with unit current sources and current
switches. A 14-bit, 3.3-V DAC was fabricated using 0.35-um
CMOS devices. The results show that the DNL and INL are from
+0.7 to -0.75 LSB and +1.5 to -1 dB, respectively, and that the
SFDR for 2.5-MHz and 10-MHz reconstructed signal waveforms
were 77 dB and 67 dB, respectively, with a 50-MHz clock. The
current consumption was 25 mA.
II. THE 14-BIT DAC ARCHITECTURE
The developed DAC adopts segmentation and R-2R ladder
architecture to realize a 14-bit resolution. A block diagram is
shown in Figure 1.
I. INTRODUCTION
In order to realize a highly accurate MOS D-to-A converter
(DAC) such as one with 14-bit resolution, precise current
matching among MOS current sources is needed [1]. Current
sources are commonly segmented and placed in a matrix form
[2] in such a high-resolution DAC, and the foreground
calibration method [4], [5] has been used for MSB current
sources to reduce mismatches; however, foreground
calibration is inconvenient to manufacturers, and it should be
avoided.
Segmentation means that current sources occupy a large
area on an LSI chip. The ground line, as a power line for
NMOS current source transistors, should go through each
current source to obtain the current which flows out of the
current source; as a result, a voltage drop along the ground
line is observed. This voltage drop causes a non-linear
mismatch in the current of the unit current source. This
problem needs to be solved if calibration is not desired.
Moreover, in a highly accurate DAC, the frequency
characteristics in the Spurious-Free-Dynamic-Range (SFDR)
of the output signal must also be investigated. In previous
978-1-4244-3896-9/09/$25.00 ©2009 IEEE
Fig. 1. Block diagrams of the designed 14-bit DAC.
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Given the adopted segmentation, the current sources and
current switches for the upper 6 bits are placed in the matrix
form as shown in Figure 1. Sixty-three unit current sources
are used to form 63 steps for the upper 6 bits from
Bit1(=MSB) to Bit6. The lower 8 bits are constructed using 8
current sources, current switches and R-2R ladder resistors.
The output circuit is prepared between the “DA-out” or “DAout/” terminal and the current switches. The outputs of two
rows of unit current sources-that is, 16 unit current sourcesare connected into one and lead to one output circuit. Due to
the differential configuration, in reality, two output circuits
are needed for every 16 unit current sources. The output
circuit stabilizes its input voltage so that the waveforms at the
“DA-out” or “DA-out/” terminal need not see a stray
capacitance change.
Fig. 2. Non-linear current mismatch along the ground line.
III. ELIMINATING CURRENT MISMATCH DUE TO GROUND
LINE VOLTAGE DROP
As we cannot have an equal length of ground line from
the ground pads for each unit current source, the voltage at the
ground line for each unit current source may differ due to the
line resistance RG. Suppose that 8 unit current sources in the
current source matrix are placed in the configuration shown in
Figure 2, with the ground line connecting them and the
ground terminal at one end, and that they are numbered 1, 9,
17, 25, 33, 41, 49, and 57. In this design, each current source
consists of one NMOS transistor, and its gate terminal is
connected to the bias circuit, which is common to all the
current sources in the current source matrix. Then, the ground
line voltage on the left side of the current source becomes
higher than that on the right side of the current source. As a
result, the current values of the unit current sources become
non-linearly distributed along the positions as shown in
Figure 2.
In order to eliminate the current error caused by the ground
line voltage drop, a new structure for the current source array
is proposed. Figure 3 shows a new layout, and the connection
structure for the current sources is shown in Figure 2. In
Figure 3, a unit current source consists of two base current
sources. For example, unit current source 57 consists of the
parallel connection of base current sources 57a and 57b. Each
unit current source was divided into two base current sources,
which were labeled “a” and “b.” In Figure 3, column “a” has
8 base current sources, and they are further split into two
subgroups: 1a, 9a, 17a, 25a and 33a, 41a, 49a, 57a. The
current values of 1a, 9a, 17a, and 25a are equal because the
ground lines are laid out in equal length using the first and
second metal layers as shown in Figure 3. Point B, the origin
point, is on the third metal layer and is common to 4 base
current sources: 1a, 9a, 17a, and 25a.
The same discussion holds for each subgroup of the base
current sources. The current values for base current sources
33a, 41a, 49a, and 57a are equal with respect to the origin
point A; the current values for base current sources 1b, 9b,
17b, and 25b are equal with respect to the origin point C; and
the current values for base current sources 33b, 41b, 49b, and
Fig. 3. New structure to realize unit current sources.
57b are equal with respect to the origin point D. The thirdlayer metals connect those origin points. As the third metal is
connected to the ground pads of the chip, we assumed that the
voltages at one end of the two third-layer metals in Figure 3
are the same. Then, the voltages at origin points A and C
become equal, and the voltages at origins B and D become
equal. Although the voltages are different between A and B,
or C and D, all the unit current sources come to have equal
current values when one unit current source is constructed by
the parallel connection of one base current source from
subgroup A and another from subgroup D, or one from
subgroup B and another from subgroup C, etc., as shown in
Figure 3.
IV. ELIMINATING THE TIME-CONSTANT CHANGE AT THE
OUTPUT TERMINAL
A DAC needs to output analog signals without distorting
the waveforms. In reality, however, the high-frequency signal
is greatly distorted. In order to take this characteristic into
account, the SFDR was observed. Harmonics are major
components of spurs that deteriorate the SFDR.
One of the major causes of distortion is considered to be
stray capacitances associated with unit current sources and
current switches [3]. However, the analyses in reference 3
were based on a small-signal equivalent circuit. We took the
dynamic operation into account, that is, the time-constant
change at the output terminal depending on the digital input
code. This is illustrated in Figure 4. Figure 4 shows the
conventional DAC circuit with stray capacitors associated
with current sources and current switches to realize the upper
bits.
Depending on the digital input code, switches from SW1 to
SWn turn on and off and the amount of current proportional to
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the value that the input digital code represents flows into the
load resistor RL, resulting in the analog output voltage.
However, the stray capacitors (Cs) become connected and
disconnected as the switch turns on and off, and the time
constant at the output terminal (Signal Out in Figure 4)
changes depending on how many switches turn on.
This phenomenon was SPICE-simulated and is shown as a
curve labeled “conventional” in Figure 5. The curve indicates
that the time constant for the rising interval changes as the
output voltage changes. As the number of current sources is
tied to the output terminal when the output voltage becomes
low, that is, when the MSB of the input digital code is high,
the time constant becomes large. This result is coincident with
the fact that a number of switches turn on and a number of
stray capacitors are tied to the output terminal.
In order to avoid this situation, the buffered cascode circuit,
which consists of an amplifier A, a MOS transistor M1, and
the bias voltage V3 in Figure 6, is placed between the output
terminal and current switches. The impedance at the minus
input terminal of amplifier A-that is, the point where all the
currents are combined-becomes low. This means there is no
signal swing at the point even when a large analog signal is
output at the output terminal. The time-constant change at the
output terminal is eliminated. This characteristic is shown as
the curve labeled “with gain-boosted cascode circuit” in
Figure 5. The impedance at the minus input terminal of
amplifier A-that is, the point where all the currents are
combined-becomes low. The time-constant change for the rise
time of the output waveform has been eliminated.
SFDR frequency characteristics were further simulated by
using 0.35-um CMOS device parameters, as shown in Figure
7. The SFDR at high frequencies is expected to be improved
greatly when the time-constant change is suppressed by using
the circuit in Figure 6.
V. DESIGN PARAMETERS OF THE CIRCUIT
The design parameters of the circuit in Figure 6 are
described. The current of the unit current source in the matrix
is chosen 185 uA and about 12 mA flows in the 50 Ω load RL,
resulting in 600 mVp-p output at the full-scale signal level.
The circuit is differentially configured. The stuck-up elements
from the ground to 3.3 V supply (VCC) are a current source
transistor, a current switch, a buffered cascode circuit and a
load resistor. The size, gm and the output conductance of the
MSB switch are 16u/0.5u, 1.4 mS and 52 uS, respectively. Its
source capacitance is 0.6 pF, and this value is relatively large
because a cascode transistor for the current source is not used
for the reason of testing the low-voltage operation of this
current source part. The voltage gain of amplifier A is 26 dB;
its -3 dB frequency bandwidth is 220 MHz and consumes 0.8
mA. In place of a cascode transistor for each current source,
only the 8 buffered cascode amplifiers are needed.
Fig. 4. Conventional DAC circuit with stray capacitors for realization of
upper bits.
Fig. 6. Modified DAC output circuit in which the time-constant variation is
eliminated.
Fig. 7. Simulated SFDR characteristics of the circuits in Fig. 4 and Fig. 6.
Fig. 5. The influence of stray capacitors.
51
The advantage is that the influence of the source capacitance
of the current switch is reduced. To guarantee the operation of
the buffered cascade circuit when all switches turns off, 0.6
mA of constant current source is connected to the source of
M1 in Figure 6. The supply voltage of the logic circuit is 2 V,
and the control signal for current switches is 2 V and 0 V.
Transistors in the current switch remain in a state of saturation.
VI. CONCLUSION
A new current source matrix which realizes high accuracy
without calibration was designed. An output circuit without
time-constant change due to the digital input code-dependent
stray capacitance change was also designed. The use of a 0.35
μm CMOS chip verified the effectiveness of the designs.
REFERENCES
V. EXPERIMENTAL RESULTS
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2
G.G.E.Gielen , “A 14-bit intrinsic accuracy Q random walk CMOS
In order to determine the effects of the new current source
matrix and the distortion-free output circuit, a 14-bit DAC
was designed and fabricated using 0.35-um CMOS devices.
Although we could observe its operation up to 200 MS/s in a
SPICE simulation, the actual chip is subject to a great deal of
digital noise generated by the large-size devices used, and
relatively good performance has been obtained only in the
case up to 50 MS/s although it operates at a speed up to 100
MS/s.
Figure 8 shows the measurement results of DNL and INL at
the 14-bit level. The DNL ranged within ±0.7 LSB and the
INL from +1.5 to -1.0 LSB when the clock was 50 MHz. A
relatively good INL performance was obtained. This may be
the result of having good matching in the unit current sources.
Figure 9 shows the frequency spectrum of the 2.5 MHz
full-scale signal output with a clock speed of 50 MHz. The
second harmonic was the largest; however, it was about the
same as the noise level. Figure 10 shows the frequency
characteristics of the measured SFDR, the second (white
circle) and the third (black triangle) harmonics for the fullscale output signal with a clock speed of 50 MHz. The SPICE
simulation result in SFDR with a 200 MHz clock is
superimposed on the graph. The slope is similar to up to onefifth of the clock speed. However, a small amount of
degradation is observed when the reconstructed signal is more
than 10 MHz. This might be the reason that the DAC adopts
R-2R ladders for the lower 8-bit realization. The measured
second and third harmonics levels are almost the same
although the differential outputs are taken. These points
should be investigated further. Table 1 summarizes the IC
performance.
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[3] A.V.Bosch, M.A.F.Borremans, M.S.J.Steyaert, and W.Sansen, “A 10-bit
1GSample/s nyquist current steering CMOS D/A converter”, IEEE
JSSC, vol.SC-36, no.3, pp.315-324, March 2001.
[4] W.Schofield, D.Mercer, L.St.Onge, “A 16b 400MS/s DAC with <-80dBc
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[5] D.A.Mercer, “Low-Power Approaches to High-Speed Current-Steering
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(a) DNL
(b) INL
Fig. 8. Measured DNL and INL of a 14-bit DAC
Table 1. Overall IC performance.
Fig. 9. Spectrum of the reconstructed 2.5-MHz analog output signal with
a 50-MHz clock.
Fig. 10. SFDR frequency characteristics of the reconstructed analog output
signal with a 50-MHz clock.
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