Design of Low Power 8-Bit Digital-to-Analog
Converter with Good Voltage-Stability
by
Anshul Agarwal
Roll Number: 200431001
anshulagarwal@research.iiit.ac.in
Thesis submitted in partial fulfillment
of the requirement for the degree of
Master of Science (by Research)
in
Electronics and Communication Engineering
Center for VLSI and Embedded System Technologies
International Institute of Information Technology
Hyderabad, India
May 2013
INTERNATIONAL INSTITUTE OF INFORMATION TECHNOLOGY
Hyderabad, India
CERTIFICATE
It is certified that the work reported in this thesis, titled “Design of Low Power 8-Bit Digitalto-Analog Converter with Good Voltage-Stability” by Anshul Agarwal, has been carried out
under my supervision and is not submitted elsewhere for a degree.
Date
Advisor: Prof. M. Satyam
Center for VLSI and Embedded System Technologies
IIIT, Hyderabad
Copyright ©Anshul Agarwal, 2013
All Rights Reserved
Dedicated to my parents
Mrs. Alpana Agarwal and Mr. Rajkumar Agarwal,
for their everlasting love and support.
Acknowledgments
This work would not have been possible without the help and support of many individuals.
I offer my sincerest gratitude to my supervisor, Prof. Satyam Mandavilli, who has supported
me throughout my research work with his patience and immense knowledge. I attribute the
level of my Masters degree to his encouragement and efforts and without him this thesis,
too, would not have been completed. He taught me how to pursue research and gave me
the much needed exposure and skill to think and give shape to my thoughts. He helped to
shape the direction of this work and filled in many of the gaps in my knowledge.
I am sincerely grateful to Prof. Govindarajulu for his constant support, encouragement
and cheerful applause for my accomplishments. I also want to thank all the staff members
and fellow research students of CVEST for their support and stimulating company during
these years.
I also take this opportunity to thank my friends at IIIT-H. Their good company, encouragement and strong support made my stay comfortable during the journey of IIIT-H
years.
Finally, I want to express my gratefulness to my parents and my sister Anushka for their
endless love, support, encouragement, patience and self-sacrifice. Neither words nor pen can
be sufficient to thank my family for what all they have done for me.
Abstract
With the advent of high performance (in terms of speed, power and area) digital circuits, the
need for data converters with high accuracy and speed for various kinds of applications, has
attracted the attention of scientists and technologists all over the world. Constant efforts
are being put in to miniaturize the data converters from the point of low power and less
area. The existing literature indicates that there is a need to have a very highly stabilized
power supply for data converters to achieve these goals. It is really difficult to achieve a
global power supply with high stability (temperature stability of the order of few ppms/‰
and voltage stability of few parts in ten thousands).
In view of this, an attempt has been made to develop a digital to analog converter (DAC)
integrated with a highly stabilized power supply. The whole architecture may be operated
with a power supply of poorer quality.
Literature survey on DACs has indicated that segmented architectures can reduce the
need for having large variations in the widths of current source transistors. The current
steering DAC architectures help in keeping the load current (i.e. current drawn by the
DAC) constant, and in achieving a higher speed of operation. The power drawn can be
minimized by choosing a low value of current for LSB. Keeping these considerations in view,
an 8-bit segmented current steering DAC has been attempted. The DAC has been divided
into two segments of 4-bits each. One segment caters to lower 4-bits of input digital word
and the other segment caters to higher 4-bits. This methodology has resulted in a maximum
required ratio of widths of transistors to be 8, in each segment. This ratio can perhaps be
achieved in any technology with reasonable accuracy. The technology used in the design
of this DAC is UMC 0.18 µm CMOS. In this, it has been possible to achieve a reasonable
accuracy with a LSB current of 2 µA. This has resulted in low power operation of the DAC.
With these considerations, a design for current steering DAC has been arrived at and
simulated using Synopsys H-Spice. It has been found that this DAC needs a power supply
of 1.8 V with a stability of ±1 mV to result in a change of less than 1 µA (less than 0.5
LSB) at the output of the DAC. Further, the current that is to be supplied is about 1.78
mA. This has led to the specifications of the power supply to be integrated with the DAC.
The supply voltage for this power supply has been chosen to be 5 V. This would enable the
development of a proper voltage reference of the required quality and the interface circuit
that may be needed between the reference and the DAC.
Literature reveals that it is the bandgap reference which yields good temperature and
voltage stability. A detailed study has revealed that the conventional bandgap reference
circuits generally give a voltage reference of about 1.2 V with a temperature stability of
around 25-50 ppm/‰. In view of this, bandgap reference has been modified, incorporating
additional elements to provide a feedback from the output to the input which leads to higher
stability. The proposed voltage reference has been found to give temperature stability of the
order of 1 ppm/‰. The voltage stability is near about 0.02% of supply voltage. Further, it
has been found possible to vary the output voltage of voltage reference from a low value of
0.7 V to 2.6 V. It has also been possible to reduce the lower end from 0.7 V to 0.3 V by
replacing the silicon junction diodes with schottky diodes.
A source follower has been used to isolate the DAC from the reference and provide the
required amount of current for DAC.
The DAC and the power supply have been integrated and the INL, DNL of the DAC are
found to be within ±0.5 LSB and ±0.8 LSB respectively. The maximum speed of operation
of the DAC is 500 MHz with a power consumption of about 13 mW .
This thesis indicates the effort put in to visualize and realize the 8-bit DAC with integrated
power supply. The thesis has been organized into 6 chapters.
ii
Contents
1 Introduction
1
1.1
Problem Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
1.2
Thesis Contribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
1.3
Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
2 Digital to Analog Conversion
4
2.1
Basic DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
2.2
DAC Performance Measures . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
2.2.1
Static Performance Measures
. . . . . . . . . . . . . . . . . . . . . .
5
2.2.2
Dynamic Performance Measures . . . . . . . . . . . . . . . . . . . . .
8
DAC Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
2.3.1
Thermometer Coded DAC Architecture . . . . . . . . . . . . . . . . .
9
2.3.2
Binary Weighted DAC . . . . . . . . . . . . . . . . . . . . . . . . . .
10
2.3.3
Hybrid DAC Architecture . . . . . . . . . . . . . . . . . . . . . . . .
10
2.3.4
DAC Architectures based on Implementation Modes . . . . . . . . . .
11
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
2.3
2.4
3 Related Work
15
3.1
High Speed DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15
3.2
High Accuracy DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
3.3
High Resolution DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
3.4
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24
4 Design of 8-bit DAC with Integrated Power Supply
25
4.1
DAC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
4.2
Current Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
iii
4.2.1
ILSB Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
29
4.2.2
DAC Current Source Segments . . . . . . . . . . . . . . . . . . . . .
34
Current Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
4.3.1
CMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
37
4.4
Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
39
4.5
Performance of DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
42
4.6
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
4.3
5 Internal Power Supply
5.1
5.2
5.3
49
Voltage Reference - Background . . . . . . . . . . . . . . . . . . . . . . . . .
49
5.1.1
Conventional Bandgap Reference . . . . . . . . . . . . . . . . . . . .
50
5.1.2
Proposed Voltage Reference . . . . . . . . . . . . . . . . . . . . . . .
52
5.1.3
Principle of Operation . . . . . . . . . . . . . . . . . . . . . . . . . .
53
5.1.4
Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
5.1.5
Typical 0.73 Reference Voltage . . . . . . . . . . . . . . . . . . . . .
55
5.1.6
Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
5.1.7
Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
58
Interface Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
5.2.1
Source Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
60
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
6 Conclusion
63
Publications
65
Bibliography
66
iv
List of Figures
2.1
Ideal DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
2.2
Offset Error for a 3-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
2.3
Gain Error for a 3-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . .
7
2.4
Example of Differential Nonlinearity for a 3-bit DAC . . . . . . . . . . . . .
7
2.5
Example of Integral Nonlinearity for a 3-bit DAC . . . . . . . . . . . . . . .
8
2.6
Settling Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
2.7
A Current Steering DAC using Binary-weighted Current Sources . . . . . . .
12
2.8
A Charge Redistribution DAC . . . . . . . . . . . . . . . . . . . . . . . . . .
12
2.9
A Resistor String DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
2.10 A R-2R DAC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
3.1
1 GHz 10-bit DAC in 90nm CMOS Process [8] . . . . . . . . . . . . . . . . .
16
3.2
6-bit DAC 3GS/s in 130nm CMOS Process [12] . . . . . . . . . . . . . . . .
18
3.3
130 MS/s 14-bit DAC Architecture [13] . . . . . . . . . . . . . . . . . . . . .
19
3.4
Current Switching Methodology to solve IBT Glitch [24] . . . . . . . . . . .
21
3.5
Simplified Circuit based on DQS . . . . . . . . . . . . . . . . . . . . . . . . .
22
3.6
Example Waveforms of DQS . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
4.1
8-Bit Current Steering DAC Architecture . . . . . . . . . . . . . . . . . . . .
27
4.2
PMOS Current Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
4.3
Current Sources with Parallel Transistors Connection . . . . . . . . . . . . .
28
4.4
Current Variation (nA) of current sources at output currents ranging from 0
to 255 µA. LSB current is 1 µA and input supply is 1.8 V. . . . . . . . . . .
4.5
30
Current Variation (nA) of current sources at output currents ranging from 0
to 255 µA. LSB current is 1 µA and input supply is 1.799 V. . . . . . . . . .
v
30
4.6
Current Variation (nA) of current sources at output currents ranging from 0
to 255 µA. LSB current is 1 µA and input supply is 1.801 V. . . . . . . . . .
4.7
Current Variation (nA) of current sources at output currents ranging from 0
to 383 µA. LSB current is 1.5 µA and input supply is 1.8 V. . . . . . . . . .
4.8
31
Current Variation (nA) of current sources at output currents ranging from 0
to 383 µA. LSB current is 1.5 µA and input supply is 1.799 V. . . . . . . . .
4.9
31
32
Current Variation (nA) of current sources at output currents ranging from 0
to 383 µA. LSB current is 1.5 µA and input supply is 1.801 V. . . . . . . . .
32
4.10 Current Variation (nA) of current sources at output currents ranging from 0
to 512 µA. LSB current is 2 µA and input supply is 1.8 V. . . . . . . . . . .
33
4.11 Current Variation (nA) of current sources at output currents ranging from 0
to 512 µA. LSB current is 2 µA and input supply is 1.799 V. . . . . . . . . .
33
4.12 Current Variation (nA) of current sources at output currents ranging from 0
to 512 µA. LSB current is 2 µA and input supply is 1.801 V. . . . . . . . . .
34
4.13 Current Peaking Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
35
4.14 A Differential Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
36
4.15 An CMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
4.16 Glitches at the output of DAC, using resistive load . . . . . . . . . . . . . .
40
4.17 Glitches at the output of DAC, using 8pf Capacitive Filter . . . . . . . . . .
41
4.18 Glitches at the output of DAC, using 16pf Capacitive Filter . . . . . . . . .
41
4.19 Glitches at the output of DAC, using RLC Filter . . . . . . . . . . . . . . .
42
4.20 INL Accuracy of 8-Bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
4.21 DNL Accuracy of 8-Bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . .
44
4.22 INL, DNL Measurement of 8-Bit DAC at 4.9 V input supply for 2 µA LSB .
45
4.23 INL, DNL Measurement of 8-Bit DAC at 5.1 V input supply for 2 µA LSB .
45
4.24 Monotonic Plot of DAC Output Current for 256 input words . . . . . . . . .
46
4.25 Circuit Diagram of 8-Bit Current Steering DAC with Integrated Power Supply
(IPS). IPS with Source Follower (BLUE), CURRENT SOURCE SEGMENTI and SEGMENT-II (RED), Switches (YELLOW) with Termination Resistances of 50W each. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
5.1
Conventional Bandgap Reference Circuit . . . . . . . . . . . . . . . . . . . .
51
5.2
Proposed Voltage Reference Circuit . . . . . . . . . . . . . . . . . . . . . . .
52
5.3
Plot between gain, A and voltage, VF for different temperatures. . . . . . . .
56
vi
5.4
Variation of gain (A) with temperature, for VF = 1.25 V . . . . . . . . . . .
57
5.5
Variation of 0.73V reference voltage with temperature. . . . . . . . . . . . .
57
5.6
Source Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
vii
List of Tables
2.1
Thermometer coding for 3-bit DAC . . . . . . . . . . . . . . . . . . . . . . .
4.1
Transistor Widths for Switch Transistors and Inverter Transistors (NMOS)
10
for 8 input bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
4.2
DAC Performance Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
4.3
Comparison with other available DACs . . . . . . . . . . . . . . . . . . . . .
48
5.1
Summary of various reference voltages . . . . . . . . . . . . . . . . . . . . .
58
5.2
Comparison of Voltage Reference Designs . . . . . . . . . . . . . . . . . . . .
59
5.3
DAC Performance Measures at different corners of Source Follower . . . . . .
61
viii
Chapter 1
Introduction
In most of the electronic systems the input and output signals are analog in nature. Hence
there are analog processing devices like amplifiers as input and output devices. However
most of the modifications to be carried out on the input signals before obtaining the outputs
are carried out in digital domain. Therefore, there is a need to convert the analog input
signals into digital signals at the input end, and after processing them in the digital domain;
they have to be converted back into analog signals in most of the applications. The circuits
that convert analog signals to digital signals are known as A/D Converters and the circuits
that convert digital signals to analog signals are called D/A Converters (DACs) [1, 2].
The penetration of electronics into areas like computers, communications, instrumentation
and embedded systems such as mobile phones, camcorders, HDTVs has given rise to the
need for DACs with stringent requirements. The requirements span over features like high
accuracy, linearity, reliability, high speed, low power and so on. There are various approaches
adopted to achieve specific characteristics as given below:
ˆ Speed : Higher speed is generally achieved by the use of current steering DAC architec-
ture [3].
ˆ Accuracy: Accuracy can be improved by adopting the segmentation approach [3] in
the design of current source array architecture where the ratio of transistor widths is
not too high in each segment.
ˆ Power : Use of low current value for LSB reduces the power consumption in the DAC.
Also, power consumption can be reduced by lowering the supply voltage provided to
the DAC [4].
1
1.1
Problem Description
From the above points, it is clear that the problem of designing a DAC insensitive to supply
voltage variations is not fully addressed. The thesis attempts at designing a DAC which is
insensitive to mainly supply variations, and temperature to some extent. The techniques
that are described above to achieve higher accuracy, good speed and lower power have been
adopted. The insensitivity to supply voltage variations has been achieved by two steps.
ˆ By integrating the power supply with the DAC architecture. This enables isolation of
outside supply variations from the DAC operation.
ˆ By designing a power supply with required high regulation demanded by the LSB
requirements.
1.2
Thesis Contribution
The key contributions of this thesis are:
1. Design of 8-bit, 500 MHz low power DAC.
2. Design Methodology of DAC with integrated power supply, immune to input supply
variation.
3. Conceiving of a voltage reference circuit which can result in high temperature stability
and voltage stability.
4. Design approach to obtain any reference voltage from 0.3 V to 2.6 V.
This thesis therefore, describes the design of a DAC which is of contemporary nature with
reasonable speed, resolution and linearity with lower power. It makes use of novel, high
stability voltage reference which is integrated with the DAC in order to achieve the required
voltage and temperature insensitivity. These efforts also have resulted in a methodology to
design a voltage reference of any value between 0.7 V and 2.6 V. The work on the design of
voltage reference has also been extended to obtain voltage references in the range of 0.3V to
0.7V, however by the use of schottky diodes rather than junction diodes.
2
1.3
Thesis Organization
The thesis is organized as follows:
ˆ Chapter 1 - Introduction: Introduction to the thesis.
ˆ Chapter 2 - Digital to Analog Conversion: Overview of the various types of archi-
tectures for implementing DAC and the figures of merit to understand the performance
of DACs.
ˆ Chapter 3 - Related Work: A survey of latest developments in realizing current
steering DACs.
ˆ Chapter 4 - Design of 8-bit DAC with Integrated Power Supply: Description
of the proposed 8-bit current steering DAC with two 4-bit current units, and discussions
on the limitations of this DAC and the requirements of the power supply.
ˆ Chapter 5 - Internal Power Supply: Description of high stability reference gen-
erator, its design principles and integration of supply with DAC, and also, a novel
methodology to arrive at variable voltage references.
ˆ Chapter 6 - Conclusion: Findings of the research and possible direction to extend
the work.
ˆ Publication: List of related publication.
At the end, references are provided.
3
Chapter 2
Digital to Analog Conversion
2.1
Basic DAC
A N-bit DAC takes an input of N-bit digital word and converts the digital input signal into
analog output signal in the form of voltage or current. A basic block diagram of N-bit DAC
is shown in Fig. 2.1 [1].
Figure 2.1: Ideal DAC
Here, an input N-bit digital word (b1 , b2 ,...bN ) has a value Bin given by Eq. (2.1)
Bin = b1 2−1 + b2 2−2 + ... + bN 2−N
(2.1)
where bi is a binary digit, i.e. 0 or 1. The bit b1 is the most significant bit (MSB) and bN
is the least significant bit (LSB).
4
Every digital word is processed through the system and the respective, output value in the
form of voltage or current is obtained at the output. Vout for a digital word can be described
through the following Eq. (2.2).
Vout = Vref · Bin
(2.2)
The various architectures for DACs are evaluated based on their performance. Therefore, various performance measures are described at the first instance and thereafter, DAC
architectures are critically discussed.
2.2
DAC Performance Measures
There are many performance measures for a DAC. They can be divided into static measures,
dynamic measures, and frequency-domain measures.
2.2.1
Static Performance Measures
The static performance measures describe the behavior of a DAC when single input words
are applied. They are the offset and gain error, the integral nonlinearity error and the
differential nonlinearity error.
Offset Error
For an input value, that is equal to zero, the output value should also be zero. The deviation
from zero is called offset error, Eof f . Fig. 2.2 shows the offset error for a 3-bit DAC. The
offset error can be calculated as shown in Eq. (2.3), where Vout is the actual output voltage
and Vlsb is the voltage for the least significant bit, LSB [1]. The zeros symbolize that the
input signal is equal to zero, independent on the number of bits.
Eof f =
Vout
Vlsb 0..0
(2.3)
Gain Error
The difference at the full-scale value between the ideal curve and the actual curve is defined
as the gain error, Egain . Before the gain error is calculated the offset error is subtracted.
5
Fig. 2.3 shows the gain error for an 3-bit DAC. The gain error can be calculated according
to Eq. (2.4) [1].
Egain = IdealSlope − ActualSlope
(2.4)
Figure 2.2: Offset Error for a 3-bit DAC
Differential Non-Linearity, Integral Non-Linearity
DNL (Differential Non-Linearity) shows how much two adjacent code analog values deviate
from the ideal 1 LSB step. Fig. 2.4 shows an example of DNL for 3-bit DAC. The actual
increment heights are labeled with respect to the ideal increment height, which is 1 LSB.
The increment height corresponding to 001 is equal to the corresponding height of the ideal
case, therefore DN L1 = 0. In case of 011, increment is not equal to the ideal curve but is
1.5 times the ideal height. Therefore, DN L3 = 1.5 LSB - 1 LSB = 0.5 LSB.
INL (Integrated Non-Linearity) shows how much the DAC transfer characteristic deviates
from an ideal one. The ideal characteristic is usually a straight line; INL shows how much
the actual voltage at a given code value differs from that line, in LSBs (1 LSB steps). Fig.
2.5 shows an example of INL for a 3-bit DAC.
Outputs corresponding to 001 and 011 are 1/2 LSB higher than the ideal values, therefore,
IN L1 = IN L3 = 0.5 LSB.
6
Figure 2.3: Gain Error for a 3-bit DAC
Figure 2.4: Example of Differential Nonlinearity for a 3-bit DAC
7
Figure 2.5: Example of Integral Nonlinearity for a 3-bit DAC
Monotonicity
If a DAC is monotonic, then the output always increases as the input increases. It is normally
not necessary to state such a condition for a DAC explicitly to have this behavior. If the
maximum DNL error is less than 1 LSB it is said that the DAC is guaranteed to be monotonic.
Monotonicity can also be guaranteed if the maximum INL error is less than 0.5 LSB.
2.2.2
Dynamic Performance Measures
The dynamic performance describes the behavior of the DAC when the input word makes
transitions between different values. The major dynamic measures described in this chapter
are settling time which decides the speed of the DAC, and glitches at the output.
Settling Time
The importance of settling time in a data conversion system is that certain analog operations
must be performed in sequence, and one operation may be accurately settled before the next
operation can be initiated. In DACs this parameter gives information about the time required
by the converter to meet the right output value after a change in the input code. The settling
time has many components as shown in Fig. 2.6. The delay time is very small and during
this interval there is no output change. During slew time, instead, the output amplifier
8
moves at its highest possible speed towards the final value or the output capacitance gets
charged. Ring time defines the region where the amplifier recovers from slewing and ceases
movement within some defined error band.
Figure 2.6: Settling Time
Glitches
Glitches are a limitation at high-speed data transfers. They occur during a transition between
two output values, as an undesired output value due to different signal propagation delay.
For a short period of time a false code could be represented at the output. For example if
the code transition is from 0111 to 1000 and if the MSB is switching faster than the LSBs,
the code 1111 may be present for a short time. This code represents the maximum value
and hence the glitch would be large.
2.3
2.3.1
DAC Architectures
Thermometer Coded DAC Architecture
The thermometer coded DAC contains number of reference elements equal to the maximum
value of the digital word. A 10-bit thermometer DAC would have 1023 segments, i.e. 2N −1
thermometer bits, corresponding to N binary bits. A 3 bit input binary code is encoded into
thermometer code as shown in the Table. 2.1.
Since elements are of equal size the matching becomes much simpler than a binary DAC.
Thus, the advantage of using thermometer code is that the disturbance from glitches is
9
Table 2.1: Thermometer coding for 3-bit DAC
Decimal Binary Thermometer Code
d0
b2 b1 b0
s8 s7 s6 s5 s4 s3 s2 s1
0
000
0000000
1
001
0000001
2
010
0000011
3
011
0000111
4
100
0001111
5
101
0011111
6
110
0111111
7
111
1111111
minimized and so it can be used for high speed operation. Monotonicity is also guaranteed
because we always add a reference source when ramping the output. This is the fastest and
highest precision DAC architecture but at the expense of high cost, due to additional chip
area and encoding circuits needed. This is used for low resolution otherwise the encoding
circuits become too large.
2.3.2
Binary Weighted DAC
Binary-weighted, binary-encoded, or binary-scaled, uses binary scaled elements e.g., current
sources, resistors, or capacitors. This means that every element is weighted with 21 , 22 , 23
... 2N where N is the number of bits.
The disadvantage of using binary-weighted is that for large number of bits, over 10, the
difference between the smallest and the largest value of the binary scaled elements becomes
large. This means that the circuit will become sensitive to matching errors and glitches [5].
The advantage of using binary-weighted DAC is that the number of reference elements and
switches are kept at the minimum value, thus saving the chip area.
2.3.3
Hybrid DAC Architecture
Hybrid DACs use a combination of more than one technique in a single converter. Most
DAC integrated circuits are of this type due to the difficulty of getting low cost, high speed
and high precision in one device [7]. The Segmented DAC, which combines the thermometer
10
coded principle for the most significant bits and the binary weighted principle for the least
significant bits, is a popular architecture. In this way, a compromise is obtained between
precision (by the use of the thermometer coded principle) and chip area with less number of
resistors or current sources (by the use of the binary weighted principle).
2.3.4
DAC Architectures based on Implementation Modes
There are three different implementation modes for DACs; voltage-mode, current-mode, and
charge- redistribution mode. In voltage mode DACs, the element values are given by voltage
levels. With current-mode DAC, the elements are given by currents as for example switched
current sources or resistors dividing a major current into weighted subcurrents. In case of
charge redistribution DAC, elements are given by capacitor values and the operation of the
DAC is given by a switched- capacitor techniques [1, 6].
Current Steering DAC
This architecture consists of weighted currents produced by current mirrors, switches to steer
the current and an adder. The reference elements are current sources and sum elements
are only wire connections. The switches are normally MOS transistors. The switches are
controlled by the input bits. In the figure, binary-weighted current sources are produced by
the use of current mirrors. This means that every element is weighted with 21 , 22 , 23 ... 2N
where N is the number of bits. The output current is given by
Iout = b0 Iunit + b1 2−1 Iunit + ... + bN 2−N Iunit
(2.5)
In Fig. 2.7, an N-bit current-steering DAC is shown. The current-steering DAC in the
figure is binary-weighted, as can be seen from the weighting of the current sources. The
switches are controlled by the input word. Depending on the input word, the current source
is switched to the load or to the ground which improves the speed of the DAC.
The advantage of current steering architecture is the ease of implementing the elements on
the chip. The current sources are current mirrors implemented using FETs. The weightage
in the current values can be obtained by simply varying the widths of the transistors. All
the switches can also be realized by using FETs. Thus, all the elements in current steering
DAC can be realized using MOSFETs. The power efficiency is also very high since most of
the power is dissipated in the small load resistor at the output. This architecture is thus
11
Figure 2.7: A Current Steering DAC using Binary-weighted Current Sources
suitable for high speed design and cost-effective to implement. The major difficulty is to
realize current sources with ideal characteristics because of device mismatches, and to avoid
the switching related glitches.
Charge Redistribution DAC
The charge-redistribution DAC is a switched-capacitor (SC) DAC, where the charge stored
on a number of scaled capacitors is used to perform the conversion. The MSB capacitor,
2N −1 , is times larger than the LSB capacitor. In Fig. 2.8 an N-bit charger distribution DAC
is shown. This is a type of switched-capacitor DAC with an amplifier at the output.
Figure 2.8: A Charge Redistribution DAC
The limitation of the converter is due to number of factors such as the matching of the
capacitors, the switch on-resistance, and the finite bandwidth of the amplifier. The matching
error of the capacitors affects the monotonicity of the DAC. Another significant problem is
12
that a substantial amount of chip area is occupied due to the use of capacitors in CMOS
technology.
Resistor String DAC
This DAC consists of a resistor string which acts as voltage divider. It provides taps for the
different voltage levels with the use of equally values resistors. An example of a 3 bit-DAC
is shown in Fig. 2.9.
Figure 2.9: A Resistor String DAC
This is one of the most common DAC architecture used in ICs due to its simple implementation. It is also fast and inherently monotonic. This architecture is however not suitable
for higher resolution DACs because it requires large number of resistors and switches as
resolution increases over 10 bits. Moreover, to avoid mismatching of resistors and maintain
accuracy, there is a need for trimming a large unary array of resistors.
13
R-2R Ladder DAC
The R-2R DAC is a binary weighted DAC that uses a repeating cascaded structure of resistor
values R and 2R as shown in Fig. 2.10. The advantage is that this type of implementation
uses a small number of components, and only two different sizes of resistors. This improves
the precision due to the relative ease of producing equal valued matched resistors. The
disadvantages are that if the number of bits is high there is a time delay between the LSB
and the MSB, and the resistors values must have high linearity.
Figure 2.10: A R-2R DAC Architecture
2.4
Summary
Since the thesis is devoted to design a DAC for high speed application with ease of using MOS
components, current steering architecture is chosen for the design of 8-bit DAC architecture
in this thesis. In chapter 3, a literature survey is described about the present high speed,
high performance DAC architectures and their limitations.
14
Chapter 3
Related Work
This chapter describes the relevant literature connected with growth of DACs. The progress
in the development of design of DAC in the last few decades has been studied through
published work and has provided knowledge of various techniques available to obtain DACs
with different attributes. The various techniques that have been employed to design high
speed, high accuracy and high resolution DACs are reported in this chapter.
3.1
High Speed DACs
High speed and high accuracy digital-to-analog converters (DACs) have become the critical components in many video and imaging applications as well as recent communication
systems. The emergence of HDTV and the convergence of PC and TV are also opening
opportunities for high speed DACs. Furthermore, DACs capable of being integrated with
digital signal processing (DSP) circuitry are more and more needed to realize system-on-achips (SoCs).
The recent advances in CMOS processes driven by the feature size reduction have led to a
considerable improvement in the performance of CMOS devices. Use of submicron CMOS,
advanced BiCMOS and SiGe technologies permit bandwidths of the order of many GHz and
are used to design DACs for various high speed applications. Therefore, speed is an issue
that is being satisfactorily addressed by exploiting the available technology. DACs that are
fabricated in some advanced CMOS processes such as 90 nm technologies have become a
popular choice and can be operated with a low supply voltage.
Chueh-Hao Yu et. Al [8] has described the design of a 10-bit current-steering segmented
15
DAC with a supply voltage of 1 V and an update rate of 1GS/s in the 90 nm CMOS
technology. Fig. 3.1 shows the architecture of the 10-bit current-steering D/A converter,
which consists of a digital thermometer decoder, current cells, and a bias circuit with a 0.6 V
bandgap circuit. To leverage the advantages of the thermometer-coded architecture and to
obtain a small area simultaneously, the 10-bit DAC is segmented into six most significant bits
(MSBs), which are thermometer decoded, and four least significant bits (LSBs) decoded by
using binary-weighted architecture. Furthermore, a dummy decoder is placed in the binaryweighted input path to equalize the delays of both decoders. Given a reference voltage VREF
and an external adjusted resistor REXT , the bias circuit generates a bias voltage for the
current source array to generate all the unary and binary-weighted current sources. The
reference voltage is generated by a sub-bandgap reference circuit.
Figure 3.1: 1 GHz 10-bit DAC in 90nm CMOS Process [8]
However, the use of decoder for thermometer coding and dummy purposes introduces
complexity and gets power hungry. Also, the use of high threshold transistors as current
sources to enhance output impedance also increases the complexity of design and leads to
more power consumption. The design presented in this paper consumes around 23 mW of
power.
There are few more high speed DACs that are fabricated in the 90 nm process [9, 10, 11].
DACs proposed by authors Takeshi Uedo [9] and Chueh-Hao Yu [10] operate only at 200
16
MS/s and 400 MS/s update rate, respectively. Jing Cao [11] presents a 1 GS/s DAC with a
higher supply of 1.8 V for current matrix. The DAC described by Jing Cao [11] is specifically
designed for the high speed digital communication SoCs, considering the need of high speed
DAC with lower power consumption and lesser chip area. The authors have used a currentsteering architecture with 6+4 (6-bit MSB plus 4-bit LSB) segmentation. The 6 MSB’s
control the switching of 63 unary current sources by thermometer decoding, while the 4
LSB’s control the switching of 4 binary weighted current sources.
Other than these recent DACs designed using 90 nm CMOS process, there are high speed
DACs reported in other various technologies such as 0.13 µm, 0.18 µm, 0.35 µm [12, 3, 13,
14, 15].
A 6-bit current steering DAC with 3 GS/s is presented by Palmer [12] and is shown in Fig.
3.2. The converter is implemented in a standard 130 nm CMOS technology with full scale
output current of 8 mA and the maximum power consumption of 29 mW . Since this work
targets moderate resolution and high speed at low power, it is implemented fully binary.
In order to obtain the high speed and good dynamic performance, the binary weighting is
implemented in a pseudo-segmented way [3]: 4-bit pseudo-unary and 2-bit binary, and the
buffered clock-tree network are used to ensure the synchronization of the current sources
[13].
A 10-bit 250 MS/s binary-weighted current steering DAC is described by Deveugele [3] and
implemented in 0.18 µm 1.8 V CMOS process, employing a modified segmentation approach
called ”pseudo-segmentation” to improve the dynamic performance of the converter and
achieve lower power consumption. Pseudo-segmentation uses segments with equal currents
as in a unary converter, but groups them in a binary weighted fashion. This eliminates the
expensive decoder that is needed in unary or segmented designs. It possesses the high speed
property of the binary-weighted architecture as well as it is able to achieve the high SFDR
performance of the segmentation architecture.
Authors T Chen et. al [13] has presented a 14-bit 130 MS/s segmented DAC where the
thermometer coded unit in the segmented part is implemented using RAM based technique,
shown in Fig. 3.3. With the RAM based thermometer decoder, an optimized switching
scheme is applied to achieve a peak-to-peak INL even better than the Random-Walk scheme
[14]. As a result, the area requirement of the current sources imposed by the matching
requirements is reduced. Tree-like buses are used to the clock net and the output net to
ensure the synchronization of the current sources.
17
Figure 3.2: 6-bit DAC 3GS/s in 130nm CMOS Process [12]
Ling Yuan [15] has proposed a 2 GS/s 10-bit CMOS digital-to-analog converter (DAC).
This DAC consists of a unit current-cell matrix for 6 MSBs and another unit current-cell
matrix for 4 LSBs, trading off between the precision and size of the chip while the Current
Mode Logic (CML) is used to ensure high speed.
It may be worthwhile to mention that DACs made with feature sizes of 0.13 µm, 0.18
µm and higher with similar performances in terms of speed occupy larger area and consume
more power.
There has also been a need of very high speed DACs to be specifically designed for the
direct digital synthesis technique. Direct Digital Synthesis (DDS) is a method for generating
a desired waveform (such as sine wave) of different frequencies from a fixed source. The
frequency of the waveform generated depends on how fast the DAC operates. The direct
digital synthesis (DDS) technique has become popular in the mobile communication arena
due to the simple control procedure [16, 17].
Since the silicon based transistors have the limitations of high mobility, the speed at which
silicon devices can operate gets limited. Therefore, SiGe based transistors are used because
of the presence of strained layers in the alloy which enhances the carrier mobility. The SiGe
18
Figure 3.3: 130 MS/s 14-bit DAC Architecture [13]
technology semiconductor provides lower-resistance layers for majority carriers and reduced
transit times for minority carriers-both beneficial for realizing fast transistors. Some SiGe
FET based high speed DACs have been reported with very high update rate in the range of
GHz [18, 19, 20, 21].
A binary weighted current steering DAC with 30 GS/s sampling rate is presented by
Haider et. al [18] which can be used as a standalone DAC as well as a sub-DAC for a higher
resolution segmented DAC.
The design of an 8-bit 20 GS/s DAC implemented using SiGe technology has also been
presented by Haider [19]. This DAC is implemented with a modified segmented current
steering architecture where the LSB sub-DAC is implemented with a R-2R ladder. In the
design of the binary weighted current steering DAC, a new heterojunction bipolar transistor
(HBT) ROM based thermometer decoder architecture has been used.
It may be seen from this description that higher speeds (higher update rates) are realized
using current mode DACs with segmentation approach, implemented in silicon. Very high
speed DACs which operate in tens of gigahertz are realized using SiGe technology.
19
3.2
High Accuracy DACs
In the above techniques used for realizing high speed DACs has been discussed. Another
important feature in the design of DAC is its accuracy. This measure indicates the closeness
of the output of the DAC to the real value associated with a digital word. This is usually
expressed in various forms like differential non-linearity (DNL) which indicates the amount of
deviation between outputs of two consecutive digital words with respect to ideal 1 LSB step ,
and integral non-linearity (INL) which indicates the deviation of actual output from expected
value for any digital word. Accuracy is also corrupted by unwanted signals such as glitches,
switching transients during the operation of the DAC. The following section describes the
various approaches adopted by various authors to overcome some of the deficiencies and
achieve higher accuracy.
As mentioned earlier in chapter 2, the accuracy as well as speed of operation are highest
in thermometer coded DACs. However, the segmented DAC is a compromise between the
binary and thermometer coded DACs. It has been shown that the converter [22] proposed
by Bosch et al uses 5-bit unary plus 5-bit binary-weighted segmentation, while the other
DAC [23] by Borremans et al uses full binary-weighted decoding. The segmented converter
achieves 10-bit dynamic accuracy up to the Nyquist frequency for a sample rate of 1 GS/s.
The binary-weighted converter, however, achieves 10-bit dynamic accuracy up to the Nyquist
frequency for only a sample rate of 30 MS/s.
However, it is shown by Deveugele [3] that high degree of segmentation adds to the power
consumption, complexity and size of the converter. Too much segmentation can worsen the
performance rather than improve it; the big dynamic core deteriorates timing and increases
the digital noise. The correct timing of a converter with a big dynamic core can become
challenging as the distances between the various segments is increased and the large portion
of logic adds more load to the clock line. Hence, the authors proposed a modified approach
to segmentation called ”pseudo-segmentation” to boost the dynamic performance of the
converter.
Moreover, the segmented architecture also introduces the problem of Inter block code
Transition (IBT) glitch [24]. For a rising monotonic input every change in the MSB bit
requires switching OFF of all the current sources in the LSB block and turning ON one
current source in the MSB block. Lack of synchronization in the timing of control signals
of the two blocks results into severe glitch, termed as IBT glitch. IBT glitch can become a
major source of non-linearity introducing noise and thereby degrading the overall dynamic
20
performance. A novel decoding architecture is used by the authors to reduce the IBT glitch
and overcome the drawbacks of segmented DAC architecture. In this proposed architecture
the complete N bit DAC is divided into numbers of M-bit sub-DACs and 1-bit sub-DACs.
Each of these sub-DACs is basically a binary DAC.
Operation principle of the proposed encoding scheme is illustrated with an example of 4
bit DAC in Fig. 3.4. The 4-bit DAC consists of one 1-bit sub-DAC and two 3-bit sub-DAC
s. The bordered blocks represent selected sub-DAC and the darkened current cell implies
it is switched ON. When the input is eight, the three current cells of the first sub-DAC,
remains ON and another one current source of the 1-bit sub-DAC is turned ON making a
total current of 8ILSB as required. This operation is unlike usual binary DAC where it is
required to turn ON a current source of 8ILSB and simultaneously switching OFF the three
cells. Keeping this three cells ON and turning ON only one extra cell removes the IBT glitch
associated with transition from 0111 to 1000.
Figure 3.4: Current Switching Methodology to solve IBT Glitch [24]
In addition to the better segmentation approaches [3, 23, 24], techniques such as trimming/calibration [25, 26], dynamic element matching (DEM) [27], geometric averaging [28],
or random-walk [14] are used to improve the static accuracy of the DAC. The dynamic
performance of the converter relies heavily on the efficient current switch design.
The 16b 500MS/s DAC reported by Schofield and Mercer [29] addresses some of the
issues of the current steering circuits. Park et al. [30] recognized the need for reducing
data dependent effects in the switches, which they achieve by use of a current switching
scheme that essentially hides the data from the current steering circuits, thereby removing
data dependent effects. They reduced the code dependency of the supply rail interference by
21
ensuring a transition of the switch driver signal on every clock cycle by using the differentialquad switching scheme.
Figure 3.5: Simplified Circuit based on DQS
Figure 3.6: Example Waveforms of DQS
Fig. 3.5 is the simplified circuit based on DQS. It uses four switches for differential
switching, and each switching transistor is driven by a signal shown in Fig. 3.6 which is
AND gated with one of the complementary clocks and hence, either side toggles every clock
instant. The output is logically the same with ordinary differential switching. Switching in
this manner eliminates the nonlinearity due to uneven pulse duration because every pulse
has the same width. There are at least two and only two signal transitions-one rising and
22
one falling-per clock transition. A major drawback of DQS is the increased dynamic power
consumption due to the increased switching frequency of each transistor and twice as many
switching transistors as differential switching.
The role of delay skews in both the timing of the current steering switches and in the
current output path is addressed by Chen et al. [31] and Bosch et al. [32]. The importance
of the crossing point of the gate drive relative to the switching threshold is also documented
by a number of authors [29, 33].
3.3
High Resolution DACs
In applications of high-resolution control loop systems like voltage-controlled oscillator (VCO),
voltage-controlled crystal oscillator (VCXO) and industrial process control, the monotonicity
of digital-to-analog converter (DAC) is the major performance parameter to make systems
reliable. These systems often require 16-bit monotonicity or higher. The standard conversion
technique used for these applications is a resistor-ladder DAC using MOS switches because
of the simplicity of implementation and the guaranteed monotonicity.
However, for resolutions of 10 bits or higher, a simple ladder DAC suffers from several
drawbacks: it requires a large number of resistors and switches and exhibits a long codedependent delay at the output [34]. Alternative resistor-ladder topologies like multi-stage
ladders [35, 36], and the intermeshed resistor-ladder [37] have been devised to improve speed
and resolution. But, the performance has been limited to 14 bits or less due to the finite
on-resistance of MOS switches or the loading of the switched sub-divider on the primary
ladder. For 14 bits and above, either on-chip calibration [36] or laser trimming becomes
necessary to overcome the inherent matching problem of resistors [38].
DACs having two operational amplifiers connected in voltage follower mode between ladder
stages have been also reported with a sacrifice in the integral nonlinearity (INL) performance
[39, 40]. Here, the performance is mainly limited by the offset voltage drift of the operational
amplifiers.
From the above, it may be seen that the problem of designing high speed and high performance DACs has been addressed from diffrent angles. However, there is a no clear mention
of the effect of supply voltage and temperature stability. It is felt that there is a need to
realize high speed DACs with good monotonicity and stable performance with respect to
variation in supply voltages and temperature. This aspect has been addressed in this thesis
23
by proposing current steering DAC with integrated power supply.
3.4
Summary
The study of the previous proposed designs and techniques for high speed DAC has been
looked into and described in this chapter. It can be summarized that the following techniques
are helpful to improve the speed of the DAC.
ˆ Use of advance CMOS technologies with reduced feature sizes such as 180nm, 90nm.
Further reduction of the transistor feature size in future can make it possible to obtain
high speed DACs.
ˆ Use of semiconductor technologies other than Si can also improve the speed of the
DAC to a very large extent as in the case of SiGe based DACs.
ˆ Use of current steering design with modified segmentation approaches for current source
array has already led to some high speed DACs. Further research and careful modifications may lead to faster DACs.
ˆ The careful design of current switches and high speed data latches for input signals
helps in better designing of DACs with high speed.
In addition to this, one may keep the following points in view while designing DACs with
high static and dynamic performance.
ˆ Use of improved segmentation approaches for the design of current source array is
necessary for more accurate DACs. The use of segmentation can affect the cost and
power of the system but accuracy can be improved if implied efficiently.
ˆ Synchronization of input signals through the use of latches
ˆ Reduction of glitches at the output due to the drain gate capacitance of switching
transistor.
ˆ Take care of mismatch effects of transistors in current source array.
Based on the available literature, the need for design of DACs with highly stable, integrated
power supply has been identified.
24
Chapter 4
Design of 8-bit DAC with Integrated
Power Supply
As already discussed in previous chapters, a current steering architecture suitable for high
speed data converters is described in this chapter. It is implemented with MOS components
with integrated power supply. The DAC designed and reported here is a low power, 8-bit
current steering DAC with a speed of about 500 M Hz. The various issues faced during the
design such as segmentation design, power consumption, delay of the switch inverters and
glitches at the output are discussed in the following sections.
4.1
DAC Architecture
An N-bit binary weighted converter has only N current mirrored sources with sizes of transistors varying from one unit to 2N units corresponding to one LSB current to 2N times
the LSB current. This kind of design of current source array leads to the use of transistors
with very large sizes in case of high resolution DACs. For example, in case of 8-bit DAC,
if width of smallest transistor in the current source array is 1 µm, the width of subsequent
transistors for higher bits would be 2 µm, 4 µm.. to 128 µm for MSB. This type of current
source architecture occupies lot of on-chip area and is expensive. Moreover, the process
variations in size of transistors can lead to large linearity errors and DAC can eventually lose
its monotonicity.
Preliminary simulation experiments, with sizing of widths of the transistors in current
sources as discussed above, did not result in the currents proportional to widths of the
25
transistors. This anamoly is perhaps due to the variation of effective width for smaller
widths of transistors. This narrowing of widths for smaller widths is known as Narrow
Width Effect [40]. To overcome this problem, the number of transistors with the same
width, are used in parallel instead of using transistors of different widths. The number of
transistors is proportional to the current of the current source. This approach also improves
the linearity and reduces the problems arising because of the mismatch of transistors.
Further, this DAC is expected to work with the voltage source which may vary by about
2%. This much of variation is not tolerated by an 8-bit current steering DAC of LSB
current of the order of few µA. Therefore, it is decided to build a power supply with very
high stability and integrate it with the DAC circuit itself. This design is called DAC with
integrated power supply. The details of the power supply are discussed in the chapter on
”Internal Power Supply”.
The block diagram of the DAC with integrated power supply is shown in Figure 4.1, and
the circuit diagram is shown in Figure 4.25.
It consists of a highly stabilized power supply, a power supply-DAC interface i.e. source
follower, one 4-bit DAC corresponding to LSBs (segment-I) and another 4-bit DAC corresponding to MSBs (segment-II). With a view to reduce the total number of transistors, a
segmentation approach consisting of two current source segments has been adopted for implementing the current sources. The minimum current corresponding to 1 LSB in segment-II
is 16 times the current corresponding to 1 LSB in segment-I. Depending upon the input digital word, respective current sources from both the segments are switched into the output
load. When the switched currents from these two DACs are added, one gets the output
proportional to the input digital word. The details of the current sources, the switches and
the interface between the power supply and the DAC are discussed in later sections.
26
VDD
Integrated Power
Supply
Current Source
Segment-I
Bit
[0:3]
Current Source
Segment - II
Switch_LSBs
Switch_MSBs
ROut
Bit
[4:7]
RGND
Figure 4.1: 8-Bit Current Steering DAC Architecture
4.2
Current Sources
A current source is one of the most important elements of the current steering DAC. It
generates the required current to be provided at the output of the DAC. Based on the
input word, the currents generated by number of current sources are properly switched and
summed at the output node. The current source can be realized either by using NMOS or
PMOS transistors. The simplest current source which corresponds to a LSB current source
as shown in Fig 4.2, is realized by a single transistor, biased with a fixed voltage to provide
constant current value. The other current sources are simply realized by using the required
number of transistors in parallel. For example, a current source which supplies 8 times
the current through the LSB source has 8 transistors in parallel. The current sources with
transistors connected in parallel are shown in Fig. 4.3.
27
VDD
M1
Vbias
I
RL
Figure 4.2: PMOS Current Source
VDD
IRef
I
RRef
I
I
I
2I
I
I
4I
I
8I
Figure 4.3: Current Sources with Parallel Transistors Connection
28
4.2.1
ILSB Selection
The selection of current for the LSB is very critical as it decides the power that is consumed
by the DAC and also affects the aacuracy and linearity of the DAC. There are parameters
like stability of supply voltage and temperature which contribute to variation in the chosen
current. So, there is a tradeoff that is to be affected between the power consumption and
performance of the DAC. One should choose minimum possible current so that variations
in current due to mismatch of various transistors and supply variations should be less than
current corresponding to 1/2 LSB, in the worst case of DAC operation.
The LSB current is, thus, has to be chosen carefully while considering the above factors
and the amount of power dissipation in DAC. The following thought process is adopted to
arrive at the minimum LSB current and the transistor size that can be used.
The technology used for this design is 0.18 µm technology. To have reasonable stability
and area for the DAC, the dimensions of the current source transistor have been chosen
corresponding to the minimum realizable values i.e. W = 0.36 µm and L = 0.18 µm. In
the proposed current mirror circuit, the variation in the supply voltage gets reflected as the
overdrive voltage (Vgs - VT ) and this in turn effects the current flowing through the circuit.
This calls for a very highly stabilised power supply.
Investigations have been carried out with different LSB currents and supply variations
through simulations using Synopsys H-Spice.
The input supply voltage is varied from 1.799 V to 1.801 V at a step of 1 mV and the
current sources are simulated to observe the output current variation. It is found that a
supply voltage variation of ±1 mV produces a change of current of about 0.8 µA when the
initial current is of the order of 1 µA, as shown in Fig. 4.4, 4.5, and 4.6. In the case of LSB
current of 1.5 µA, the maximum current variation is found to be more than 1 µA for ±1
mV of supply variation, as shown in Fig. 4.7, 4.8 and 4.9. In both the cases, the current
variation is more than 1/2 LSB. Since there are 256 equivalent transistors (current sources)
feeding the output in the worst case design, the variation in the output current should not
be more than 500 nA and 750 nA in case of LSB currents of 1 µA and 1.5 µA respectively .
In other words, the tolerable change in current due to supply voltage variations and ambient
conditions, should be less than 2 nA/transistor. To achieve this level of stability, the supply
voltage variation should be much less than 1 mV (Even 1 mV variation in 1.8 V supply
voltage is very tough to realize). Keeping all these factors in view, simulations are carried
out with LSB current of 2 µA and the obtained results are shown in Fig.4.10, 4.11 and 4.12.
29
600
Current Variation, nA
400
200
0
−200
−400
0
50
100
150
200
250
Current Output (0:255), uA
Figure 4.4: Current Variation (nA) of current sources at output currents ranging from 0 to
255 µA. LSB current is 1 µA and input supply is 1.8 V.
200
Current Variation, nA
0
−200
−400
−600
−800
0
50
100
150
200
250
Output Currents, (0:256 uA)
Figure 4.5: Current Variation (nA) of current sources at output currents ranging from 0 to
255 µA. LSB current is 1 µA and input supply is 1.799 V.
30
1000
Current Variation, nA
800
600
400
200
0
−200
0
50
100
150
200
250
Output Current (0:255), uA
Figure 4.6: Current Variation (nA) of current sources at output currents ranging from 0 to
255 µA. LSB current is 1 µA and input supply is 1.801 V.
Current Variation, nA
500
0
−500
−1000
0
75
150
225
300
375
Output Current (0:383), uA
Figure 4.7: Current Variation (nA) of current sources at output currents ranging from 0 to
383 µA. LSB current is 1.5 µA and input supply is 1.8 V.
31
400
Current Variation, nA
200
0
−200
−400
−600
−800
−1000
0
75
150
225
300
375
Output Current (0:383), uA
Figure 4.8: Current Variation (nA) of current sources at output currents ranging from 0 to
383 µA. LSB current is 1.5 µA and input supply is 1.799 V.
700
600
Current Variation, nA
500
400
300
200
100
0
−100
−200
0
75
150
225
300
375
Output Current (0:383), uA
Figure 4.9: Current Variation (nA) of current sources at output currents ranging from 0 to
383 µA. LSB current is 1.5 µA and input supply is 1.801 V.
32
1500
Current variation, nA
1000
500
0
−500
−1000
0
100
200
300
400
500
Output Current (0:512), uA
Figure 4.10: Current Variation (nA) of current sources at output currents ranging from 0 to
512 µA. LSB current is 2 µA and input supply is 1.8 V.
0
Current Variation, nA
−500
−1000
−1500
500
0
−500
−1000
−1500
0
100
200
300
400
500
Output Current (0:512), uA
Figure 4.11: Current Variation (nA) of current sources at output currents ranging from 0 to
512 µA. LSB current is 2 µA and input supply is 1.799 V.
33
1200
Current Variation, nA
1000
800
600
400
200
0
−200
0
100
200
300
400
500
Output Current (0:512), uA
Figure 4.12: Current Variation (nA) of current sources at output currents ranging from 0 to
512 µA. LSB current is 2 µA and input supply is 1.801 V.
With this current per transistor, the maximum change in current is found to be less than 1
µA i.e. 1/2 LSB.
Thus, the LSB current for this DAC is 2 µA, the transistors used have W = 1.6 µm, L =
0.18 µm and the supply voltage variation that can be tolerated is ±1 mV in 1.8 V.
4.2.2
DAC Current Source Segments
The stable current source of 2 µA has been generated using peaking current source as shown
in Fig. 4.13. Peaking current source enables realization of small currents with reasonably
small resistor values. It has been possible to get an output current of 2 µA with transistor
sizes of W = 1.6 µA and L = 0.18 µA, and resistor values R1 = 500 W, R2 = 2 kW and R3
= 4.2 kW. The supply voltage used is 1.8 V. This current source has itself been simulated
and checked for the stability of the current with respect to supply. This variation in output
current is sufficiently low (1/256 µA).
On the same lines, the source current of 32 µA is generated. These two current sources are
mirrored into segments -I and segments -II respectively to generate various current sources
for different outputs of DAC. The stable VDD has been generated using a highly stabilised
voltage reference. This design of the voltage reference with the interface (source follower)
34
VDD
ILSB
R1
R2
M2
M1
R3
Figure 4.13: Current Peaking Source
are dealt with in the next chapter.
In what follows is the description of the switches that are used in realizing current-steering
DAC.
4.3
Current Switches
A current source is supposed to supply current irrespective of the load connected. If the
current is to flow into the load, the current source should be connected to the load. When
it is not connected to the load, there is a need for diverting this current to some other sink.
In our case when the source current is not flowing in the load, it is diverted to ground,
thus ensuring that the current flowing through the source is always maintained. The circuit
diagram indicating the current steering or switching mechanism is given in Fig. 4.14 .
From the figure, it may be seen that there are 2 switches used, one ’M1’ for connecting the
current source to the load and the other ’M 10 ’ to ground. The switches are operated by the
corresponding bit in the input digital word and its compliment. If the bit is high ’1’, switch
M1 is on and switch M1’ receives the complement of the bit, namely ’0’ and it is put off.
35
VDD
Current
Source
Vbias
I
M1'
M1
Vbit
Vbit
Inv
ROut
RGND
Differential
Switch
Figure 4.14: A Differential Switch
36
The complement of the bit is derived by using an inverter as indicated in the Figure 4.12.
This ensures the diversion of the current to the load and simultaneously cutting off current
from the ground. When the input bit is low ’0’: M1 is off and M1’ is on, thus bringing down
the current to the load to zero value and the entire current then flows to the ground. This
mode of switching is known as differential switching.
One differential switch for each of the current sources, operated by the corresponding bits
in the input word is used. All the branches of switches namely M1, M2, ... MN are connected
to the load directly. The other branches of switches are connected to the ground through
M1’, M2’, ... MN’.
The widths of the transistors are kept to a minimal value possible so that the speed of
switching can be improved. Since the larger width transistor has more gate-drain capacitance, it takes time for the switch to completely steer the current to either of the node. Hence,
to decrease the internal capacitance of the transistor and improve the speed of switching,
transistors with the width 0.6 µm are used.
This scheme ensures that there is no change in the current flowing through each of the
current sources from one digital word to another.
4.3.1
CMOS Inverter
As the inverter that has been used to obtain the complement of the bit is CMOS inverter as
shown in Fig. 4.15. It is the usual CMOS inverter with PMOS as load and NMOS as active
device.
The inverter itself has some amount of delay while propagating the signal from its input
to the output and this delay should be as small as possible to improve the speed of the
DAC without degrading its accuracy. It has been found that the width of the inverter
transistor is dependent on the width of the transistors in differential switch. As the width of
the switched transistor is increased at higher currents, the inverter transistor width is also
increased to minimize the propagation delay of the inverter. The widths of switches and
inverter transistors for 8 input bits are given in Table 4.1.
This arrangement also ensured that glitches due to delay between input bit signal and its
inverted signal, are reduced. In this 8-bit DAC, 8 CMOS inverters are used. Since input bit
voltage, when high is 1.8 volts, the VDD of every inverter is also 1.8 volts. The width of the
PMOS transistor has been taken as 2.5 times the width of NMOS transistor. The minimum
width of the NMOS transistor in inverter is 3 µm and the propagation delay of each inverter
37
VDD
MP
Vin
VOut
MN
Figure 4.15: An CMOS Inverter
Table 4.1: Transistor Widths for Switch Transistors and Inverter Transistors (NMOS) for 8
input bits
Bits Switch Transistor
Inverter NMOS Transistor
Widths (µm)
Widths (µm)
b0,4
0.6
3.0
b1,5
1.2
6
b2,6
2.4
12
b3,7
4.8
24
38
is less than 2 ns.
4.4
Glitches
The definition of glitch with reference to the output of the DAC is given in chapter 2.
Glitch is unintended excursion in the output of a DAC and affects the performance of the
DAC in terms of its speed and accuracy. A glitch can appear on the output during a code
transition. Ideally, when a DAC output changes it should move from one value to its new
one monotonically. In practice, the output is likely to overshoot, undershoot, or both. This
uncontrolled movement of the DAC output during a transition can arise from the following
mechanisms:
ˆ During switching phase a significant voltage variation will occur at the drain of the
PMOS current source causing it go out of saturation region. This can cause the unit
current to change and cause glitch related distortion. Therefore, as described in section
4.3 , differential switching is used to avoid large voltage fluctuations at the drain during
switching.
ˆ The delay in control signals at the transistors M and M’ of differential switches can
lead to large glitches and eventually to a major degradation in speed of DAC. It is
necessary that the control signals should be properly synchronized and they should be
available without any delay. To minimize the delays between the input bit signal and
its inverted signal, propagation delay of inverter is improved by matching the width of
the inverter transistor in correspondance to the width of the switches as mentioned in
section 4.3.1.
ˆ The coupling of the switching control signals to the output lines through the parasitic
gate-drain capacitance of the switching transistors is also a major source of glitches.
To improve the accuracy and remove these unwanted signals, filters can be used to
minimize these glitches. Various filter designs are used to understand their affect on
the performance of the DAC.
The complete design of DAC with integrated power supply has been simulated and glitches
are recorded at the output of the DAC, for various filter designs. The output of the DAC is
read only after DAC output settles (i.e. glitch dies off).
39
1. Simple resistive load: This is the case without any filter. Maximum glitches are observed at the output. The glitches waveform is shown in Fig. 4.16.
600u
400u
Currents (lin)
200u
0
-200u
-400u
-600u
0
200n
400n
600n
Time (lin) (TIME)
Figure 4.16: Glitches at the output of DAC, using resistive load
2. Capacitor filter: The use of capacitor at the output filters the unexpected spikes and
glitches get minimized at the output. However, a large capacitor has to be used and
this affects the settling time of the DAC as the capacitor takes time to charge. Hence
a compromise between speed and accuracy has to be made to suit the requirements of
the designer.
The glitches waveforms using capacitor of 8 pF and 16 pF at the output have been
shown in Fig. 4.17 and Fig. 4.18 The settling time of the DAC with 8 pF capacitor is
found to be 4 ns, and with 16 pf capacitor, it is 10 ns.
3. RLC filter: RLC filter is connected at the output of the DAC and the amplitude of
the glitches are observed. From the observation of the waveform shown in Fig. 4.19 ,
it is clear that this filter has been found to minimize the glitches at the output. The
maximum speed of the DAC is also maintained at 500 MHz using this type of filter.
The performance of the integrated DAC has been evaluated through simulations. The
various parameters measured are described in the next section.
40
500u
Currents (lin)
400u
300u
200u
100u
0
0
200n
400n
600n
Time (lin) (TIME)
Figure 4.17: Glitches at the output of DAC, using 8pf Capacitive Filter
500u
Currents (lin)
400u
300u
200u
100u
0
0
200n
400n
600n
Time (lin) (TIME)
Figure 4.18: Glitches at the output of DAC, using 16pf Capacitive Filter
41
500u
Currents (lin)
400u
300u
200u
100u
0
0
200n
400n
600n
Time (lin) (TIME)
Figure 4.19: Glitches at the output of DAC, using RLC Filter
4.5
Performance of DAC
The entire DAC including the power supply has been integrated and simulated using Synopsys H-Spice. Its characteristics have been measured and are given in Table 4.2. It may be
seen that this DAC has acceptable characteristics of speed and accuracy. The power that
is consumed by this DAC is also lower than most of the available DACs. Further voltage
sensitivity is such that it can tolerate ±2% of 5 V at the input without any deterioration in
the performance.
The characteristics (INL, DNL, Settling Time) have been measured at different input
rates. It has been found that the performance (from the point of above parameters) has
been satisfactory, upto a speed of 500 M Hz. The input supply voltage to the DAC is 5 V
±0.1 V with a total current drawn by the system is about 2.6 mA. Thus, the power drawn
by the integrated DAC is about 13 mW . This power is almost constant over the frequency
(500 M Hz) of operation as the current drawn by the DAC is almost constant.
At the maximum input rate of 500 M Hz, INL accuracy as can be seen in the Fig. 4.20
is within the range ±0.5 LSB and the DNL accuracy is around ±0.8 LSB, as shown in Fig.
4.21 for all the 256 input words. To measure the INL, 256 input words are given as stimulus
42
Table 4.2: DAC Performance Summary
Resolution
8-bit
Update Rate
500 M Hz
INL
±0.49 LSB
DNL
±0.8 LSB
Full Scale Output Current
519.88 µA
Supply Voltage
5 V ±2%
Total Power Consumption
13 mW
Technology
UMC 0.18 µm
to the DAC starting from 0000 0000 to 1111 1111. The output current is obtained for each
input word and is subtracted from the expected current value to obtain the INL value which
is then normalized in terms of LSB. To measure DNL, difference of two output currents for
two adjacent input words is calculated and then subtracted from 1 LSB of current to obtain
the DNL which is then normalized in terms of LSB.
The INL and DNL of the DAC are measured and verified over the supply variations of
±0.1 V in 5 V. The input voltage is changed to 4.9 V and the complete simulations with 256
input words are carried out to measure the INL and DNL. It may be seen from Fig. 4.22
that the INL is within the limits of 0.5 LSB and DNL is less than 1 LSB. Similarly, input
supply voltage is changed to 5.1 V and the measured INL and DNL are shown in Fig. 4.23.
In this case also, INL and DNL are within the limits. Thus, the output of the DAC provides
accurate outputs within the limits of INL and DNL for a supply variation of ±0.1 V.
Since INL is less than 0.5 LSB, DAC output is also monotonic in nature for all the 256
input words. Monotonocity of DAC output current can be seen from Fig. 4.24. The accurate
reading of 256 output values at a maximum update rate of 500 M Hz, thus, also confirms
that the DAC works satisfactorily upto 500 M Hz with 8-bit resolution.
Performance of this proposed DAC has been compared with previous published works
(mentioned in chapter 3), and with the high speed DACs available in market. The comparison
has been indicated in Table 4.3. The listed parameters are the bit resolution, maximum
speed of operation, the power dissipation, INL, DNL, and the technology used. Some of the
parameters are missing because they are not listed in the published work and data sheets.
It may be seen that the proposed DAC has very low power dissipation (13 mW) at the
maximum speed of 500 MHz as compared to other DACs. In case of [3, 7], the power
43
INL (LSB)
0.5
0
−0.5
0
50
100
150
200
250
Input Words [0:255]
Figure 4.20: INL Accuracy of 8-Bit DAC
1
0.8
DNL (LSB)
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
0
50
100
150
200
Input Words [0:255]
Figure 4.21: DNL Accuracy of 8-Bit DAC
44
250
1
INL, DNL (LSB)
INL
DNL
0.5
0
−0.5
−1
0
50
100
150
Input Words [0:255]
200
250
Figure 4.22: INL, DNL Measurement of 8-Bit DAC at 4.9 V input supply for 2 µA LSB
1
INL
DNL
0.8
INL, DNL (LSB)
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
0
50
100
150
200
250
Input Words [0:255]
Figure 4.23: INL, DNL Measurement of 8-Bit DAC at 5.1 V input supply for 2 µA LSB
45
DAC Output Current (uA)
600
500
400
300
200
100
0
50
100
150
200
250
Input Word (0:255)
Figure 4.24: Monotonic Plot of DAC Output Current for 256 input words
consumption is higher even with the use of low feature size transistors. The 8-bit high speed
DAC [18] based on SiGe technology consumes lot of power i.e. 2.5 W. The 8-bit high speed
DACs presently availble in the market from various chip makers, have the maximum speeds
upto 200-330 MHz with much larger power consumptions.
4.6
Summary
This chapter describes the architecture of the DAC and the description of the various component blocks and their designs. As mentioned earlier, the performance of this DAC depends
to some extent on the integrated power supply. The design methodology of this power supply
is dealt with in next chapter.
46
b7
b6
ROut
RGND
b5
b4
b3
b2
b1
b0
VDD
Figure 4.25: Circuit Diagram of 8-Bit Current Steering DAC with Integrated Power Supply (IPS). IPS with Source Follower (BLUE), CURRENT SOURCE SEGMENT-I and
SEGMENT-II (RED), Switches (YELLOW) with Termination Resistances of 50W each.
47
Table 4.3: Comparison with other available DACs
Resolution Speed Power Consumption
INL
DNL
Technology
(Bits)
(MHz)
(mW)
(±LSB)
(±LSB)
This work
8
500
13
0.5
0.8
0.18-µm CMOS
[3]
10
250
22
0.1
0.1
0.18-µm CMOS
[7]
10
1000
23
-
-
90-nm CMOS
[10]
10
1000
49
-
-
90-nm CMOS
[14]
10
2000
790
0.6
0.6
0.35-µm CMOS
[18]
8
20000
2500
-
-
0.25-µm SiGe
AD9748 [41]
8
210
135
0.1
0.1
-
ADV7125 [42]
8
330
>30
1
1
-
THS5641A [43]
8
100
100
1
0.5
-
DAC908 [44]
8
200
170
0.5
0.5
-
MAX5852 [45]
8
165
74
0.25
0.15
-
48
Chapter 5
Internal Power Supply
This chapter is devoted to describe the design of power supply, integrated with 8-bit digital
to analog converter. The design of power supply includes a highly stable voltage reference
circuit and an interface to provide the stabilized supply voltage to the DAC. Due to the
stringent requirements for supply voltage stability to maintain linearity at the DAC output,
the voltage reference has been carefully designed and simulated.
In this chapter, the voltage reference circuit is described in detail which employs a feedback
control technique to achieve a stable reference voltage. It has a facility to obtain any reference
voltage in the range of 0.7 V to 2.6 V with high stability. As an example, it has been shown
through simulations that a voltage reference for 0.73 V with a temperature stability of about
1 ppm/‰ over the temperature range of 0 to 80‰ is possible. Later, these concepts have been
extended to arrive at a design which provides a reference voltage of 2.6 V with temperature
stability of 3.2 ppm/‰. This stability is found to be sufficient for the proposed integrated
DAC. Proposed voltage reference circuit is simulated using transistor models of 0.18 µm
CMOS process.
5.1
Voltage Reference - Background
Voltage references are needed to stabilize the power supplies against variation of voltage and
temperature. Several voltage references have been reported in literature. The most famous
one is zener diode based reference, which is based on the breakdown voltage of junction diode
(normally known as zener diode). This breakdown voltage depends on the conductivity of
the p and n regions of the diode and the lowest value is around 2 V. Further, this voltage
49
is sensitive to temperature. The forward voltage drop of a junction diode is fairly constant
above a certain minimum current through it and hence it may be used as a voltage reference.
This forward voltage depends on the semiconductor and it is about 0.7 V for silicon diode,
0.2 V for germanium diode and 0.4 V for GaAs diode. However, all of them are highly
sensitive to temperature.
There is a popular reference which is stabilized against variations of temperatures and
supply voltages. This is known as bandgap reference [46]. This voltage reference uses silicon
diodes and requires an ideal operational amplifier as main components. This reference gives
good stability and the reference voltage is about 1.2 V, the bandgap of silicon. This reference
gives a general stability of the order of 25-50 ppm/‰ over a narrow temperature range [47].
With the advances in fabrication processes, VLSI circuits use devices with smaller feature
sizes (usually mentioned as 180 nm, 90 nm and so on) and are operated with lower supply
voltages (0.8 V for 45 nm). Hence there is a need for references with voltages less than 1.2
V. Further, some of the present day circuits like D/A converters are designed with higher
resolutions such as 12 bits. If an accuracy of at least 1/2 LSB has to be maintained, then
power supplies with much higher stability than that of conventional bandgap references are
needed (based on preliminary simulations).
In this regard, a voltage reference with a curvature compensation technique based on
subtraction of two first order bandgap reference currents, was proposed by Ker et al [48] to
provide a low output voltage of around 0.55 V with a temperature coefficient of about 19.5
ppm/‰. Also, a voltage reference circuit reported by Dong et al [49] shows a high stability
with respect to supply variations. The circuit uses the feedback technique to compensate
the supply variations and provides a supply independent threshold-referenced low voltage
of about 0.5 V. However, it is found that these circuits still have inadequate stability with
respect to temperature variations and cannot be used as a precision voltage reference.
5.1.1
Conventional Bandgap Reference
In conventional bandgap reference circuit [50], an ideal operational amplifier OP1 along with
two silicon bipolar junction transistors (BJTs) with different emitter areas are used, as shown
in Fig. 5.1. It is shown thatVREF is given by,
VREF = VBE2 +
kT
R3
(1 +
)lnN
q
R2
50
(5.1)
where k is Boltzmann’s constant (1.38 ∗ 10−23 J/K), q is electronic charge (1.6 ∗ 10−19 C),
T is absolute temperature, and N is the emitter-area ratio of the BJTs.
The temperature stability in this circuit is achieved by compensating the negative temperature coefficient of VBE2 with positive temperature coefficient of the second term (kT/q). In
principle, temperature variations can be compensated over a fixed temperature range within
tolerable limits of the VREF . In general, it turns out that VREF is around 1.2 V.
Vdd
M2
M1
I1
I2
R1
VREF
R2
OP1
R3
VBE1
VBE2
Figure 5.1: Conventional Bandgap Reference Circuit
In this kind of reference, stability is poor due to the mismatch of MOS transistors M1M2, improper realization of ideal operational amplifier and only the first order temperature
compensation through linear (kT/q) term [2]. Moreover, stable output voltage is restricted
to the value of about 1.2 V, which makes BGR inadequate for low voltage ICs.
In view of this, a new architecture for a reference circuit is designed which is based on
correcting the variation of reference voltage with temperature through a feedback mechanism.
Further, the proposed architecture enables one to set the reference voltage at any specified
value in a range of 0.7 V to 1.4 V. The temperature stability that may be achieved with this
design is of the order of a few ppm/‰.
The later sections explain the principle of operation of the proposed circuit and the method
of designing the circuit with practically realizable components. This chapter also indicates
51
the method to extend the reference voltage range beyond 0.7 V to 1.4 V. Moreover, a discussion has been included in a separate section to indicate the various issues and modifications
related to the proposed circuit design.
5.1.2
Proposed Voltage Reference
The circuit diagram of proposed voltage reference is shown in Fig. 5.2. It consists of:
1. A constant current source,
2. A voltage reference generator and,
3. A control circuit.
Current
source
Control circuit
VDD
R5
M1
Vg
R6
Vz
R7
VF
VREF
R1
R2
VBE2
R4
R3
OP1
VBE1
OP3
VA
R3
OP2
R4
D1
D2
Voltage reference
generator
Figure 5.2: Proposed Voltage Reference Circuit
The constant current source is essentially an NMOS FET M1 which is operated in the
saturation region. The voltage reference generator consists of two bipolar junction transistor
(BJT) based diodes D1 and D2 with two resistors R1 and R2 , connected as shown in Figure
52
2. This part of the circuit has a dual purpose of providing the reference voltage VREF and
serving as a temperature sensor.
The control circuit consists of a zener diode with breakdown voltage VZ and the potential
divider through which one can obtain the required reference voltage. The control circuit also
senses the temperature through the voltage difference between the diode drops (VBE1 -VBE2 )
that vary with temperature, which is further amplified with the help of differential amplifier
OP3. This information is then made use of to adjust the current through the current source
in order to keep the reference voltage at a constant value. In what follows is a detailed
explanation of the principle of operation of this variable voltage reference.
5.1.3
Principle of Operation
The required reference voltage is generated by injecting a certain amount of current from the
current source into the voltage reference generator circuit. This circuit contains two BJT
diodes also serving as temperature sensor to develop a small differential voltage (VBE1 -VBE2 )
depending on the variation in temperature. This temperature dependent voltage is amplified
and used to control the injected current to achieve stable reference voltage with respect to
temperature variations.
The current source is realized by operating NMOS M1 at a specific gate source voltage (Vg
-VREF ) depending on the required reference voltage. M1 has to be operated in saturation
region to provide a constant current, I.
The current, I, required for a particular reference voltage is passed through the voltage
reference generator and the reference voltageVREF is given by
VREF = I1 R1 + VBE1
(5.2)
VREF = I2 R2 + VBE2
(5.3)
I = I1 + I2
(5.4)
VBE1 , VBE2 , R1 , R2 , I1 and I2 vary with temperature and hence the current, I. This
change in I with temperature is compensated through the control circuit.
The control circuit consists of a differential amplifier OP3 with resistor R3 of 1 kW and
a variable resistor R4 . OP1 and OP2 are unity gain buffers to prevent loading of the input
53
impedance of the differential amplifier. A zener diode (zener voltage VZ of 2.4 V) is connected
between the supply voltage V DD of 2.5 V and the output of the amplifier VA , through resistor
R5 of 100 W variable resistor R7 and a fixed resistor R6 of 1 kW are connected across the
zener diode. The gate voltage Vg , required for specific reference voltage VREF , is set by
choosing a fixed voltage VF (derived from VZ ) along with the output of the amplifier, VA .
The required variation in Vg to get the required variation in current I with temperature,
is obtained through the variation of the input to the amplifier, (VBE1 -VBE2 ). This input
voltage variation is amplified and used to obtain the required variation in current, I. Thus,
the feedback circuit is used to generate appropriate variation in current, I so that negative
TC of diodes gets compensated. This results in a reference voltage with high stability against
temperature variations.
5.1.4
Design Methodology
The saturation current of the diode D1 is chosen to be ’14 ∗ 10−15 A’ and that of D2 as
’2 ∗ 14 ∗ 10−15 A’. The value of R1 is 7 kW and R2 is 5 kW at room temperature. After
fixing the parameters and values of the components in the voltage generator, the (I-V)
characteristics of the diodes (D1, D2) are generated using H-Spice. I1 , I2 ,VBE1 and VBE2 are
determined for a given reference voltage at room temperature from Eqs. (5.2) and (5.3) in
conjunction with obtained I-V characteristics of diodes. Then, the current I to be supplied
by the current source, is arrived at from Eq. (5.4). The gate voltage Vg needed to obtain a
current I is calculated from the Eq.
1
W
I = µCox (Vg − VREF − VT H )2
(5.5)
2
L
where µ is the mobility, Co x is gate oxide capacitance, W is width and L is length of the
transistor M1 and VT H is its threshold voltage. This Vg is realized in two parts i.e. fixed
voltage VF and output voltage of the amplifier. Thus the value of Vg may be represented as
Vg = A(VBE1 − VBE2 ) + VF
(5.6)
where the gain of the differential amplifier A, and the voltage VF are given by
A=
R4
R3
54
(5.7)
R7
VZ
(5.8)
R6 + R7
have been obtained for a specific reference voltage,
VF =
Since, the values of VBE1 and VBE2
their temperature variations have been obtained using simulations and hence, the variation
of (VBE1 -VBE2 ) with temperature. The temperature variation of I1 , I2 and I can be obtained
from Eqs. (5.2), (5.3) and (5.4) respectively. Further, taking variation of threshold voltage
VT H , with temperature into account [51], variation of gate voltage Vg with temperature is
obtained using Eq. (5.5). As it may be seen from Eq. (5.6), one can have different A and
VF for a particular Vg , at any temperature. For chosen values of A and VF corresponding to
a value of Vg , resistance values R4 and R7 are arrived at through Eqs. (5.7) and (5.8). This
procedure is adopted to obtain various reference voltages in the range of 0.7 V to 1.4 V.
The detailed procedure followed to arrive at the value of gain A and voltage VF is illustrated
below through the design of 0.73 V voltage reference.
5.1.5
Typical 0.73 Reference Voltage
This section describes the design of a typical voltage reference namely 0.73 V. The (I-V)
characteristics of BJT diodes are obtained through simulations and the values of I1 , I2 are
found to be around 26 µA and 37 µA respectively from Eqs. (5.2) and (5.3). Value of current
I is 63 µA through Eq. (5.4). The gate voltage Vg is obtained using Eq. (5.5) where various
process parameters such as µ, Cox are taken from 0.18 µm BSIM3 model, and value of W/L
= 200µ/14µ. The threshold voltage VT H of transistor M1 is about 0.4 V. The gate voltage
Vg is thus obtained as 1.3 V. Through simulated temperature variations of VBE1 and VBE2 ,
temperature variations of I1 , I2 , I, and Vg are obtained from Eqs. (5.2), (5.3), (5.4) and
(5.5) respectively.
For any given temperature, Vg is fixed and it can be obtained for various values of A and
VF , satisfying the Eq. (5.6). It may be seen that the relation between A and VF for a given
temperature is a straight line. Fig. 5.3 describes variation of (A vs VF ) for temperatures
between 0 and 80‰.
In Fig. 5.3, graphs (A vs VF ) for different temperatures, converge at a point where gain
variations are minimal with respect to temperature variations. Therefore, VF has been chosen
at this point. The required variation of gain with temperature has been found from Eq. (5.6),
knowing the value of Vg with temperature. A typical variation in gain with temperature for
55
200
0°C
20°C
40°C
60°C
80°C
Gain, A
150
100
50
0
0
0.2
0.4
0.6
0.8
VF (V)
1
1.2
1.4
Figure 5.3: Plot between gain, A and voltage, VF for different temperatures.
a reference voltage of 0.73 V and VF of 1.25 V is shown in Fig. 5.4. Since the variation of
gain with temperature is marginal (6.67 to 6.59 over temperature range of 0 to 80‰), the
required gain is taken as 6.65 which has been realized with R4 equal to 6650W. R7 is obtained
as 1100W for VF equal to 1.25 V using Eq. (5.8).
5.1.6
Results
The proposed circuit is designed and simulated in H-Spice using BSIM3 model of 0.18 µm
technology. The variation with temperature of all the components is taken into account
without any exception. The variation in the reference voltage with temperature for the 0.73
V reference is shown in Fig. 5.5. It may be seen that the reference voltage variation with
temperature is less than 60 µV over the temperature range 0 to 80‰, at a constant supply
voltage of 2.5 V. This indicates a temperature stability of about 1 ppm/‰. When the supply
voltage is varied by ±0.1 V, the reference voltage variation is less than ±1 mV.
For other reference voltages, gain of the amplifier and voltage VF are set by varying the
resistors R4 and R7 and simulations are carried out. It has been possible to get any voltage
reference with low TC and high stability over supply variations. The maximum variations
56
6.75
gain, A
6.7
6.65
6.6
6.55
0
20
40
temperature (°C)
60
80
Reference voltage (V)
Figure 5.4: Variation of gain (A) with temperature, for VF = 1.25 V
0.72982
0.72981
0.72980
0.72979
0.72978
0.72977
0.72976
0
20
40
Temperature (°C)
60
Figure 5.5: Variation of 0.73V reference voltage with temperature.
57
80
with temperature for different reference voltages in the range of 0.7 V to 1.4 V are shown
in Table 5.1. The values of R4 and voltage VF needed for various reference voltages are also
mentioned.
Table 5.1: Summary of various reference voltages
Reference Voltage
TC
R4
VF
VREF , (V)
(ppm/‰)
(W)
(V )
0.7
3.23
7100
1.2
0.73
1.04
6650
1.25
0.8
5.52
5300
1.36
0.9
8.15
4700
1.51
1.0
8.3
4800
1.65
1.1
7.7
5400
1.77
1.2
6.9
6250
1.9
1.3
6.44
7250
2.0
1.4
5.13
8500
2.13
2.6
3.2
18600
3.25
(VDD = 5 V)
It may be observed from the results obtained that various reference voltages have low TCs
and are realizable with reasonable values of gain of the differential amplifier, thus avoiding
the use of ideal amplifier in the circuit.
Further, the performance of the proposed voltage reference is compared with other recently
reported references and is indicated in Table 5.2. It can be seen that this work achieves the
lowest temperature coefficient of 1.04 ppm/‰ for 0.73 V reference voltage.
5.1.7
Discussions
It may be seen that the feedback circuit in Fig. 5.2 can be used to realize voltage references
with high stability. It is shown in Table 5.1 that the maximum stability is obtained with
0.73 reference voltage. When the same circuit is used to obtain other reference voltages by
changing only the current through the transistor M1, the temperature stability has deteriorated up to a maximum of 8.3 ppm/‰ for 1 V reference voltage. However one may fine
tune the circuit by modifying the component values of R1 , R2 , R4 and R7 to obtain better
58
Table 5.2: Comparison of Voltage Reference Designs
This Work Tam
Gomez
Leung
De Vita
Leung
et. al [52]
et. al [53]
et. al [54]
et. al [55]
et. al [56]
0.18-µm
0.18-µm
0.18-µm
0.6-µm
0.35-µm
0.6-µm
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
2.5
1.8
1.4
2
3
1.5
0.73
0.658
1.012
1.14
0.891
1.252
TC (ppm/‰)
1.04
5.36
4
5.3
12
14.36
Line Regulation
0.7
5.8
0.6
1.43
4
5.5
Technology
Supply Voltage
(V)
Reference Voltage
VREF (V)
(mV/V)
stability than one could get with this circuit. In fact, in the case of 1 V reference voltage,
temperature stability has been improved to 5 ppm/‰ by modifying the values of R1 , R2 and
R4 . Thus, it may be seen that a feedback reference circuit meant for particular reference
voltage with maximum stability may not give the same order of stability for other reference
voltages but it can be designed to achieve good stability by fine tuning all the components.
It appears that this circuit is limited to a reference voltage range between 0.7 V and 1.4
V. The limitations are due to the diode forward voltage drop and the supply voltage. With
silicon diodes as used in this case, the lowest reference voltage that can be obtained is about
0.7 V. The maximum reference voltage that can be obtained is limited by the supply voltage
and overdrive voltage of the transistor M1. In this case, it happened to be 1.4 V. This
reference voltage can be increased to higher value by increasing the supply voltage and the
desired stability can be obtained by fine tuning the resistors. It has been found that a
high reference voltage of 2.6 V can be obtained with a supply voltage of 5 V
with high stability.
Since there is still a need to develop voltage references for smaller voltages than 0.7 V with
high order of stability, they may be realized by replacing the silicon diodes with germanium
based diodes [57] or schottky diodes [58] of lower forward voltage drops.
There is another modification that is possible in the control circuit. The three operational
amplifiers OP1, OP2 and OP3 along with the associated resistors can perhaps be replaced by
simple single stage differential amplifier which can provide the required high input impedance
59
and reasonable output impedance. This aspect is to be carefully looked into from the point
of achieving required stability.
The voltage reference circuit in Fig 5.2 is not completely based on single technology like
CMOS technology. At present it uses bipolar junction diodes and zener diode along with
NMOS transistor. Therefore one may have to go for BiCMOS process or search for diodes in
MOS technology like source-drain-substrate junctions and parasitic transistors and examine
their suitability for this purpose.
Future work will be on realizing this reference circuit with CMOS technology by exploiting
parasitic bipolar elements available in this.
5.2
Interface Design
In chapter 4, it is described that the 8-bit DAC is highly sensitive to supply voltage variations
and the supply voltage should be regulated within the limits of 0.1 mV to maintain high
linearity of DAC. Thus, to achieve the stability of this order, a voltage reference design is
proposed and described in the section 5.1. The voltage reference can achieve a very high
stability of upto ±1 mV over ±0.1 V variation in supply voltage. One may try to design
the voltage reference to obtain 1.8 V directly and apply it to the DAC. However, DAC while
operating at 1.8 V input voltage requires a constant current of 1.78 mA and this current
requirement is difficult to obtain directly from the voltage reference. Therefore, an interface
between voltage reference circuit and DAC is required to provide specified reference voltage
and required current for the operation of the DAC.
Due to these reasons, a source follower ”buffer” is introduced as an interface for the
integration of DAC and the reference circuit. This section describes the design of the interface
and design issues.
5.2.1
Source Follower
The circuit diagram of source follower is shown in Fig. 5.6, where V DD is the supply
voltage, M1 is NMOS transistor, Vin is the reference voltage and Vout is the output voltage
to be provided to the DAC.
The circuit is simulated to obtain the constant voltage of 1.8 V with V DD of 5 V and
the resistor Rs of 30 kW. This value of resistance is chosen to be used to obtain the required
current of 1.78 mA for DAC. Smaller value of resistors could be used. However, the power
60
VDD
M1
Vin
Vout
Io
Rs
Figure 5.6: Source Follower
consumed by source follower itself increases. The source follower has been designed with Rs
= 30 kW. This called for an input gate voltage of 2.6 V which has been derived from the
voltage reference. This ensures that the NMOS transistor works in saturation region keeping
the output current constant.
The DAC has been connected to the output terminal of the source follower and effects
of supply voltage variation on output voltage and the current drawn by the DAC (Io ) have
been measured and are indicated in Table 5.3. In addition to this, the maximum analog
output current (IoDAC ) from the DAC corresponding to the input word 1111 1111, is also
measured and given in the table.
Table 5.3: DAC Performance Measures at different corners of Source Follower
Min
Typ
Max
V DD, V
4.9
5.0
5.1
Vin , V
2.685
2.686
2.687
Vout , V
1.799
1.8
1.801
Io , mA
1.783
1.786
1.79
IRs , µA
59.96
60.04
60.12
IoDAC , µA
518.88
519.88
520.89
From the table, it may be seen that the output voltage varied by ±1 mV . The maximum
61
variation in DAC output current (IoDAC ) is ±1 µA which is less than 0.5 LSB. The current
drawn by the DAC (Io ) itself varies by about ±3 µA indicating that the power consumption
does not change much with the supply variation.
5.3
Summary
This chapter describes the design of highly stabilized power supply with input supply voltage
of 5 V ±2%. The output of the power supply is 1.8 V ±1 mV and is capable of driving a
constant load current of 1.78 mA. The power supply essentialy consists of a voltage reference
circuit which is designed to give 2.6 V and a source follower interface circuit which can
deliver 1.78 mA at 1.8 V ±1 mV. Using this power supply, the DAC has been tested and
the simulation results have been given in the previous chapter 4.
62
Chapter 6
Conclusion
It is known that realising low power, high speed and high accuracy DACs is still a problem.
The main sources of errors are due to the instability of supply voltage. For example, in high
resolution (8-Bit), low power DACs as described in this thesis, the power supply variations
that could be tolerated are in the range of ±0.02% of 5 V. It is very difficult to supply a
DAC direcly an input voltage which is stable to this level. Therefore, it is thought that a
stable power supply can be built along with the DAC which can provide the required voltage
stability. The input to this power supply can be perhaps of slightly poorer quality.
In view of this, DAC with integrated power supply has been proposed, implemented and
reported in this thesis. This DAC with integrated power supply has the following features.
It is a 8-bit current steering DAC with segmented architecture: One segment catering to
4 MSBs and other to 4 LSBs. The current drawn by the DAC is almost constant for all the
digital words that are to be converted. The power drawn has been kept to minimum due to
the low LSB current of 2 µA.
The power to the DAC (for both the segments) has been provided by the internal power
supply. This power supply consists of highly stabilized voltage reference and a source follower
interface both operated by a DC power supply of 5 V ±2%. The output of the internal power
supply is 1.8 V ±1 mV and supplies a current of 1.78 mA. The high stability of the power
supply has been achieved by proposing and developing a voltage reference similar to bandgap
reference with additional feedback mechanism. The voltage reference designed is capable of
providing 2.6 V ±1 mV . This ensures that the integrated DAC is capable of working with
a supply voltage whose variation can be ±0.1 V in 5 V. This reference itself is not directly
loaded and is connected with the DAC through the source follower interface, which provides
63
the enhanced current needed by the DAC.
The DAC characteristics (DNL, INL, settling Time) have been measured at different input
rates. It has been found that the performance (from the point of above parameters) has been
satisfactory, upto a speed of 500 M Hz. The power drawn by the integrated DAC is 13 mW .
This power is almost constant over the frequency of operation as the current drawn by the
DAC is almost constant. It is also found that this DAC along with the integrated power
supply consumes very less power at high speed of operation as compared to other available
DACs in the market, and the DACs described in published literature.
This thesis reports the possibility of designing an integrated DAC with reasonably low
power dissipation, high frequency of operation and good linearity. The design of the highly
stabile voltage reference has led to the development of a design procedure to generate voltage
references in the range of 0.7 V to 2.6 V, with temperature stability of the order of few ppms.
The earlier voltage reference circuits are of discreet values whereas this voltage reference can
provide any voltage that may be needed.
The lower end of 0.7 V can be further lowered to 0.3V by using schottky diodes which
can have lower forward voltage drop, in this voltage reference design. This is the order
of reference voltage needed for the present day VLSI circuits based on nanometer feature
size devices and also for low power VLSI designs. Thus, the thesis provides a design
procedure for low power DAC with integrated power supply, and a continuously
variable voltage reference over a range of 0.3 V to 2.6 V.
This structure of integrated DAC has to be realized in silicon which calls for: layout of the
various components and looking into the issues that may arise because of the power supply
and DAC to be built on the same substrate. Since the simulation has been carried out in
0.18 µm technology devices, there may be a possibility of reducing the power and area of
the DAC if one adopts the lower feature size technologies such as 65 nm, 45 nm.
64
Publications
1. Anshul Agarwal and Satyam Mandavilli, Variable Voltage Reference using Feedback Control Technique, in the proceedings of IEEE Asia Symposium on Quality
Electronic Design (ASQED 2009), Kuala Lumpur, Malaysia, 15-16 July 2009.
2. Anshul Agarwal, Madhava Kumar and Satyam Mandavilli,A 1 ppm/‰Voltage Reference in the range of 0.73V to 1.4V, (IEEE NEWCAS-TAISA 2009), Toulouse,
France, 28 June- 1 July 2009.
3. Anshul Agarwal and Satyam Mandavilli, Feedback Controlled Variable Voltage
Reference using Schottky Diodes, in the proceedings of International Conference
on Mechanical and Electronics Engineering (ICMEE 2009), Chennai, India, 24-26 July
2009.
65
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