8th WSEAS International Conference on POWER SYSTEMS (PS 2008), Santander, Cantabria, Spain, September 23-25, 2008
Improving Dynamic Performance of a Segmented Current-Steering
Digital-to-Analog Converter
LUCIAN JURCA1, CONSTANTIN VOLOSENCU2, MIRCEA TOMOROGA1, IOAN FILIP2
1
Faculty of Electronics and Telecommunications Engineering
2
Faculty of Automation and Computer Science and Engineering
“Politehnica” University of Timisoara
B-dul Vasile Parvan nr.2, Timisoara
ROMANIA
Abstract: - In this paper we present an optimized structure of a 10-b current-steering digital-to-analog converter (DAC)
with very good dynamic performance, especially regarding spurious-free dynamic range (SFDR). To reduce the
influence of matching errors, an appropriate dynamic element matching (DEM) technique was implemented and
OrCAD simulations were used to confirm more realistic improvements than in related works.
Key-Words: Spurious-free dynamic range, dynamic element matching, current-steering DAC.
is to use the thermometer code, as in [3], [4], [6], [7], [8]
and in our case, but there are other redundant codes as
well [3]. In fact all these works adopted segmented
architectures where the dynamic randomization or, more
exactly, the pseudo randomization was made inside the
most significant segment only. This segment was built
with unary current sources (unit elements) while the
least significant part was designed with binary-weighted
current sources. Adopting partial randomization and not
full randomization happened because the area of the
circuitry grows exponentially with the number of
scrambled bits.
Typically, the full-randomization techniques are used
in lower-bit DACs and for example in the feedback
DACs in sigma-delta ADCs. Only few works discuss or
implement the full randomization for Nyquist-rate data
conversion [3], [4], but there the number of input bits is
still limited.
In this paper we present a structure of a 10-b currentsteering digital-to-analog converter (DAC) with partial
pseudo randomization which uses a low-complexity
circuitry to achieve good dynamic performance. We
adopted the structure of the converter presented in [8] in
which the whole converter was included in a subbandgap mechanism. The segmentation with five most
significant bits (MSBs) and five least significant bits
(LSBs) was made by means of two identical binaryweighted current source blocks connected at the output
node through two resistors of appropriate values to
ensure the correct weighting in the output voltage
contribution.
In the present work the most significant segment of
the converter described in [9] was built with unary
current sources and it will be controlled by a modified
1 Introduction
High-speed, high resolution digital-to-analog converters
(DACs) are essential components in a wide range of
modern applications such as wired and wireless
communications [1], precision analog microcontrollers,
direct digital synthesis, high-resolution displays or video
signal processing. In particular, the current-steering
DACs have proved to be suitable candidates for these
applications which demand high spectral purity and
small output errors. Another important feature of this
type of converter is that it can be built by using the unit
element approach where special layout techniques and
switching schemes can be used to reduce the influence
of matching errors [2], [3], [4], [5]. In this way the effect
of the deterministic mismatch-generating process caused
by the long correlation distance (the matching is
dependent of the distance between transistors over the
wafer and originates from wafer fabrication and
oxidation process) is averaged and static parameters of
DAC as integral nonlinearity (INL) and gain error are
improved.
Furthermore, in order to obtain a better dynamic
performance, especially regarding the spurious-free
dynamic range (SFDR) of the converter, the dynamic
randomization of the unit current sources or dynamic
element matching (DEM) are used. Thus, the effect of
the stochastic mismatch-generating process caused by
the short correlation distance (arising from local
irregularities and characterized by the standard deviation
σ of the current generated by one unit element) is
dynamically averaged. In this way we can spread the
undesired harmonics as white noise over the output
spectrum. The technique can be applied if and only if we
use redundant codes in the DAC. The classical approach
ISSN: 1790-5117
201
ISBN: 978-960-474-006-2
8th WSEAS International Conference on POWER SYSTEMS (PS 2008), Santander, Cantabria, Spain, September 23-25, 2008
digital input according to DEM techniques, case in
which each unary current source is controlled by a
switch.
The segmentation of the DAC was also changed,
according to the analysis results obtained in [10] where
the area, matching errors and power consumption
considerations were simultaneously taken into account.
In this way the input code of the proposed DAC contains
six MSBs and four LSBs.
Lowering the supply voltage of this converter (1.1V)
is also possible and easy to implement by adopting the
modified structure presented in [11].
The outline of the paper is as follows. In section 2 we
present SFDR considerations where we explain way this
parameter is representative for the dynamic behavior of
a current-steering DAC and we discuss the manner in
which it can be evaluated. In section 3 we will present
the architecture of the converter and the simulation
results regarding SFDR. In section 4 we will conclude
the paper.
different delays by properly choosing the distribution of
switches and current cells in the floor plan of the layout.
Regarding the third factor, the element (i.e. the unit
current source) mismatch, it affects both the static and
dynamic performances of the converter and it introduces
significant noise and distortion to the output, limiting the
achievable SFDR of the DAC, at least at low
frequencies. Because of the stochastic-nature component
of the mismatch, one single-tone measure (one single
input sinusoid to measure SFDR) may not be sufficient
to characterize the dynamic performance. Applying
several single-tone sinusoidal inputs at different
frequencies represents a better solution. Sometimes
dual-tone or even multi-tone measurements are more
informative, since more repetitive combinations of non
ideal output voltages are possible and the output signal
is more realistically distributed through the frequency
domain. This is for why the SFDR definition must be
revised as we already specified.
The effect of matching errors can be diminished by
using DEM techniques but the problem which still
remains is that these techniques, for the thermometer
case, basically destroy the low-glitch properties.
However, the current-steering segmented DACs
proposed in [9] and [11] present very good immunity to
the switching activity. This feature is extremely
important because it will allow us to simplify the
thermometer encoder while keeping the achieved
dynamic performance with a classical encoder.
One single aspect is still to be discussed here. Very
elaborate theoretical models of DEM DACs [3], [4], [7],
and static element matching (SEM) DACs [4], [5] were
presented in the field literature and rigorous behaviorallevel simulations such as Matlab simulations confirmed
the functionality of the mathematical models.
Using Matlab instead of a PSpice simulator a more
flexible interface is allowed and you can generate more
easily the test digital signals. For example, using
OrCAD you can not apply the dB(..) function after the
FFT tool was used or you can have convergence
problems for complex circuits and long run to time in
transient analysis as in our case and the simulations are
very slow. But despite of these disadvantages, a PSpice
simulator using a model library supplied by an IC
manufacturer is incontestably more accurate and gives
us information which is closer to the behavior of a real
converter.
Moreover, in one single cited work [7], a comparison
concerning SFDR between simulated (with Matlab) and
measured results (for the implemented converter) was
presented and the differences for several input
frequencies were more than 6dB. All the cited works
which presented implemented converters [6], [7] and [8]
applied DEM techniques inside of an input segment of at
most four bits while for example the theoretical work [7]
2 SFDR Considerations
The most recent definition for the spurious-free dynamic
range (SFDR) that we found in the field literature is this
one: “For a pure sine wave input of specified amplitude
and frequency, SFDR is the ratio of the amplitude of the
DAC output averaged spectral component at the input
frequency to the amplitude of the largest unwanted
spectral component observed over a specified frequency
band” [12]. Usually, the frequency band is limited to
Nyquist frequency. As we can see, this definition
requires the specification of amplitude and frequency of
the input sine wave. This would mean that we can have
different values of SFDR for different inputs and an
intrinsic parameter of DAC would be signal dependent.
Our experience says that a more correct definition would
include “measured SFDR” instead of “SFDR” only. The
real SFDR would be close to the maximum measured
SFDR for a big number of tests with different inputs.
We will explain this further on in this section.
Three major factors influence the dynamic behavior
of current-steering DACs: finite output impedance,
physical position of the current cells (especially for high
resolution DACs) and the mismatch between the unit
current sources. The first two generate delay differences
in the current sources switching and consequently
glitches in the output voltage and spurs in the output
spectrum. The finite output impedance and its influence
depending on the output voltage was analyzed in detail
in [3] and [13] and the problem was almost entirely
solved by adopting the differential output [13], as we
have already done in [9] and [11]. The influence of the
second factor was also minutely analyzed in [5] and the
authors elaborated a technique to homogenize the
ISSN: 1790-5117
202
ISBN: 978-960-474-006-2
8th WSEAS International Conference on POWER SYSTEMS (PS 2008), Santander, Cantabria, Spain, September 23-25, 2008
random control bit PRB (AA4) can produce either a
16-b shift or it doesn’t shift the data, while the bit A4 of
the input code can shift or not the data with one bit.
Thus the total amount of shift is randomly selected
between 0 and 31. The synchronization latch was used to
equalize the delays between the four least significant bits
and the pseudo-randomized bits. The unary current
source block contains 63 identical cells and each cell has
a current source and a switch. The low-gain opamp
forces almost the same potential at the two outputs of the
DAC and leads to a non-critical voltage step during the
parasitic capacitance switching when the input code
changes. Thus, the output glitches were almost
suppressed and we do not need to put much effort on the
design of the thermometer encoder anylonger. The bit
line A4 will directly feed the output B0, the bit line A5
will directly feed the outputs B1 and B2, the bit line A6
will directly feed the outputs B3, B4, B5, B6 and so on.
To simulate the DAC SFDR we used the OrCAD
program and a library including PSpice models of the
0.35µm CMOS technology. Special parameters were
included in the models of the pMOS transistors used as
unary current sources which allowed the Monte Carlo
expanded this segment up to six bits, but with an
important area penalty. So, despite of an enlarged
dynamic-matching possibility, we can conclude that for
practical reasons the designers haven’t invested yet
effort and time to extend the most significant segment of
the DAC. The more complex the converter is, the PSpice
analysis can fail. However this type of accurate
simulation with low-level of idealization (i. e. OrCAD
simulation) can have success for a 6-b DEM segment,
but with simpler randomization circuitry, as we will see
in the next section.
3 DAC Architecture. Simulation Results
The block diagram of the proposed DEM DAC is
presented in Fig.1. The output of the thermometer
encoder is a 63-bit word corresponding to the 6-bit
segment of the input code, but because the simulator
doesn’t support a bus with more than 32 bits, we used
two buses of 32 bits and 31 bits for the lower and the
upper sections respectively. The barrel shifter has five
layers and it is controlled in such a way that the pseudo
Fig.1 DEM DAC architecture
ISSN: 1790-5117
203
ISBN: 978-960-474-006-2
8th WSEAS International Conference on POWER SYSTEMS (PS 2008), Santander, Cantabria, Spain, September 23-25, 2008
analysis using these active components with stochastic
matching. To obtain the test digital signal we used a fullscale sinusoid (Voff=256mV, Vamp=256mV and
FREQ=8393Hz) and a 10-b ideal ADC. The sampling
frequency was 100kHz. To avoid major convergence
problems and to reduce the simulation duration we
settled to 0 the four input bits of the least significant
segment and we simulated the DAC without DEM and
with DEM. As we can see in Fig.2 we gain 15dB in
SFDR and thus our solution is confirmed.
[4] D.H. Lee, Y.H. Lin and T.H. Kuo, Nyquist-Rate
Current-Steering Digital-to-Analog Converters with
Random Multiple Data-Weighted Averaging
Technique and QN Rotated Walk Switching Scheme,
IEEE Transactions on Circuits and Systems, Vol.53,
No.11, November 2006, pp.1264-1268.
[5] T. Chen, G. Gielen, The Analysis and Improvement
of a Current-Steering DACs Dynamic SFDR - I: The
Cell Dependent Delay Differences, IEEE
Transactions on Circuits and Systems – I: Regular
Papers, Vol.53, No.1, January 2006, pp.3-15.
[6] K. O’Sullivan, C. Gorman, M. Hennessy, and V.
Callaghan, A 12-bit 320-MSample/s CurrentSteering CMOS D/A Converter in 0.44 mm2, IEEE
Journal of Solid-State Circuits, vol. 39, No.7 July
2004, pp.1064-1072.
[7] N.U. Andersson, K.OAndersson, M. Vesterbacka,
and J. J. Wikner, Models and implementation of a
dynamic element matching DAC, Analog Integrated
Circuits and Signal Processing, Vol. 34 , Issue 1,
January 2003, pp. 7-16.
[8] W. Chen, J. Bauwelinck, P. Ossieur, X.Z. Qiu and J.
Vandewege, A Current-Steering DAC Architecture
with Novel Switching Scheme for GPON BurstMode Laser Drivers, IEICE Trans. on Electronics,
Vol. E90-C, No.4, April 2007, pp. 877-884.
[9] M. Tomoroga, L. Jurca, M. Ciugudean and C.
Toma, Low Glitch Current-Steering DAC with Split
Input Code, Proceedings of the 6th WSEAS Int.
Conf. on Electronics, Hardware, Wireless and
Optical Communications, Corfu Island, Greece,
February 16-19, 2007, pp. 40-45.
[10] M. Tomoroga, L. Jurca, Study of Matching Errors
in Unit Element Approach of Current-Steering
Segmented DAC Design, Proceedings of the 6th
WSEAS International Conference on System Science
and Simulation in Engineering (ICOSSSE), Venice,
Italy, November 21-2, 2007, pp.115-120.
[11] M. Tomoroga, L. Jurca, M. Ciugudean, C. Toma,
Low Voltage Low Glitch Current-Steering DAC
Overlapping the Voltage Reference Circuit, WSEAS
Transactions on Circuits and Systems, Issue 3, Vol.6,
March, 2007, pp. 273-280.
[12] E. Balestrieri, S. Rapuano, Defining DAC
Performance in Frequency Domain, Measurement,
No.40, 2007, pp.463-472.
[13] T. Chen, G. Gielen, The Analysis and Improvement
of a Current-Steering DACs Dynamic SFDR - II:
The Output Dependent Delay Differences, IEEE
Transactions on Circuits and Systems – I: Regular
Papers, Vol.54, No.2, February 2007, pp.268-278.
(a)
(b)
Fig.2 Simulated SFDR without DEM (a)
and with DEM (b)
4 Conclusion
In this paper we presented a simple DEM technique to
reduce the influence of matching errors in the dynamic
performance of a 10-b current-steering segmented DAC.
The structure was optimized and the gain in the SFDR
range was 15dB.
References:
[1] C. Volosencu, Identification in Sensor Networks, 9th
WSEAS International Conference on Automation and
Information (ICAI'08), Bucharest, Romania, 2008.
[2] R. Jacob Baker, CMOS: Circuit Design, Layout, and
Simulation, 2nd Edition, Wiley-IEEE Press, 2007.
[3] J.J. Wikner, Studies on CMOS Digital-to-Analog
Converters,
Dissertation No.667, Linköping
University, Sweden, 2001.
ISSN: 1790-5117
204
ISBN: 978-960-474-006-2