IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 22, NO. 3, MARCH 2014
593
Segmented Architecture for Successive
Approximation Analog-to-Digital Converters
Mehdi Saberi and Reza Lotfi, Member, IEEE
Abstract— In this paper, the structure of a binary-weighted
capacitive digital-to-analog converter (DAC) in a successiveapproximation analog-to-digital converter (SA-ADC) is modified
to a unary or segmented configuration to reduce the power
consumption and improve the static linearity performance. In
order to be able to choose the optimum value of the segmentation
degree (i.e., the number of unary bits), the power consumption
and the static linearity behavior of the segmented architecture
as functions of the segmentation degree are analyzed. Circuitlevel simulation results are presented to show the accuracy of
the proposed equations. It is shown that for moderate and highresolution ADCs, a segmentation degree of four or five bits
is the optimum choice from the power-consumption viewpoint.
Simulation results of a 1 V, 10-bit, 100-kS/s SA-ADC show
that the power consumption of the entire capacitive DAC and
the digital circuit of the segmented implementation with a
segmentation degree of 4 is 30% less than the conventional design
while the standard deviation
of the differential nonlinearity is
√
reduced by a factor of 2 2.
Index Terms— Differential nonlinearity (DNL), integral nonlinearity (INL), power dissipation, segmented capacitor-based
digital-to-analog converter (DAC), successive approximation
analog-to-digital converter (SA-ADC).
I. I NTRODUCTION
S
UCCESSIVE approximation analog-to-digital converter
(SA-ADC) has been of increasing research interest for
a wide range of resolutions and sampling frequencies due
to its minimum active analog circuits leading to low-power
consumption [1]–[3]. As shown in Fig. 1, a conventional
SA-ADC consists of a sample-and-hold (S/H) circuit, a comparator, a successive approximation register (SAR), and a
digital-to-analog converter (DAC). Using a binary search algorithm, the DAC output voltage (VDAC ) successively approximates the sampled input voltage (V H ) and in each clock cycle
one bit of the digital output word (Di ) is obtained [4]–[10].
One of the most important building blocks that determine
the accuracy and conversion speed of the converter and
also consumes a major part of the overall power of the
SA-ADC (specifically for medium-to-high resolutions) is
the DAC [1], [5]. The DAC required in the SA-ADC
can be realized in various ways; e.g., capacitor-based DAC
[1]–[25], switched-current DAC [26]–[28], or R-2R ladder
Manuscript received July 17, 2012; revised January 30, 2013; accepted
February 5, 2013. Date of publication March 29, 2013; date of current version
February 20, 2014.
The authors are with the Department of Electrical Engineering, Ferdowsi University of Mashhad 9177948974, Iran (e-mail: me.saberi@
stu-mail.um.ac.ir; r-lotfi@um.ac.ir).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2013.2246592
Vin
S/H
Vref
VH
VH
Vcomp
VDAC
SAR
VDAC
3Vref/4
CLK
Vref/2
Vref/4
DAC
D1,D2,…,DN
Out
Fig. 1.
0
D1=1 D2=0 D3=1 D4=1 D5=0 D6=1
0
1
2
3
4
5
6
CLK
Principle of the SA-ADC operation.
DAC [29]–[31]. Among these architectures, the capacitorbased DAC has become more popular because of its zero
quiescent current. Furthermore, in most technologies, resistor
mismatch and variation are greater than those of a capacitor.
Similar to current-steering DAC, the capacitive-array DAC
used in SA-ADC can be implemented in three different
ways, i.e., binary-weighted, unary-weighted, and segmented
capacitive array [32]–[35]. Since the binary-weighted array
benefits from the simplicity of implementation and does
not suffer from the design complexity and power consumption overhead of the thermometer decoder required in unary
capacitive array, almost all radix-2 architectures reported
in literature use the binary-weighted capacitive-array DAC
with different structures, e.g., conventional capacitive array
[3]–[8], capacitive array with attenuation capacitor [9]–[12],
split capacitive array [13], [14], SA-ADC with dual capacitive array [15]–[17], C-2C capacitive array [18]–[21], charge
redistribution DAC with step-wise charging [22], capacitive
array with monotonic switching method [23], and capacitive
array with merged capacitor switching [24]. On the other
hand, the unary-weighted capacitive array has the advantage of
low-differential non-linearity (DNL) and also guarantees the
monotonicity of the converter. In addition, the power consumption of the unary capacitive DAC due to capacitor switching
can be reduced by around 37% in comparison with the binaryweighted DAC due to the reduction in the switching activity
of the capacitive DAC. However, it suffers from complexity
and power consumption overhead of the required binaryto-thermometer decoder and increased number of switches,
which rises exponentially with the number of bits. Therefore,
trading the implementation complexity, power-consumption,
and the linearity in the binary- and unary-weighted DACs,
a segmented structure where the more significant bits are
implemented in the unary scheme and the remaining less
significant bits in the binary-weighted structure will be the
optimum choice [33], [34]. In literature, the unary-weighted
capacitive array has been mainly reported to implement
non-radix-2 SA-ADCs to avoid geometrically non-binary-
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