Digital-to-Analog Converter
(DAC)
Tai-Cheng Lee
Electrical Engineering/GIEE
1
Tai-Cheng Lee
Spring 2011
General Considerations for DAC
•
Digital-to-analog converter has a set of digital inputs (D) and an
analog output (A).
A  D,  sets both the dimension and full - scale range of A.
D is dimensionl ess
Example: A 3-bit D/A converter
Analog
Output
7
6
5
4
3
2
000 001 010 011 100 101 110 111
2
Digital
Input
Tai-Cheng Lee
Spring 2011
Codes for DAC
•
DAC codes
Decimal
0
1
2
3
Binary
00
01
10
11
Thermometer
0
0
0
0
0
0
0
1
0
0
1
1
0
1
1
1
1-of-n
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
0
Gray
00
01
11
10
3
Tai-Cheng Lee
Spring 2011
DAC Performance Metrics
•
Differential nonlinearity (DNL):
max(abs(output step size – ideal value of 1 LSB))
•
Integral nonlinearity (INL):
•
Offset
•
Gain error
maximum( (DNL))
•
Settling time
•
Glitch Impulse
•
Latency
•
SNDR
Analog
Output
INL
DNL+1 LSB
Offset
Digital
Input
4
Tai-Cheng Lee
Spring 2011
Reference Multiplication and Division
• Voltage multiplication: Can we multiply
a voltage, say 3 V, by 2?
→
Requires active circuit.
• Voltage division: An m-bit DAC requires a ladder with 2m-1
resistors. As m↑, equivalent resistance ↑or delay
in the ladder must ↑.
VREF
• Resistor mismatch introduces DNL and INL.
R
Vin
R
R
1−of−n code
R
m bits
5
Tai-Cheng Lee
Spring 2011
Reference Multiplication and Division
Example: doping gradient
j 1
Vj 
 ( R  kR)
k 0
N 1
 ( R  kR)
VREF
k 0
j ( j  1)
jR 
R
2

VREF
N ( N  1)
NR 
R
2
j ( j  1)
R
j
2
INL j  VREF 
VREF
N ( N  1)
N
NR 
R
2
j( N  j)
R
VREF

( N  1)
2
N
R
R
2
N
R
INL j , MAX  N
VREF , at j 
8R
2
jR 
6
VREF
R+(N−1)
R
VN−1
V3
R+2
R
V2
R+
R
V1
R
Tai-Cheng Lee
Spring 2011
Example Continued
INL profile (Transfer curve):
Vj
j
DNL:
VREF

N
R
, at j  1 and j  N-1
2R
DNL j  V j 1  V j 
DNL j , MAX  VREF
7
Tai-Cheng Lee
Spring 2011
Random Mismatch in Resistor
R
L
Wt
 2 Rc
W
L
How to find the total mismatch in R?
R

R
t
Nonlinearity due to random mismatch
1.
Assume a probability density function for the value of each
resistor.
2.
Find the PDF for each tap voltage.
3.
Calculate mean and standard deviation.
8
Tai-Cheng Lee
Spring 2011
Random Mismatch in Resistor Ladder
j
Vj 
R
k 1
N
VREF
k
 Rk
VREF , If Rk , Gaussian, R  R,  R  R
RN
k 1
j
VREF
N
j
j R
V j 
(1  )
VREF
2
N
N R
V3
mean 
R3
→ INLMAX 
1 R
VREF
4N R
Conclusion: If R/R remains constant, as N ↑, Vjmax↓.
Vjmax in LSB:
V j max,LSB 
R2
R1
N R
4 R
This suggests that if we go from 8 bits to 10 bits, resistor
matching must be improved by a factor of ?
→ Matching requirement can be relaxed when a large number of
random variables are added to each others.
9
Tai-Cheng Lee
Spring 2011
Monte Carlo Simulation
If it is difficult to calculate the effect of random mismatch, one can
use random values of a parameter in a large number of
simulations to predict its effect.
Example: (Brute Force Approach) Define a vector R[N]; Do a loop
in which a Gaussian value is assigned to each R[ ]. Now, can
calculate all Vj and their deviation from their ideal value.
If this is repeated many times, the maximum INL will exhibit a
certain distribution.
10
Tai-Cheng Lee
Spring 2011
Current Division & Multiplication
Division:
Uniform (Unary)
Binary
• IREF consumes voltage headroom.
• IREF requires a very large device.
Multiplication
I REF
I1
I2
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Tai-Cheng Lee
Spring 2011
Binary and Segmented Arrays
Binary
Unary
I out
Vout
8I
4I
2I
I
• Unary arrays are unconditionally monotonic.
• Unary arrays have much less glitch impulse than binary
arrays.
• But, binary arrays require no decoding.
How to convert current to voltage?
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Tai-Cheng Lee
Spring 2011
Current Source Mismatch
Design considerations:
I1
1.
2.
3.
Current source mismatch.
Finite output impedance of current source.
Voltage dependence of the load resistor.
I2
VG
M1
M2
Current source mismatch, for long channel device
•
I D ( Cox ) W L
2VTH




ID
Cox
W
L VGS  VTH
I1
I2
VG
• Current source mismatch, for long channel
device with source degeneration
M1
M2
R s1
R s2
I D
1
( Cox ) W L
2VTH

[



 g m Rs ]
I D 1  g m Rs Cox
W
L VGS  VTH
13
Tai-Cheng Lee
Spring 2011
Current Source Finite Output Impedance
Finite output impedance of current source
r
Vout   jI ( R1 // 0 )
j
R
•
2
INLMAX
IR1 N 2

4r0
1
Vout
Full scale  NIR1
N 2 R1
 INL 
(in LSB)
4r0
I
D1
•
→
I
rO
D2
I
rO
rO
DN
Load resistor nonlinearity
Polysilicon resistors exhibits a hyperbolic sine I-V
characteristics.
14
Tai-Cheng Lee
Spring 2011
Charge Division (I)
•
Simple but impractical
QREF
C1
• Identical capacitor
(Unary)
DN
CN
D N−1
C1  C2    C N
C N−1
The same top plates are shared and
their bottom plates can be switched
from ground to a reference.
D1, D2 … DN are binary codes.
•
Vout
D1
C1
Binary capacitor
C1  2 N 1  C2  2 N  2    C N
VREF
15
Sp
Tai-Cheng Lee
Spring 2011
Charge Division (II)
Nonideality
•
Capacitor mismatch
WL
C W L tox
C




tox
C
W
L
tox
To calculate the INL due to capacitance mismatch, we follow the
procedure for resistor ladders. For unary arrays, the results are
identical. For binary arrays, it becomes complicated because of
cross-correlations → may have to resort to
simulations.
•
Capacitor voltage dependence
C  C0  C01V  C0 2V 2  
dq  C0 (1  1V   2V 2  )dV
v2
Q  C0  (1  1V   2V 2  )dV
v1
16
Tai-Cheng Lee
Spring 2011
Charge Division (III)
INL for this case:
Vout

VREF Vout
( N  j )C0 ( 1   1V )dV  
0
0
jC0 ( 1   1V )dV
 1Vout  2
j
VREF 
Vout
2
N
2   1VREF  2 1Vout  2 1Vout / VREF
V
2V
j
 VREF  1 out ( VREF  2Vout  out )
N
2
VREF
2
Vout
INLMAX 
C 1 =jC(V)
VREF
Vout
C 2 =(N−j)C(V)
3
 1VREF 2 , at Vout  ( 3  3 )VREF / 6
36
Switch junction capacitance nonlinearity (Sp)
C0
C junc 
m
(1  V j /  ) j
jC
j
C
• Top plate capacitance V0 
VREF  (1  T )VREF
NC  CT
N
NC
•
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Tai-Cheng Lee
Spring 2011
Switching Function in Resistor-Ladder DAC(I)
VREF
•
Binary switch
1.
Tree-structure switches perform
digital decode.
2.
For a m-bit DAC, 2 switches
appears at output.
3.
Need a buffer at the output to
drive resistive or heavy load.
4.
The top level equivalent
resistance limits the performance.
D1
D1
D2
D2
Dk
Vout
Time constant( ) 
18
Tai-Cheng Lee
Spring 2011
Switching Function in Resistor-Ladder DAC(II)
•
1-of-n code switch
1.
It is faster because lower
equivalent R. For a m-bit
DAC, 2m (=n) switches at
output and might create
significant parasitic
capacitance.
2.
VREF
1−of−n
Code
Thermometer
Code
Vout
The digital decode logic is
very complex.
Time constant( ) 
19
Tai-Cheng Lee
Spring 2011
Switching Function in Current-Steering DACs
•
Current steering
1.
M1 and M2 are in saturation region.
Faster!  ROUT  ro 3 g m12 ro12
2.
I out
D
I out
M2
M1
D
X
M1 and M2 are in linear region.
VB
M3
 ROUT  ro 3  RON
•
RN
CN
R j+1
C j+1
Rj
Cj
Capacitor DAC
The output settling behavior is
independent of C in the array!
  OUT
Vout
VREF
RC L

N
C1
R1
C1
VREF
20
Tai-Cheng Lee
Spring 2011
Switching Function in Other DACs
•
The size of the switches must be minimized to alleviate the
charge injection.
•
The impedance of VREF must be small enough. Ex: if 128
0.5-pF switch to VREF = 2 V and the ON resistance of switched
are 1 k, the initial current is larger than 50 mA.
•
Binary to thermometer code conversion
ABC
T1 T2 T3 T4 T5 T6 T7
000
001
010
011
100
101
110
111
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
T1 = A + B + C
T2 = A + B
0
0
0
0
0
0
0
1
T3 = A + BC
T4 = A
T5 = A (B + C)
T6 = A B
T7 = A B C
21
Tai-Cheng Lee
Spring 2011
Resistor DAC Architecture (I)
•
Ladder architecture with a switched subdivider
Two-stage resistor divider to interpolate the fine voltage.
 It can reduce the number of switches.
Analog Multiplexer
Analog Multiplexer
VREF
j bits
k bits
22
Vout
Tai-Cheng Lee
Spring 2011
Resistor DAC Architecture (II)
•
Possible implementation (next page)
Finite resistance in the interpolation network introduces DNL
and INL.
Long settling time when changing from one segment to the
other segment.
23
Tai-Cheng Lee
Spring 2011
Resistor DAC Implementation
Coarse Conversion
VFS
A 31
S 31
Fine Conversion
R on
VP
R 31
A 31
R 30
A 30
B 31
R F29
B 30
Vout
R u2
A0
A
R1
A1
S1
1
R F1
A0
R0
R F0
S0
VN
A 0 ~ A 31
1−of−n
Encoder
B ~ B
0
B2
B1
B0
31
1−of−n
Encoder
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Tai-Cheng Lee
Spring 2011
Intermeshed Ladder Architecture
•
A primary ladder divides the main references voltage into
equal segment, each of which is subdivided by a separate,
fixed secondary ladder.
 It does not introduce DNL.
 The load ing to primary ladder is constant and uniform.
VREF
Drawback: Larger area.
Vout
Vout
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Tai-Cheng Lee
Spring 2011
Current Steering DAC (I)
•
High-speed D/A converters use this architecture. It only
involves the current steering rather than charge transfer or
charging/discharging.
 Can use binary - weighted current source to implement DAC.
 Significan t area for high resolution DACs.
•
R-2R Network based architecture.
Ex: a 3-bit R-2R DACs
I 2
I 1
Q2
VB
Q1
4A E
2R
R 2R
I 0
I a
Qa
Q0
2AE
Q0 + Qa
AE
AE
R 2R
I 0+ I a
R R
2A E
R
VEE
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Tai-Cheng Lee
Spring 2011
Current Steering DAC (III)
•
In the above approach, resistors can be either R or 2R
→don’t need to scale them from 2m-1 to 1. But, the
transistors must be scaled. What happens if we don’t scale
the transistors?
I2
I1
 VBE 2  VBE1 
Vb
2R
R
•
Correct the error by inserting a voltage source=Vtln2:
I2
I1
Vb
2R
R
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Tai-Cheng Lee
Spring 2011
Current Steering DAC (II)
•
Another R-2R architecture: no more than 2-1 scaling.
 Reduce the area significan tly.
2R
R 2R
I out
I3
R
R
I2
I1
•
Glitch problem: when switching from 0111 to 1000.
•
Requires tighter matching to ensure monotonicity.
R1
R1
Vout
8I
4I
2I
Vout
I
8I
28
4I
2I
I
Tai-Cheng Lee
Spring 2011
Segmented Current Steering DAC (I)
•
For a n-bit DAC, segmented requires 2n identical current
sources.
 Monotonicity is guaranteed .
 Gltich can be minimized.
•
Full segmented DACs require binary-to-thermometer code
converter. Thus, for higher resolution DAC, this decoder
occupies significant area and consumes huge power.
R1
Vout
I
I
I
I
Binary−Thermometer Decoder
Binary Input
29
Tai-Cheng Lee
Spring 2011
Segmented Current Steering DAC (II)
•
For an m-bit DAC, partially segmented DAC can be
decomposed into k+n, where k most significant bits are
converted to thermometer codes and drive 2k-unit unary
arrays, while the remaining n bits are applied to an n-bit
binary array that requires n binary –weighted current
sources.
 The complexity of binary - to - thermomete r decoder
can be reduced. Ex: k=6 and n=4
Binary
R1
Segmented
I out
2R
I1
I
2
I 63
R 2R
R 2R
I0
30
R 2R
I
0
RR
I0
I0
Tai-Cheng Lee
Spring 2011
Segmented Current Steering DAC (III)
•
The segmented DAC proposed by Shoeff:
 It acheives 12 - bit resolution without trimming.
I
OUT
I 3
VB
I 2
4A E
2AE
0.25R
I7
I6
I5
D3
I4
I 1
AE
0.5R
D2
R
I 0
A E
R
D1
D4
Segment Decoder
D5
Problem: Stack devices obviates this technique in today’s low
voltage technologies.
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Tai-Cheng Lee
Spring 2011
Matrix Architecture DAC
•
Arrange the current sources in a matrix.
•
Perform the decoding in two or three steps, with part of it
inside each cell in the matrix.
D3
D2
D1
Column Decoder
D5
Row Decoder
D4
Local
Decoder
D6
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Tai-Cheng Lee
Spring 2011
Use of Clocks in DACs
Status of each row:
(1) All current sources are on;
(2) All current sources are off;
(3) Some current sources are on.
Local decoding takes these cases into account,
Issues: Coupling and output node capacitance.
In principle, DACs do not need any clocks; the digital input
simply ripples through and eventually generates an analog
output.
In practice, most high-speed DACs use clocks and latches
to “synchronize (align)” the data and also perform the logic
in pipelined stages.
33
Tai-Cheng Lee
Spring 2011
DAC Calibration (I)
The measurement of the mismatch of two capacitors:
•
First, S1, S2, and S5 are ON. Next, S3 and S4 turn on.
S1
VREF
S4
C1
S3
VREF
C2
V 
S2
S5
V is a measure of mismatch between C1 and C2.
Main DAC
C cal
V ref
Calibration
DAC
C j  2 j 1 C1 for j  1
k 1
CM
C M−1
C1
C0
Successive
Approximation
Logic
Sp
C jk   C j for 1  k  m
j 0
Error
Register
34
Tai-Cheng Lee
Spring 2011
DAC Calibration (II)
•
Calibration starts with Cm and proceeds as follows.
Vres,m is a residue voltage between Cm and Cm-1+ …..+ Co.
The procedure is repeated for the mismatch between Cj and
Cj-1+ …..+ Co for j=m-1,….1, thus producing the digital
representation of Vres,m-1 ,……, Vres,1 .
m
VREF m j 1 C
2
(
)
D

Vj D j


j
j
2 m j 1
C
j 1
, where (C/C)j denotes the relative mismatch of Cj and
Verror 
m
1
Vj  (Vres , j   Vk )
2
k  j 1
The digital calibration only needs adders and simple logic
gates but no digital multipliers.
Note: The nonlinearity of capacitor can not be calibrated by
this scheme.
35
Tai-Cheng Lee
Spring 2011
DAC Calibration (III)
•
Current-steering DACs: Each current cell is calibrated by a
VDD
master current source.
I1  I 2  I REF 
S1
The analog voltage is stored at CH .
I 1
Vb
M1
I 2
M2
S2
CH
Current cell
Two drawbacks:
(1) The current cell must be smaller than the master current
source
(2) Single-ends operation suffers from the charge injection
of the switch.
Vdd
M4
Bidirectional current source
M5
I5
S1
I D1  I D 3  I D 5  I REF
I1
S2
S3
M2
C1
36
M1
M3
Vb
C1
Tai-Cheng Lee
Spring 2011
Case Study for DAC Calibration
[1] M. Tiilikainen, “A novel high precision adjustment method for
The transconductance of a MOSFET,” in Proc. CICC, May 1999,
pp.525–528.
[2] M. Tiilikainen, “A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC”,
JSSC, July, 2001, pp.1144-1147.
[3] A. V. d Bosch, M. Borremans, M. Steyaert, W. Sansen, “A 10bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter”
JSSC, March, 2002, pp.315-324.
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Tai-Cheng Lee
Spring 2011
A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC
Five terminal devices: putting a resistor across gate.
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Tai-Cheng Lee
Spring 2011
A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC
Calibrated current using 5-terminal devices:
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Tai-Cheng Lee
Spring 2011
A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC
Distributed calibrated devices:
40
Tai-Cheng Lee
Spring 2011
A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC
Distributed calibrated cascode devices:
41
Tai-Cheng Lee
Spring 2011
A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC
14 bits= 4 MSB + 5 middle +5 LSB
42
Tai-Cheng Lee
Spring 2011
A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC
Calibration circuits
and building blocks.
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Tai-Cheng Lee
Spring 2011
A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC
44
Tai-Cheng Lee
Spring 2011
A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter
45
Tai-Cheng Lee
Spring 2011
A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter
46
Tai-Cheng Lee
Spring 2011
A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter
47
Tai-Cheng Lee
Spring 2011
A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter
48
Tai-Cheng Lee
Spring 2011
A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter
49
Tai-Cheng Lee
Spring 2011
A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter
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Tai-Cheng Lee
Spring 2011
A 10-bit 1-GSample/s Nyquist Current-Steering CMOS D/A Converter
M0 B0
B0 B0
B0 M0
16 14
14 16
8
4
2
6
6
2
4
8
5
1
3
7
7
3
1
5
13 16
15 13
B3 B2
B1 B1
B4
B2
B1 B1
B4
13 16
5
8
16 13
1
3
7
7
4
2
6
6
15 14
3
1
5
2
4
8
14 15
M0 B0
B0 B0
B0 M0
Fig. 7. Double centroid switching scheme
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Tai-Cheng Lee
Spring 2011
Mixed-Signal method – Capacitor
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
32
32
16
16
32
32
16
8
8
8
16
32
32
16
4
4
8
16
32
32
16
2
1
2
16
32
32
16
4
4
8
16
32
32
16
8
8
8
16
32
32
16
32
32
16
16
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
16
16
16
32
32
16
8
8
8
D
16
16
8
4
4
D
16
16
8
4
4
D
16
16
8
2
2
32
32
16
8
8
1
32
32
16
16
16
16
32
32
32
32
32
32
 Common Centroid
Structure (2n Ratio)
32
32
32
32
32
32
52
32 32 16 8
8 16 32 32
32 32 16 8
8 16 32 32
32 32 16 8
8 16 32 32
32 32 16 8
8 16 32 32
32 32 16 4
4 16 32 32
32 32 16 4
4 16 32 32
32 32 16 2
2 16 32 32
32 32 16 1
D 16 32 32
Tai-Cheng Lee
Spring 2011