10 BIT 500 MHZ CURRENT STEERING DAC
SREEMOL S S
Dept. of Electronics and Communication, Amrita School of Engineering
Abstract- In this paper 10bit, 500M segmented current steering Digital to Analog converter is designed. The DAC is
implemented using 90nm technology with a supply voltage of 1.2V.The design is implemented with the matching network,
required for the current sources. Segmented architecture of the DAC is used in order to decrease the glitch and to improve
the Monotoncity, even though that increases the cost. The spurious free dynamic range (SFDR) and signal to noise and
distortion ratio (SNDR) performance of the segmented DAC architecture is also analyzed in this paper.
Index Terms- Segmented architecture, Monotoncity, Spurious free dynamic range (SFDR), Signal to noise ratio (SNDR)
select the current sources doubles and the decoding
logic complexity increases significantly. A direct
challenge is a compromise in the maximum operating
speed.
I. INTRODUCTION
Cost effective data converters with high speed,
conversion rate and resolution are very important in
application like wireless communication, digital
video and audio .Thus a wide range of digital to
analog converters (DAC) exists, each have its own
advantage. The current-steering DACs can achieve
high conversion rate and thus are commonly used in
high frequency signals. This type is called currentsteering DAC because it uses current throughout the
conversion as compared to other DACs where a
voltage is converted into current which is then used to
generate voltage at the output. Current-steering type
of DACs requires high precision current sources that
are summed in various fashions. Current-steering
DACs have an advantage of high current drive
capability and so there is no need of output buffers to
drive resistive load at the output and thus they are
used in high speed applications. To achieve good
linearity and less glitch energy, segmented
architecture of the DAC is implemented here.
The 10 bit input are split in to two, 5 bits each. Each
of these five bits will go as the input to the binary to
thermometer decoder. In the first step of decoding,
the binary code is decoded into a row and column
decoder. The selection of the current cell is
corresponds to the input value of the row and column
decoder. Thus combination of row and column binary
to thermometer decoder generates 1024 control
signals go to the switches .This switch are connected
to the current sources. In the output of the switching
logic is given to the DFF and this will go as a input to
the current cell. Since a 10 bit DAC , 1024 current
cell will be there which is implemented in a matrix
fashion. Each block in the matrix consists of a current
cell, switching logic and a DFF.
II. DAC ARCHITECTURE
In Fig.1the block diagram of a conventional 10 bit
current steering DAC is shown. To achieve good
linearity [1] and less glitch energy, segmented
architecture of the DAC, is implemented here. In the
thermometer-code implementation, each unit cur-rent
source is connected to a switch which is controlled by
the signal coming from the binary to thermometer
decoder. When the digital input is increases by 1
LSB, one more current source is switched from the
negative to the positive side. Thus the monotoncity is
guaranteed by using this segmented architecture [2][3]. At the mid-code, a one LSB transition causes
only one current source to the switch as the digital
input increases by one. This will reduce the glitch
problem. Glitches hardly contribute to the nonlinearity in the thermometer coded DAC. One major
drawback of the thermometer coded DAC is the area
and power consumption. To achieve a good DNL
specification and glitch implemented in the unity
decoded part, the number of control lines needed to
Fig.1. Basic block diagram of DAC
A. Current Cell and Switching Logic
When the MOS transistor is used as a conventional
switch the signal can be couple through the gate to
the output through the gate to drain capacitance. In
the current cell, two cascaded current source are used
to increase the output impedance and the input signal
to the switching transistor D and DB are opposite in
logic. The low to high transition to one of the
Proceedings of 12th IRF International Conference, 26th June, 2016, Hyderabad, India, ISBN: 978-93-86083-47-0
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10 Bit 500 MHZ Current Steering DAC
transistor bring in to the linear region and the other
will in off mode .The problem in the output voltage
variation occur ,when the switching transistor
forming a channel, the cascade transistor are off and
the signal path from the drain of the switching to the
output node is open. The cascade current source also
improves the input resistance of the current source, so
the output voltage variation can be suppressed. The
switching logic for successive selection of the current
cell is modeled using the OR gate and NAND gate.
The input to the selection logic will be the
thermometer code that will corresponds to number of
the current cell. The corresponding
architecture for the unit current cell and the biasing
circuit are shown in the Fig. 2 and Fig. 3.
Fig. 5.unit current cell with D=0
Fig.2. Circuit diagram of unit current cell
Fig.6.unit current cell with Db=0
B. Binary to Thermometer Decoder
The binary code is decoded into a row decoder and a
column decoder .Each of the row and column decoder
will have 32 output lines, each with a input of five
bits. Thus with combination of the column and row
decoder the 1024 current cells are made. The
thermometer code T1 to T32 are made using NAND
gate and OR gate.
T32 =a*b*c*d*e
T31=a*b*c*d
.
.
.
T1=a+b+c+d+e
Fig. 3.Biasing circuit
Fig.4. DC operating point of the biasing circuit
Fig.7.Decoded logic for each current cell
Proceedings of 12th IRF International Conference, 26th June, 2016, Hyderabad, India, ISBN: 978-93-86083-47-0
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10 Bit 500 MHZ Current Steering DAC
Fig.11.Differentional output with the DFF
IV. SIMULATION RESULTS
Fig.8.Decoded logic with example
III.COMPLETE ARCHITECTURE FOR
THERMOMETER CODE DAC
The complete current block used in the thermometer
coded DAC will have a switching logic and the
output of that will
go to the DFF so that it will shift the crossing of the
switching transistor only at the clock edge. The
output of the DFF will go to the switches
Fig.12. FFT of the current steering DAC with resistive load
Fig.9.Simple resistive load at the output
Fig.13.FFT of the DAC using transimpedance with a gain of
40dB
Fig.10.Transimpedance logic at the output
A single resistor at the output converts current into
voltage. Here we are using 50 ohm resistor. In this
case, the full-scale output current is enough to
produce responsible voltage swing across resistor.
Due to parasitic capacitance, the node will experience
the entire output voltage swing. By replacing resistor
with a transimpedance amplifier (TA) so that voltage
variation at the node will be less due to the virtual
node action. Output settling will be determined by the
op amps speed (ideal op-amp have high impedance at
the node connected to current steering DAC).
Because of this reason non-linearity will be less and
this system will provide better SFDR [4]-[6].
Fig.14.FFT of the DAC using transimpedance amplifier with a
gain of 60dB
Proceedings of 12th IRF International Conference, 26th June, 2016, Hyderabad, India, ISBN: 978-93-86083-47-0
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10 Bit 500 MHZ Current Steering DAC
TABLE.1 COMPARISON ON SFDR FOR
DIFFERENT DAC ARCHITECTURE
REFERENCES
[1]
[2]
[3]
CONCLUSION
[4]
In this paper a Current Steering DAC with Segmented
architecture is designed in 90 nm technology. It has
been observed that monotoncity is guaranteed by
using segmented
kind of architecture. Moreover the SFDR and SNDR
is more when we replace the resistor at the output of
the DAC by transimpedance amplifier .SFDR and
SNDR values has seen to be improved by increasing
the gain of transimpedance amplifier, due to virtual
ground property of op-amp .
[5]
[6]
A. van den Bosch,M. S. J. Steyaert, and W. Sansen, “An
accurate yield model for CMOS current-steering D/A
converters,” in Proc. IEEE Int. Symp. Circuits and
Systems (ISCAS), 2000, pp. 105–108.
A. van den Bosch, M. Borremans, M. Steyaert, and W.
Sansen, “A10-bit 1-GSample/s Nyquist current-steering
CMOS D/A converter,”IEEE J. Solid-State Circuits, vol.
36, no. 3, pp. 315–324, Mar. 2001.
J. Bastos, A. M. Marques, M. S. J. Steyaert, and W.
Sansen, “A 12-bit intrinsic accuracy high-speed CMOS
DAC,” IEEE J. Solid-State Circuits,vol. 33, no. 12, pp.
1959–1969, Dec. 1998.
T. Chen and G. G. E. Gielen, “The analysis and
improvement of a current-steering DACs dynamic SFDRII: The output-dependent delay difference,” IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 268–279,
Feb. 2007.
W.-H. Tseng, C.-W. Fan, and J.-T. Wu, “A 12 b 1.25 GS/s
DAC in 90nm CMOS with 70 dB SFDR up to 500 MHz,”
in IEEE Solid-State Circuits Conf. Dig. Tech. Papers,
2011, pp. 192–193.
P. Palmers and M. S. J. Steyaert, “A 10-bit 1.6-GS/s 27mW current-steering D/A converter with 550-MHz 54-dB
SFDR bandwidth in 130-nm CMOS,” IEEE Trans.
Circuits Syst. I, Reg. Papers, vol. 57, no. 11, pp. 2870–
2879, Nov. 2010.
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Proceedings of 12th IRF International Conference, 26th June, 2016, Hyderabad, India, ISBN: 978-93-86083-47-0
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