Overview
Data Converters
• Introduction
• Type of converters
Nyquist-rate D/A Converters
• Architectures based on resistors
• Architectures based on capacitors
• Architectures based on current sources
• Other architectures
Pietro Andreani
Dept. of Electrical and Information Technology
Lund University, Sweden
Data Converters
DAC applications
Nyquist-rate D/A Converters
2
Introduction – I
• Video: HDTV monitors display more than 1000 lines per frame, in
addition to a higher contrast ratio and a more detailed color range
The input of a DAC is a multi-bit digital signal, while the output is a
voltage or a current capable of driving an external load
– To maximize the viewing quality on a state-of-the-art display, a 12-bit
150 MSPS conversion rate is often necessary
• Wired: DACs for ADSL and ADSL2+ must handle bandwidths of
1.1MHz or 2.2MHz with 12-bit resolution
• Wireless: GSM/EDGE, WCDMA, LTE require high conversion rates
and high resolutions when multiple carriers are used
– Conversion rates of 200-1000 MSpS and 12-16 bits of resolution may be
necessary
Often a current is used to drive an off-chip coaxial cable to yield a
voltage across the termination
• Audio: typically, 16-24 bits to headphones/speakers, with a conversion
rate of 44 kSpS
Data Converters
Nyquist-rate D/A Converters
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Data Converters
Nyquist-rate D/A Converters
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Introduction – II
Voltage and current references
Voltage and current references can be either generated on-chip, or
provided via an external pin
• Many DACs use integrated resistances or capacitances to attenuate (or,
more seldom, to amplify) the reference
Any error affecting the references limits the overall system performance
Æ should be constant independently of PVT variations, load, and time
• A careful layout design (common-centroid, dummy components,
temperature-insensitive, etc) leads to matching accuracies in the order
of 0.1-0.02% Æ resolutions up to 60-70dB are possible without
trimming of analog passive components, and without using digital
correction or digital calibration
Static errors are usually irrelevant; dynamic errors are much more
important Æ speed and linearity are affected
• Use of analog CMOS switches Æ low on-resistance, high speed of
switching, minimum side effects
– Natural in CMOS processes (MOS device is a better switch than transistor!)
– Complementary MOS or bootstrapped nMOS (gate voltage is a shifted-up
replica of the signal to be switched)
– Control of clock feedthrough (MOS channel charge flowing to D/S when the
gate control goes off)
Data Converters
Nyquist-rate D/A Converters
2
The noise spectral density vRef,n
must be well below the quantization floor:
2
<<
vRef,n
5
Data Converters
Reference noise – an example
2
vFS
22 N ⋅ 6 f s
2
<<
or iRef,n
2
I FS
22 N ⋅ 6 f s
Nyquist-rate D/A Converters
6
Types of converters
The demand on the noise floor of the reference becomes very
challenging for resolutions above 14 bits: if IFS=20mA, the noise
spectrum of the current reference must be below 0.79nA/sqrt(Hz),
which, across 50Ω, results in a noise voltage density of 39.5nV/sqrt(Hz)
(fairly low)
The basic components used in a DAC architecture normally classify the
DAC. We distinguish between:
• Architectures based on resistors
As a comparison, the spectral density of the input-referred noise of a
MOS transistor
t
i t is
i
• Architectures based on capacitors
vn2 Δf = 4kT γ g m
• Architectures based on current sources
and even a single transistor with g m = 0.2mA / V gives rise to a noise
voltage density as large as
vn = 7.4nV
Data Converters
Hz
Nyquist-rate D/A Converters
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Data Converters
Nyquist-rate D/A Converters
8
Resistor based
Resistive divider – I
Strips of resistive layers with a given specific resistance, ρ . The
effective number of squares, (L/W)eff, and the contact resistance, Rcont,
give the total resistance value ( ρ ranges from a few Ω/□ to kΩ/□)
⎛W ⎞
R = ρ ⎜ ⎟ + 2 Rcont
⎝ L ⎠eff
Resistive (Kelvin) divider, invented by Lord Kelvin in the 18th century
2:1 matching (no dummies,
resistance of metal layer is
neglected)
Absolute resistance value only important for power and area
consumption; relative value (matching) is what really counts
Data Converters
Nyquist-rate D/A Converters
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Resistive divider – II
i
8
Nyquist-rate D/A Converters
10
Alternative approach – unary selection
23 equal resistor, RU, generate 8 discrete analog voltages:
Vi = Vref
Data Converters
Only one switch on the divider-to-buffer path, but many control lines
i = 0...7
The resistive divider in (b) shifts the voltages by ½ LSB (Vref/2n+1) by
moving ½ unit resistance from the top to the bottom of the divider.
The selection of a voltage is done by a tree of switches whose state is
controlled by a digital input Æ n switches between ladder and buffer
Æ RC delay
The decoding method used to select the divider voltage depends
on a trade-off between speed, complexity, and power consumption
The buffer provides a very high input impedance, performing a voltage
measurement, and a very low output impedance for adequate driving of
the DAC load
Data Converters
Nyquist-rate D/A Converters
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Data Converters
Nyquist-rate D/A Converters
12
Digital potentiometer
Trade-off – matrix selection
A limit to the ladder DAC is set by the number of switches/control lines
(2n) required. The matrix approach reduces the complexity to 2⋅2n/2
(<< 2n); however, two switches in series in the signal path
• Another embodiment of the resistive ladder topology
• Same functionality as the conventional potentiometer, except that the
wiper terminal is controlled by a digital signal, so only discrete steps
are allowed
• Selection of the wiper position controlled via an n-bit register value
p , n=8,, the
In this example,
DAC is partitioned in 4
MSBs (rows) and 4 LSBs
columns)
• Communication and control of the device can be supported by a
parallel or serial interface
• Volatile or non-volatile logic to retain the wiper setting. For volatile
logic, the wiper is normally set at mid-range at power-up
Data Converters
Nyquist-rate D/A Converters
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Data Converters
Settling of the output voltage
Nyquist-rate D/A Converters
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X-Y selection with shunt resistances
Assume the speed of the buffer is very high Æ the voltage at the input
and output of the buffer depends only on the divider, approximated by
an RC time constant (with C concentrated at the buffer input). If the
output k is selected, then
Rs
( k −1) RU ⋅ ( 2N − k +1) RU
( k −1) ( 2N − k +1)
Req =
+ Non Ron =
RU + Non Ron
2N
( k −1) RU + ( 2N − k +1) RU
Rs
Cin = Cin , B + N on C p ,on + N off C p ,off
Rs
where Cin is the total capacitance at the buffer input. Cin,B is the input
capacitance of the buffer; Non and Noff are on and off switches connected
to the buffer input (their number is constant; in our example, Non=3,
Noff=2N-3); and Cp,on ≈ Cp,off are the associated parasitic capacitances
RS in parallel to k RU units:
higher speed, but also
higher power consumption;
for each line, the
equivalent resistance is
Req ( t ) = kRU || RS =
kRU RS
kRU + RS
Rs
Cin is almost constant, while Req depends on the selected tap (Req is
parabolic, maximum at mid-point) Æ signal-dependent time constant Æ
distortion! Æ unit resistor should be small enough
Data Converters
Nyquist-rate D/A Converters
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Data Converters
Nyquist-rate D/A Converters
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Settling of the output voltage – I
Settling of the output voltage – II
If slew-rate and bandwidth of the buffer matter (and disregarding RC
from divider) Æ assume an input step ΔVin ( 0 ) Æ
Non-linear combination of linear ramp and exponential ramp
Reconstruction filter yields the time average of the output waveform Æ
average of non-linear error causes distortion
τ
If the settling time is long enough, the integrated error during the
slewing period (area A in figure) is
From
continuity
of first
Vout ( t ) = Vin 0 − + SR ⋅ t
derivative
− ( t − t slew ) τ
@ t=tslew Vout ( t ) = Vin 0 − + ΔVin ( 0 ) − ΔV ⋅ e
( )
( )
ΔV τ = SR
τ = 1 2πβ fT
t slew =
⎞
1 ⎛ ΔVin
1 ⎛ ΔVin2
⎞
−
Δ
V
t
+
Δ
V
⋅
t
=
− SR ⋅τ 2 ⎟
⎜
slew
⎜
⎟ slew
2 ⎝ SR
2 ⎝ SR
⎠
⎠
for t < t slew
while during the settling period it is
ΔVin ⋅τ
for t > t slew
ΔVin ( 0 )
SR
In both cases, it is signal dependent Æ distortion may be an issue
For a quantitative estimate of distortion, a transistor-level simulation is
required
−τ
β = feedback factor (we assume: buffer = opamp +
feedback) ; fT = unit gain frequency of op-amp
Data Converters
Nyquist-rate D/A Converters
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Data Converters
Remarks on linearity
Nyquist-rate D/A Converters
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Segmented resistive DAC – principle
The use of shunting resistors has generated an auxiliary n/2-bit DAC Æ
evolution: segmentation realizes a high-resolution DAC by combining
the operation of two or more DACs (3+3 bits in DAC below: cascade of
3-bit MSB DAC + eight 3-bit LSB DACs)
• If linearity is an important issue, remember:
– A code-dependent settling of the output causes distortion
– A high SFDR demands that the variation of the settling time be much
smaller than the hold period Æ a low resistance is needed at every node
Data Converters
Nyquist-rate D/A Converters
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Data Converters
Nyquist-rate D/A Converters
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Segmented DAC
Effect of mismatch
Only one LSB DAC is needed, if good buffers are available – buffers
must have the same offsets, high input impedance and low output
impedance, and an input common-mode range of Vref
The ith resistance is
It is also possible to replace buffers with current sources: there is no
current flowing from LSB DAC to MSB DAC if the equation on the right
is satisfied
where εa is the absolute error, and εr,i is the relative mismatch. The voltage
at tap k is
k
Ri = Ru (1 + ε a ) (1 + ε r ,i )
Vout ( k ) = Vref
∑
∑
2
0
IL =
=
ΔVLSB
2 nLSB RL
2
2
nLSB
Ri
k = 0...2 n − 1
Ri
and is of course independent of εa:
k + ∑ 0 ε r ,i
k
Vref + − Vref −
nMSB
0
n −1
Vout ( k ) = Vref
RL
2
n −1
+ ∑0
2 n −1
ε r ,i
k = 0...2 n − 1
The error depends on the accumulation of mismatches, and is of
course zero at the two endings of the string
Data Converters
Nyquist-rate D/A Converters
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Mismatch with linear gradient
Nyquist-rate D/A Converters
22
INL with linear gradient: straight and folded line
Recall that INL ( k ) = Vout ( k ) − Vout ( k ) . Curves (a) and (b) show the INL
for α Δx = ±10 −4, and result in a maximum INL of ±0.8LSB
A straight string with unity elements spaced by ΔX and gradient α in
their relative values gives
Rk = R0 (1 + kα ΔX )
Data Converters
If the divider layout is folded around the mid-point, then the mid-point
voltage is correct; for the same value of the gradient, the maximum INL
becomes ±0.2LSB, curve (c). Careful layouts are generally required
k = 0...2 n − 1
and the output at the tap k becomes
Vout ( k ) = Vref
k + α ΔX ⋅ k ( k + 1) 2
2 − 1 + α ΔX ⋅ ( 2 n − 1) 2 n 2
n
Æ parabolic with initial value 0 and final value Vref
Data Converters
Nyquist-rate D/A Converters
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Data Converters
Nyquist-rate D/A Converters
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Example
Simulations/calculations
Vin ≈ Vref
Harmonic distortion caused by a linear gradient:
k
2n
and Vout ( k ) = Vref
Consider a gradient α = 2.5 ⋅10 −5 μ in the resistivity of a straight string
of resistors spaced by ΔX=4μ. The DAC is a resistive-string divider
connected between 0V and 1V.
Vout ( k ) ≈
(
2 n ⎡⎣Vin (1 + α ΔX 2 ) + Vin2 ⋅ 2 n α ΔX
(
)
50dB
which is enough for detecting spurs higher than -65dBc (18dB above
the noise floor)
A2nd
A fund
n
n
ref
2
( 2V )
ref
≈
Vin2 ⋅ 2 n α ΔX
( 4V )
ref
Vin
If Vin = Vin ,max = Vref 2 , then
A2nd
A fund
Nyquist-rate D/A Converters
)
2 − 1 + α ΔX ⋅ 2 − 1 2
n
( 2V )⎤⎦
1
⎡ 2
⎤
⎢sin (ω t ) = 2 (1 − cos ( 2ω t ) ) ⎥
⎣
⎦
nQ = −1.78 − 6.02 ⋅ 8 − 10 log 212 2 = −83dBc
Data Converters
→
)
2 − 1 + α ΔX ⋅ 2 n − 1 2 n 2
≈ Vin (1 + α ΔX 2 ) + Vin2 ⋅ 2 n α ΔX
The FFT of an input sequence made of 212 points gives a noise floor for
an 8-bit
8 bit DAC att
(
k + α ΔX ⋅ k ( k + 1) 2
n
25
Data Converters
Effect of random mismatch on resistors
=
(
)
28 ⋅ 2.5 ⋅10 −5 ⋅ 4
8
= 0.0032
= −49.9dB
Nyquist-rate D/A Converters
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Trimming and calibration
• Mismatch effects are often investigated with Monte Carlo simulations
If the resistor variations are as high as 10%, but they are not correlated
Æ noise floor is increased, but very small distortion (DNL is high, but
INL is very low)
• Trimming corrects statically the mismatches caused by inaccuracies in
the fabrication process
• Thin-film technologies that realize resistors on top of the passivation
layer of the IC are particularly suitable; resistors are trimmed very
accurately with a laser
≅ 67dB
• Use of fuses or anti-fuses for respectively opening or closing the
interconnections of a network of resistive elements
• Connection with fuses or anti-fuses is done during testing (either before or
after packaging) and is permanent
Data Converters
Nyquist-rate D/A Converters
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Data Converters
Nyquist-rate D/A Converters
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Calibration
R-2R resistor ladder DAC
Reduces the total number of resistors from 2n to (2+1)n = 3n
• Switches turned on or off at power-on (off-line or foreground
calibration) or during the normal operation of the converter (ideally,
without interfering with it: on-line or background calibration)
The resistance to
the left of every
node is 2R!
• These kinds of calibration are not permanent Æ can compensate for
slow drift, like aging, or, for background calibration, even temperature
effects (which is particularly important)
voltage mode
trade-off,
off, correction at the group level
• If too many elements Æ trade
INL
improvement
with 3-point
calibration of
8-bit DAC
current mode
virtual ground
Data Converters
Nyquist-rate D/A Converters
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Data Converters
Nyquist-rate D/A Converters
R-2R resistor ladder with buffer
30
Voltage mode
It can be verified (e.g. with Thevenin’s theorem) that connecting the kth
switch to Vref leads to a contribution
Vout = Vref 2 k
voltage mode
The output
p of the R-2R ladder in the voltage
g mode is the superposition
p p
of terms that are the successive divisions-by-2 of Vref
Vout =
current mode
Vref
2
bn −1 +
Vref
4
bn − 2 + ... +
Vref
2
n −1
b1 +
Vref
2n
b0
which is the DAC conversion of the digital binary input
Data Converters
Nyquist-rate D/A Converters
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Data Converters
Nyquist-rate D/A Converters
32
Current mode
Limits of R-2R resistor ladder
The current-mode circuit performs a successive division-by-2 of the
reference current Iref, provided that the voltage at the output node is
(virtual) ground
• About the output resistance of the reference source: the load seen by
the voltage ref. source is code-dependent Æ this may cause
harmonic distortion Æ use reference generators whose output
impedance is much lower than the minimum load
The superposition of the currents selected by the switches yields the
output current
I out =
I reff
2
bn −1 +
I reff
4
bn − 2 + ... +
I reff
2
n −1
b1 +
I reff
2n
• About the R-2R algorithm: the input-output characteristics of the R-2R
ladder (either voltage or current mode) is NOT intrinsically monotonic
(as it was for the resistive ladder)
b0
•
• The parasitic capacitance of the switched node remains at the same
voltage (analog ground or virtual ground) independently of the code
(desirable: faster switching, linear)
This is because in the R-2R ladder an increment by an LSB switches the
connection in all those arms where the control bit changes value Æ
because of random mismatches, it may happend that an increase by
1LSB switches off a contribution whose value is higher than the amount
that is switched on Æ worst case is at midpoint
• Glitches (because of large switched currents) may affect the dynamic
response of the current-mode R-2R (undesirable, of course)
Data Converters
Nyquist-rate D/A Converters
33
Data Converters
Current mismatches
Nyquist-rate D/A Converters
34
Replacing resistors with MOS
For medium accuracy, area can be saved by replacing passive resistors
with MOS devices, as in the current-mode ladder below.
(
n
Consider the switching at mid scale: I ref 1 2 −1 2
)
→ I ref 2
Observe that two equal parallel MOS networks divide the input current
into two equal parts regardless of the non-linear response of the single
element, as long as the two networks operate at the same (non-linear)
point.
If, because of mismatches, the MSB current is I ref (1 − ε ) 2, the midscale transistion becomes
(
I ref 1 2 −1 2 n
(
)
→ I ref (1 − ε ) 2
The step amplitude is ΔI ≈ I ref − ε 2 + 1 2 n
)
If ε > 1 2
the step amplitude is negative, and the transfer function
becomes non-monotonic
n −1
Data Converters
Nyquist-rate D/A Converters
35
Data Converters
Nyquist-rate D/A Converters
36
Deglitching
Capacitive divider DAC
A track-and-hold (T&H) after the DAC can highly improve the DAC
performance by removing the glitches. However, the linearity of the
T&H must be at least 10dB higher than the DAC’s, which may be
difficult to obtain
Vout = Vref
Data Converters
Nyquist-rate D/A Converters
37
Data Converters
Integrated capacitors
C1
C1 + C 2
Vout = Vref
k
2n
Nyquist-rate D/A Converters
38
Parasitic limitations
Capacitors may be implemented with parallel plates (poly-oxide-poly,
metal-insulator-metal (MIM)), or with vertical plates (see right), which
yields denser capacitors in modern fine-line processes with up to 10
different metal levels
• The parasitic capacitances connected to Vref or ground receive the
required charge by low-impedance nodes (good)
• The parasitic capacitances connected to the output node change the
output voltage (bad)
• If the parasitic capacitances are independent of the output voltage,
only a gain error is introduced (ok)
Vout = Vref
∑
∑
n
0
n
1
bi Ci
Ci + ∑ 0 C p ,i
n
• Non-linear parasitic capacitances that change with the output voltage
cause harmonic distortion (bad)
Data Converters
Nyquist-rate D/A Converters
39
Data Converters
Nyquist-rate D/A Converters
40
N-bit capacitor-divider DAC
Attenuation capacitor
The attenuation capacitor CA reduces the capacitor count
n
−1
The largest element in the right array is 2 2 CU instead of 2 n −1 CU
(
ideally, infinite
impedance
)
The total capacitance drops from 2 n CU to 2 ⋅ 2 n 2 − 1 CU + C A ≈ 2 ⋅ 2 n 2 CU
The value of CA is found by considering that CA in series with the leftside array must yield CU:
n
attenuator reduces
capacitance
spread
d
C A ⋅ 2 2 CU
n
2
C A + 2 CU
n
yielding C A =
22
n
2
= CU
CU
2 −1
Unfortunately, the value of CA is a fraction of CU: obtaining the desired
accuracy requires a great deal of care in the layout; furthermore, CA is
floating, and its bottom-plate parasitic capacitance is in parallel to the
left array
Data Converters
Nyquist-rate D/A Converters
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Data Converters
Capacitive multiplying DAC (MDAC)
Nyquist-rate D/A Converters
42
Offset cancellation in MDAC
During the reset phase, the op-amp is connected as a feedack unity
buffer, and the offset voltage is loaded onto the feedback capacitance
and all other capacitances. During the active phase, the offset is
effectively cancelled from the output.
MDAC avoids the demands on large input dynamic range for the opamp (and performs offset cancellation as well)
However, the feedback factor around the opamp is ½ during the active
phase and 1 during reset, complicating the frequency compensation of
the opamp.
Vout
Data Converters
Nyquist-rate D/A Converters
∑
=−
n −1
0
bi 2i CU
2 n CU
43
Data Converters
Nyquist-rate D/A Converters
44
Flip-around MDAC
A reminder
The previous MDAC has as many as 2 n+1 − 1 CU. The ”flip-around”
MDAC has only half as many, by charging k capacitors to Vref -Voff (all
others to -Voff) during Φ R, and then connecting them in parallel to
the other 2 n − k capacitors during Φ DAC – all caps are tied together and
connected to the output, performing charge sharing. Top-plate parasitics
are discharged (to -Voff) and then kept to virtual ground, while bottomplate parasitic caps are driven by voltage sources.
Vout = Vref
basic idea
• Any capacitor-based DAC architecture requires a reset phase to make
sure that the capacitor array is initially discharged
• The output is not valid during reset Æ a T&H is required to sustain the
output during reset
kCU
2 n CU
φR
+
GND
Vref
+
-
Data Converters
φDAC
Nyquist-rate D/A Converters
45
Data Converters
Hybrid capacitive-resistive DAC
Nyquist-rate D/A Converters
46
Current-based DAC
Resistance ladder implements the MSB conversion (3 bits here) while
the capacitive flip-around DAC performs the LSB conversion (n bits)
Vout = VMSB + Δ MSB
k currents out of 2 n − 1 are steered toward the output node, obtaining, as
usual
I out = I u b0 + 2b1 + 2 2 b2 + ... + 2 n −1 bn −1
(
)
k
2n
binaryy weighted
g
LSB
unary weighted
VMSB
Data Converters
VMSB +1
Nyquist-rate D/A Converters
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Data Converters
Nyquist-rate D/A Converters
48
Simplified model of single current cell
Ru
I N = Iu
;
Ru + Ron
Distortion
Vout ,max = I N RL
RN = Ru + Ron
k cells
2n − 1
;
1 + α ( 2 n − 1)
Vout ,max, nom = I N RL ( 2 n − 1)
The endpoint-fit INL measured in LSBs is then
Norton
INL ( k ) =
Vout ( k )
Vout ,max, nom
− Vout , nom ( k )
Vout ,max
Δ ( = I N RL )
=
(
(
))
k 1 + α 2n − 1
1+αk
− k;
k = 0...2 n − 1
Its maximum is at mid-scale, and is approximately INLmax = α ⋅ 2 2 n − 2
Vout
R ⋅R k
k
= kI N L N
= I N RL
;
RL + R N k
1+αk
INL < 1LSB → Ru > RL ⋅ 2 2 n − 2 ; if RL = 25Ω, n = 12 → Ru > 100 M Ω
R
α= L
RN
If we have a full-scale sinusoidal input with amplitude k p = 2 n −1 ,
the fundamental output harmonic has amplitude I N RL k p , while
the 2nd harmonic has amplitude I N RLα k p2 4, resulting in an SDR
of RL Ru ⋅ 2 n 4 . With the above values, SDR=-72dB
Vout depends non-linearly on k, i.e. on the signal Æ distortion!
Data Converters
Nyquist-rate D/A Converters
49
To summarize
Data Converters
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50
Unity current generator (BJT and MOS)
• The output resistance of the unity current source causes second-order
harmonic distortion
• The use of differential architectures eliminates (ideally) all even-order
distortion, relaxing the requirements on the unit current source
• A load resistance (coaxial cable) is only needed for very high speed
applications; for lower speeds,
speeds op
op-amps
amps can be used to present a
virtual ground to the DAC, again much relaxing the requirements on
the output impedance of the current sources
Rout ≈ rds 2 ( g m 4 rds 4 )
• Using current sources with high output resistance secures linearity at
low frequencies – at high frequencies, parasitic (non-linear)
capacitances dominate
• In general, complex schemes reduce the speed of operation
Data Converters
Nyquist-rate D/A Converters
51
Data Converters
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52
Random mismatch in current mirrors
ID =
β
(V
2
− Vth ) ;
2
gs
Example – scaling of transistor size
W
L
β = μ Cox
The required ΔI/I (for a given yield) for a 12-bit current-steering DAC is
0.3%; μCox is 39μA/V2, the unit current IU is 4.88μA; AVth is 2mV⋅μ and
Aβ is 0.3%⋅μ. Plot ΔI/I as a function of the MOS area. Estimate the MOS
size for a gate overdrive of 0.4V
Assume mismatches on β and Vth:
⎛ Δβ
2 ΔVth
I1 = I ⎜ 1 +
+
⎜
β Vgs − Vth
⎝
⎞
⎟⎟
⎠
⎛ Δβ
2 ΔVth
I 2 = I ⎜1 −
−
⎜
β Vgs − Vth
⎝
⎞
⎟⎟
⎠
(WL )min
Assume Δβ and ΔVth are uncorrelated Æ the total error becomes
4 ΔVth2
Δ I 2 Δβ 2
=
+
β 2 (Vgs − Vth )2
I2
Δβ 2
with
β
2
Aβ2
=
WL
;
ΔVth2 =
AV2th
⎛
4 AV2th
2
⎜
= Aβ +
2
⎜
(Vgs − Vth )
⎝
⎞
⎟
⎟
⎠
ΔI 2
I2
WL=12.11μ2,
WL
β=2IU/V2ov=60.0μA/V2,
Aβ and AVth are process constants; to halve the error, the device
area must increase 4 times
W/L=1.56
W=4.35μm
L=2.78μm
Data Converters
Nyquist-rate D/A Converters
53
Data Converters
Random mismatch with unary selection
ΔI out , r ( k ) ≈ ∑ 1 ΔI r ,i − k ⋅ 2 − n ∑ 1 ΔI r ,i
ΔI out ( k ) = ∑ i ΔI r , j − k ΔI r + ∑ i ΔI s , j − k ΔI s
The variance is calculated as
“systematic”
where ΔI r and ΔI s are average errors cancelling the possible gain error
(
2n
1
Δ I r ,i + 2 n I u ≡ g ⋅ 2 n I u
→
g=
2
−n
∑
2n
1
Maximum at mid-range:
Δ I r ,i + I u
Iu
ΔI out , r
Data Converters
k
1
ΔI r ,i + kI u
g
− kI u
∑
=
k
1
k m = 2 n −1
Δ I r ,i − k ⋅ 2 − n ∑ 1 ΔI r ,i
2n
2− n
1+
Iu
Nyquist-rate D/A Converters
∑
2n
1
→
2
n−2
ΔI out
ΔI r2
, r ,max ( k ) ≈ 2
It is usually required that the maximum INL error must be lower than
½ LSB, which results in the following requirement on ΔI r :
The gain-normalized current error becomes:
(k ) = ∑
)
2
2
2 −2 n
ΔI out
⋅ 2 n ΔI r2 − 2 k 2 − n ⋅ k ΔI r2 = k − k 2 2 − n ΔI r2
, r ( k ) = k ΔI r + k 2
Explicitly, we have that the gain g at the endpoint is given, with Iu unary
current, by (considering only random effects):
∑
2n
k
k
“random”
54
Random mismatch with unary selection – II
The endpoint-fit error for k selected unit current sources is
k
Nyquist-rate D/A Converters
2 n − 2 ΔI r2 = 2 n 2 −1 ΔI r <
Δ I r ,i
55
Data Converters
1
Iu
2
→
Nyquist-rate D/A Converters
ΔI r
< 2−n 2
Iu
56
Random mismatch with unary selection – III
Random mismatch with unary selection – IV
With a normal distribution of x = ΔI r Iu , the probability of having an
error equal to x is (with σ2 the variance of x ):
The normal distribution results in a yield of 0.99 at 2.57σ, and a yield of
0.999 at 3.3σ. In order to comply with these yields, we must then have:
x2
− 2
1
p ( x) =
e 2σ
σ 2π
2.57σ < 2 − n 2 → σ = ΔI r I u < 0.39 ⋅ 2 − n 2
and
3.3σ < 2 − n 2 → σ = ΔI r I u < 0.30 ⋅ 2 − n 2
However, it must be considered that this analysis does not account for
the effect of systematic mismatch, which can be even worse than the
random mismatch
Data Converters
Nyquist-rate D/A Converters
57
Data Converters
Selection of current sources
Nyquist-rate D/A Converters
58
Gradient error
Unit current sources are usually arranged in a two-dimensional array.
The simplest selection mode is a sequential unary thermometric
selection by lines and columns, starting in one corner of the array.
Below we see an 8-bit DAC where 70 cells are selected (code
01000110)
Let us assume that the error is linearly dependent on the cell position:
I u ( i , j ) = I u (1 + iγ x Δ x ) (1 + iγ y Δ y )
γx and γy being the gradients
Maximum error is approx. n 2 ⋅ γ x Δ x and m 2 ⋅ γ y Δ y , and periodic
• The above error causes INL
• Moreover, it is worth pointing out that unary selection ensured
monotonicity and enables flexibility, but requires one control signal for
each element
• This makes the unary selection approach unpractical for 8-bit or more
Data Converters
Nyquist-rate D/A Converters
59
Data Converters
Nyquist-rate D/A Converters
60
Selection of current sources
Current switching methods
The goal is to randomize the mismatches, keeping the accumulated
error low
• Binary-weighted DAC, combining 2k-1 unit current sources in parallel
(with single control signal for entire parallel connection)
3
– Virtually no decoding logic is required; however, possible nonmonotonicity
– With a random error, the maximum DNL (at mid-point) is
(
1
2
– Intrinsic monotonicity, minimum glitch power, good DNL/INL;
however, each current source needs an individual control signal;
– The maximum DNL is, for any code transition
a) Line and column shuffling (in common-centroid fashion); b) Use of
multiple local references, each close to the respective sector Æ lower
threshold mismatch; c) multiple reference + random walk selection of
sectors and unit cells Æ turns correlated error into pseudo-random noise
Data Converters
)
DNLmax = ⎜⎛ 2 n −1 ΔI r ΔI u + 2 n −1 − 1 ΔI r ΔI u ⎟⎞ ≈ ±2 2 n −1 ΔI r ΔI u
⎝
⎠
• Unary-control DAC (thermometer, shuffled, random)
Nyquist-rate D/A Converters
DNLmax = 2 ΔI r ΔI u
61
Data Converters
Segmentation with current switching
Nyquist-rate D/A Converters
62
Area of segmented DAC
Conceptual schematic of a 3-step segmented current-steering DAC
• The area of a segmented architecture depends on the area of the unit
current sources and the area of the circuitry necessary to generate
and distribute the control signals
thermometric
• The maximum allowed DNL determines the value of the gate area WL
of the MOS transistor used to generate IU in the binary-weighted LSB
DAC (see previous eq. on max. DNL in binary-coded DACs):
⎛
4 AV2th
WL > 2 nL +1 ⎜ Aβ2 +
2
⎜
V
V
−
(
)
gs
th
⎝
thermometric
⎞
⎟
⎟
⎠
DNL2max
Thus, the area of the single LSB cell is proportional to 2 nL , and
can be written as
AU = Au 2 nL
binary
Au being the area of the unit current cell with unary selection
( nL = 0)
Data Converters
Nyquist-rate D/A Converters
63
Data Converters
Nyquist-rate D/A Converters
64
Area of segmented DAC – II
Area of segmented DAC – III
• The area of the logic circuitry necessary to generate and distribute a
single thermometric code increases (roughly) linearly with the number
of MSB:
On the left, plots of
normalized DAC area for 12bit, 11-bit, and 10-bit
segmented DACs, versus nL
AU − MSB ,extra = Ad nM
• For a segmentation n = nL + nM , we obtain in total
ADAC = 2 n AU + 2 nM AU − MSB ,extra = 2 n Au 2 nL + 2 nM Ad nM
⎛
A n − nL ⎞
ADAC = 2 n AU ⎜ 2 nL + d
⎟
Au 2 nL ⎠
⎝
With a 3-step segmented current-steering DAC, the area becomes:
• If Ad Au = 8 and n = 12 , the DAC area is minimum for nL = 3
Data Converters
Nyquist-rate D/A Converters
⎛
⎞
A
ADAC = 2 n AU ⎜ 2 nL + n d nI 2 nI + nM 2 nM ⎟
2 Au
⎝
⎠
(
65
Data Converters
Switching of current sources
Nyquist-rate D/A Converters
)
66
Switching phase generator
• Remember: when generating the control phases, never leave the
connection of a unit current generator open, since the transistor would
be pushed into the triode region, with a long recovering time
both off: problem!
never both off: ok!
Data Converters
Nyquist-rate D/A Converters
67
Data Converters
Nyquist-rate D/A Converters
68