Design for Leading-Edged Mixed-Signal ICs
Analog Intellectual Property:
Why, When, How
Rob A. Rutenbar
Carnegie Mellon University
Pittsburgh, PA, USA
rutenbar@ece.cmu.edu
http://www.ece.cmu.edu/~rutenbar
© R.A. Rutenbar 2001
Be Honest: I Say “Analog”… You Think This
© R.A. Rutenbar 2001
Analog--Who Really Cares?
+
Copyright © 1993, The National Gallery, London
Copyright © 1993, The National Gallery, London
© R.A. Rutenbar 2001
Modern Systems Have Analog Interfaces
Telecom
Consumer
Analog
Interface
Automotive
Digital
Computing
Core
Medical
© R.A. Rutenbar 2001
Lots of Digital “Support” Functions Are Analog
¢
Some obvious, some not
Wireless
connectivity
Is analog
IO pads use
analog to control
signal shape
RF
Frontend
Modem frontend
also analog
Clock synch is
an analog problem
MODEM
Clock
PLL
LAN
Interface
Physical LAN layer
(Ether, Firewire, ..)
is all analog
© R.A. Rutenbar 2001
Lots of “Digital” Signals—Aren’t
¢
Ex: What the bits really look like read off a magnetic disk
The bits
are the bumps
on these sine waves,
by the way…
Courtesy
Jim Bain
CMU
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 01
© R.A. Rutenbar 2001
Result: An Increasing Design Problem
Commercial Mixed Signal ASIC
% Effort
Digital
Analog
© R.A. Rutenbar 2001
Why This Happens
Digital Methodology
Analog Methodology
ü CAD tools
ü Abstraction
ü Reuse & IP
à CAD tools
à Abstraction
à Reuse & IP
© R.A. Rutenbar 2001
Why This Matters
12000
SoC Design Starts
10000
8000
SoC Designs
Mixed Signal
6000
4000
2000
0
1997
1999
{
2001
Source: BT Alex Brown Research
© R.A. Rutenbar 2001
Outline
¢
Quick tour of mixed-signal System-on-Chip (SoC) design
¢
Design problems & strategies for analog building blocks
¢
Design problems & strategies for mixed-signal chips
¢
Talk emphasis
{
{
{
{
We do all this analog design by hand, as painful full custom, today
That has got to change—too many opportunities, too few designers
What are the prospects for “buy it”or “reuse it” for analog?
This is the hot topic in analog today: analog intellectual property
© R.A. Rutenbar 2001
Outline
¢
Quick tour of mixed-signal System-on-Chip (SoC) design
¢
Design problems & strategies for analog building blocks
¢
Design problems & strategies for mixed-signal chips
¢
Talk emphasis
{
{
{
{
We do all this analog design by hand, as painful full custom, today
That had got to change—too many opportunities, too few designers
What are the prospects for “buy it”or “reuse it” for analog?
This is the hot topic in analog today: analog intellectual property
© R.A. Rutenbar 2001
CMOS Scaling: Different Impact on Analog
¢
Central fact of life for digital: ICs get smaller, denser, faster
More…
More…
IC
Yesterday
¢
Today
Tomorrow
Scaling matters for analog too; but it’s different
© R.A. Rutenbar 2001
Analog: The Eggshell Model
¢
Analog circuits don’t get a lot bigger with scaling
{
{
{
Analogy credited to Paul Gray of Berkeley
Scaling provides more opportunities for analog interfaces
10K-20K analog devices/chip is common
Scaling
Digital
Core
Digital
Core
Shell is the
analog here:
thin layer of
interface to
continuous
real world
More egg;
not much
more shell
© R.A. Rutenbar 2001
What “More Mixed-Signal SoCs” Means
¢
Larger fraction of SoCs need some analog interfaces
Yesterday
Today
Tomorrow
A
A
A
A
A
A
A
A
A
A
A
© R.A. Rutenbar 2001
Example: Automotive Mixed-Signal ASIC
Mem
Logic
Mem
Mem
digital
CPU
© R.A. Rutenbar 2001
Example: Automotive Mixed-Signal ASIC
DAC
Driver
Support
Analog
ADC
Supply
© R.A. Rutenbar 2001
Example: Alcatel ISDN Chip
DSP
CPU Core
Logic
Analog
Frontend
Courtesy Frank Op’t Eynde, Alcatel
Memory
© R.A. Rutenbar 2001
Example: Alcatel GSM Cellular Chipset ‘96
LNA
R
F
PA
C
H
I
P
VCO
L
F
A
N
A
L
O
G
BBIC
MAC
LAYER
DIGITAL CHIP
C
O
D
E
C
MicroProcessor
MicroProcessor
RAM
ROM
Battery
Manager
Courtesy Frank Op’t Eynde, Alcatel
© R.A. Rutenbar 2001
Example: Alcatel GSM Cellular Chipset ‘98
LNA
LNA
PA
R
F
C
H
I
P
VCO
L
F
A
N
A
L
O
G
BBIC
MAC
LAYER
DIGITAL CHIP
C
O
D
E
C
MicroProcessor
MicroProcessor
RAM
ROM
Battery
Manager
© R.A. Rutenbar 2001
Alcatel GSM Frontend Chip
LNA
LNA
PA
R
F
C
H
I
P
VCO
L
F
A
N
A
L
O
G
BBIC
MAC
LAYER
DIGITAL CHIP
C
O
D
E
C
MicroProcessor
MicroProcessor
RAM
ROM
Battery
Manager
Courtesy Frank Op’t
Eynde,
Alcatel
© R.A.
Rutenbar
2001
Alcatel GSM Power Manager Chip
LNA
LNA
PA
R
F
C
H
I
P
VCO
L
F
A
N
A
L
O
G
BBIC
MAC
LAYER
DIGITAL CHIP
C
O
D
E
C
MicroProcessor
MicroProcessor
RAM
ROM
Battery
Manager
Courtesy Frank Op’t Eynde, Alcatel
© R.A. Rutenbar 2001
Example: Alcatel GSM Telecom Chipset ‘00
LNA
LNA
PA
R
F
C
H
I
P
VCO
¢
L
F
A
N
A
L
O
G
BBIC
MAC
LAYER
DIGITAL CHIP
C
O
D
E
C
MicroProcessor
MicroProcessor
RAM
ROM
Battery
Manager
Natural result of scaling is analog integration: fewer chips
© R.A. Rutenbar 2001
Outline
¢
Quick tour of mixed-signal System-on-Chip (SoC) design
¢
Design problems & strategies for analog building blocks
¢
Design problems & strategies for mixed-signal chips
¢
Talk “spin”
{
{
{
{
We do all this analog design by hand, as painful full custom, today
That had got to change—too many opportunities, too few designers
What are the prospects for “buy it”or “reuse it” for analog?
This is the hot topic in analog today: analog intellectual property
© R.A. Rutenbar 2001
Example of a Basic Building Block (or Cell)
Mixed-Signal System-on-Chip
Digital
Example:
one analog cell on
analog-side of a
mixed-signal ASIC
Vref Cell
Analog
© R.A. Rutenbar 2001
Just What Is An “Analog Building Block?”
¢
Typical analog cell
~5-100 devices (if bigger, usually use some hierarchy)
{ Active devices (FET, BJT, etc) and passives (R, L, C)
{ Often requires precision devices/passives for performance
{ Often requires sensitive device placement, wiring
{
11/4
Gain 60dB
UGF 111MHz
Phase 60deg
Slew 2V/us
CMRR: 60dB
PSRR: 70dB
THD: 1%
160/12
10pF
In54µA
23µA
In+
42/3
3/52
42/3
¿10pF
3/3
3/4
Specification
11/4
3/3
3/4
Circuit topology & sizing
Physical layout
Need all 3 of these to have a “complete” cell
© R.A. Rutenbar 2001
Analog Cells: Common Examples
¢
¢
Common cells
OpAmp
OpAmp
Comparator
Comparator
Bandgap
Bandgap
Voltage
VoltageRef
Ref
Oscillator
Oscillator
LNA
LNA
Mixer
Mixer
Analog
Analog
Switch
Switch
Etc...
Common subsystems composed from basic cells
Filter
Filter
PLL
PLL
General
General
A/D
A/D&&D/A
D/A
Audio
Audio
A/D
A/D
Regulator
Regulator
CODEC
CODEC
I/O
I/OLine
Line
Drivers
Drivers
Etc...
© R.A. Rutenbar 2001
Analog Cell Design: Critical Tasks
¢
No matter how you do it, you have to do these tasks
{
Basic device-level circuit design
80/4
80/4
Vdd
M3
M4
M8
Vbias3
Vdd
MX
Rc
11/4
11/4
M1
M2
Gain 60dB
UGF 111MHz
Phase 60deg
Slew 2V/us
CMRR: 60dB
PSRR: 70dB
THD: 1%
...
Generate
proper
specs
Cc
160/12
Vin–
M4
M5
M6
M7
Vout
Vin+
Cload
MY
Vbias2
Gnd
M19 M18
10pF
In54µA
In+
23µA
42/3
Vdd
42/3
M4
3/52
Vbias1
M5
M9
M5
Vb3
¿10pF
Vss
M19 M18
3/3
3/3
M6
3/4
Vout+
M7
M17
M16
M15
Vin+
Vout–
Vcm
M17
M16
M15
Vin+
Vout–
M1
M2
M12
M2
VinM9
M9
Vb2
Vout+
M13
M10
Vout+
Vin-
M8
Vb2
M13
M1
M8
M14
Vout+
Vcm
M14
3/4
Vb3
M3
M11
M12
M10
M3
M11
Vb1
Vb1
Vss
Choose
proper
circuit topology
Vss
Design
proper device
sizing/biasing
Optimize for
centering,
yield
© R.A. Rutenbar 2001
Analog Cell Design: Critical Tasks
No matter how you do it, you have to do these tasks
¢
{
Basic device-level layout design
vdd
Vdd
M4
M5
M19 M18
M6
M7
Vb3
M17
M16
M15
M14
Vout+
Vin+
Vout–
Vcm
M1
M2
Vin-
M8
M9
Vout+
Vb2
M13
M12
M10
M3
M11
Vb1
Vss
vss
From
sized
schematic
Choose
proper
cell footprint
Design
individual
device geometries
Place/route devices,
optimize area,
coupling, etc.
© R.A. Rutenbar 2001
Why Is This Actually Difficult…?
¢
Common misperceptions here
{
¢
Myth of “limited size”
{
{
¢
Based mostly on familiarity with digital cells, digital libraries,
and with digital design scenarios
“Hey--only 50 transistors? How hard can that be to design?”
“I don’t see people obsessing over NAND gate design!”
Myth of “limited libraries”
{
“There’s not much analog on chip, and it’s mostly understood
functions like A/D and D/A, so why not just design all the required
cells once, put them in a library, reuse them?”
© R.A. Rutenbar 2001
Reminder: Cell-Based Digital Design
¢
Digital ASIC design
{
{
{
Digital
HDL
Often starts from assumed library of cells (maybe some cores too)
Supports changes in cell-library; assumed part of methodology
Cell libraries heavily reused across different designs
Logic
Synthesis
Tech
Mapping
Physical
Design
Gate-Level Cell Library
© R.A. Rutenbar 2001
Cell-Based Design Strategies: Digital
¢
Where do digital cells come from?
Foundries:
3rd Party IP:
Optimized for
this fab
Emphasize
portability, quick use
Migration Tools:
Manual, Custom Design:
Old cells -> new cells
Proprietary or custom library
Migrate
© R.A. Rutenbar 2001
Cell-Based Design Strategies: Analog
¢
Where do analog cells come from?
{
{
{
¢
Mainly manual design
Often, manual redesign
Almost no reuse
Why is this?
© R.A. Rutenbar 2001
Analog Cells: Strong Fab Dependence
¢
No digital abstraction to “hide” process
{
No logic levels, noise margins, etc, on analog cells
Can’t hide behind nice 1s and 0s...
¢
Exploits physics of fab process, instead of avoiding it
{
{
{
Individual devices designed to achieve precise behaviors
Especially true with precision passive devices, which might require
separate process steps (eg, double poly for capacitors)
Circuits sensitive to all aspects of device/interconnect behavior,
even modest changes due to simple dimensional shrinks
© R.A. Rutenbar 2001
Analog Cells in Digital Processes
¢
¢
For SoC designs, want analog in standard digital process
Common problems
Low supply voltages preclude some circuit topologies
{
Vdd
M31
M27
M28
M4
M3
Ibias1
Vout+
M24
M23
M18
M20
M29
M33
M25
{
M8
M6
Cc
Vin–
Custom opamp
{
M7
M21 M19
M1
M2
Vout–
Vcm
M30
M5
Cc
M9
M11
M13
M15
M26
Vin+
Vout+
M12
M10
M16
M14
M17
4-high gate stack works
fine in 2 m, fails in
deep submicron due to
lack of VGS
Vss
Precision structures may be hard/impossible to build if special
layers are unavailable (eg, poly-poly capacitor)
Digital processes do not characterize devices for analog uses,
eg, models do not capture subthreshold ops, matching, etc
© R.A. Rutenbar 2001
Result: Analog Cells Resist Scaling/Migration
¢
Analog cells manipulate precise electrical quantities
{
{
{
Depend on precise physical parameters, precise device geometry
Scale or migrate: process changes, so must redo circuit and layout
Retarget circuit function: specs change (even a little), must redo ckt
Scale/migrate
Scale/migrate/retarget
© R.A. Rutenbar 2001
Note: Feature Size Is Scaling…
Min Wire Widths
0.5um
0.35u 0.25u 0.18u
© R.A. Rutenbar 2001
Note: … Electrical Interface Specs May Not
¢
Example: currents in critical wires affects min allowed width
Min Wire Widths
0.5um
0.35u 0.25u 0.18u
Min Wire Width
to Carry Current ~ 2.5mA
~1 um / mA
of current,
independent of
feature size
© R.A. Rutenbar 2001
Major Impact: Analog is Less Library-able
¢
Cell design difficulty, libraries
OK, so, maybe it’s hard to design an analog cell.
{ So, why not just design it once, add to lib, reuse it?
{
¢
Problem: leverage not same for analog libraries
{
How big is a digital library? Big enough to get all necessary logic
functions, IO variants, timing variants, drive strengths, to first order
Logic
functions
X
D Q
Fanin &
fanout
variants
X
Timing,
latch/FF,
scan
variants
X
Drive
strength
(1X, 2X
4X, 8X)
variants
= ~1k-2k
cells
© R.A. Rutenbar 2001
Analog Cell Libraries: Dimensionality
¢
Problem: many continuous specs for analog cells
11/4
11/4
160/12
10pF
=
In54µA
23µA
In+
42/3
3/52
42/3
¿10pF
3/3
3/3
3/4
X
¢
Spec=LOW
Spec=HIGH
variants
for ALL
combinations
=
10 independent
performance
specifications
3/4
=
~ 1000 variants
for just this cell
Can’t just build a practical-size, universal analog library
© R.A. Rutenbar 2001
Analog Cell Libraries: Dimensionality
¢
Dimensionality: Reality check
OK, do you really need all 1000 of those variants?
{ Can’t we make do with just a few--like we do for digital gates?
{
¢
Maybe: depends on your application
Performance
+
worst
+
+
+
But not out here, on
high-performance apps,
where every spec
matters, most are
interdependent, and
there is little slack on
meeting design goals
+
+
Ble
edi
n
+
ge
dg
+
e...
+
best
best
Performance
At modest levels of
performance, you may be
able to survive with
limited variants, specs
worst
© R.A. Rutenbar 2001
Analog Cells: Design & Reuse Strategies
¢
2 major issues
How do I make it easier to design this cell in the first place?
{ How do I avoid designing it again? Can I reuse it, wrap/buy it as IP?
{
¢
Design: focuses at 3 levels
{
¢
Devices, cells, cores
IP/reuse: focuses on 3 strategies
{
Hard, firm, soft IP strategies
© R.A. Rutenbar 2001
Analog Cells: Design & Reuse Strategies
¢
Simple taxonomy
IP/REUSE
hard
device
soft
Libraries of difficult,
exotic device layouts
Parametric device
layout generators
Libs of generic cell
Parametric templates
for schematic, layout
Analog ckt synthesis
and layout synthesis
Libs of useful block
Parametric templates
for useful cores
Mixed-signal system
assembly
cell layouts for specific fab
DESIGN
firm
core layouts for specific fab
Focus is on
layout reuse
Focus is on
reusable circuit
& layout templates
--
Focus is on
synthesis, from
spec to ckt to layout
© R.A. Rutenbar 2001
Analog Cell Design & Reuse
¢
What are people most commonly doing right now?
{
(Actually, they’re mostly designing by hand, one device at a time…)
IP/REUSE
device
DESIGN
cell
hard
firm
Libraries of difficult,
exotic device layouts
Parametric device
layout generators
Libs of generic cell
layouts for specific fab
Parametric templates
for schematic, layout
Analog ckt synthesis
and layout synthesis
Libs of useful block
Parametric templates
for useful cores
Mixed-signal system
assembly
core layouts for specific fab
soft
--
© R.A. Rutenbar 2001
First, Look at Device-Level Issues
¢
Question: why the emphasis on individual devices…?
IP/REUSE
device
hard
firm
Libraries of difficult,
exotic device layouts
Parametric device
layout generators
Libs of generic cell
Parametric templates
for schematic, layout
Analog ckt synthesis
and layout synthesis
Libs of useful block
Parametric templates
for useful cores
Mixed-signal system
assembly
DESIGN
cell layouts for specific fab
core layouts for specific fab
soft
--
© R.A. Rutenbar 2001
Analog Device IP
¢
Basic idea
Analog cells require “difficult” device structures
{ May need large devices, aggressive matching, unusual precision
{ Can save device layouts in a library, or more commonly...
{ ... write layout generators; may be provided by your foundry
{ Implementations vary: can use commercial frameworks (Mentor
GDT, Cadence PCELL), or write your own (C++, JAVA, etc)
{
Ν7
Device
IP
Gen.
© R.A. Rutenbar 2001
Device-Level IP: What “Large” Means
Digital FET
Analog FET
© R.A. Rutenbar 2001
Device-Level IP: Limited Porosity
Analog FET
Also,
precision devices
almost never
allow wires
over the top,
to minimize
potential coupling.
This whole
object is
blocked for
upper metals.
© R.A. Rutenbar 2001
Large Can Mean Very Large, Too
A small
CPU core
1 FET
A few
capacitors
© R.A. Rutenbar 2001
Example: Analog Precision Tricks for Devices
¢
Consider a resistor which uses a resistive poly layer
Resistive
material
Metalstrapped
Low-precision R, pins
poly snake resistor
High-precision R, add dummy
bars at ends, well and guard ring
Higher-precision R, poly bars
with all-metal interconnect
Interdigitated pair of
precise-ratio 2:1 resistors
© R.A. Rutenbar 2001
Industrial Ex: Precision Interdig Resistor Array
Courtesy Neolinear
© R.A. Rutenbar 2001
Next, Look at Hard Analog IP
¢
Question: how much can you reuse complete layouts?
IP/REUSE
hard
soft
Libraries of difficult,
exotic device layouts
Parametric device
layout generators
cell
Libs of generic cell
layouts for specific fab
Parametric templates
for schematic, layout
Analog ckt synthesis
and layout synthesis
core
Libs of useful block
layouts for specific fab
Parametric templates
for useful cores
Mixed-signal system
synthesis
device
DESIGN
firm
--
© R.A. Rutenbar 2001
Hard Analog Cell IP
¢
Basic idea
{
{
{
Hard IP (layouts) for common, generic cell functions
Performance ranges estimated to target common application areas
(eg, audio, video, LAN, IO driver, etc)
Available from some foundries; also some 3rd party IP shops who
design for standard digital fabs
Performance
worst
+
+
Tend to stay away from
maximally aggressive
performance specs;
target common
mid-range performance
+
+
Ble
edi
n
+
+
ge
dg
e...
best
best
Performance
worst
© R.A. Rutenbar 2001
Hard Analog Cell IP: Analysis
¢
Pro
{
¢
Again, makes it easy to do some simple functions
Con
{
{
Unlike digital libraries, unlikely that 100% of needed cells available
And, cell portfolio will differ significantly from vendor to vendor
Vendor 3
Coverage
Vendor 2
Coverage
Your mixed
signal ASIC
Vendor 1
Coverage
Sorry, this requires
custom analog-more design effort,
impact on design risk
© R.A. Rutenbar 2001
Focus Now on Design & Synthesis
¢
OK, suppose you can’t just buy the analog cells you need;
what can you do to help design them faster, better?
IP/REUSE
hard
device
soft
Libraries of difficult,
exotic device layouts
Parametric device
layout generators
Libs of generic cell
Parametric templates
for schematic, layout
Analog ckt synthesis
and layout synthesis
Libs of useful block
Parametric templates
for useful cores
Mixed-signal system
synthesis
cell layouts for specific fab
DESIGN
firm
core layouts for specific fab
--
© R.A. Rutenbar 2001
Cell-Level Strategies
¢
Aside from doing everything manually, are there options?
¢
Template-based design
{
{
¢
If you keep designing the same cells, for similar ranges of
performance, try to capture central characteristics as a template
Parameters fill in the template, change resulting design
Analog synthesis
{
{
For more general case, specify critical performance constraints
(electrical, geometric, etc)
Synthesis tool uses numerical/geometric search to create circuit to
match your design goals
© R.A. Rutenbar 2001
Analogy from Digital World
¢
How do people put big ASICs together today?
{
In big pieces, compiling & synthesizing the chunks as needed
I need 75,0000 gates
of random logic:
Use logic synthesis
followed by
physical synthesis
Digital ASIC
I need an Embedded SRAM:
Use a RAM generator tool
I need a Regular Datapath:
Use a Datapath compiler
I need a Register File:
Use a RegFile compiler
© R.A. Rutenbar 2001
On the Analog Side of a Mixed-Signal SoC…
¢
We want the same sort of functionality
{
{
Synthesis: for the very custom cells that determine analog performance
Templates: for the less custom, more regular stuff left over
Mixed-SignalASIC
I need a custom
Voltage Reference
Use analog circuit &
physical synthesis
I need a custom
Video Amplifier
Use analog circuit &
physical synthesis
I need a set of custom
High-Precision Passives
Use a Device generator
I need a custom A/D Converter
Use a mix of template compilers
and custom analog synthesis
© R.A. Rutenbar 2001
Template Example: CMOS Analog Cells
¢
Manually capture regularities as procedures for high-use cells
{
{
Can mix device generators, cell generators, compaction ideas, etc.
Still requires significant manual setup & maintenance investment
Courtesy Koen Lampaert, Conexant
© R.A. Rutenbar 2001
Template Example: RF Components
¢
Optimizes LC-oscillators from
specs to layout [Deranter DAC’00]
{
{
{
Simulated annealing in combination
with circuit simulations and some equations
FEM simulations to characterize inductor coils
Auto template-based generation of VCO layout
Rs
Low resistive sub
CMOS 0.35µm
1.26 nH
6.5 Ω
High resistive sub
µm
BiCMOS 0.65
2.3 nH
5.2 Ω
Rad, W, Turns
109 µm, 40 µm, 2
141 µm, 5 µm, 2
32 mW
8.2 mW
Parameter
Ls
Power
Courtesy Georges Gielen, K. U. Leuven
© R.A. Rutenbar 2001
Template Example: RF Components
¢
RF mixer, circuit & layout optimized
together, [Gielen ICCAD01]
An optimized layout
One quarter of the mixer core
Complete mixer floorplan, with
quarter-piece above highlighted
Courtesy Georges Gielen, K. U. Leuven
© R.A. Rutenbar 2001
More General Attack: Analog Synthesis
¢
Basic idea
Circuit synthesis: transform cell spec into sized/biased schematic
{ Layout synthesis: transform device-level netlist into laid-out cell
{
Gain 60dB
UGF 111MHz
Phase 60deg
Slew 2V/us
CMRR: 60dB
PSRR: 70dB
THD: 1%
Circuit
Synthesis
11/4
11/4
160/12
10pF
In54µA
23µA
In+
42/3
3/52
42/3
¿10pF
3/3
3/4
3/3
3/4
Mimics ideas from digital
logic/layout synthesis
{ But, focus is transistor-level synthesis
{ A few alternative approaches
{
Circuit
Layout
© R.A. Rutenbar 2001
Cell-Level Synthesis: Framework
¢
Most approaches have this overall structure
Optimization
Engine
Evaluated
Circuit
Performance
Candidate
Circuit
Design
Evaluation
Engine
¢
Uses heuristic or numerical search
Optimization engine:
{ Evaluation engine:
{ Cost-based search:
{
proposes candidate circuit solutions
evaluates quality of each candidate
cost metric represents “goodness” of design
© R.A. Rutenbar 2001
20 Years of Synthesis Distilled Onto 1 Slide…
(1) Scripting
Optimization Engine
You
(2) Equation-Based
Optimization Engine
Numerical
optimizer
Evaluation Engine
Evaluation Engine
Eqns you write:
Eqns you write:
I = K’/2 W/L (Vgs-Vt)2
(3) Symbolic analysis
I = K’/2 W/L (Vgs-Vt)2
(4) Simulation-Based
Optimization Engine
Numerical
optimizer
Optimization Engine
Global
optimizer
Evaluation Engine
Auto-derived eqns
Evaluation Engine
I = K’/2 W/L (Vgs-Vt)2
Industrial simulator
© R.A. Rutenbar 2001
Eqn-Based Optimization: Example
¢
Example: posynomial-formulation
{
{
[Hershenson ICCAD98]
If you can render all equations as posynomials (like polynomials,
but real-valued exponents and only positive terms, eg 3x2y2.3z-2),
can show resulting problem is convex, has one unique minimum
Geometric programming can solve these to optimality
Example:
opamp
circuit
synthesized,
fabbed in
TSMC
0.35 m
CMOS
Optimal trade-off curves
Courtesy Mar Hershenson, Stanford
© R.A. Rutenbar 2001
Symbolic Analysis Example
¢
Katholieke Univ. Leuven, ISAAC/SYMBA tool [Gielen JCTh’95]
AV 0 =
g m, M 2
g m, M 4
g m, M 1  g o , M 4 g o , M 5
Ga + g o, M 9 + g o,Q 2 


+
 g m, M 5 + g mb, M 5

Q2


Courtesy Georges Gielen, KUL
© R.A. Rutenbar 2001
Simulation Based Example: Cells from TI
¢
Done using CMU A NACONDA tool [Phelps CICC99]
Run on CPU farm
5 runs shown here
All specs met
All specs fully simulated
Power (mW)
20
{
Folded cascode opamp,
high-drive output stage
{
{
33 devs, 2 Rs, 2 Cs; 0.8um CMOS
Difficult goals
High drive amplifier, 5Ωload
{ Nominal THD, 0.1%
{ 1kHz, 2.6V p-p input voltage
{
18
TI’s manual design
Slightly
overdesigned
16
14
75
135
95
115
Area (1000 sq. grids)
© R.A. Rutenbar 2001
Large Sim-Based Example: TI ADSL CODEC
¢
¢
[R. Hester, et al.. IEEE Int’l Solid-State Circuits Conf., 1999]
[R. Phelps, et al., ACM/IEEE Design Automation Conf, 2000]
EQF
Equalizer
Analog
Low-Pass
Filter
Programmable
Gain
Amplifier
Analog to
Digital
Converter
Digital
Low-Pass
Filter
Decimation
1.54MHz,
corner
0dB gain
0-25dB/MHz
gain, in
5dB/MHz
steps
2.5-11.5 dB
gain, in
0.25dB
steps
4416KHz
14bits
1.1MHz
corner,
0dB gain
Input fc
4416KHz
Output fc
2208KHz
© R.A. Rutenbar 2001
EQF: What It Does
EQF = equalizer + 4th-order elliptical low-pass C-T filter
¢
{
{
Programmably amplifies signal (since attenuated by copper)
Filters data from spectrum (avoiding phone voice band)
Spectral Mask
A ll6 Eq Settings
Flat Eq Setting
Eq5
30
0
10
Eq1
Gain (dB)
Gain (dB)
Eq4
Eq3
Eq2
0
Eq0
-60
20
-40
Eq0
-80
-10
0
-20
0.4
0.8
1.2
Freq (M H z)
1.6
0
2
4
6
8
10 12 14 16
Freq (M H z)
© R.A. Rutenbar 2001
EQF Block: What It Looks Like
¢
¢
5 low-noise amps, ~100 passives, 36
program switches, 6 op-modes,
~400 devices, flat; ~2-3hrs to SPICE
OP
OM
OM
B
A
A
Vin
A
+
B
B
+
+
+
+
Vout
© R.A. Rutenbar 2001
CMU Synthesis Results: Noise vs Area
¢
Full sizing/biasing ~10hours on 20 CPUs; all TI specs met
125
Max Noise 25-1104KHz @25oC (nV/Hz1/2)
CMU3
CMU1 TI Hand
CMU2
100
Smaller 75
&
Biggest &
less noise
least noise
50
25
1000
1100
1200
1300
1400
1500
Area (1000 square grids)
© R.A. Rutenbar 2001
Synthesis Results: Spectral Mask
Eq0 Passband
TI Hand
Gain (dB)
0
-2
Eq0 Spectral Mask
CMU1
-4
0
CMU2
-20
CMU3
-8
0
0.4
0.8
1.2
Freq (MHz)
1.6
Gain (dB)
-6
-40
-60
¢
¢
~ 2 months designed manually
Synthesized automatically overnight -80
0
2
4
6
8
10 12 14 16
Freq (MHz)
© R.A. Rutenbar 2001
One More Messy Issue: Design Centering
¢
Cannot ignore this entirely in any analog design flow
{
Optimization-based attacks can find “bad” corners of design space
Phase Margin 95
Manual design
90
Input spec:
85
Phase margin > 77°80
75
at Vdd = 5.0V
70
If ignore range / mfg variations,
you only get what you ask for:
Phase OK at 5V, but not elsewhere
Synthesis
65
60
4.5
4.7
4.9 5.0
5.1
5.3
5.5
V dd (V)
¢
2 broad, overall strategies
{
{
{
Use first-order heuristics in numerical synthesis, then run centering
Combine full statistical optimization in with numerical synthesis
Examples: [Mukherjee TCAD’00], [Debyser, ICCAD’98]
© R.A. Rutenbar 2001
Example: Centering Heuristics in Synthesis
¢
Simple designer-derived constraints in ANACONDA synthesis
{
Require matched devices to be “big”; sensitive devices to be “far
enough” into desired region of operation (eg, 250mV above VT)
Example
Monte Carlo
spread for a small
TI opamp
120
60
Hand design
3 process,
+/-10% supply
& temp. variation
Plots show
low-frequency
gain for
manual, auto
designs
0
2000
2500
3000
(V/V)
2000
Synthesized
design
3000
2500
(V/V)
120
60
0
© R.A. Rutenbar 2001
Cell-Level Analog Layout Synthesis
¢
Basic task
11/4
11/4
160/12
10pF
In54µA
23µA
In+
42/3
3/52
42/3
¿10pF
3/3
3/4
¢
3/3
3/4
Layout
Synthesis
From schematic +
geometric constraints
to physical layout
Major strategies
{
{
{
Enhanced polygon-editing
Analog compaction & templates
Physical synthesis: full device-level custom place/route
© R.A. Rutenbar 2001
Analog-Specific Optimizations: Place/Route
¢
Placement symmetric and diffusion merging
No symmetry
No merging
¢
Symmetry
No Merging
Symmetry
Merging
Routing: differential symmetric and coupling avoidance
Wiring task
with
Obstacle
Symmetry
No crosstalk
No symmetry
No crosstalk
Symmetry
Crosstalk
[Cohn, JSSC91]
© R.A. Rutenbar 2001
Small Physical Synthesis Example: Close-up
¢
Commercial
tools emerging
{
¢
Neolinear’s
NeoCell
This example
{
{
{
CMOS
~50 devices
Layout < 1 hr
Courtesy Neolinear
© R.A. Rutenbar 2001
Large Physical Synthesis Example
¢
Proprietary CMOS comparator auto-layout from NeoCell
Courtesy Neolinear
© R.A. Rutenbar 2001
Subsystem Example: Cells + Glue Circuits
GLUE
CELL1
CELL1
CELL2
CELL2
MORE GLUE
Courtesy RocketChips and Neolinear
© R.A. Rutenbar 2001
Historically—Why has this been so Hard?
Mediocre
analog point tools
Ad hoc, incomplete
capture of design intent
Aaargh…!
Tools!
…what the
heck is t hat ?
¢
Too much art,
not enough science
With new synthesis/analysis tools, improved methodologies, &
improved attitudes about design—stage set for radical changes
© R.A. Rutenbar 2001
New Idea: Analog IP = Capture + Synthesis
¢
Commercial example from Neolinear NeoCircuit/NeoCell flow
Unsized commercial
diff-amp cell
0.6um proprietary
CMOS fab
Circuit
Synthesis
TSMC 0.35um
CMOS fab
Circuit
Synthesis
W=83
L=6
Physical
Synthesis
Physical
Synthesis
78% less area; 42% less power
© R.A. Rutenbar 2001
Outline
¢
Quick tour of mixed-signal System-on-Chip (SoC) design
¢
Design problems & strategies for analog building blocks
¢
Design problems & strategies for mixed-signal chips
¢
Talk emphasis
{
{
{
{
We do all this analog design by hand, as painful full custom, today
That has got to change—too many opportunities, too few designers
What are the prospects for “buy it”or “reuse it” for analog?
This is the hot topic in analog today: analog intellectual property
© R.A. Rutenbar 2001
What’s Left to Do: Chip-Level Design
¢
OK, you design/buy/synthesize all your cells…then what?
Chip-level design. (…and, problems don’t get easier)
IP/REUSE
hard
device
DESIGN
soft
Libraries of difficult,
exotic device layouts
Parametric device
layout generators
Libs of generic cell
Parametric templates
for schematic, layout
Analog ckt synthesis
and layout synthesis
Libs of useful block
layouts for specific fab
Parametric templates
for useful cores
Mixed-signal system
assembly
cell layouts for specific fab
core
firm
--
© R.A. Rutenbar 2001
Hard Analog Core IP (= Mixed-Signal IP)
¢
Recent commercial idea
{
{
{
Don’t focus on basic cells, focus on bigger mixed-signal cores
Industry standards fix many specs; target big ASIC foundries
Interesting technical (& business) issues here
IP/REUSE
hard
DESIGN
device
cell
core
Libraries of difficult,
exotic device layouts
firm
Parametric device
layout generators
soft
PLL
A/D, D/A
Filter
Codec
Ethernet IO
Firewire IO, ….
--
Libs of generic cell
layouts for specific fab
Parametric templates
for schematic, layout
Analog ckt synthesis
and layout synthesis
Libs of useful block
layouts for specific fab
Parametric templates
for useful cores
Mixed-signal system
assembly
MixSig
Core
cell
cell
Digital blocks
cell
cell
cell
cell
Hide low-level analog;
basic cells hand-crafted to
exploit foundry process
© R.A. Rutenbar 2001
Template-Based System Layout Example
¢
Analogy: just like digital datapath generators
{
Can exploit analog regularities you know; procedurally generate
14-bit 150-Ms/s 0.5um CMOS DAC
ANALOG
CLOCK
DRIVER
DIGITAL
CLOCK
DRIVER
FULL DECODER
[ISSCC’99]
J. Vandenbussche, G. Van
der Plas, A. Van den Bosch,
W. Daems, G. Gielen,
M. Steyaert, W. Sansen
SWATCH ARRAY
CURRENT SOURCE ARRAY
Courtesy Georges Gielen, K.U. Leuven
© R.A. Rutenbar 2001
Mixed-Signal SoC Revisited…
¢
We want block-level IP & assembly for both digital and analog
{
{
Synthesis: for the very custom, performance-sensitive circuits
Templates: for the less custom, more regular stuff left over
I need 75,0000 gates
of random logic:
Use logic synthesis
followed by
physical synthesis
I need a custom
Video Amplifier
Use analog circuit &
physical synthesis
Mixed-SignalASIC
I need an Embedded SRAM:
Use a RAM generator tool
I need a set of custom
High-Precision Passives
Use a Device generator
I need a custom A/D Converter
Mix of templates and
custom analog synthesis
© R.A. Rutenbar 2001
Example: Dual-Tone Multi-Frequency Decoder
Analog
PLL Clock
Results Converter
( FFT )
Authored with
Neolinear and Cadence
Authored with Cadence
ROM ( 512 x 16A )
RAM ( 256 x 16 )
DSP Core
RAM ( 128 x 16 )
I/O pads
Glue Logic
Authored with
Artisan ROM Compiler
Authored with
Artisan RAM Compiler
Authored with Cadence
Courtesy Artisan, Cadence and Neolinear
© R.A. Rutenbar 2001
Pushing Inside
the PLL PLL
Decoder
¢
All analog done via custom synthesis on this design
Counter (3-bit)
Divider ( 2-bit )
Buffers
Authored with Cadence
Authored with Cadence
Bias Xtors
Voltage-Controlled
Oscillator
Phase Detector
Authored with Cadence
Charge Pump
Authored with NeoCell
Cadence ® Generic PDK
.18 6LM Generic Process
Top block & support logic
assembled using Cadence
Courtesy Cadence and Neolinear
Authored with NeoCell
© R.A. Rutenbar 2001
Next Problem: Mixed-Signal Chip Assembly
¢
¢
…or, “When Bad Things Happen to Good Cells”
Noise upsets on delicate/precise analog
{
{
¢
Thermal issues
{
{
¢
From noisy digital wires nearby
From noisy shared substrate and from noisy power grid
Large digital blocks switching, or large analog devices: heat
Temperature changes can affect precision analog
Solutions
{
{
Segregate (away from digital)
Isolate, shield (from noise)
Analog
© R.A. Rutenbar 2001
Noise At Mixed-Signal Chip Level
¢
Coupled through supply rails and common substrate
{
Precise analog biasing easily vulnerable to voltage upset
pad
Analog
(Sensitive)
Power bus
interconnect
Digital
(Noisy)
pad
Power bus
interconnect
Substrate
pad
Chip/package
interconnect
L wirebonds
© R.A. Rutenbar 2001
One Assembly Example: IBM Data Channel
¢
Digital switching is the source of (almost) all evil for analog
Power
Measurements from IBM disk data channel;
Substrate noise spec 4mV -- exceeded
VDD
Switching
current
Power
Substrate
Substrate Gnd
5mV
Ground
Courtesy Bob Stanisic/Tim Schmerbeck, IBM
© R.A. Rutenbar 2001
Another Example: TI High-Speed Video DAC
Texas Instruments
High-speed video DAC, ~1994
Measured chip
performance at 14.4MHz
ADC
codes
Volts
4.2
DAC
Sparkle
codes,
errors
2.8
1.4
Samples
0
Substrate
800mV p-p
-1.4
30
90
150
210
Time (ns)
Courtesy Texas Instruments
© R.A. Rutenbar 2001
CAD Solution: Power Grid Synthesis
¢
Auto power grid synthesis
{
{
{
{
{
Re-synthesized IBM grid
Power grid routed, sized
Power IOs assigned
Substrate contacts configured
Decoupling caps added
Analog
[Stanisic JSSC 94]
Vnoise
[mV] (mV)
Dynamic
Noise
Vdrop
[mV] (mV)
Static
IR Drop
60
100
50
80
40
60
30
20
40
10
20
0
0
Bus +I/O +Sub +Caps
only cells cons
Bus +I/O +Sub +Caps
only cells cons
© R.A. Rutenbar 2001
Mixed-Signal Chip-Level Assembly Today
¢
Embarrassingly ad hoc
{
{
{
¢
Lots of guessing (and lots of praying) about floorplan, global signal
routing, block-level isolation structures, etc
Often vastly over-conservative; sometimes just plain wrong
Often takes a few silicon spins to iron out ( “few” may mean 5-10 at
RF and higher frequencies)
Where the action is
{
{
Full-chip and package extraction and simulation for noise coupling
Smarter circuit design methodologies for noise immunity (think
“echo cancelation”, but replace “echo” with “substrate noise”…)
© R.A. Rutenbar 2001
Conclusions
¢
Analog circuits: here to stay
{
{
¢
Mixed-signal design realities
{
{
{
{
¢
In an SoC world, big systems need to talk to the external world
The world is analog (…get used to it); analog does this communication
Analog cells != digital cells
Not as easily library-able; don’t scale; don’t migrate
Tightly bound to fab process, difficult precision requirements
Chip level assembly is nasty
Design strategies
{
{
Less art, more science: better methodologies, real synthesis tools
Analog IP: design for migrating, retargeting is the next big thing
© R.A. Rutenbar 2001
Where all this Analog IP Stuff is Heading
Analog folks want IP / reuse, too
Analog Synthesis
Analog IP
M ic roso
ft
New
New
Low
Low
Price!
Price!
© R.A. Rutenbar 2001
Select References
¢
General Analog CAD Survey
{
{
{
{
¢
R. A. Rutenbar, "Analog Design Automation: Where are We? Where are we Going?", Proc.
IEEE CICC, May 1993.
L. R. Carley, G. Gielen, R. A. Rutenbar, W. Sansen, "Synthesis Tools for Mixed-Signal ICs:
Progress on Frontend and Backend Strategies,“ Proc. ACM/IEEE DAC, June 1996.
G. G. E. Gielen, R. A. Rutenbar, “Computer Aided Design of Analog and Mixed-Signal
Integrated Circuits”, Proceedings of the IEEE, December 2000.
Computer Aided Design of Analog and Mixed-Signal ICs, B. Antao, G. Gielen, R. Rutenbar,
editors, IEEE Press, to appear 2001.
IP Issues
{
{
{
Steve Ohr, “Analog IP Slow to Start Trading”, EETimes, Issue 1053, March 22 1999.
http://www.eet.com (Steve Ohr covers analog design/EDA for EETimes)
K.C. Murphy, “A Time for Analog Design”, Electronic News Online, August 2 1999.
http://www.electronicnews.com/enews/BackIssues/BackIssues.asp
http://www.vsia.com -- Virtual Socket Interface Alliance working on specs for interchange of
analog IP
© R.A. Rutenbar 2001
Select References
¢
Analog Synthesis
{
{
{
{
{
{
{
{
{
{
M.G.R. DeGrauwe et. al, “IDAC: An Interactive Design Tool for Analog CMOS Circuits”, IEEE
Journal of Solid-State Circuits, December 1987.
H.Y. Koh, C.H. Sequin, P.R. Gray, “OPASYN: A Compiler for CMOS Operational Amplifiers”,
IEEE Transactions on CAD, Feb. 1990.
R. Harjani, R.A. Rutenbar and L. Richard Carley, “OASYS: A Framework for Analog Circuit
Synthesis”, IEEE Transactions on CAD, Dec. 1989.
G. Gielen, Walscharts, W. Sansen, “Analog circuit design optimization based on symbolic
analysis and simulated annealing”, IEEE Journal of Solid-State Circuits, June 1990.
J. P. Harvey, M.I. Elmasry and B. Leung, “STAIC: An Interactive Framework for Synthesizing
CMOS and BiCMOS Analog Circuits”, IEEE Transactions on CAD, Nov. 1992.
P.C. Maulik, L.R. Carley and R.A. Rutenbar, “Integer Programming Based Topology Selection
of Cell-Level Analog Circuits”, IEEE Transactions on CAD, April 1995.
B. Antao and A. Brodersen, “ARCHGEN: Automated Synthesis of Analog Systems”, IEEE
Transactions on VLSI Systems, June 1995.
W. Kruiskamp and D. Leenaerts, “DARWIN: CMOS Opamp Synthesis by Means of a Genetic
Algorithm”, Proc. 32nd ACM/IEEE DAC, pp. 433-438, 1995.
G. Gielen, et al., “An analog module generator for mixed analog/digital ASIC design,” John Wiley
International Journal of Circuit Theory and Applications, Vol. 23, pp. 269-283, July-August
1995.
J. Crols, S. Donnay, M. Steyaert and G. Gielen, “A high-level design and optimization tool for
analog RF receiver front-ends,” Proc. IEEE/ACM ICCAD, pp. 550-553, November 1995.
© R.A. Rutenbar 2001
Select References
¢
Analog Synthesis, cont.
{
{
{
{
{
{
{
{
{
{
F. Medeiro, F. Fernandez, R. Dominguez-Castro, A. Rodriguez-Vazquez, “A Statistical
Optimization Based Approach for Automated Sizing of Analog Cells”, Proc. ACM/IEEE ICCAD,
1994.
E.S. Ochotta, R. A.Rutenbar and L.R. Carley, “Synthesis of High-Performance Analog Circuits in
ASTRX/OBLX”, IEEE Transactions on CAD, March 1996.
M. Hershenson, S. Boyd, T. Lee, “GPCAD: a Tool for CMOS Op-Amp Synthesis”, Proc.
ACM/IEEE ICCAD, pp. 296-303, 1998
M. Krasnicki, R. Phelps, R. Rutenbar, L. R. Carley, “MAELSTROM: Efficient Simulation-Based
Synthesis for Custom Analog Cells”, Proc ACM/IEEE DAC, June 1999.
R. Phelps, M. Krasnicki, R. Rutenbar, L. R. Carley, J. Hellums, “ANACONDA: Robust Synthesis of
Analog Circuits Via Stochastic Pattern Search”, Proc. IEEE CICC., May 1999.
R. Phelps, M. Krasnicki, R. Rutenbar, L. R. Carley, J. Hellums, “A Case Study of Synthesis for
Industrial-Scale Analog IP: Redesign of the Equalizer/Filter Frontend for an ADSL CODEC”, Proc.
ACM/IEEE DAC, June 2000.
R. Phelps, M. Krasnicki, R. Rutenbar, L. R. Carley, J. Hellums, ANACONDA: Simulation-Based
Synthesis of Analog Circuits Via Stochastic Pattern Search, IEEE Transactions on CAD, June 2000.
T. Mukherjee, L.R. Carley and R.A. Rutenbar, “Efficient Handling of Operating Rangeand
Manufacturing Line Variations in Analog Cell Synthesis," IEEE Transactions on CAD, Aug 2000.
G. Debyser, G. Gielen, “Efficient analog circuit synthesis with simultaneous yield and robustness
optimization”, Proc. IEEE/ACM ICCAD, pp. 308-311, November 1998.
C. De Ranter, et al., “CYCLONE: automated design and layout of RF LC-oscillators,” Proc.
ACM/IEEE DAC, June 2000.
© R.A. Rutenbar 2001
Select References
¢
Symbolic Analysis
{
{
{
{
{
{
{
{
{
G. Gielen, H. Walscharts, W. Sansen, "ISAAC: A Symbolic Simulator for Analog Integrated
Circuits, " IEEE Journal of Solid-State Circuits, Vol 24, No. 6, pp. 1587-1597, Dec 1989
F. Fernandez, A Rodriguez-Vazquez, J. Huertas, "Interactive AC Modeling and Characterization
of Analog Circuits Via Symbolic Analysis," Kluwer Journal on Analog Integrated Circuits and
Signal Processing, Vol. 1, pp. 183-208, November 1991.
J. Starzyk,, A. Konczykowska, "Flowgraph Analysis of Large Electronic Networks,“ IEEE
Transactions on Circuits and Systems, Vol. 33, No. 3, pp 302-315, March 1986.
B. Li, D. Gu, "SSCNAP: A Program for Symbolic Analysis of Switched Capacitor Circuits, "
IEEE Transactions on CAD, Vol. 11, No. 3, pp. 334-340, March 1992.
P. Wambacq, F. Fernandez, G. Gielen, W. Sansen, A. Rodriguez-Vazquez, "Efficient symbolic
generation of approximated small-signal characteristics of analog integrated circuits," IEEE
Journal of Solid-State Circuits, pp. 327-330, March 1995.
Q. Yu and C. Sechen, "A Unified Approach to the Approximate Symbolic Analysis of Large
Analog Integrated Circuits“, IEEE Trans. Circuits and Sys-I, vol.43, pp 656-669, August 1996
Q. Yu and C. Sechen, "Efficient Approximation of Symbolic Network Functions Using Matroid
Intersection Algorithms," IEEE Transactions on CAD, vol. 16, no. 10. pp. 1073-1081, Oct. 1997.
C. Shi, X. Tan, "Symbolic Analysis of Large Analog Circuits with Determinant Decision
Diagrams," Proc. ACM/IEEE ICCAD, pp. 366-373, 1997.
P. Wambacq, G. Gielen, P. Kinget, W. Sansen, “High-frequency distortion analysis of analog
integrated circuits,” IEEE Trans. Circuits and Sys-I, Vol. 46, No. 3, pp. 335-345, March 1999
© R.A. Rutenbar 2001
Select References
¢
Analog Layout
{
{
{
{
{
{
{
{
{
J. Rijmenants, J.B. Litsios, T.R. Schwarz, M.G.R. Degrauwe, "ILAC: An Automated Layout
Tools for Analog CMOS Circuits," IEEE Journal of Solid-State Circuits, Vol. 24, No. 4, pp. 417425, April 1989.
J.M. Cohn, D.J. Garrod, R.A. Rutenbar, L.R. Carley, "KOAN/ANAGRAM II: New Tools for
Device-Level Analog Placement and Routing," IEEE Journal of Solid-State Circuits, Vol. 26,
No. 3, March 1991.
U. Choudhury, A Sangiovanni-Vincentelli, "Automatic Generation of Parasitic Constraints for
Performance-Constrained Physical Design of Analog Circuits," IEEE Transactions on CAD, Vol.
12, No. 2, pp. 208-224, February 1993.
E. Malavasi, E. Felt, E. Charbon and A. Sangiovanni-Vincentelli, "Automation of IC Layout with
Analog Constraints, " IEEE Transactions on CAD, vol. 15, no. 8, August 1996.
K. Lampaert, G. Gielen, W. Sansen, "A Performance-Driven Placement Tool for Analog
Integrated Circuits," IEEE Journal of Solid-State Circuits, Vol. 30, No. 7, pp. 773-780, July 1995.
E. Malavasi, E. Felt, E. Charbon, A. Sangiovanni-Vincentelli, "Symbolic Compaction with
Analog Constraints, " John Wiley International Journal on Circuit Theory and Applications,
Vol.23, No.4, pp. 433-452, July/Aug. 1995
E. Malavasi, D. Pandini, "Optimum CMOS Stack Generation with Analog Constraints," IEEE
Transactions on CAD, Vol. 14, No. 1, pp. 107-12, Jan. 1995.
B. Basaran, R.A. Rutenbar, ““An O(n) Algorithm for Optimum CMOS Device Stacking with
Analog Constraints,” Proc. ACM/IEEE DAC, June 1996.
G. Van der Plas, J. Vandenbussche, G. Gielen, W. Sansen, “Mondriaan: a tool for automated
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© R.A. Rutenbar 2001
Select References
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Analog Layout
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{
Mitra, R.A. Rutenbar, L.R. Carley, D.J. Allstot, "Substrate-Aware Mixed-Signal Macrocell
Placement in WRIGHT," IEEE Journal of Solid-State Circuits, Vol. 30, No. 3, pp. 269-278,
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S. Mitra, S. Nag, R.A. Rutenbar, and L.R. Carley, "System-Level Routing of Mixed-Signal
ASICs in WREN," Proc. ACM/IEEE ICCAD, November 1992.
B.R. Stanisic, N.K. Verghese, R.A. Rutenbar, L.R. Carley, D. J. Allstot, "AddressingSubstrate
Coupling in Mixed-Mode ICUs: Simulation and Power Distribution Synthesis," IEEE Journal of
Solid-State Circuits, Vol. 29, No. 3, March 1994.
G. Gielen et al, “A Layout Aware Synthesis Methodology for RF Circuits,” to appear ACM/IEEE
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© R.A. Rutenbar 2001