Slide -1
MYTHS
Signal Integrity:
Problems and Solutions
Dr. Eric Bogatin
President
Bogatin Enterprises
www.BogatinEnterprises.com
(copies of the presentation are available for download on the web site)
Presented at Lockheed,
Sunnyvale, CA, March 1, 2000
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -2
MYTHS
Overview
• What is Signal Integrity?
• Why is it growing in importance?
• What can you do about it?
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -3
Signal Integrity and
Interconnect Design
MYTHS
How the electrical properties of the
interconnects screw up the beautiful,
pristine signals from the chips
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -4
The Confusing Mix of Signal
Integrity Problems
MYTHS
LINE DELAY
TERMINATIONS
PARASITICS
EMISSIONS
EMI/EMC
ATTENUATION
SUSCEPTABILITY
NON-MONOTONIC EDGES
GROUND BOUNCE
CAPACITANCE
LOADED LINES
POWER AND
GROUND DISTRIBUTION
SKIN DEPTH
LOSSY LINES
IR DROP
INDUCTANCE
CRITICAL NET
SIGNAL INTEGRITY
CROSSTALK
RINGING
RETURN CURRENT PATH
STUB LENGTHS
GAPS IN PLANES
TRANSMISSION LINES
IMPEDANCE DISCONTINUITIES
REFLECTIONS
DELTA I NOISE
UNDERSHOOT, OVERSHOOT
RC DELAY
 Eric Bogatin 2000
DISPERSION
www.bogatinenterprises.com
Slide -5
MYTHS
The Four High Speed Problems
1. Signal quality of one net: reflections and
distortions from impedance discontinuities
in the signal or return path
2. Cross talk between multiple nets: with ideal
return paths, and without (SSO)
3. Rail collapse in the power and ground
distribution network
4. EMI from a component or the system
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -6
MYTHS
Signal Quality on One Net:
Distorted by the Interconnect
Initial output signal
Signal distorted
by interconnect
Simulated with Hyperlynx
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -7
Cross Talk Between Two Adjacent
Conductors- Ideal Return Path
MYTHS
Near end
Active line
far end
50Ω
Ω
Near end
The far end
noise is ~ 10x
larger than the
near end noise
Far end
rise time ~ 100 psec,
TD ~ 1 nsec
(HP 83480 High speed scope and TDR)
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -8
Conceptual Origin of SSO Noise
MYTHS
On Chip
Icharge
Idischarge
Switching lines
Quiet data line
V SS
V CC
L Bonding
L Bonding
GND
common
lead
inductance
Power
15836
© 1991 Integrated Circuit Engineering Corporation
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -9
MYTHS
Simple Example of Rail
Collapse
To
regulator
Cdecoupling
100 nF
Current On
Current Off
Rail collapse:
∆V ~ - dI/dt
Vdd nominal
Vdd rail collapse
Source: National Semiconductor
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -10
MYTHS
Radiated Emissions and
Power and Ground Routing
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -11
Two Classes of
High Speed Problems
MYTHS
• Timing: setup, hold, propagation delay, skew
ü Scales with decreasing clock period
• Electrical Noise: signal integrity and EMI
ü Scales with decreasing rise time
dI
dt
dV
dt
f, f2
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -12
“…it’s the rise time, …”
MYTHS
On Chip
Icharge
Idischarge
Switching data lines
Quiet data line
V SS
V CC
L Bonding
L Bonding
GND
common
lead
inductance
Power
NxL
15836
© 1991 Integrated Circuit Engineering Corporation
SSO noise ~
τ
N = number of switching leads per ground leads
L = lead inductance or lead length
τ = rise time
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -13
Shorter Delays Mean Shorter Clock
Periods, Higher Clock Frequencies
MYTHS
Digital Clock Frequencies are Increasing: doubling every 2 years!
Clock frequency of Intel Processors
1000
100
10
1
1970
1975
1980
1985
1990
1995
2000
Introduction Year
High speed usually refers to increasing clock frequency
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -14
Increase in Clock Frequencies
MYTHS
3500
3000
Clock Frequency (MHz)
Clock Frequency (MHz)
10000
on-chip
2500
2000
1500
on-board
1000
500
0
1996
1998
2000
2002
2004
2006
2008
2010
2012
2014
Year
Source: SIA Roadmap
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -15
MYTHS
Rise Times Are Loosely
Related to Clock Frequency
1 nsec rise time
10 nsec period
Approximate Rise Time (nsec)
100
10
1
0.1
0.01
1
10
100
1,000
10,000
Clock Frequency (MHz)
τ~
1 1
10 Fclock
What is the consequence of higher speed?
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -16
MYTHS
The Driving Force Fueling the
Electronics Revolution:
Gate Length Feature Size Reduction
50% reduction every 4 years
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -17
MYTHS
Transistors Switch Faster As
Channel Length Shrinks
Shorter channel length means:
->> shorter delay
->> shorter rise time
out
in
What can happen to the clock period and clock frequency?
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -18
MYTHS
•
•
•
•
Situation Analysis
Clock frequency will get faster
Rise times for every chip will get shorter
SI problems will be more significant
Design cycle times will be decreasing
Conclusion:
Getting new products to market on time will be harder.
Solution:
A new design methodology is needed.
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -19
The Old Design Strategy
MYTHS
Guess a design
Hope it works
Build it
Test it
Try to Fix it
Ship it
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -20
Details of the Three Design
Approaches
MYTHS
The earlier in the design cycle problems
can be identified and solved, the lower the
development cost and the faster time to
market.
Correct by design
Design by virtual iteration
Design by correcting
Source: G. Doyle, Mentor Graphics
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -21
Two Critical Processes for
Virtual Design and Test
MYTHS
Modeling:
Translating the physical world into an
equivalent electrical circuit model (Schematic)
Lpower
Lpower
Lpin
Lconn
PCB #1
Zo,
Lconn
Backplane
Zo,
D
Lpin
PCB #2
τ
τ
Gate1
τ
D
Zo,
D
Clk1
Gate2
Cconn
Cconn
Cpin
Cpin
Lgnd
Lgnd
Clk1
Simulation: Predicting voltage/current waveforms based on
the circuit behavior
V3 10
8
R4
680
V(3)
Q10
4
VOUT
QN3906
R1 50
2
L1 1U
1
V(10)
3
Q2
VLOAD
V(7) VEMITTER
QN3904
R3 10
V1
X1 WIRE
C1
30P
7
6
10
PULSE
R2
C2
5K
7P
V2 10
9
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -22
MYTHS
Where do Models Come From?
0.5
0.0
M24a:i24a1
M16:i161
M09:i091
21
M01:i011
26
11
16
ü Rules of thumb
ü Analytic approximation
ü Parasitic extraction numerical tools: field solvers
1.0
1
• Calculations: (03, 06)
1.5
6
Inductance (nH)
2.0
• Measurements: (06)
ü Impedance analyzer (LCZ)
ü Network Analyzer (NA)
ü Time Domain Reflectometer (TDR)
Courtesy of TDA Systems
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -23
MYTHS
Two Tools for Simulating
Circuits
• SPICE: Simulation Program with
Integrated Circuit Emphasis
ü
ü
ü
ü
ü
ü
PSPICE from OrCAD/Cadence
IsSPICE from Intusoft
Advanced Design System (ADS) from HP Eesof
Maxwell SPICE from Ansoft
Micro-CAP from Spectrum
HSPICE from Avant!
• IBIS based simulators: Input/output
Buffer Interface Specification
ü
ü
ü
ü
ü
Hyperlynx (Pads)
Veribest/Mentor Graphics
Zukan Redac
Viewlogic
Interconnectix (Mentor Graphics)
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -24
MYTHS
Design Principles for Good SI
Noise Categories
Design Principles
Signal Quality
Signals should see the same
impedance through all interconnects
Cross talk
Keep spacing of traces greater than
a minimum value, minimize mutual
inductance of non ideal returns
Rail Collapse
Minimize the impedance of the
power and ground path
EMI
Minimize bandwidth, minimize
ground impedance and shield
When are you done? How much reduction is enough?
 Eric Bogatin 2000
www.bogatinenterprises.com
Slide -25
MYTHS
…just follow
these RULES
Cost factors:
money
Performance
(meet specs)
risk
time

www.bogatinenterprises.com
Eric Bogatin 2000
Slide -26
MYTHS
Design Tradeoffs Are Negotiated
With a Budget
• Total voltage swing is 3.3v
• Within 500 mV, all the noise sources must be accounted for:
An example:
Noise Source
Allocated Budget
Ringing/reflections
Discontinuities
Cross talk
SSO noise
Rail collapse
Total*
Margin
*
100mV
40mV
90mV
120mV
100mV
450mV
~50mV
Rail collapse
22%
Ringing
22%
Discontinuities
9%
SSO noise
27%
Cross talk
20%
*dynamic effects important
• In hi speed systems, keeping within the noise budget is HARD!
• The more accurately you can predict performance, the less margin needed and the higher the
performance

Eric Bogatin 2000
www.bogatinenterprises.com
Slide -27
MYTHS
The Most Important General
Design Principles
1. Slow down edges
2. Minimize the length of all interconnects
3. Use low dielectric constant materials for signal layers
4. Use controlled impedance lines and terminate
5. Minimize loop mutual inductances between signal lines
6. Use continuous, closely spaced, adjacent power and
ground planes

Eric Bogatin 2000
www.bogatinenterprises.com
Slide -28
MYTHS
#1 solution:
slow down the edges
50 Ohm line
Top view
2 short stubs (capacitive discontinuity)
150 mils spacing
Longer the
rise time,
smaller the
impact, or,
the shorter the
discontinuity,
the smaller the
impact
50 psec

Eric Bogatin 2000
www.bogatinenterprises.com
Slide -29
MYTHS
Minimize Bandwidth
Spread Spectrum Clock Generator (SSCG)
Avoid resonance and clock harmonics
At 2 GHz
At 2.3 GHz
Figure 28. Data from Ansoft HFSS showing the field distribution on and
off resonance for a 208 lead QFP, excited at one lead.
AVX Z chip: integrated RC, with low stray C

Eric Bogatin 2000
www.bogatinenterprises.com
Slide -30
#2 solution:
shorter is better
MYTHS
• Reflections:
• Cross talk
• Rail collapse
• EMI
Near end
Mutual C, mutual L, scale with length
Series L scales with length
Radiated emission scales with length of current path

Eric Bogatin 2000
www.bogatinenterprises.com
Slide -31
MYTHS
Terminations will Minimize
Reflected Noise from the Ends
Series R terminate
RC terminate at far end, changing C
Source: Analog Devices

www.bogatinenterprises.com
Eric Bogatin 2000
Slide -32
MYTHS
Avoid Stubs and Branches
branches
daisy chain
(for 0.5 nsec edges, stub length < 0.5 inches)

Eric Bogatin 2000
www.bogatinenterprises.com
Slide -33
MYTHS
Thin Power and Ground Layers
Reduce Switching Noise
Conventional, 10
mil thick spacing, 2
plane pairs
Small daughtercard
“A Low-Cost Technique for Reducing the
Simultaneous Switching Noise in Sub-Board
Packaging Configurations”, Koike and Kaizu, IEEE
Trans CPMT part B vol 21(4) Nov 1998 p. 428

Eric Bogatin 2000
Thin layer, 2 mil
thick, 4 plane pairs
www.bogatinenterprises.com
Slide -34
MYTHS
Reduced Switching Noise
Reduces SSO noise
Improves effectiveness of the
decoupling caps

Eric Bogatin 2000
www.bogatinenterprises.com
Slide -35
MYTHS
Reducing Emissions:
Low Impedance Power and Ground Layers by
Thinner Dielectric

www.bogatinenterprises.com
Eric Bogatin 2000
Slide -36
MYTHS
Avoid Splits in Return Path
with split
no split
Archambeault, Bruce; “Proper design of intentional splits
in the ground reference plane of PC Boards to minimize
emissions from I/O wires and cables”, Proc. 1998 IEEE
conf on EMC, p. 768
Avoid all splits in the return path!

Eric Bogatin 2000
www.bogatinenterprises.com
Slide -37
Unintentional Splits
MYTHS
Figure 9. How a via field for a connector can create a gap. By decreasing
the clearance hole diameter in the ground plane, a continuous return
path can be provided.
Decreasing
size of
clearance
holes
reduced
radiated
emissions
Figure 10. Data from [10]. Left is the emission from a board with gaps
under via fields- failing the Class A test. Right: the exact same board, but
with smaller clearance holes and no gaps under traces- passing Class A
test.

Eric Bogatin 2000
www.bogatinenterprises.com
Slide -38
MYTHS
The Design Strategy
1. Use design guidelines as design guidelines to shoot for
2. Estimate the magnitude of each effect and the benefit from a
design or technology solution
3. Verify the models and simulations based on measurements of test
vehicles and previous designs
4. Evaluate cost/performance trade offs
5. Keep optimizing until the noise budget is met
6. The earlier in the design cycle correct design decisions can be
made, the shorter time to market and lower the development cost

Eric Bogatin 2000
www.bogatinenterprises.com
Slide -39
MYTHS
SI Problems Apply Across
ALL Interconnects
BOLData Corp
Courtesy of ICE

Eric Bogatin 2000
www.bogatinenterprises.com
Slide -40
MYTHS
“There are two kinds of design
engineers, those that have signal
integrity problems, and those that will”
Good Luck!

Eric Bogatin 2000
www.bogatinenterprises.com