DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
FEATURES
GENERAL DESCRIPTION
The IDTF1240 (0.5 dB steps) is an IF VGA for Diversity
Basestation receivers. The device offers significantly
better Noise and Distortion performance than currently
available devices. It is packaged in a compact 5x5
Thin QFN with 200 ohm differential input and output
impedances for ease of integration into the receiver
lineup.
COMPETITIVE ADVANTAGE
The IDTF1240 IF VGA improves system SNR, especially
at lower gain settings. Via IDT’s proprietary FlatNoiseTM
technology both IP3O & NF are kept virtually flat
while gain is backed off, enhancing SNR significantly
under high level interferer conditions, and greatly
benefiting 2G/3G/4G Multi-Carrier IF sampling receivers.
The fast-settling, parallel mode gain step of 0.50 dB
coupled with the excellent differential non-linearity allow
for SNR to be maximized further by targeting the
minimum necessary gain in small, accurate increments.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Ideal for systems with high SNR requirements
20 dB typical Maximum Gain
31.5 dB gain control range
6 bit control
0.50 dB Gain Steps
Excellent Noise Figure = 4.0 dB
5mm x 5mm 32 pin package
200 Ω Differential Matched Input
200 Ω Differential Matched Output
No termination resistors required
NF degrades just 1.3 dB @ 10 dB below
Ma x G a i n
10 MHz – 500 MHz frequency range
Ultra-Linear: IP3O +47 dBm typical
Excellent 2nd Harmonic Rejection
Selectable Parallel or Serial Control
External current setting resistors
Very fast settling < 15 nsec
Individual Power Down Modes
Extremely Low Power: 80 mA / Chan
The matched output does not require a terminating
resistor, thus the gain and distortion performance are
preserved when driving Bandpass Anti-Alias filters.
DEVICE BLOCK DIAGRAM
See the ‘Applications Information’ section starting on
Page 19 for more details of the benefits of the F1240 in
IF sampling receivers.
Part#
F1240
F1241
Range /
Step
20 to -11.5
0.5
20 to -11
1.0
AMP
out A
ATTN
In A
PART# MATRIX
IP3O
47
IF freq
range
NF
10 - 500
4
Pinout
Compatibility
Gain
Control
NSM
SPI
47
10 - 500
4
VDD
ADI
VMODE
12
VCC
Decode
Logic
STBYA
Bias
Control
STBYB
2
ISET
ORDERING INFORMATION
Omit IDT
prefix
ATTN
In B
0.8 mm height Tape &
Reel
package
AMP
out B
IDTF1240NBGI8
RF product Line
IDT FlatNoiseTM IF VGA
Green
Industrial
Temp range
1
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
ABSOLUTE MAXIMUM RATINGS
VCC to GND
GA[5-0], GB[5-0], DATA, CSb, CLK, VMODE, STBYA, STBYB
OUT_A-, OUT_A+, OUT_B-, OUT_B+
IN_A-, IN_A+, IN_B-, IN_B+
ISET_A, ISET_B to GND
RF Input Power (IN_A-, IN_A+, IN_B-, IN_B+) @ GMAX
Continuous Power Dissipation
θJA (Junction – Ambient)
θJC (Junction – Case) The Case is defined as the exposed paddle
Operating Temperature Range (Case Temperature)
Maximum Junction Temperature
Storage Temperature Range
Lead Temperature (soldering, 10s) .
-0.3V to +5.5V
-0.3V to (VCC_ + 0.25V)
-0.3V to (VCC_ + 0.25V)
-0.3V to +2.2V
-0.3V to +2.2V
+15 dBm
1.5W
+40°C/W
+3°C/W
TC = -40°C to +100°C
150°C
-65°C to +150°C
+260°C
Stresses above those listed above may cause permanent damage to the device. Functional operation of the
device at these or any other conditions above those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
ESD Caution
This product features proprietary protection circuitry. However, it may be
damaged if subjected to high energy ESD. Please use proper ESD precautions
when handling to avoid damage or loss of performance.
TRUTH TABLE
Gain Set
Target
20.0
19.5
19.0
18.5
18.0
17.5
17.0
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
IDT FlatNoiseTM IF VGA
Gain
CodeWord
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
Code
Name
G20
G19.5
G19
G18.5
G18
G17.5
G17
G16.5
G16
G15.5
G15
G14.5
G14
G13.5
G13
G12.5
G12
G11.5
G11
G10.5
G10
Gain Set
Target
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
Gain
CodeWord
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
2
Code
Name
G9.5
G9
G8.5
G8
G7.5
G7
G6.5
G6
G5.5
G5
G4.5
G4
G3.5
G3
G2.5
G2
G1.5
G1
G0.5
G0
G-0.5
Gain Set
Target
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
-5.5
-6.0
-6.5
-7.0
-7.5
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-11.0
-11.5
Gain
CodeWord
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
Code
Name
G-1
G-1.5
G-2
G-2.5
G-3
G-3.5
G-4
G-4.5
G-5
G-5.5
G-6
G-6.5
G-7
G-7.5
G-8
G-8.5
G-9
G-9.5
G-10
G-10.5
G-11
G-11.5
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
IDTF1240 SPECIFICATION
Specified values apply at VCC = +5.0V, fRF = 200MHz, TC= +25°C,, VMODE > VIH (parallel mode), STBYA, STBYB = 3.3V or NC, R34 & R36 =
3.83K unless otherwise noted. EVkit transformer losses are de-embedded
Parameter
Comment
Symbol
min
Logic Input High
VIH
2.0
Logic Input Low
VIL
0
0.8
V
IIH, IIL
-2
+2
µA
VIH = 3.45 V, VIL = 0V
IIH, IIL
-10
+1
µA
Temperature
Operating Case Temp Range
TCASE
Voltage
All Supplies Operating Range
VCC
GA[5-0], GB[5-0]
Logic Current
Logic Current
VIH = 3.45 V, VIL = 0V
VMODE, STBY_A, STBY_B
3
typ
max
V
degC
-40 to 100
4.75
units
5.00
5.25
1
V
Supply Current
Total, All VCC
ISUPP
160
176
mA
Standby Current
Total, All VCC
STBY_A, STBY_B < VIL
ISTBY
2.3
5
mA
fRF
50 to 400
MHz
fRF
5 to 560
MHz
Frequency @ 1dB Gain
reduction vs. 100 MHz Gain
BW
400
MHz
Differential ( > 10 dB RL)
RIN
200
Ω
ROUT
200
Ω
20
dB
Low Distortion Range
Frequency Range
IP3O > 40 dBm, Pout +3 dBm/Tone
Gain Set = G20
Operating Range
Frequency Range
1dB Gain Rolloff
Input Resistance
4
4
Output Resistance
Gain > 17 dB
With L1,L2,L3,L4 = 1500 nH
Differential ( > 15 dB RL)
Maximum Gain
G20 or
GMAX
Minimum Gain
G-11.5 or
GMIN
-11.5
18
dB
-9
Minimum Gain Step
Parallel or Serial Mode
LSB
0.50
dB
Phase Error
Maximum phase change
between GMAX and any state
down to G-4
IPE
2.7
deg
Differential Gain Error
Between any two adjacent 0.5
dB steps
DNL
0.08
dB
Integral Gain Error
Error vs. line (G20 Ref)
INL
0.19
Noise Figure
At G20
Noise Figure
At Gain Set = 10 dB (G10)
Output IP3 –
Narrowband offset
Output IP3 –
Wideband offset
IDT FlatNoiseTM IF VGA
NF
4.0
4.5
dB
NFBACK
5.3
5.8
dB
Set GMAX,
Pout = +3 dBm per tone
800 KHz Tone Separation
IP3O1
Set GMAX,
20 MHz Tone Separation
Pout = +3 dBm per tone
IP3O2
3
dB
2
42
46.5
dBm
45
dBm
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
IDTF1240 SPECIFICATION (CONT.)
Parameter
Comment
Output IP3 –
Mid Gain
nd
2 Harmonic
Output IP2
1 dB Compression
Symbol
min
typ
IP3O3
42
44.5
dBm
H2
-90
dBc
IP2H
76
dBm
Set Gain = 10 dB (G10 )
Pout = +3 dBm per tone
800 KHz Tone Separation
Set G10, FRF = 200 MHz
Pout = +3 dBm
Set G10, FRF = 190 MHz, 210 MHz
Pout = +3 dBm per tone
Measure @ G20
max
units
P1dBO
16
19.7
dBm
ISOC
60
69
dBc
T1dB
12
nsec
ctrl
Both
OUT_B vs. OUT_A w/ IN_A input
Channel Isolation
Settling Time
200 MHz
Measured @ G20 for both
channels
In Parallel Mode or In Serial Mode
from CSb high
Any two Adjacent 1dB Steps
+/-0.10 dB Pout settling
Control Scheme
SPITM (VMODE = VIL or GND)
Parallel (VMODE = NC or VIH)
Serial Clock Speed
SPI 3 wire bus
FCLOCK
20
Parallel to Serial
Setup Time
Minimum Interval after VMODE is
pulled low to initiate serial
programming via a CSb
assertion
TMODE
100
Data to Clock Setup
Minimum Interval between
valid data bit and Clock Rising
Edge
TS
5
ns
Data Hold Time
Minimum Interval after Clock
Rising Edge that Data Bit must
be held
TH
5
ns
Clock to CSb Setup
CSb must be pulled low this
minimum interval BEFORE the
next rising clock edge
TEN
8
ns
Clock Pulse Width
Minimum clock interval from
rising to falling edge
TW
15
50
MHz
ns
ns
SPECIFICATION NOTES:
1 – Items in min/max columns in bold italics are Guaranteed by Test
2 – All other Items in min/max columns are Guaranteed by Design Centering
3 - VMODE, STBY_A, and STBY_B all have internal pullup resistors such that they float to > VIH
4 - Measured with 4:1 Transformers (see applications Circuit)
IDT FlatNoiseTM IF VGA
4
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
SERIAL MODE
Serial mode is selected by grounding VMODE (pin4) or pulling it to a voltage < VIL. In serial mode the IDTF1240
Ch_A and Ch_B gains can be programmed independently via the serial port by asserting Chip Select (CSb).
SERIAL MODE TIMING DIAGRAM HIGH LEVEL:
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLK
Data Word
Latched into
Register
CS
Address Word A7 – A0
DATA
0
RSV
0
0
0
0
0
RSV RSV RSV RSV
Data Word D7 – D0
0
RSV RSV
1 = On
16 dB
0 = Off
0=A
1=B
EN
CH
G5
MSB
1 = 16 dB
ATTN
8 dB
4 dB
2 dB
G4
G3
G2
1 dB
G1
0.5 dB
G0
0
RSV
LSB
SERIAL MODE TIMING DIAGRAM ZOOM:
Ts
TH
DATA
A7
A6
CLK
CS
TEN
IDT FlatNoiseTM IF VGA
5
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
SERIAL MODE DEFAULT VALUES
Serial Register Default Values on Power Up. These apply to a hard reset when first applying VCC.
ChanA D7 – D0 Register Defaults
Addr A7 – A0 Register Defaults
0
0
0
0
0
0
0
0
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
0
D1
0
D0
ChanB D7 – D0 Register Defaults
A7
A6
A5
A4
A3
A2
A1
Both Channels On with 0 dB
Attenuation (~ 20 dB Gain)
A0
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
0
D1
0
D0
SERIAL MODE ENABLE FUNCTIONS
Note that the STBY_A and STBY_B pins can be used in Serial mode for fast disable. These pins float high and can
be left disconnected for serial operation. Alternately one can connect these pins to allow much faster enabling and
disabling of the two VGA channels. Note the following:
•
•
•
•
When a VGA channel is disabled, the serial register will hold* the last enabled gain state.
To enable a channel Serial D7 must be 1 AND the STBY pin must be high
To disable a channel Serial D7 can be 0 OR the STBY pin can be low
Through the Serial interface, only the channel addressed by A0 will be enabled or disabled via
D7. For instance, to disable both Channel A and Channel B a serial programming cycle must be
nd
initiated and completed with A0 = 0 and D7 = 0 and then a 2 serial programming cycle must be
executed with A0 = 1 and D7 = 0.
*Note – This does not apply when disabling through the Serial Bus. In this case, the gain value [D6 – D1]
written during the subsequent Enable write replaces the Gain Setting. For the Serial Disable write, the
recommended Data Word is [01111110]
IDT FlatNoiseTM IF VGA
6
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
TYPICAL OPERATING CURVES (GMAX, 5.00V, TCASE = 25C, 200 MHz, TC4 de-embedded unless otherwise noted)
All temperatures are TCASE unless noted as TAMB or TA = Ambient
Gain vs. Frequency [Gain Set = 20 dB]
Extended Applications Range [TAMB = 25C]
25
Tcase = +25C
Tcase = +100C
24
22
20
15
Gain (dB)
Gain (dB)
EVKit Alt Configuration
Replace L1,L2,L3,L4 with 1500nH
Usable BW = 10 MHz to 470 MHz
10
Gain 390nH
Gain 1500nH
Delay 390nH
Delay 1500nH
28
20
24
18
20
16
16
EVKit STD Configuration
L1,L2,L3,L4 = 390nH
Usable BW = 23 MHz to 535 MHz
14
5
0
1.00E+07
1.00E+08
12
12
8
10
4
8
1.00E+06
1.00E+09
32
1.00E+07
Frequency (Hz)
1.00E+08
Delay (nsec)
Tcase = -40C
0
1.00E+09
Frequency (Hz)
S21 vs. Frequency [TCASE = 25C]
S11 vs. Frequency [TCASE = 25C]
25
0
20
-5
-10
10
Gain Set = 20
5
ΓIN (dB)
Gain (dB)
15
Gain Set = 12
Gain Set = -4
0
Gain Set = -11.5
-15
-20
Gain Set = 20
-5
Gain Set = 12
-10
-15
1.00E+07
Gain Set = -4
-25
Gain Set = -11.5
1.00E+08
-30
1.00E+07
1.00E+09
1.00E+08
Frequency (Hz)
Frequency (Hz)
S12 vs. Frequency [TCASE = 25C]
S22 vs. Frequency [TCASE = 25C]
0
Gain Set = 20
1.00E+09
0
Gain Set = 12
-5
Gain Set = -4
-5
Gain Set = -11.5
-15
-10
-20
ΓOUT (dB)
Reverse Isolation (dB)
-10
-25
-30
-35
-15
-20
Gain Set = 20
Gain Set = 12
-40
Gain Set = -4
-25
-45
-50
1.00E+07
1.00E+08
-30
1.00E+07
1.00E+09
Frequency (Hz)
IDT FlatNoiseTM IF VGA
Gain Set = -11.5
1.00E+08
1.00E+09
Frequency (Hz)
7
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
TOCS CONTINUED (-2-)
S22 vs. Gain Setting [200 MHz]
S11 vs. Gain Setting [200 MHz]
0
0
-40 degC - 5.00 V
-40 degC - 5.00 V
25 degC - 5.00 V
-5
25 degC - 5.00 V
-5
100 degC - 5.00 V
100 degC - 5.00 V
-10
-15
S22 (dB)
S11 (dB)
-10
-15
-20
-25
-20
-30
-25
-35
-40
-30
20
16
12
8
4
0
-4
20
-8
16
12
8
4
0
-4
Phase Error vs. Gain Setting [200 MHz]
S12 vs. Gain Setting [200 MHz]
40
0
-40 degC - 5.00 V
-40 degC - 5.00 V
35
Normalized Phase Change (deg)
25 degC - 5.00 V
-5
100 degC - 5.00 V
Reverse Isolation (dB)
-8
Gain Setting (dB)
Gain Setting (dB)
-10
-15
-20
-25
-30
-35
25 degC - 5.00 V
100 degC - 5.00 V
30
25
20
15
10
5
0
-5
-10
-40
20
16
12
8
4
0
-4
20
-8
16
12
8
4
0
-4
-8
Gain Setting (dB)
Gain Setting (dB)
EVKit Measurement Corrections [TC4-1W, TAMB]
S21 vs. Gain Setting [200 MHz]
22
4.0
-40 degC - 5.00 V
18
25 degC - 5.00 V
100 degC - 5.00 V
Measurement Correction (dB)
Power Gain (dB)
14
10
6
2
-2
-6
3.5
Gain Correction
3.0
NF Correction
2.5
IP3O Correction
Adjust the measured Gain by
this much to account for both
Transformer losses
2.0
1.5
1.0
0.5
0.0
Adjust the measured NF by
this much to account for the
Input Transformer loss
-0.5
Adjust the measured IP3O by
this much to account for the
Output Transformer loss
-1.0
-10
-1.5
-14
20
16
12
8
4
0
-4
-2.0
1.00E+07
-8
IDT FlatNoiseTM IF VGA
1.00E+08
1.00E+09
Freq (Hz)
Gain Setting (dB)
8
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
TOCS CONTINUED (-3-)
Channel Isolation vs. Frequency [TAMB = 25C]
Channel Matching [200 MHz, TCASE = 25C]
0.8
-30
0.6
-40
0.4
Channel Isolation (dBc)
Channel Matching Error (deg, dB)
ChA and ChB both set to 20 dB Gain
0.2
0.0
-0.2
-0.4
∆Phase (deg)
∆Gain (dB)
-0.6
16
12
8
4
0
-4
-8
ChB to ChA
-60
-70
-80
-90
-100
1.00E+07
-0.8
20
ChA to ChB
-50
-12
1.00E+08
1.00E+09
Frequency (Hz)
Gain Setting (dB)
DNL vs. TCASE [200 MHz]
DNL vs. VCC [200 MHz]
0.8
0.8
-40 degC - 5.00 V
25 degC - 5.25 V
25 degC - 5.00 V
0.6
25 degC - 5.00 V
0.6
100 degC - 5.00 V
25 degC - 4.75 V
0.4
Gain Step Error (dB)
Gain Step Errror (dB)
0.4
0.2
0.0
-0.2
-0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.6
-0.8
-0.8
20
16
12
8
4
0
-4
20
-8
16
12
8
4
0
-8
INL vs. TCASE [200 MHz]
INL vs. VCC [200 MHz]
1.0
1.0
-40 degC - 5.00 V
25 degC - 5.25 V
0.8
25 degC - 5.00 V
25 degC - 4.75 V
0.6
Absolute Gain Error (dB)
Absolute Gain Error (dB)
-4
Gain Setting (dB)
Gain Setting (dB)
0.4
0.2
0.0
-0.2
-0.4
-0.6
0.8
25 degC - 5.00 V
0.6
100 degC - 5.00 V
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-0.8
-1.0
-1.0
20
16
12
8
4
0
-4
20
-8
IDT FlatNoiseTM IF VGA
16
12
8
4
0
-4
-8
Gain Setting (dB)
Gain Setting (dB)
9
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
TOCS CONTINUED (-4-)
Noise Figure vs. Gain Setting [TCASE = 25C]
Noise Figure vs. Frequency [Gain Set = 20 dB]
36
10
9
32
25 degC - 5.00 V
25 degC - 5.00 V - 200 MHz
100 degC - 5.00 V
8
25 degC - 5.00 V - 305 MHz
28
Noise Figure (dB)
Noise Figure (dB)
25 degC - 5.00 V - 100 MHz
-40 degC - 5.00 V
7
6
5
4
3
24
20
16
12
8
2
4
1
0
0
50
100
150
200
250
300
350
20
400
16
12
8
4
0
36
36
-40 degC - 5.00 V - 200 MHz
25 degC - 5.25 V - 200 MHz
32
32
25 degC - 5.00 V - 200 MHz
25 degC - 4.75 V - 200 MHz
25 degC - 5.00 V - 200 MHz
100 degC - 5.00 V - 200 MHz
28
Noise Figure (dB)
28
Noise Figure (dB)
-8
Noise Figure vs. TCASE [200 MHz]
Noise Figure vs. VCC [200 MHz]
24
20
16
12
24
20
16
12
8
8
4
4
0
0
20
16
12
8
4
0
-4
20
-8
16
8
4
0
-4
-8
2nd Harmonic vs. Frequency [TCASE = 25C]
Output IP3 vs. Frequency [TCASE = 25C]
-20
H2 Rejection [Pout = +3 dBm] (dBc)
55
50
45
40
35
30
20.0 dB Gain
16.0 dB Gain
10.0 dB Gain
-3.5 dB Gain
25
20
1.0E+08
12
Gain Setting (dB)
Gain Setting (dB)
Output IP3 (dBm)
-4
Gain Setting (dB)
Frequency (MHz)
1.5E+08
2.0E+08
2.5E+08
3.0E+08
3.5E+08
-40
20.0 dB Gain
16.0 dB Gain
10.0 dB Gain
-3.5 dB Gain
-50
-60
-70
-80
-90
-100
1.0E+08
4.0E+08
1.5E+08
2.0E+08
2.5E+08
3.0E+08
3.5E+08
4.0E+08
Frequency (Hz)
Frequency (Hz)
IDT FlatNoiseTM IF VGA
-30
10
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
TOCS CONTINUED (-5-)
Output IP3 vs. VCC [200 MHz]
55
55
50
50
45
45
Output IP3 (dBm)
Output IP3 (dBm)
Output IP3 vs. TCASE [200 MHz]
40
-40 degC - 2.0E+08 Hz - 5.00 V
35
25 degC - 2.0E+08 Hz - 5.00 V
100 degC - 2.0E+08 Hz - 5.00 V
30
40
25 degC - 5.25 V
35
25 degC - 5.00 V
25 degC - 4.75 V
30
25
25
20
20
20
16
12
8
4
0
20
-4
16
4
0
-4
-20
H2 Rejection [POUT = +3 dBm] (dBc)
55
50
Output IP3 (dBm)
8
2nd Harmonic vs. TCASE [200 MHz]
Output IP3 vs. Pout [TAMB = 25C, Gain Set = 20 dB]
45
40
35
200 MHz
30
150 MHz
25
20
-30
-40 degC - 5.00 V
-40
25 degC - 5.00 V
100 degC - 5.00 V
-50
-60
-70
-80
-90
-100
-4
-3
-2
-1
0
1
2
3
4
5
6
20
16
Output Power (dBm/Tone)
12
8
4
0
-4
0
-4
Gain Setting (dB)
2nd Harmonic vs. TCASE [250 MHz]
Output IP2 vs. TCASE [200 MHz]
-20
95
90
-30
-40 degC - 5.00 V
-40
85
25 degC - 5.00 V
Output IP2 (dBm)
H2 Rejection [POUT = +3 dBm] (dBc)
12
Gain Setting (dB)
Gain Setting (dB)
100 degC - 5.00 V
-50
-60
-70
80
75
70
65
-40 degC - 5.00 V
-80
25 degC - 5.00 V
60
100 degC - 5.00 V
-90
55
-100
50
20
16
12
8
4
0
-4
20
Gain Setting (dB)
IDT FlatNoiseTM IF VGA
16
12
8
4
Gain Setting (dB)
11
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
TOCS CONTINUED (-6-)
Gain Compression vs. Frequency [TAMB = 25C]
Gain Compression [200 MHz, TAMB = 25C]
21
21
P1dBO = 19.8 dBm
150 MHz
P1dBO = 19.7 dBm
20
Output Power (dBm)
Output Power (dBm)
20
19
200 MHz
18
250 MHz
17
19
5.00 V
18
5.25 V
4.75 V
17
16
16
-4
-3
-2
-1
0
1
2
-4
-3
-2
-1
Input Power (dBm)
0
1
2
Input Power (dBm)
ICC vs. TCASE
Output IP3 vs. ICC [TAMB = 25C]
0.162
55
Icc = 80 mA / Chan
Icc = 70 mA / Chan
R34, R36 = 3.83K
R34, R36 = 4.3K
50
0.160
VCC = 5.00 V
45
Output IP3 (dBm)
Total Icc (A)
VCC = 5.25 V
0.158
0.156
40
35
Icc = 60 mA / Chan
R34, R36 = 5.1K
30
VCC = 4.75 V
0.154
25
0.152
25
20
1.00E+08
85
2.00E+08
3.00E+08
Case Temperature (Degrees C)
Settling Time (1dB Step, 200 MHz, MSB+)
Settling Time (1dB Step, 200 MHz, MSB-)
0.30
15
Gain(5dB) to Gain(4dB)
0.25
12
9
0.05
0.00
6
-0.05
-0.10
3
-0.15
-0.20
0
-3
5
10
15
20
25
30
35
40
45
50
0.00
6
-0.05
-0.10
3
-0.15
0
Settles in 13.5 nsec after CSb cycle w/serial
control. Parallel Control is 1 nsec faster
-0.30
55
-3
-5
Time (nsec)
IDT FlatNoiseTM IF VGA
9
0.05
-0.25
-0.30
0
0.10
-0.20
Settles in 11.3 nsec after CSb cycle w/serial
control. Parallel Control is 1 nsec faster
-5
12
0.15
Output (Volts)
0.10
MSB Transition:
[100000] to [011110]
CSb
0.20
Chip Select Tirgger (Volts)
0.15
-0.25
15
Gain(4dB) to Gain(5dB)
0.25
0.20
Output (Volts)
0.30
MSB Transition:
[011110] to [100000]
CSb
4.00E+08
Frequency (Hz)
0
5
10
15
20
25
30
35
40
45
50
55
Time (nsec)
12
Rev O Mar 2012
Chip Select Tirgger (Volts)
-40
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
PIN DIAGRAM (F1240 – COMPATIBILITY W/LMH DEVICES)
Note: VMODE, STBY_A, and STBY_B have internal Pullup resistors
GA1
IN_A+
IN_A-
GND
VCC
ISET_A
GA0
32
31
30
29
28
27
26
25
m
m
1
24
OUT_A+
23
OUT_A-
22
STBY_A
21
GND
20
GND
19
STBY_B
Exposed Pad
2
GA5
3
VMODE
4
NC
5
C
GA4 / CLK
O
0.
35
GA3 / DATA
GA2 / CSb
TOP View
(looking through the top of the package)
Package Drawing
5 mm x 5 mm package dimension
3.10 mm x 3.10 mm exposed pad
0.5 mm pitch
32 pins
0.75 mm height
GB5
0.25 mm pad width
6
0.40 mm pad length
IDT FlatNoiseTM IF VGA
9
10
11
12
13
13
14
15
16
GB0
OUT_B+
ISET_B
17
VCC
8
GND
GB3
IN_B-
OUT_B-
IN_B+
18
GB1
7
GB2
GB4
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
PACKAGE DRAWING
IDT FlatNoiseTM IF VGA
14
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
PIN DESCRIPTIONS
Pin #
Pin Name
1
GA3 / DATA
2
GA4 / CLK
3
GA5
4
VMODE
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NC
GB5
GB4
GB3
GB2
GB1
IN_B+
IN_BGND
VCC
ISET_B
GB0
OUT_B+
OUT_BSTYB_B
GND
GND
STYB_A
OUT_AOUT_A+
GA0
ISET_A
VCC
GND
IN_AIN_A+
GA1
32
GA2 / CSb
EP
Exposed Paddle
IDT FlatNoiseTM IF VGA
Pin Function
4 dB ATTN ctrl bit for Channel A (Parallel Mode)
OR DATA (Serial Mode)
8 dB ATTN ctrl bit for Channel A(Parallel Mode)
OR CLK (Serial Mode)
16 dB Attenuation ctrl bit for Channel A
Pull low for serial mode.
Float or pull high for parallel mode. Has internal Pullup
This pin is internally grounded
16 dB Attenuation ctrl bit for Channel B: 1 or high = 16 dB ATTN
8 dB Attenuation ctrl bit for Channel B: 1 or high = 8 dB ATTN
4 dB Attenuation ctrl bit for Channel B: 1 or high = 4 dB ATTN
2 dB Attenuation ctrl bit for Channel B: 1 or high = 2 dB ATTN
1 dB Attenuation ctrl bit for Channel B: 1 or high = 1 dB ATTN
Channel B Differential Input +. AC couple
Channel B Differential Input -. AC couple
Connect this pin to Ground
Connect this pin to the 5V DC Power Bus
ChB Icc set: Use the recommended value from the BOM section
0.5 dB Attenuation ctrl bit for Channel B: 1 or high = 0.5 dB ATTN
Channel B Differential Output +. Pull up to Vcc through an inductor
Channel B Differential Output-. Pull up to Vcc through an inductor
Pull low to Power Down ChB. Float or Pull high to enable ChB
Connect this pin to Ground
Connect this pin to Ground
Pull low to Power Down ChA. Float or Pull high to enable ChA
Channel A Differential Output -. Pull up to Vcc through an inductor
Channel A Differential Output +. Pull up to Vcc through an inductor
0.5 dB Attenuation ctrl bit for Channel A
ChA Icc set: Use the recommended value from the BOM section
Connect this pin to the 5V DC Power Bus
Connect this pin to Ground
Channel A Differential Input -. AC couple
Channel B Differential Input +. AC couple
1 dB Attenuation ctrl bit for Channel A
2 dB ATTN ctrl bit for Channel A (Parallel Mode)
OR chip select (Serial Mode)
Connect to Ground with multiple vias for good thermal relief
15
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
EVKIT SCHEMATIC
The diagram below describes the recommended applications / EVkit circuit:
J1
Vcc
C12
T1
C10
C2
IN_A+
IN_A-
GND
VCC
ISET_A
GA0
2
GA1
1
R34
GA2 / CSb
JP6
32
31
30
29
28
27
26
25
T5
L1
J4
3
GA3 / DATA
1
GA4 / CLK
2
GA5
3
4
SPI
Block
24
OUT_A+
23
OUT_A-
22
STBY_A
21
GND
C3
C1
Vcc
5
6
VMODE
7
4
Bias
Control
8
R38
R37
9
Decoder
A
10
NC
5
GB5
6
GB4
7
C4
L2
JP7 – Pin2
JP7 – Pin1
Decoder
B
20
GND
19
STBY_B
18
OUT_B-
L4
T6
11
C5
12
GB3
8
17
C8
OUT_B+
12
13
14
15
16
IN_B+
IN_B-
GND
VCC
ISET_B
GB0
14
11
GB1
13
10
GB2
J5
9
L3
Vcc
C7
Vcc
R36
VCC
14
C6
J8
C18
VCC
27
R39
C16
T3
VCC
IF1
VCC
IF2
JP1
TP1
R40
TP2
R41
TP3
R42
TP4
C17
J3
Vcc
IDT FlatNoiseTM IF VGA
16
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
EVKIT OPERATION (Email: RFsupport@IDT.com to request an EVkit and Control Cable)
The picture and graphic below describe how to operate the EVkit
Unused
Unused - ChA
F1241 ISET
Power
Down ChA
Power Down ChB
DC Power
ChA F1240 ISET
Pin1
Pin3
Pin14
JP6 – 14 pin
connector: Plug IDT
provided Parallel
Control Cable in here
IDT FlatNoiseTM IF VGA
4:1
Transformers
ChB F1240 ISET
Unused - ChB
F1241 ISET
17
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
EVKIT BOM (F1240)
REF
DES
R34
R36
R37
R38
R39
R40
R41
R42
L1
L2
L3
L4
C1
C2
C3
C4
C5
C6
VALUE
3.83K +/-1%
3.83K +/-1%
0 ohm
DNP
0 ohm
0 ohm
0 ohm
0 ohm
390 nH
390 nH
390 nH
390 nH
1,000 pF
0.1 uF
0.1 uF
0.1 uF
1,000 pF
0.1 uF
IDT FlatNoiseTM IF VGA
CASE
SIZE
0402
0402
0402
0402
0402
0402
0402
0402
0805
0805
0805
0805
0402
0402
0402
0402
0402
0402
MFG
Coilcraft
Coilcraft
Coilcraft
Coilcraft
REF
DES
C7
C8
C10
C12
C16
C17
C18
T1
T3
T5
T6
J1
J3
J4
J5
J8
JP1
J6
J7
18
VALUE
0.1 uF
0.1 uF
1,000 pF
0.1 uF
1,000 pF
0.1 uF
10 uF
4:1
4:1
4:1
4:1
SMA
SMA
SMA
SMA
SMA
DNP
14 pin- CTRL
4 pin - STBY
CASE
SIZE
0402
0402
0402
0402
0402
0402
0603
TC4-1WG2+
TC4-1WG2+
TC4-1WG2+
TC4-1WG2+
MFG
MiniCircuits
MiniCircuits
MiniCircuits
MiniCircuits
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
APPLICATIONS INFORMATION
The F1240 has been optimized for use in high performance IF sub-sampling applications. They have unique
features that make them ideal for these very demanding applications.
Matched Output
Unlike competing devices the F1240 features a matched 200 ohm differential output. All of the datasheet
parameters are specified as such. For instance, the Gain of 20 dB is a true Transducer Power gain (Power
delivered to the matched load minus Power available from the source). This is in contrast to competing
devices that usually have a high or low impedance output and must be terminated with resistors to operate
properly. In IF sampling applications, the IF VGA usually drives a Bandpass anti-alias filter which precedes
the ADC. These filters typically need to ‘see’ matched terminations. Only the F1240’s performance is
preserved in this environment. See directly below for a comparison to popular VGA styles.
Example 1: ‘Voltage Mode’ VGA
50 ohm Bandpass Anti-Alias Filter
25
In
2 ohms
200 ohms
+
VS
-
Out
50
50
25
Termination Resistors:
Ensure BPF is terminated properly with 50 ohms
Must Adjust Datasheet Values:
Total load = 100 ohmsS..Available Power = V2S / 100
Gain with 100 ohm load = 22 dB
True Gain in-system = 19 dB
Half the Power is dissipated in the terminating resistors:
(0.5VS)2 / 50
The other half of the power is delivered to the input of the BPF
Output IP3 with 100 ohm load = +44 dBm
True IP3O in-system = +41 dBm
Effectively, the Gain drops by 3 dB
Example 2: ‘Current Mode’ VGA
300 ohm Bandpass Anti-alias Filter
In
150 ohms
IS
5K
Out
300
300
300
Termination Resistor:
Ensures BPF is terminated properly with 300 ohms
Must Adjust Datasheet Values:
Total load = 150 ohms...Available Power = I2S X 150
Gain with 150 ohm load = 19 dB
True Gain in-system = 16 dB
Half the Power is dissipated in the terminating resistor:
(0.5IS)2 X 300
The other half of the power is delivered to the BPF
Output IP3 with 150 ohm load = +46 dBm
True IP3O in-system = +43 dBm
IDT FlatNoiseTM IF VGA
Again Effectively, the Gain drops by 3 dB
19
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
APPLICATIONS INFORMATION (CONT.)
Matched Output (cont.)
IDT: ‘Matched’ VGA
200 ohm Bandpass Anti-Alias Filter
0
+
In
200 ohms
VS
200 ohms
Out
200
200
0
-
Termination Resistors NOT NEEDED:
NO NEED to Adjust Datasheet Values:
VGA itself terminates BPF with proper Z = 200
Total external load = 200 ohms
Gain with 200 ohm load = 20 dB
True Gain in-system = 20 dB
Output IP3 with 200 ohm load = +49 dBm
True IP3O in-system = +49 dBm
Available Power = V2S / 200
ALL of the power is delivered to the input of the BPF
Effectively, the Gain is unchanged!
Noise Contour
The remarkable FlatNoiseTM feature of the device (see first four graphs on page 10) has great benefits when
implemented in wideband multi-carrier systems. For the first 13 dB of attenuation range, the device has only
2.3 dB degradation in noise figure. This is in stark contrast to standard VGAs like the voltage or current mode
devices described earlier. These devices have a linear dB-for-dB degradation in Noise Figure with increasing
attenuation.
Refer to the figure below. It depicts the F1240 driving a matched Anti-Alias Filter which is followed by an ADC
with a differential resistive 200 ohm termination. Note that at each point in the system the matching is
preserved.
ZDIFF = 200 ohm
ZDIFF = 200 ohm
200 MHz Discrete Anti-Alias Filter
CB
VGA_OUT+
CB
F1240/1
5V
VGA_OUT-
C2
L1
L3
V_IN+
CB
L5
C1
100
VCML
C4
Unbuffered
Pipeline ADC
100
L2
C3
V_IN-
L4
CB
ZDIFF = 200 ohm
Loss = -2 dB
ZDIFF = 200 ohm
IDT FlatNoiseTM IF VGA
20
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
APPLICATIONS INFORMATION (CONT.)
Noise Contour (cont.)
A discrete realization of a 3rd order Anti-Alias filter is shown below. Sampling occurs in Nyquist Zone3 for a
60 MHz multi-carrier signal. Noise just 20 MHz above & below the signal bandedges will alias from either
Zone4 or Zone2 and show up as added noise in the desired band at the digital output of the ADC.
10
Chebyshev Discrete LC
filter 3rd order
Zone2 Alias
noise rejection
only ~ 6 dB
0
-10
Multi-Carrier
BW = 170 to 230
MHz
-20
30 dB filtering for
H2 and IM2
products
Amplitude (dBc)
-30
-40
Zone4 Alias noise
rejection only ~ 3 dB
-50
-60
-70
-80
-90
-100
Sample Rate ~ 160 MHz
-110
Digital
Downconversion BW
-120
1st Nyquist Zone =
0 to ½ f SAMP
2nd Nyquist Zone =
½ f SAMP to f SAMP
3rd Nyquist Zone =
f SAMP to
3
4th Nyquist Zone =
3
/ 2 f SAMP
/ 2 f SAMP to 2f SAMP
-130
0
40
80
120
160
200
240
280
320
360
400
440
Frequency (MHz)
The result is that the F1240 with it’s unique noise contour will improve SNR significantly in this multi-carrier
instance . Note in the graph below: SNR improves over 2 dB at high attenuation settings which potentially
allows for the use of a lower cost 12-bit ADC in the Rx path.
13.0
Full Rx System Noise Figure (dB)
Standard VGA w/14 bit ADC
11.0
F1240/1 w/14 bit ADC
F1240/1 w/12 bit ADC
9.0
SNR @ 200 MHz
with 165 fsec clock
jitter = 69.3 dB
7.0
Up to 2.1 dB advantage
in SNR!
Enables use of low cost
12-bit ADC with no loss
of performance
SNR @ 200 MHz
with 165 fsec clock
jitter = 67.7 dB
5.0
3.0
1.0
0
4
8
12
16
20
24
VGA Attenuation below Max Gain (dB)
IDT FlatNoiseTM IF VGA
21
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
APPLICATIONS INFORMATION (CONT.)
Other Key Features:
Current Setting Resistors – The IDTF1240 already offers the best IM3 distortion performance over the widest Power range
when driving a matched load w/ 160 mA Total ICC. The user has the option to reduce ICC even further at the expense of Output IP3. See
the graph at Middle Right on Page 12 for details. Note that ChA and ChB ICC can be independently set.
Settling Time – The IDTF1240 has been optimized to settle quickly and smoothly without any ‘glitching’ when changing gain
between ANY adjacent steps. Note the two graphs at the bottom of Page 12. Even for 1 dB steps that involve MSB transitions the
settling time is still <15 nsec.
Gain Controller Software
Pulldown to select
F1240 (6 bit ctrl) or
F1241 (5 bit ctrl)
Connect IDT Cable
to 14 pin connector
on EVkit
Slide to Set
Gain for Both
ChA and ChB
Connect IDT Cable
to ‘Parallel Port’ of
Desktop PC
Scroll to
Adjust Gain
Value
Type Gain
value in
here
Download Controller Software:
●
●
●
●
●
Point your browser to: ftp3.idt.com
User Name: prodemo
Password: Fa9HsG2I
File Name: F12xx_G_CTRL_8.4.2.0.zip
Run setup.exe right from the zip file…
Contact your IDT Sales Professional
or Email: RFsupport@IDT.com to request applications support
IDT FlatNoiseTM IF VGA
22
Rev O Mar 2012
DATASHEET
Dual Intermediate Frequency Digital Variable Gain Amplifier
IDTF1240NBGI
APPLICATIONS INFORMATION (CONT.)
Operation into a 100 ohm load
The F1240 can be dropped directly into a 100 ohm termination environment without any topology changes, so
no board redesign is necessary. The example schematic below is for a 153 MHz IF center frequency. Simply
replace the pullup inductors already on the board with 91 nH and replace the series AC coupling capacitors
already on the board with 18 pF. The F1240 in this case will then drive a 100 ohm filter with ~16 dB return
loss. See schematic and measured results when matched to 100 ohms below:
AC coupling
Capacitor
ZDIFF = 100 ohm
153 MHz +/- 20MHz AAF
ZDIFF = 100 ohm
18 pF
Pins 24, 23
CB
V_IN+
VGA_OUT+
91 nH
CB
F1240/1
CB
50
VCML
Unbuffered
Pipeline ADC
5V
50
91 nH
VGA_OUT-
Pins 18, 17
V_IN-
18 pF
Pullup Inductors:
Coilcraft 0805CS
CB
ZDIFF = 100 ohm
ZDIFF = 100 ohm
AC coupling
Capacitor
25
55
20
174 MHz
50
15
S21
5
S22
Output IP3 (dBm)
S21 and S22 (dB)
45
10
0
-5
40
134 MHz
154 MHz
35
30
-10
25
-15
20
-20
15
-25
1.0E+08
1.2E+08
1.4E+08
1.6E+08
1.8E+08
-2
2.0E+08
0
2
4
6
8
10
12
14
16
18
20
Gain Setting (dB)
Frequency (Hz)
-50
0.6
0.4
-60
154 MHz Gain Step Error
-65
DNL & INL (dB)
2nd Harmonic [0 dBm Pout] (dBc)
-55
-70
174 MHz
154 MHz
-75
-80
-85
-90
0.2
0.0
-0.2
-0.4
-95
154 MHz Absolute Gain Error
134 MHz
-100
-0.6
-2
0
2
4
6
8
10
12
14
16
18
20
-4
Gain Setting (dB)
IDT FlatNoiseTM IF VGA
-2
0
2
4
6
8
10
12
14
16
18
20
Gain Setting (dB)
23
Rev O Mar 2012