arXiv:1503.00327v2 [cs.CG] 18 Aug 2015
Computing in continuous space with
self-assembling polygonal tiles (extended
abstract)
Oscar Gilbert ? , Jacob Hendricks ?? , Matthew J. Patitz
Rogers †
???
, and Trent A.
Abstract. In this paper we investigate the computational power of the
polygonal tile assembly model (polygonal TAM) at temperature 1, i.e.
in non-cooperative systems. The polygonal TAM is an extension of Winfree’s abstract tile assembly model (aTAM) which not only allows for
square tiles (as in the aTAM) but also allows for tile shapes which are arbitrary polygons. Although a number of self-assembly results have shown
computational universality at temperature 1, these are the first results to
do so by fundamentally relying on tile placements in continuous, rather
than discrete, space. With the square tiles of the aTAM, it is conjectured
that the class of temperature 1 systems is not computationally universal. Here we show that for each n > 6, the class of systems whose tiles
are the shape of the regular polygon P with n sides is computationally
universal. On the other hand, we show that the class of systems whose
tiles consist of a regular polygon P with n ≤ 6 sides cannot compute
using any known techniques. In addition, we show a number of classes
of systems whose tiles consist of a non-regular polygon with n ≥ 3 sides
are computationally universal.
?
??
???
†
Department of Mathematical Sciences, University of Arkansas, Fayetteville, AR,
USA. oogilber@email.uark.edu. This author’s research was supported in part by
National Science Foundation Grants CCF-1117672 and CCF-1422152.
Department of Computer Science and Computer Engineering, University of
Arkansas, Fayetteville, AR, USA. jhendric@uark.edu. This author’s research was
supported in part by National Science Foundation Grants CCF-1117672 and CCF1422152.
Department of Computer Science and Computer Engineering, University of
Arkansas, Fayetteville, AR, USA. mpatitz@self-assembly.net. This author’s research was supported in part by National Science Foundation Grants CCF-1117672
and CCF-1422152.
Department of Computer Science and Computer Engineering, University of
Arkansas, Fayetteville, AR, USA. tar003@uark.edu. This author’s research was
supported by the National Science Foundation Graduate Research Fellowship Program under Grant No. DGE-1450079, and National Science Foundation grants CCF1117672 and CCF-1422152.
1
Introduction
Self-assembly is a process by which systems that evolve based only on simple
local interactions form. Studying self-assembling systems can lead to insights
into everything from the origin of life [25] to new and novel ways to guide atomically precise manufacturing. Theoretical modeling of self-assembling systems
has uncovered important mathematical properties [1–3, 7, 8, 14, 23], and physical realizations have been experimentally verified in the laboratory and used to
create intricate nanostructures [4, 10, 15, 17, 22, 24]. In order to facilitate the design of these systems, a number of mathematical models have been introduced.
The work presented in this paper examines a model of self-assembly which is
an extension of Erik Winfree’s abstract Tile Assembly Model (aTAM) [27]. In
the aTAM, the fundamental components are square “tiles” with “glues” on their
edges. These tiles can then combine depending on their glues to form surprisingly
complex and mathematically interesting structures [7, 16, 21, 23, 26].
A long standing open conjecture in regards to the aTAM is that systems
in which tile attachments depend only on one exposed glue (we call such systems temperature-1 systems) are not computationally universal [9,18,19]. It may
appear clear that this conjecture is certainly true, but the ability of tile assembly systems to place a tile which prevents the attachment of a later tile gives
these systems a surprising amount of power [6, 11–13] and has made proving
such a result elusive. In fact, the exploitation of this ability has been used to
show that temperature-1 systems in other models are computationally universal [5, 11–13, 20].
This paper examines the computational power of a model which is similar to
the aTAM with the exception that the shape of the tiles in the systems is relaxed
to include any shape which is a polygon. Unlike all previous work, our model
makes no assumption about an underlying lattice and discrete space. Instead,
we must work in the real plane, and fundamentally exploit continuous space to
precisely position polygonal tiles. We call this model the polygonal TAM and
show that certain classes of temperature-1 systems in the polygonal TAM are
computationally universal. In order to show our results about computational
universality, we explicitly construct “lattices” for polygons and create geometric
“bit-readers”. In the case of regular polygons with n > 6 sides, we exploit the
inability of these polygons to tile the plane to read bits. In fact, we show that
for regular polygons which do tile the plane, bit-reading gadgets are impossible
to construct. Interestingly, our exploits do not work for pentagons. In particular,
we show that even though pentagons cannot tile the plane, bit-reading gadgets
are impossible to construct with them.
The layout of the paper is as follows. We first introduce the polygonal TAM.
Next, we introduce our main results which concentrate on the computational
power of polygonal TAM systems at temperature 1. Our first main result states
that for any regular polygon P with n > 6 sides, there exists a polygonal TAM
system consisting of tiles of shape P which simulates any Turing machine on
any input. We then provide evidence that this computational boundary is tight
by showing that the class of polygonal TAM systems composed only of tiles of
a single shape which is any regular polygon P with n ≤ 6 sides cannot compute
using any currently known techniques. On the other hand, we show that the
class of polygonal TAM systems whose tiles are composed of any two regular
polygons is capable of simulating any Turing machine on arbitrary input. We
then show two positive results about computing with systems whose tiles have
the shape of non-regular polygons with less than seven sides. In order to show
these results we have two supporting sections. One shows how we can create a
“lattice” in the plane out of any regular polygon. The other uses these “lattices”
to connect together several components which “read bits”.
2
Preliminaries
In this section we sketch definitions of the Polygonal Tile Assembly Model
(Polygonal TAM) and relevant terminology.1 Please see the Appendix for more
detailed definitions.
Polygonal Tiles A simple polygon is a plane geometric figure consisting of straight,
non-intersecting line segments or “sides” that are joined pair-wise to form a
closed path. As is commonly the case, we omit the qualifier “simple” and refer
to simple polygons as polygons. A polygon encloses a region called its interior.
The line segments that make-up a polygon meet only at their endpoints. Exactly
two edges meet at each vertex. We define the set of edges of a polygon to be the
line segments that make-up a polygon. In our definition we find it useful to give
a polygon a default position and rotation. First, we assume that the centroid, c
say, of any polygon is at the origin in R2 . Then, for a polygon Pn with n edges,
let v = (x, y) ∈ R2 be some vertex of Pn such that v 6= c. By possibly rotating
Pn about c, we can ensure that y = 0 and x > 0. For a given polygon P and
some vertex v of P that is not equal to the centroid of P , we call this position
and rotation the standard position for P given v.
A polygonal tile is a polygon with a subset of its edges labeled from some glue
alphabet Σ, with each glue having an integer strength value. Two tiles are said
to be adjacent if they are placed so that two edges, one on each tile, intersect
completely. Two tiles are said to bind when they are placed so that they have
non-overlapping interiors and have adjacent edges with complementary glues and
matching lengths; each complementary glue pair binds with force equal to its
strength value. An assembly is any connected set of polygons whose interiors do
not overlap such that every tile is adjacent to some other tile. 2 Given a positive
integer τ ∈ N, an assembly is said to be τ -stable or (just stable if τ is clear from
context), if any partition of the assembly into two non-empty groups (without
cutting individual polygons) must separate bound glues whose strengths sum to
≥ τ . We say a tile is in standard position if the underlying polygon defining its
shape is in standard position. We also refer to the centroid of a polygonal tile as
the centroid of the underlying polygon defining the shape of the tile.
Tile System A tile assembly system (TAS) is an ordered triple T = (T, σ, τ )
where T is a set of polygonal tiles, and σ is a τ -stable assembly called the seed.
1
2
The Polygonal TAM is simply a case of the polygonal free-body TAM defined in [6]
with no rotational restriction and no tile flipping. We define it here for completeness.
As with the aTAM, the edges of two tiles of an assembly may intersect, but we do
not allow for the interiors of two tiles of an assembly to have non-empty intersection.
τ is the temperature of the system, specifying the minimum binding strength
necessary for a tile to attach to an assembly. Throughout this paper, the temperature of all systems is assumed to be 1, and we therefore frequently omit the
temperature from the definition of a system (i.e. T = (T, σ)). If the tiles in T
all have the same polygonal shape, T is said to be a single-shape system; more
generally T is said to be a c-shape system if there are c distinct shapes in T .
If not stated otherwise, systems described in this paper should by default be
assumed to be single-shape systems.
We define a configuration of T to be a (possibly empty) arrangement of tiles
in R2 where tiles of this arrangement are translations and/or rotations of copies
of tiles in T . Formally, we define a configuration of T as follows. For a c-shaped
system T = (T, σ, τ ), let P1 , P2 , . . . , Pc denote the polygons that make up
the shapes of T . For each i such that 1 ≤ i ≤ c, assume that each Pi is in
standard position given some vertex vi of Pi . Then, a configuration of T is a
partial function α : R2 × [0, 2π) 99K T . One should think of this function as
mapping centroid locations and an angle of rotation, (r, θ) say, to a tile in T
as follows. Starting from t in standard position, t is rotated counter-clockwise
by θ and translated so that the centroid of t is at r. Note that the definition of
configuration makes no claim as to whether or not two tiles of a configuration
have overlapping interiors or have matching glues. Similarly, we can define an
assembly to be a configuration such that every tile is adjacent to some other tile
and the intersection of the interiors of any two distinct tiles is empty. Then an
assembly α0 is a subassembly of α if dom (α0 ) ⊆ dom (α) and if (r, θ) ∈ dom (α0 )
then α((r, θ)) = α0 ((r, θ)). We define subconfiguration analogously to the way
we defined subassembly.
3
Geometric Bit-reading, Grids, and Turing Machine
Simulation
In this section we state our main results and then give a high-level description of
the machinery used to prove these results. In particular, we describe bit-reading
gadget assemblies and grid assemblies, and briefly show how to simulate a Turing
machine using these assemblies. The general strategy that motivates the work in
this paper is similar to the the techniques used in [5,11,13]. Unlike the techniques
used in [5,11,13], we do not have an underlying integer lattice that is being tiled,
and therefore, must rely on analysis of polygonal tile assemblies in R2 .
3.1 Main results
We now state our main results. The first set of results are positive and state
that there are a variety of systems with polygons which can simulate any Turing
machine. The last result is a negative result which states that the class of systems whose tiles are composed of regular polygons with less than 7 sides cannot
compute using known techniques in self-assembly.
Informally, our first theorem states that if P is a regular polygon with ≥ 7
sides, then the class of systems with tiles of shape P is computationally universal.
Theorem 1. Let Pn be a regular polygon with n sides such that n ≥ 7. Then
for every standard Turing machine M and input w, there exists a directed TAS
with τ = 1 consisting only of tiles of shape Pn that simulates M on w.
The following theorem states that if we are allowed two different regular
polygons as tile shapes, then the class of systems consisting only of these two
shapes is computationally universal.
Theorem 2. Let Pn and Qm be regular polygons with n and m sides of equal
length. Then for every n ≥ 3 and m ≥ 3 such that n 6= m, and every standard
Turing machine M with input w, there exists a directed 2-shaped system Tn,m =
(Tn,m , σn,m ) consisting only of tiles of shape Pn or Qm that simulates M on w.
The next theorem differs from the previous two theorems in that it discusses
the computational power of polygons which are not regular. Roughly, it states
that if we relax the condition that the polygon is regular (but still equilateral),
then there exist polygons with only four sides which are capable of composing a
class of computationally universal single shape systems. It also implies this for
shapes with five and six sides as well.
Theorem 3. Let M be a standard Turing machine with input w. Then for all
n ≥ 4, there exists an equilateral polygon Pn with n sides and a directed singleshaped system Tn = (Tn , σn ) consisting only of tiles of shape Pn that simulates
M on w.
Our final positive result shows that there exists a class of single-shaped systems of obtuse isosceles triangle which is computationally universal.
Theorem 4. Let M be a standard Turing machine with input w. Then, there
exists an obtuse isosceles triangle P and a directed single-shaped system T =
(T, σ) consisting only of tiles of shape P that simulates M on w.
We now state the negative result, which is based on the fact that regular
polygonal tiles with ≤ 6 sides cannot form paths capable of blocking each other in
specific ways allowing important geometric information encoding and decoding.
Theorem 5. Let n ∈ N be such that 3 ≤ n ≤ 6. Then, there exists no temperature 1 single-shaped polygonal tile assembly system T = (T, σ, 1) where for all
t ∈ T , t is a regular polygon with n sides, and a bit-reading gadget exists for T .
Due to space constraints in this extended abstract, the proofs of most results
are relegated to the Appendix. However, in the main body we now sketch an
overview of how the positive results work and a portion of the proof of Theorem 1
for n ≥ 15, which gives the general overall scheme for all of the positive results.
3.2 Bit-Reading Gadgets Overview
First, we discuss a primitive tile-assembly component that enables computation
by self-assembling systems. This component is called the bit-reading gadget, and
essentially consists of pre-existing assemblies, bit writers, that appropriately encode bit values (i.e., 0 or 1) and paths that grow past them and are able to “read”
the values of the encoded bits; this results in those bits being encoded in the tile
types of the paths beyond the encoding assemblies. The notion of bit-reading
gadget was defined in [11]. For completeness, we present the definition here and
note that the definition applies even to systems of polygonal tiles. Figure 1 provides an intuitive overview of a temperature-1 system with a bit-reading gadget.
Essentially, depending on which bit is encoded by the assembly to be read, exactly one of two types of paths can complete growth past it, implicitly specifying
the bit that was read. It is important that the bit reading must be unambiguous,
i.e., depending on the bit written by the pre-existing assembly, exactly one type
of path (i.e., the one that denotes the bit that was written) can possibly complete
growth, with all paths not representing that bit being prevented. Furthermore,
the correct type of path must always be able to grow. Therefore, it cannot be the
case that either all paths can be blocked from growth, or that any path not of
the correct type can complete, regardless of whether a path of the correct type
also completes, and these conditions must hold for any valid assembly sequence
to guarantee correct computation.
The key to the correct functioning of a bit-reading gadget at temperature-1,
where glue cooperation is not available and one source of “input” to the growing bit-reader must instead be provided by geometry, in the form of geometric
hindrance which prevents exactly one path from continuing growth but allows
another to proceed, is the fact that it must work when reading either of two
different bit values. Using Figure 1 as a guide, one can see that it is easy to read
the “1” bit in this example by blocking the blue path. However, the difficulty
which is encountered is in correctly blocking the yellow path while allowing the
blue to continue in order to read a “0” bit. With square tiles (and as we show,
several others), this is in fact impossible. However, with most polygonal tiles
this can be accomplished by careful design of paths and blocking assemblies so
that a gap remains between the blocked path and the blocking assembly in such
a way that the other path can assemble through the gap. The techniques for
accomplishing this will be demonstrated throughout this paper.
t1
t
t
t0
x
x
y
y
Fig. 1: Abstract schematic of a bit-reading gadget. (Left) The blue path grown
from t “reads” the bit 0 from α0 (by being allowed to grow to x < 0 and placing
a tile t0 ∈ T0 ), while the yellow path (which could read a 1 bit) is blocked by
α0 . (Right) The yellow path grown from t reads the bit 1 from α1 , while the
blue path that could potentially read a 0 is blocked by α1 . Clearly, the specific
geometry of the used polygonal tiles and assemblies is important in allowing the
yellow path in the left figure to be blocked without also blocking the blue path.
3.3
Grid assemblies
As we will see in Section 3.4, our construction to simulate a Turing machine with
a Polygonal TAM system consisting of the polygon P will require us to string
together several bit writers which we will then read with a series of bit readers.
In order to ensure that the path which is assembling the bit readers is placing
the bit readers at the correct positions, we need to keep track of where the bit
writers are located. We accomplish this by constructing a lattice in the plane
with P . We can then place our bit writers at periodic positions in this lattice so
that the path which is assembling the bit readers will know where to place the
bit readers.
3.4 Turing machine simulation
Let M be a Turing machine and let w be some input to M . Figure 2 shows a
high-level schematic diagram of how a Polygonal TAM system simulates M on
input w. The input w is encoded as a sequence of bit writers with spacers placed
in between them (shown at the bottom of Figure 2 as shaded regions labeled
with an “s”). These spacers allow for our bit readers to shift back on grid without
encroaching on the territory of other bit writers. As indicated by the arrows in
Figure 2, bit readers then “read” the bit writers corresponding to the inputs.
Growth proceeds by growing to the north (shown as a dark unlabeled region in
Figure 2, and then a bit writer is assembled depending on what was read by
the bit reader. After assembling the bit writer above, growth then continues by
growing a path so that the next bit writer can be “read” (shown as the lightly
shaded region labeled “wr” in Figure 2. This growth continues until the last bit
of the row is encountered at which point, the bit reader begins “reading” the
next row. Each row of bit writers can be thought of as representing the tape of
M . The symbols on the tape and location of the head of M are all encoded in
geometry as bit writers. If the head is not located at the set of bit writers the
bit reader is currently reading, the symbols represented by the bit writers are
simply rewritten as bit writers in the row above. Otherwise, the transition may
be carried out by writing the new symbol on the tape specified by the transition
function of M in the row above as a sequence of bit writers. Also, bit writers
are assembled to indicate that the head has moved as specified by the transition
function. See [11] for most complete exposition on this technique.
Thus, to show our positive rewr bit writer
wr bit writer
wr bit writer
bit writer
sults, our task has become to 1)
bit reader
bit reader
bit reader
bit reader
show that bit reading gadgets exist for the claimed systems and
wr
bit writer wr
bit writer wr
bit writer
bit writer
2) show that we can string them
bit reader
bit reader
bit reader
bit reader
together. The first task is accoms
s
s
bit writer
bit writer
bit writer
bit writer
plished in Section 6 and the grid
which allows us to show the latter Fig. 2: Schematic of simulating a Turing mais shown in Section 5.
chine with bit-reading gadgets (from [11]).
Given an n-sided regular polygon P where n > 6, a Turing machine M and an input w, Algorithm 1 shows a
high-level schematic view of an algorithm that produces a single shape Polygonal
TAM system which simulates the Turing machine M on input w and consists
of tiles of shape P . Note that here, we are abstracting the way in which the
mathematical structures appearing in the algorithm are represented. In Section 5, we give a construction which implicitly defines an algorithm which we
call FORM GRID. This algorithm takes an integer n as input and returns a grid
formed by the n-sided regular polygon. Given a grid G and an n-sided regular
polygon, in Section G our construction implicitly gives an algorithm which we
call FORM GADGETS, that takes a grid G and an integer n, and produces a
normalized bit-reading gadget. Once we have a normalized bit reading gadget,
we can use the algorithm implicitly described in Section 3.2 of [11], which we call
INITIALIZE, that produces a system, say T = (T, σ), which grows a geometric
representation of the input w. Finally, also in Section 3.2 of [11], an algorithm is
implicitly given, which we call TRANSITION TILES, that returns a set of tiles
which are added to T so that the system T is able to simulate a transition of
the Turing machines M .
Data: n, M , w
Result: Tile assembly system T which simulates M on w
G ← FORM GRID(n);
NRG ← FORM GADGETS(G, n);
T = (T, σ) ← INITIALIZE(n, M , w, NRG);
T ← T ∪ TRANSITION TILES(n, M , NRG);
return T ;
Algorithm 1: High level algorithm for constructing a system T which simulates M on w.
4
Regular Polygonal Tile Analysis With Complex Roots
In order to construct the grid assemblies and to show the correctness of the bitreading gadgets we must show that the grid configurations and the bit-reading
gadget configurations result in a valid assembly. In other words, we must show
that the intersection of the interiors of any two distinct polygonal tiles in the
configuration is empty. Moreover, in order to show that this assembly is indeed a
valid bit-reading gadget we show that in the presence of the bit writer tiles, only
one of two bit reading assemblies (representing either a 0 or a 1) can assemble
depending on the bit writer tiles.
To prove that each bit-reading gadget configuration can be used to obtain a
valid assembly, we must compute the distances from the center of a given polygon
to the center of another polygon. For convenience, we assume that the length
of the apothem (the line segment from the center of a polygon to the midpoint
of one of its sides) of all of the regular polygons is 21 , so that the distance from
the centers of abutting polygons is 1. Then, let T be a polygonal tile, and let T 0
be a polygonal tile that abuts T . We say that a polygonal tile has the standard
orientation if after being translated so that it is centered at the origin, it has a
side that corresponds to a vertical line l segment with midpoint at 21 , 0 . See
Figure 3a for a depiction of a polygonal tile with standard orientation that is
also centered at the origin. For a polygonal tile with an odd number of sides, we
say that a polygonal tile has negated orientation if after being translated so that
it is centered at (0, 0), it is the reflection of a tile which has standard orientation
across the imaginary axis. This is depicted in Figure 3b.
We enumerate the sides of
T counter-clockwise starting from
the side s0 corresponding to l and
ending at sn−1 where n is the
number of sides of T . Similarly,
if T has negated orientation, then
we enumerate the sides as {s0i }n−1
i=0
as shown in Figure 3b. Then, rel(a) A polygonal (b) A polygonal
ative to T , if T 0 abuts T along s0 ,
tile with standard tile with negated
0
then the center of T is (1, 0). In
orientation with orientation with
0
general, for θ = 2π
n , if T abuts T
center (0, 0).
center (0, 0).
along sm , then the center of T 0 is Fig. 3: Regular polygonal tile orientations
(cos (mθ) , sin (mθ)). For the calculations in the following sections, it is convenient to identify R2 with the complex plane C so that (x, y) is identified with x + iy. Then according to Euler’s formula, (cos (mθ) , sin (mθ)) ∈ R2 corresponds to the complex number
emiθ = cos (mθ) + i sin (mθ). In other words, when T has standard orientation,
the centers of abutting polygons correspond to complex nth roots of unity, as the
centers correspond to the roots of the complex polynomial xn +1 = 0 (recall that
n is the number of sides of T ). Now let ω = eiθ . Then these roots of unity are
{ω i }n−1
i=0 . See Figure 7 for an example in the heptagonal tile case. Finally, notice
that if T has negated orientation and T 0 abuts T along s0m , then the center of
T 0 is (− cos (mθ) , − sin (mθ)), and so the center of T 0 corresponds to −ω m .
Now let T be a TAS with tiles of a
single regular polygon shape, and let α
be an assembly in T such that α contains a tile, T , with standard orientation
and let T 0 be any tile in α (including
T ). Then, since addition (respectively,
subtraction) of complex numbers corre- Fig. 4: Relative to T , the center of T1
sponds to vector addition (respectively, corresponds to ω 6 and the center of
subtraction) in R2 , the center of T 0 cor- T2 corresponds to ω 6 − ω 3 .
responds to some polynomial in ω with
integer coefficients. See Figure 4 for an example of the correspondence to the
centers of heptagonal tiles to such polynomials.
5
Overview of Polygonal Grid Construction
Given a regular polygon P , a junction polyform P is constructed in the following
manner. We begin with a polygon in standard position centered at the origin.
Starting from side s0 , we traverse the sides of the polygon counterclockwise until
we come across the edge sk where k is such that Re(ω k ) <= 0 and j ≥ k for
all j ∈ Z such that Re(ω j ) <= 0. We place our next polygons of type P in
non-standard positions centered at locations ω k and ω k as shown in Figure 5a.
Call this shape X. We create a new shape X 0 by reflecting X across the line
x = 12 . We then take the union of the shapes X and X 0 obtaining our junction
polyform shown in Figure 5b.
We form a “grid” of
these junction polyforms
a
b
by attaching an infinite
number of them to each
other so that the polygons with sides labeled
a
b
“a” are adjacent to each
other and the polygons
(a) Left half
(b) Fully formed
labeled “b” are adjacent
Fig.
5:
Constructing
a
junction polyform.
to each other.
6
Bit-reading Gadgets Overview
In the cases where tiles consist of regular polygons with 15 or more sides, we
give a general scheme for obtaining bit-reading gadgets for each case. Figure 6
depicts the bit-reading gadgets for each case. The others are handled explicitly
in the technical appendix. For the top configurations of Figure 6, note that since
each polygonal tile of these bit-reading gadgets is adjacent to another tile, we
need only show that for each top configuration depicted in Figure 6, of the two
exposed glues, g0 and g1 of the tile R, B prevents a tile from binding to g0 . In
the bottom configurations of Figure 6, we not only need to show that B prevents
a tile from binding to g1 , but we must also show that B does not prevent a tile
(the tile centered at c2 in the bottom configurations for Figure 6) from binding
to the tile that binds to g0 . The latter statement ensures that when we use
the bit-reading gadgets obtained from these configurations to simulate a Turing
machine, in the case that a 0 is read by attaching a tile to g0 , B does not prevent
further growth of an assembly.
(a) Pentadecagonal tiles
(b) Hexadecagonal tiles
(c) Heptadecagonal tiles
Fig. 6: Bit-reading gadget portions. (top) Reading a 1 and preventing placement
of a tile at c3 , (bottom) Reading a 0 and preventing placement of a tile at c4 .
Now, consider a polygon Pn with n ≥ 15 sides and let ω be the nth root of
2πi
unity e n . Then, the general scheme for constructing a bit-reading gadget falls
into two cases. First, if n is odd (the cases where n is even are similar), relative
to a tile with negated orientation (the polygon labeled R in the configurations
in Figure 6), the two configurations that give rise to the bit-reading gadget are
as follows. Let k be such that n = 2k + 1 (n = 2k if n is even). Referring to the
top configurations of Figure 6, to “write” a 1, the configuration is obtained by
centering a blocker tile with negated orientation, labeled B, at −ω n−1 + ω k+1
(whether n is even or odd) relative to R. Then to “read” a 1, R exposes two
glues g1 and g0 such that if a tile binds to g1 , it will have standard orientation
and be centered at −ω n−1 (whether n is even or odd) and if a tile binds to g0 ,
it will have standard orientation and be centered at −1. We will show that B
will prevent this tile from binding. This gives the configuration depicted in the
top figures of Figure 6. Now, referring to the bottom configurations of Figure 6,
to “write” a 0, the configuration is obtained by centering a blocker tile with
negated orientation, labeled B, at −1 + ω k−1 (−1 + ω k−2 if n is even) relative
to R. In this case, we will show that B prevents a tile from binding to g1 . In
addition, we place a glue on the tile that binds to g0 that allows for another tile
k−2
k−1
to bind to it so that its center is at c2 = −1 + ω b 2 c (c2 = −1 + ω 2 if n is
even) relative to R. This gives the configuration depicted in the bottom figures
of Figure 6a and Figure 6c. Moreover, we show that neither R nor B prevent
the binding of this tile.
In order to perform the calculations used to show the correctness of these bitreading gadgets, we consider the cases where n is even and where n is odd. Here
we give brief version of the calculations that show that a regular polygon centered
at c1 and regular polygon centered at c2 do not overlap when n ≥ 15 is odd. For
more detail and calculations for the case where n is even, see Section H.1.
Suppose that n = 2k + 1. We now refer to the bottom configurations of
Figure 6a. To show that a polygon centered at c1 and a polygon centered at c2
do not overlap, consider the case where k is odd (the case where k is even is
k−1
similar). Note that relative to c0 , c1 = 1 and c2 = ω 2 . Then the distance dn
from c1 to c2 satisfies the following equation.
2
dn =
1 − cos
(k − 1) π
n
2
+ sin
2
(k − 1) π
n
3π
Substituting k = n−1
for k and simplifying, we obtain d2n = 2 + 2 sin 2n
.
2
It is well known that for regular polygons with n sides and apothem 12 , the
circumradius is given by cos1 π . Hence, to show that a polygon centered at c1
(n)
and a polygon centered at c2 do not overlap, we show that d2n > cos21 π for
(n)
n ≥ 15. (See Section H.1. It then follows that dn > cos1 π . Therefore, dn is
(n)
greater than twice the circumradius of our polygons. Hence, a polygon centered
at c1 and a polygon centered at c2 do not overlap. We then perform similar
calculations to show that for n ≥ 15, the configurations described in this above
indeed give bit-reading gadgets.
Thus, we have shown that bit-reading gadgets can be formed, along with grids
that allow bits to be written and read, using polygonal tiles with ≥ 15 sides.
Combined with standard tile assembly techniques to simulate Turing machines,
this proves that such systems are computationally universal.
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Appendix
A
Full Description of the Polygonal TAM
We now give a full description of the Polygonal TAM.
Polygonal Tiles A simple polygon is a plane geometric figure consisting of straight,
non-intersecting line segments or “sides” that are joined pair-wise to form a
closed path. As is commonly the case, we omit the qualifier “simple” and refer
to simple polygons as polygons. A polygon encloses a region called its interior.
The line segments that make-up a polygon meet only at their endpoints. Exactly
two edges meet at each vertex. We define the set of edges of a polygon to be the
line segments that make-up a polygon. In our definition we find it useful to give
a polygon a default position and rotation. First, we assume that the centroid, c
say, of any polygon is at the origin in R2 . Then, for a polygon Pn with n edges,
let v = (x, y) ∈ R2 be some vertex of Pn such that v 6= c. By possibly rotating
Pn about c, we can ensure that y = 0 and x > 0. For a given polygon P and
some vertex v of P that is not equal to the centroid of P , we call this position
and rotation the standard position for P given v.
A polygonal tile is a polygon with a subset of its edges labeled from some
glue alphabet Σ, with each glue having an integer strength value. Two tiles
are said to be adjacent if they are placed so that two edges, one on each tile,
intersect completely. Two tiles are said to bind when they are placed so that they
have non-overlapping interiors and have adjacent edges with matching glues and
matching lengths; each matching glue binds with force equal to its strength value.
An assembly is any connected set of polygons whose interiors do not overlap such
that every tile is adjacent to some other tile. 3 Given a positive integer τ ∈ N, an
assembly is said to be τ -stable or (just stable if τ is clear from context), if any
partition of the assembly into two non-empty groups (without cutting individual
polygon) must separate bound glues whose strengths sum to ≥ τ . We say that
a tile is in standard position, if the underlying polygon defining the shape of the
tile is in standard position. We also refer to the centroid of a polygonal tile as
the centroid of the underlying polygon defining the shape of the tile.
Assembly Process Given a tile-assembly system T = (T, σ, τ ), we now define
the set of producible assemblies A[T ] that can be derived from T , as well as the
terminal assemblies, A [T ], which are the producible assemblies to which no
additional tiles can attach. The assembly process begins from σ and proceeds by
single steps in which any single copy of some tile t ∈ T may be attached to the
current assembly A, provided that it can be translated and/or rotated so that its
placement does not overlap any previously placed tiles and it binds with strength
≥ τ . For a system T and assembly A, if such a t ∈ T exists, we say A →T1 A0
3
As with the aTAM, the edges of two tiles of an assembly may intersect, but we do
not allow for the interiors of two tiles of an assembly to have non-empty intersection.
(i.e. A grows to A0 via a single tile attachment). We use the notation A →T A00 ,
when A grows into A00 via 0 or more steps. Assembly proceeds asynchronously
and nondeterministically, attaching one tile at a time, until no further tiles can
attach. An assembly sequence in a TAS T is a (finite or infinite) sequence α =
(α0 = σ, α1 , α2 , . . .) of assemblies in which each αi+1 is obtained from αi by the
addition of a single tile. The set of producible assemblies A[T ] is defined to be the
set of all assemblies A such that there exists an assembly sequence for T ending
with A (possibly in the limit). The set of terminal assemblies A [T ] ⊆ A[T ]
is the set of producible assemblies such that for all A ∈ A [T ] there exists no
assembly B ∈ A[T ] in which A →T1 B. A system T is said to be directed if
|A [T ]| = 1, i.e., if it has exactly one terminal assembly.
B
Formal Definition of Bit-Reading Gadget
For the following definition is taken from [11] and modified slightly to account
for the fact that polygonal tiles are placed in continuous, rather than discrete,
space. Here and throughout the paper, if we refer to a tile having an x (or y)
coordinate i, we are referring to its centroid being on the line x = i (or y = i)
for i ∈ R.
Definition 1. We say that a bit-reading gadget exists for a tile assembly system
T = (T, σ, τ ), if the following hold. Let T0 ⊂ T and T1 ⊂ T , with T0 ∩ T1 = ∅,
be subsets of tile types which represent the bits 0 and 1, respectively. For some
producible assembly α ∈ A[T ], there exist two connected subassemblies, α0 , α1 v
α (with w equal to the maximal width of α0 and α1 , i.e., the largest extent in
x-direction spanned by either subassembly), such that if:
1. α is translated so that α0 has its minimal y-coordinate ≤ 0 and its minimal
x-coordinate ≥ 0,
2. a tile of some type t ∈ T is placed at (w + n, h), where n, h ≥ 1, and
3. the tiles of α0 are the only tiles of α in the first quadrant to the left of t,
then at least one path must grow from t (staying strictly above the x-axis) and
place a tile of some type t0 ∈ T0 as the first tile with x-coordinate < 0, while no
such path can place a tile of type t0 ∈ (T \T0 ) as the first tile to with x-coordinate
< 0. (This constitutes the reading of a 0 bit.)
Additionally, if α1 is used in place of α0 with the same constraints on all tile
placements, t is placed in the same location as before, and no other tiles of α
are in the first quadrant to the left of t, then at least one path must grow from t
and stay strictly above the x-axis and strictly to the left of t, eventually placing
a tile of some type t1 ∈ T1 as the first tile with x-coordinate < 0, while no such
path can place a tile of type t0 ∈ (T \ T1 ) as the first tile with x-coordinate < 0.
(Thus constituting the reading of a 1 bit.)
We refer to α0 and α1 as the bit writers, and the paths which grow from t
as the bit readers. Also, note that while this definition is specific to a bit-reader
gadget in which the bit readers grow from right to left, any rotation of a bit
reader is valid by suitably rotating the positions and directions of Definition 1.
C
Complex roots of unity example using heptagonal tiles
In this section, we give example assemblies using heptagonal tiles by computing
2π
the distances of relevant tile centers using 7th roots of unity. Let ω = e 7 . For a
polygonal tile T with standard orientation, Figure 7(a) depicts the complex roots
of unity corresponding to the centers of adjacent tiles. Similarly, for a polygonal
tile T with negated orientation, Figure 7(b) depicts the negated complex roots
of unity corresponding to the centers of adjacent tiles.
(a)
(b)
Fig. 7: Representing the vector from the center of a heptagon (gray) to each
center of an adjacent heptagon using the 7th roots of unity.
If T denotes a polygonal tile with standard
orientation (the case of negated orientation is
similar) in an assembly α producible in a TAS
T , we can compute the centers of any polygonal tile in α using complex addition and subtraction relative to the center of T . Figure 8
shows the complex numbers corresponding to
the centers of tiles T1 and T2 . First, ω 6 corresponds to the center of T1 . Then note that
relative to T1 , the center of T2 corresponds to
−ω 3 . Therefore, relative to T , the center of T2
corresponds to ω 6 − ω 3 . In a similar fashion, Fig. 8: Relative to T , the center
given any two polygonal tiles, T and T 0 , the of T1 corresponds to ω 6 and the
center of T 0 relative to T can be represented center of T2 corresponds to ω 6 −
as a polynomial of ω with integer coefficients. ω 3 .
For a more in depth example of computing
the centers of heptagonal tiles, consider the
following TAS. Let T be the polygonal tile assembly system consisting of 10
tile types all with shape of a single regular heptagon. Moreover, suppose that
each tile type has two edges with strength-1 glues, and that there are 10 glues
Fig. 9: An example of computing the centers of heptagons using polynomials
of complex roots of unity. The center of each heptagonal tile is labeled with a
corresponding polynomial in ω. Glue labels are not shown.
appropriately defined so that starting from a single seed tile (the gray tile in
Figure 9), the assemble proceeds until the closed “loop” of heptagonal tiles
shown in Figure 9 assembles. At this point the assembly is terminal. Call this
assembly α. Then let T be the seed tile. Keeping Figure 7 in mind, we can
compute the centers of each polygonal tile in α relative to T . These are shown
in Figure 9. In fact, we can even compute that the center of T to obtain the
polynomial ω 6 − ω 3 + ω 5 − 1 + ω 4 − ω 6 + ω 3 − ω 5 + 1 − ω 4 , and note that this
polynomial is 0 reflecting the fact that α is a closed “loop” of heptagonal tiles.
D
Polygonal Grid Construction
Given a polygon P , we now show how to form a lattice consisting of P . This grid
will act as a coordinate system for our polygonal TAM systems and allow us to
string several bit reading gadgets together so that we may simulate any Turing
machine on any input. In order to do this, we first show that we can construct a
single polyform from P which can “grid” the plane. It will then follow that we
can form a lattice in the plane with P by placing polygons at the same locations
and with same orientations as the polygons composing the grid formed with
polyforms.
We begin by describing the construction of the polyform which we will use
to construct our grid. We then show that this is indeed a valid polyform. Next,
we shown that there exists a polygonal system which can tile the grid formed
by the polyform.
Before we begin our construction, it is necessary to introduce a couple of
definitions.
Definition 2. Let P be a regular polygon. A polyform P is a connected shape
in the plane which is constructed by combining a finite number of copies of P so
that the following requirements are met:
1. the interior points of all instances of P are disjoint
2. every instance of P completely shares a common edge with some other instance of P .
The bounding rectangle B around a polyform P is the rectangle with minimal
area that contains the interior points of P.
Junction Polyforms Given a regular polygon P , a junction polyform P is constructed in the following manner. We begin with a polygon which has standard
orientation centered at the origin. Starting from side s0 , we traverse the sides of
the polygon counterclockwise until we come across the edge sk where k is such
that Re(ω k ) <= 0 and j ≥ k for all j ∈ Z such that Re(ω j ) <= 0. We place
our next polygons of type P with negated orientations centered at locations ω k
and ω k as shown in Figure 10a. Call this shape X. We create a new shape X 0
by reflecting X across the line x = 21 . We then take the union of the shapes
X and X 0 obtaining our junction polyform shown in Figure 10b. We call k the
polyform constant.
5
2
1
3
(a) The left half
of a junction polyform.
4
6
(b)
The
fully
formed
junction
polyform.
Fig. 10: The construction of a junction polyform.
We now prove that this is indeed a valid polyform. First, we begin with some
observations.
Observation 6 For any √
n ∈ N with n > 2, there exists a point p in the nth
roots of unity such that − 23 ≤ Re(p) ≤ 0.
For 3 < n < 8, this observation is mechanical. If n >= 8, the observation
must hold since the nth roots of unity are evenly spaced around the unit circle.
Observation 7 Let P be a regular polygon with n sides in standard orientation.
Also, let k ∈ N ∪ {0} be such that k ≤ n and Im(−ω k ) ≤ 0. Denote the vertices
that compose side sk by vl and vr where vl is the counterclockwise most vertex
and vr is the clockwise most vertex. Set v = vr − vl . Then the following hold:
1. if Re(−ω k ) > 0, then Im(v) > 0, and
2. if Re(−ω k ) ≤ 0, then Im(v) ≤ 0.
This observation falls out of the fact that ω k and v must be orthogonal.
Observation 8 Let k be the polyform constant for some polyform composed of
regular polygons with n sides. Let P be a regular polygon with n sides centered
at the origin in standard orientation. Then
1. the clockwise most vertex that composes s0k is a southernmost point in P ,
and
2. the location of the counterclockwise most vertex that composes sk , call this
point z, is such that Im(z) ≥ 0.
To see the first part of this observation, note that Re(−ω k−1 ) < 0. This along
with the observation 7 implies that the clockwise most vertex of side s0k−1 must lie
to the north of the clockwise most vertex that composes s0k . Note that the clockwise
most vertex of side s0k+1 also must not lie to the south of the counterclockwise
most vertex of side s0k . Consequently, because P is convex, the clockwise most
vertex that composes s0k is a southernmost point in P .
The second part of this observation follows from Observation 6 and the fact
that a regular polygon in standard orientation centered at the origin will always
have a vertex with an absent imaginary part and a real part that is less than 0.
Lemma 1. Let P be a regular polygon, and let k be the junction polyform constant obtained from the junction polyform composed of P . Then the sets of interior points of the following polygons are pairwise disjoint: 1) the polygon in
standard orientation centered at the origin, 2) the polygon with negated orientation centered at ω k , and 3) the polygon with negated orientation centered at
ωk .
Proof. It follows from the discussion in Section 4 that the interior points of the
polygon centered at the origin and the polygon centered at ω k are disjoint. Also
since the complex conjugate of a root of unity is also a root of unity, it follows
from the discussion in Section 4 that the interior points of the polygon centered
at the origin and the polygon centered at ω k are disjoint.
It is left to show that the interior points of the two polygons centered at the
roots of unity are disjoint. To see this, first note that it follows from Observation 8
that no interior point of the polygon centered at the location ω k has real part that
is less than or equal to 0. Indeed, first note that the clockwise most vertex of side
s0k of the polygon centered at location ω k will overlap the counterclockwise most
vertex of side sk of the polygon centered at the origin by construction. It follows
immediately from Observation 8 that all interior points in the polygon centered
at ω k have imaginary parts greater than 0. Since the polygon centered at ω k is a
reflected copy of the polygon centered at ω k , it follows that the interior points in
this polygon have imaginary parts less than 0. Consequently, the interior points
of the two polygons are disjoint.
Lemma 2. Given a regular polygon P , the junction polyform constructed above
is indeed a valid polyform.
Proof. To see that the junction polyform constructed above is a valid polyform,
we check that all of the requirements in the definition of polyform are met. Since
the center of polygons labeled “2” and “3” are each located at one of the nth
roots of unity, it follows from the discussion in Section 4 that polygons labeled
“1” and “2” as well as polygons labeled “1” and “3” are joined along a common
edge and share that edge entirely. This same line of reasoning shows that the
polygon labeled “4” is joined along a common edge and shares that edge entirely
with the polygon labeled “1”. Since the shape formed by polygons labeled “4”,
“5” and “6” is a reflection of the left side of the shape, all of the polygons are
joined along a common edge and shares that edge entirely. It is readily seen from
this argument that our shape is also connected.
It is now left to show that no two polygons in the shape overlap. We denote
the polyform constant obtained from P by k. It follows from Lemma 1 that the
interior points of the polygons labeled “1”, “2”, and “3” are pairwise disjoint.
Since, the polygons labeled “4”, “5”, and “6” are a reflection of the polygons
labeled “1”, “2”, and “3”, they too are pairwise disjoint. To show that the
polygons in the two reflected halves of the shape are pairwise disjoint, first
observe that the centers of the polygons labeled “2” and “3” have real parts less
than or equal to the real part of the polygon labeled “1”. Consequently, after the
reflection and “attachment” of the two halves, the polygons labeled “2” and “5”
and the polygons labeled “3” and “6” have no less distance between each other
than the polygons labeled “1” and “4”. Since the polygons labeled “1” and “4”
have disjoint interior points, it follows that the polygons mentioned above have
disjoint interior points. Consequently, no two polygons in the shape overlap.
Polygonal Grid Technical Lemmas The following lemma will assist us in
proving Lemma 4. Informally, it states that the bounding rectangle of the junction polyform described above and shown in Figure 10b will “touch” sides s00
of the polygons labeled “2” and “3” and sides s0 of the polygons labeled “5”
and “6”. This will imply that we can attach the polyform junctions by attaching
sides s0 of polygons labeled “5” and “6” to sides s00 of polygons labeled “5” and
“6”.
Lemma 3. Consider the polygons composing the junction polyform P constructed
above from some regular polygon P (shown in Figure 10b). Also, let B be the
bounding rectangle around P. Let E be the set of points consisting of the union
of the following sets of points: 1) the set of boundary points on side s00 of the
polygon labeled “2”, 2) the set of boundary points on side s00 of the polygon labeled
“3”, 3) set of boundary points on side s0 of the polygon labeled “5”, and 4) the
set of boundary points on side s0 of the polygon labeled “6”. Then E ⊂ E ∩ B.
Proof. We prove that the boundary points on side s0 of the polygons labeled
“4” and “6” in Figure 10b lie on the bounding rectangle B. The proof that
the boundary points on side s00 of the polygons labeled “2” and “3” lie on the
bounding rectangle will then follow from a similar argument.
First, observe that for a polygon P with standard position centered at the
origin, the boundary points on side s0 are the easternmost points contained in
the polygon. Furthermore, all of these points lie on the line x = 12 . Now note that
by our construction of the junction polyform, one of the tiles labeled “5” and
“6” will contain the easternmost point of the polyform. Indeed, let x4 be the real
part of the point in the center of the polygon labeled “4”. Since our construction
ensures the real part of the√point in the center of the polygon labeled “5” is of
the form x4 + r for r ∈ [0, 23 ], the polygon labeled “5” will contain a point as
east or further east than the points in the polygon labeled “4”.
We claim that the polygons labeled “5” and “6” have centers with equal
real parts. To see this, recall that the centers of the polygons labeled “2” and
“3”have the same real parts since they are conjugates of each other. Since the
polygons labeled “5” and “6” are in the same position relative to each other as
the polygons labeled “2” and “3” just reflected across the line y = 12 i, it follows
that the polygons labeled “5” and “6” have equal real parts.
From our construction of the junction polyform, it is clear that none of the
polygons labeled “1”, “2”, or “3” have a point that is an easternmost point
of the polyform. Thus, the s0 sides of the polygons labeled “5” and “6” are
all easternmost points of the polyform. Consequently, these points lie on the
bounding box B.
Observation 9 Let P be a regular polygon, P be a polyform junction formed
from P , B be the bounding rectangle for P, and let k be the polyform constant.
Furthermore, let hb be the height of the bounding rectangle and let hw be the
width of the bounding rectangle. Then, the following constraints hold for hb and
hw : 1) hb ≤ 4 Im(ω k ) and 2) hw = 2 Re(−ω k + 1).
Figure 11 shows the dimensions of the polyform. Note that the width of the
polyform is clearly 2 Re(−ω k + 1). To see that hb ≤ 4 Im(ω k ), note that by the
way we constructed the junction polyform no interior points of the polyform can
lie on the dotted lines shown in Figure 11. Since the distance between these two
dotted lines is 4 Im(ω k ), it must be the case that hb ≤ 4 Im(ω k ).
The next lemma states that given any regular polygon, we can form a a
periodic grid of the plane.
Constructing the Polygonal Grid
Lemma 4. Given a regular polygon P , there exists a directed, polygonal tile
system T = (T, σ) (where the seed is centered at location (0, 0) and the tile set
Fig. 11: The vectors showing the dimensions of the polyforms.
a
b
b
a
Fig. 12: The preformed assembly which is composed of the tile set of the system
described in the proof of Lemma 4. The preformed assembly has two glues labeled
“a” and “b” placed as shown.
a
b
a
b b
a a
b
a
b b
a a
b b
a a
b
a
b b
a a
b b
a a
b b
a a
b
b
a a
b b
a a
b b
a a
b b
a
b
a a
b b
a a
b b
a
b
a a
b b
a
a
b
Fig. 13: An assembly formed by the system described in the proof of Lemma 4.
a
b
a
b
a
b b
a
b
a a
b
b
a
b
a
(a) The path of vectors which yields the
vector v.
(b) The path of vectors which yields the
vector w.
Fig. 14: Choosing the vectors v and w.
T contains a tile t) and vectors v, w ∈ Z2 , such that T produces the terminal
assembly α, which we refer to as a grid, with the following properties. (1) Every
position in α of the form c1 v + c2 w, where c1 , c2 ∈ Z, is occupied by the tile t,
and (2) for every c1 , c2 ∈ Z, the position in Z2 of the form c1 v + c2 w is occupied
by the tile t.
Proof. For the first part of this proof, we think of our polygonal tile system
as first forming the junction polyform P before attaching it to our assembly.
Later on in the proof, we will see that this is a valid assumption. Our tile set T ,
will consist of tiles of shape P that form the junction polyform with the glues
labeled “a” and “b” exposed as shown in Figure 12. Note that for the first part
of the proof we are essentially thinking of the assembly shown in Figure 12 as a
tile. Thus, we refer to the junction polyform as a tile and we refer to a polygon
composing the polyform as a pixel. More formally, a pixel in the polyform is a
location in the complex plane given by the center of a tile in the polyform shown
in Figure 10 (where we assume that the center of the tile labeled “1” is placed
at the origin).
To begin, we position our single seed so that the polygon labeled “1” in
Figure 10b is centered at the origin. An assembly formed by such a system is
shown in Figure 13.
Let P be a junction polyform composed of the polygon P and let k be the
polyform constant as discussed in the construction of the junction polyform. Set
v = −ω k + (1 + 0i) − −ω k + (1 + 0i) = −2ω k + 2(1 + 0i) and w = −ω k + (1 +
0i) − ω k + (1 + 0i) − ω k + ω k = −2ω k + 2(1 + 0i). The intuition behind choosing
these vectors is shown in Figure 14a and Figure 14b.
The following terminology is borrowed from [11]. Define P[i, j] = p+i·v+j·w
for i, j ∈ Z2 . Here, p acts as a distinguished pixel that we use as a reference
point. Then, for two polyforms P[i, j] and P[k, l], we say that these polyforms
are neighboring if i = k and |j − l| = 1 or j = l and |i − k| = 1.
As in [11] we prove the following claim.
Claim: P[i, j] for all i, j ∈ Z2 defines a grid of non-overlapping polyforms
such that any two neighboring polyforms P[i, j] and P[k, l] contain pixels with
a shared edge. Such a grid of polyforms is shown in Figure 13.
To begin, we show that if i 6= k or j 6= l, then the interior points of P[i, j]
and P[k, l] are disjoint. Let a = (k − i) and b = (l − j). In order to show that
P[i, j] does not overlap P[k, l], we show that 1)| Re(av + bw)| ≥ |2 Re(−ω k + 1)|
or 2) | Im(av + bw)| ≥ |4 Im(ω k )|. Since, by Lemma 9, these are the dimensions
of the bounding box of P, it will then follow that their interiors are disjoint.
We consider three cases 1) a + b > 0, 2) a + b = 0, and 3) a + b < 0. First
note that
av + bw = a(−2ω k + 2(1 + 0i)) + b(−2ω k + 2(1 + 0i))
= −2(aω k + bω k ) + 2(a + b)
For case 1, observe that
| Re(av + bw)| = | Re(−2(aω k + bω k ) + 2(a + b))|
= | − 2(a Re(ω k ) + b Re(ω k )) + 2(a + b)|
= | − 2 Re(ω k )(a + b) + 2(a + b)|
≥ | − 2 Re(ω k ) + 2|.
In the case that a + b = 0, we have
| Im(av + bw)| = | Im(−2(aω k + bω k ) + 2(a + b))|
= | Im(−2(aω k + bω k ))|
= | Im(−2((−b)ω k + bω k ))|
= | − 2(b)(Im(−ω k ) + Im(ω k ))|
= | − 2(b)(2 Im(ω k ))|
≥ | − 4 Im(ω k )|.
Although case 3 is similar to case 1, we include it here for completeness. If
a + b < 0, notice that
| Re(av + bw)| = | Re(−2(aω k + bω k ) + 2(a + b))|
= | − 2(a Re(ω k ) + b Re(ω k )) + 2(a + b)|
= | − 2 Re(ω k )(a + b) + 2(a + b)|
≥ |2 Re(ω k ) − 2|.
Now suppose that P[i, j] and P[k, l] are neighboring polyforms. First, suppose
that i = k and |j − l| = 1. We consider the case where l = j + 1 and note that
the case where l = j − 1 is similar. Consider the polygons in the lower left hand
corner of the bounding rectangle of the polyforms and denote this polygon p.
Note that the polygon p in P[k, l] lies at a position
(kv + lw) − (iv + jw) = (iv + (j + 1)w) − (iv + jw)
=w
relative to the polygon p in P[i, j].
Now, notice that P[i, j] has a polygon that lies at position −ω k +(1+0i)−ω k
relative to p in P[i, j](this is the polygon that lies in the bottom right hand corner
of the bounding box), and P[k, l] has a polygon that lies at position −ω k + ω k
relative to p in P[k, l] (this is the polygon that lies in the top left hand corner of
the bounding box). Call the first pixel described p0 and the latter p00 . Observe
that by the construction of the junction polyform, p0 has standard orientation
and p00 has negated orientation. Furthermore, observe that p00 lies at location
(w + (−ω k + ω k ) − (−ω k + (1 + 0i) − ω k ) = −2ω k + 2(1 + 0i) + (−ω k + ω k ) − (−ω k + (1 + 0i) − ω k )
= (1 + 0i)
relative to p0 . Since p0 has standard orientation, p00 has negated orientation and
p00 lies at position (1+0i) relative to p0 , it follows from the discussion in Section 4
that polygon p0 and polygon p00 completely share a common edge.
Conversely, assume that j = l and |i − k| = 1. We consider the case where
k = i − 1, and, once again, note that the case where k = i + 1 is similar. Notice
that the polygon p in P[k, l] lies at a position
(kv + lw) − (iv + jw) = ((i − 1)v + jw) − (iv + jw)
= −v
relative to the polygon p in P[i, j].
Denote the polygon that lies at position −2ω k +(1+0i) relative to p in P[k, l]
by p0 (this is the polygon that lies in the top right hand corner of the bounding
box). Observe that, relative to polygon p in P[i, j], the polygon p0 in P[k, l] lies
at position
−v + (−2ω k + (1 + 0i)) = −(−2ω k + 2(1 + 0i)) + (−2ω k + (1 + 0i))
= −(1 + 0i).
Since p in P[i, j] has negated orientation, p0 in P[k, l] has standard orientation,
and p0 lies at a position −(1 + 0i) relative to p, it follows from the discussion in
Section 4 that polygon p and polygon p00 completely share a common edge.
Now, note that since none of the “polyform junction tiles” overlap, there
are not any race conditions. Consequently, we can build the assembly described
above by attaching one polygon tile at a time (instead of an assembly of polygons). The seed of our assembly will be the southwest tile of P[0, 0].
D.1
Grid Notation
For some polygon P , we let gα denote the terminal assembly of the tile system
given in Lemma 4 (i.e. the grid assembly obtained from P ). Furthermore, for a
tile system T of shape P , α ∈ A[T ], and t a tile of α centered at the location x,
we say that t is on grid with respect to gα if there exists a tile t0 ∈ gα such that
t0 is centered at the location x and has the same orientation of t. If there does
not exist such a t0 , then we say that t is off grid with respect to gα .
D.2
Normalized Bit-reading Gadgets
Let a bit reading gadget have the properties that: 1)the tile from which the bit
writer begins growth is on grid, 2) the last tile to be placed in the bit writer
is on grid, and 3) the tile t from which the bit reader grows is also placed on
grid. We call such a bit-reading gadget an on grid bit-reading gadget. A pair of
normalized bit-writers αu0 and αu1 have the property that 1) αu0 and αu1 are
the two bit writers for some bit reading gadget and 2) the location and position
of the first tile placed in the two assemblies is the same as well as the location
and position of the last tile placed. A normalized bit-reading gadget is an on grid
bit-reading gadget with normalized bit-writers.
E
Polygons Which “Can’t Compute” at Temperature 1
In this section, we prove Theorem 5 by showing a set of polygons for which it
is impossible to create bit-reading gadgets at τ = 1, namely regular polygons
with less than 7 sides (i.e. equilateral triangles, regular pentagons, and regular
hexagons), as this was already shown to be true for squares in [11]. This provides
a sharp dividing line, since we have shown that all regular polygons with ≥ 7 sides
can form bit reading gadgets, and thus are capable of universal computation, at
τ = 1.
We now restate the Theorem for completeness and give its proof.
Theorem 10. Let n ∈ N be such that 3 ≤ n ≤ 6. Then, there exists no temperature 1 single-shaped polygonal tile assembly system T = (T, σ, 1) where for all
t ∈ T , t is a regular polygon with n sides, and a bit-reading gadget exists for T .
To prove Theorem 10, we break it into two main cases and prove lemmas
about (1) equilateral triangles and hexagons, and (2) pentagons.
E.1
Equilateral triangles, squares, and regular hexagons
Equilateral triangles, squares, and regular hexagons are all capable of tessellations of the plane. That is, using tiles of only one of those shapes it is possible
to tile the entire plane with no gaps. (As a side note, these are the only regular
polygons which can do so.) In a system consisting of tiles of only one of those
shapes, all tiles must be placed into positions aligning with a regular grid (i.e.
no tile can be offset or rotated from the grid). It was shown in [11] that squares
cannot form bit-reading gadgets at τ = 1, and because of the tessellation ability
of equilateral triangles and regular hexagons and their restriction to fixed grids,
the proof of [11] can be extended in a straightforward way to also prove that
equilateral triangles and regular hexagons cannot form bit reading gadgets at
τ = 1. Thus, the following proof is nearly identical to that for squares of [11].
Lemma 5. There exists no temperature 1 polygonal tile assembly system T =
(T, σ, 1) where for all t ∈ T , t is an equilateral triangle, and a bit-reading gadget
exists for T .
Lemma 6. There exists no temperature 1 polygonal tile assembly system T =
(T, σ, 1) where for all t ∈ T , t is a regular hexagon, and a bit-reading gadget
exists for T .
Proof. We prove Lemmas 5 and 6 by contradiction. Also, since each will use
exactly the same arguments, we will prove both simultaneously and note the
single location in the proof where the shapes of the tiles is relevant. Therefore,
assume that there exists a single-shape system T = (T, σ, 1) such that T has
a bit-reading gadget. (Without loss of generality, assume that the bit-reading
gadget reads from right to left and has the same orientation as in Definition 1.)
Let (tx , ty ) be the coordinate of the tile t from which the bit-reading paths
originate (recall that it is the same coordinate regardless of whether or not a 0
or a 1 is to be read from α0 or α1 , respectively). By Definition 1, it must be the
case that if α0 is the only portion of α in the first quadrant to the left of t, then
at least one path can grow from t to eventually place a tile from T0 at x = 0
(without placing a tile below y = 0 or to the right of (tx − 1)). We will define
the set P0 as the set of all such paths which can possibly grow. Analogously, we
will define the set of paths, P1 , as those which can grow in the presence of α1
and place a tile of a type in T1 at x = 0. Note that by Definition 1, neither P0
nor P1 can be empty.
Since all paths in P0 and P1 begin growth from t at (tx , ty ) and must always
be to the left of t, at least the first tile of each must be placed in location
(tx − 1, y). We now consider a system where t is placed at (tx , ty ) and is the
only tile in the plane (i.e. neither α0 nor α1 exist to potentially block paths),
and will inspect all paths in P0 and P1 in parallel. If all paths follow exactly the
same sequence of locations (i.e. they overlap completely) all the way to the first
location where they place a tile at x = 0, we will select one that places a tile
from T0 as its first at x = 0 and call this path p0 , and one which places a tile
from T1 as its first at x = 0 and call it p1 . This situation will then be handled
in Case (1) below. In the case where all paths do not occupy the exact same
locations, then there must be one or more locations where paths branch. Since
all paths begin from the same location, we move along them from t in parallel,
one tile at a time, until the first location where some path, or subset of paths,
diverge. At this point, we continue following only the path(s) which take the
clockwise-most branch. We continue in this manner, taking only clockwise-most
branches and discarding other paths, until reaching the location of the first tile
at x = 0. (Figures 15a and 16a show examples of this process.) We now check
to see which type(s) of tiles can be placed there, based on the path(s) which we
are still following. We again note that by Definition 1, some path must make it
this far, and must place a tile of a type either in T0 or T1 there. If there is more
than one path remaining, since they have all followed exactly the same sequence
of locations, we randomly select one and call it p0 . If there is only one, call it
p0 . Without loss of generality, assume that p0 can place a tile from T0 at that
location. This puts us in Case (2) below.
Case (1) Paths p0 and p1 occupy the exact same locations through all tile
positions and the placement of their first tiles at x = 0. Also, there are no other
paths which can grow from t, so, since by Definition 1 some path must be able
to complete growth in the presence of α0 , either must be able to. Therefore,
we place α0 appropriately and select an assembly sequence in which p1 grows,
placing a tile from T1 as its first at x = 0. This is a contradiction, and thus Case
(1) cannot be true.
Case (2) We now consider the scenario where α1 has been placed as the bitwriter according to Definition 1, and with t at (tx , ty ). Note that path p0 must
now always, in any valid assembly sequence, be prevented from growing to x = 0
since it places a tile from T0 at x = 0, while some path from T1 must always
blocked by p'
p'
p'
t
t
x
x
y
y
(a) Example sets P0 and P1 , with p0
traced with a red line. Red triangles represent branching points of paths, gold
triangles represent overlapping points of
different branches.
(b) An example of the growth of p0
(traced with a red line) blocked by α1 .
By first letting as much of p0 grow as possible, it is guaranteed that all other paths
must be blocked from reaching x = 0.
Fig. 15: Failed bit-readers with equilateral triangles.
blocked by p'
p'
p'
t
t
x
x
y
y
(a) Example sets P0 and P1 , with p0
traced with a red line. Red hexagons represent branching points of paths, gold
hexagons represent overlapping points of
different branches.
(b) An example of the growth of p0
(traced with a red line) blocked by α1 .
By first letting as much of p0 grow as possible, it is guaranteed that all other paths
must be blocked from reaching x = 0.
Fig. 16: Failed bit-readers with regular hexagons.
succeed. We use the geometry of the paths of T1 and path p0 to analyze possible
assembly sequences.
We create a (valid) assembly sequence which attempts to first grow only p0
from t (i.e. it places no tiles from any other branch). If p0 reaches x = 0, then
this is not a valid bit-reader and thus a contradiction. Therefore, p0 must not
be able to reach x = 0, and since the only way to stop it is for some location
along p0 to be already occupied by a tile, then some tile of α1 must occupy such
a location. This means that we can extend our assembly sequence to include the
placement of every tile along p0 up to the first tile of p0 occupied by α1 , and note
that by the definition of the regular grid of equilateral triangle tiles, or of regular
hexagon tiles, some tile of p0 must now have a side adjacent to some tile of α1 .
At this point, we can allow any paths from P1 to attempt to grow. However,
by our choice of p0 as the “outermost” path due to always taking the clockwisemost branches, any path in P1 (and also any other path in P0 for that matter)
must be surrounded in the plane by p0 , α1 , and the lines y = 0 and x = tx
(which they are not allowed to grow beyond), and thus cannot be connected and
extend beyond that boundary. (Examples can be seen in Figures 15b and 16b.)
Therefore, no path from P1 can grow to a location where x = 0 without colliding
with a previously placed tile or violating the constraints of Definition 1. (This
situation is analogous to a prematurely aborted computation which terminates
in the middle of computational step.) This is a contradiction that this is a bitreader, and thus none must exist.
t
u
E.2
Regular pentagons
Because regular pentagons don’t tessellate the plane, the proof that they can’t
form bit-reading gadgets is slightly different than for equilateral triangles, squares,
and regular hexagons. However, the fact that they can only bind in two relative
rotations and the ratio of their side lengths to perimeters ensure that they are
still unable to form bit-reading gadgets due to the fact that it is still impossible
for one path of regular pentagons to be blocked from continued growth without
trapping all other paths on one side. This means that the “outermost” path,
along with any part of the bit-writer which blocks its full growth, can always
prevent any inner paths from sufficient growth.
Lemma 7. There exists no temperature 1 polygonal tile assembly system T =
(T, σ, 1) where for all t ∈ T , t is a regular pentagon, and a bit-reading gadget
exists for T .
Proof. The proof of Lemma 7 is nearly identical to that for Lemmas 5 and
6, with the only slight change being due to the fact that regular pentagons
aren’t constrained to a single fixed grid. First, because of this we will slightly
adapt Definition 1 so that rather than requiring tiles to be at specific discrete
coordinates, they instead are constrained by lines in R2 . For instance, we no
longer require the bit-reader to grow a path to x-coordinate 0, but instead just
beyond a set vertical line x = r for some r ∈ R. (without loss of generality we’ll
assume x = r = 0 for that constraint.) This change is merely a technicality and
does not affect the proof, and therefore, we will use the previous proof up to the
point where Case (2) makes the argument that the regular grid of tiles ensures
that the last tile which can be placed along p0 must have an edge adjacent to a
tile of α1 . Due to the lack of such a grid, we will now only be able to guarantee
that some portion of the next position of p0 , i.e. the location where α1 first
prevents the addition of another tile (which we will now refer to as location p0b ),
is occupied by a tile of α1 (whose location we will now refer to as p0α . Referring
to the location of the last tile which can be placed on p0 as p0end , by the fact that
p0 would have been a connected path which included p0b , and that the tile at pα
prevents its placement, the location p0b must consist of the area of a tile oriented
so that it has an edge adjacent to p0end . Also, although the tiles at p0α and pend
need not share an adjacent edge and there may in fact be a gap between them,
p0α must overlap with p0b . (See Figure 17b for an example.)
p'
t
t
x
x
y
y
(a) Example sets P0 and P1 , with p0
traced with a red line. Red pentagons
represent branching points of paths, gold
hexagons represent overlapping points of
different branches.
(b) An example of the growth of p0
(traced with a red line) blocked by α1 .
By first letting as much of p0 grow as possible, it is guaranteed that all other paths
must be blocked from reaching x ≤ 0.
The location outlined in dashed red represents the location of the first tile of p0
which is blocked by α1 .
Fig. 17: Failed bit-readers with regular pentagons.
At this point, we continue the direction of the previous proof and allow
any paths from P1 to attempt to grow. However, by our choice of p0 as the
“outermost” path due to always taking the clockwise-most branches, any path
in P1 must be surrounded in the plane by p0 , α1 , and the lines y = 0 and x = tx
(which they are not allowed to grow beyond), with the only discontinuity being
the possible gap consisting of the portion of p0b which is not occupied by the tile at
p0α . We prove that this gap must be insufficient to allow a path p from P1 to grow
through using a simple case analysis. A key feature of regular pentagonal tiles is
the fact that although their relative offsets are not fixed on a grid, their relative
rotations are constrained to a total of only two orientations while allowing them
to be connected to the same assembly.
3
2
2
1
1
(a) Tile 2 has the same orientation as
p0b and attaches at an offset slightly
below
(b) Tile 2 has the same orientation as
p0b and attaches at an offset slightly
above
3
3
2
2
1
(c) Tile 2 has the opposite orientation as p0b and attaches with its nearest vertex below the bottom corner
of p0end and p0b
1
(d) Tile 2 has the opposite orientation as p0b and attaches with its nearest vertex above the bottom corner
of p0end and p0b
Fig. 18: A case analysis of why one path, p0 , of regular pentagonal tiles cannot
be blocked while allowing another, p, to grow through a gap. Let the yellow tile
be at p0end , the location of the last placed tile of path p0 , the grey represent some
blocking tile of α1 , at p0α (which may be in either possible orientation), and the
red dashed location be p0b , the first tile of p0 prevented from being placed. The
blue tiles represent a portion of path p which attempts to grow from below to
above p0 , with the tiles labeled in order of their placements.
To prove the gap is insufficient for p, we perform a case analysis as outlined in
Figure 18. We first note that the blocker may never occupy space inside the black
diagonal shown across a portion of the red dashed box, since that would leave
a maximum distance of one side length for the gap throughout a portion of the
gap, and for any pair of regular pentagonal tiles, the narrowest location is never
less than that, occurring at the boundary of two adjacent tiles and immediately
increasing on both sides of that. We now analyze the various cases.
In Figure 18a, having the tile at position 2 at the same orientation but an
offset below p0b requires that that tile fill the bottom edges of the location p0b ,
leaving the blocker only the top left edge through which to block. However, in
order to allow the tile at location 3 to bind to the top right side, the tile at
location 2 must be offset up and left in order not to collide with the yellow tile
at p0end (since the width of the pair of adjacent tiles increases on both sides of
their adjacent edge), forcing it (or a portion of tile 3) to overlap with the blocker.
In order for the tile at location 3 to instead bind to the top left side of the tile at
location 2, it would have to overlap with the blocker. This means that p would
be blocked and the bit-reader fails, so this case must not be true.
In Figure 18b, having the tile at position 2 at the same orientation but an
offset above p0b requires that that tile fill the entire right side of p0b in order
to avoid the yellow tile at p0α , thus making it collide with the blocker and the
bit-reader again fail.
In Figure 18c, having the tile at position 2 at the opposite orientation as
p0b but with its southeast corner below the southwest corner of the tile at p0end
forces the tiles at positions 2 and 3 to cover all of the left side of p0b and thus
collide with the blocker, once again making the bit-reader fail.
In Figure 18d, having the tile at position 2 at the opposite orientation as p0b
with with its southwestern corner above the southwest corner of the tile at p0end
again requires that the tiles at positions 2 and 3 to cover the entire left side of
p0b , colliding with the blocker and making the bit-reader fail.
The cases discussed, along with all others which are the same up to rotation,
prevent the growth of path p. Therefore, no path from P1 can grow to a location
past the line x ≤ 0 without colliding with a previously placed tile or violating
the constraints of Definition 1. (This situation is analogous to a prematurely
aborted computation which terminates in the middle of computational step.)
This is a contradiction that this is a bit-reader, and thus none must exist.
t
u
The combination of Lemmas 5, 6, 7, and Theorem 6.1 of [11] suffice to prove
Theorem 10.
F
Bit-reading Gadgets
In this section, we give configurations that are then used to construct bit-reading
gadgets for 1) single shape systems with regular polygonal tiles with 7 or more
sides (See Section F.1.), 2) 2-shaped systems with regular polygonal tiles for pairs
of distinct polygons with 3 to 6 sides (See Section F.2.), and 3) single shaped
systems with equilateral polygonal tiles with 4, 5, or 6 sides (See Section F.3.).
Finally, in Section F.4, we give a bit-reading gadget for a single shaped system
with tiles having the shape of an obtuse isosceles triangle. All of the configurations presented here will be used to obtain bit-reading gadgets that read bits
from right to left. It should be noted that for all of the polygons considered
here, configurations that yield left to right bit-reading gadgets can be obtained
by simply reflecting the corresponding right to left configurations.
F.1
Single shape systems with regular polygonal tiles
In the following subsections, we give configurations that will be used to construct
bit-reading gadgets for single shape systems with regular polygonal tiles with 7
or more sides. While the configurations presented here do not technically fit
Definition 1, in Section G we describe how to turn these configurations into
bit-reading gadgets that do conform to that definition. In this section, we are
concerned with showing how to use the geometry of polygonal tiles to ensure that
our bit-reading gadgets properly read and write bits as described in Definition 1.
Therefore, combining the results of this section with Section G, we show the
following lemma.
Lemma 8. Let Pn be a regular polygon with n sides. Then, for all n ≥ 7, there
exists a single-shaped system Tn = (Tn , σn ) with shape Pn such that a bit-reading
gadget exists for Tn .
In order to prove Lemma 8, we first consider the cases where n is 7, 8, 9, 13,
or 14, since these cases are handled by giving a specific bit-reading gadget for
each case. Second, we give bit-reading gadgets for the cases where n is 10, 11,
or 12. These cases are simpler than the former cases and are handled using a
more generic approach. Finally, we give the bit-reading gadgets for the cases
where n ≥ 15. These cases are handled by using a single generic scheme for
constructing the bit-reading gadgets for each case.
Tiles with 7, 8, 9, 13, or 14 sides In this section we give a description of the
bit-reading gadget for heptagonal tiles and give a brief example of a calculation
that shows that certain tiles do not overlap. Figure 19 gives a depiction of a
bit-reader for heptagonal tiles.
In Figure 19, the gray tiles represent the bit writer tiles (representing either
0 or 1), while the white tiles are the bit reader tiles. In our construction, we
ensure that we have an assembly sequence such that the gray tiles of a bitreading gadget bind before any white tiles. Figure 19b depicts the case in which
a 1 has previously been written and is then read. In this case, we observe that
the bit writer tiles prevent the formation of the path of tiles depicted in 19a
from R to T1 , ensuring that a tile is a tile binds to the glue g1 , resulting in a 1
being read. Moreover, since the configuration of Figure 19b consists of abutting
heptagonal tiles with non-overlapping interiors, we see that with appropriately
defined glues, the bit writer configuration and the bit reader configuration are
valid assemblies. We can also see that no two tiles of the bit writer configuration
and the bit reader configuration have overlapping interiors; this ensures that
these two assemblies can be part of the same larger assembly.
(a) A 0 is read, and a 1 cannot be read by
mistake since the tile B prevents a heptagonal
tile from attaching via the glue labeled g1 .
(b) A 1 is read. This time a 0 cannot be read
by mistake since the tile B prevents growth of
a path of heptagonal tiles that attach via the
glue labeled g0 . Note that some of this path
may form, but B prevents the entire path from
assembling, and thus prevents a 0 from being
read.
Fig. 19: A connected bit-gadget consisting of heptagonal tiles.
Similarly, Figure 19a depicts the case in which a 0 has previously been written and is being read. Though much of this configuration consists of abutting
heptagonal tiles with non-overlapping interiors, it is not clear that all of the
heptagonal tiles have non-overlapping intersection. For example, it is indeed the
case that R and T2 have non-overlapping intersection (It turns out that they do
share a portion of an edge.) but it is not clear that the interiors of these tiles do
not overlap on some tiny set of points. Moreover, it is not clear that a tile could
not attach to the glue g1 . Therefore, we must calculate the distance between
these tiles to show that, with appropriately defined glues, the bit reader configuration is a valid assembly, and that no two tiles of the bit writer configuration
and the bit reader configuration have overlapping interiors.
Referring to Figure 19a, we will first show that the tile labeled R does not
prevent the binding of the tile labeled T1 or the tile labeled T2 . Let c denote
the center of the tile R, c1 denote the center of T1 , and c2 denote the center of
T2 . Then, to calculate c1 and c2 relative to c, we assume that R has standard
orientation and is centered at the origin. Following the path of tiles from R
to T1 and summing the appropriate roots of unity, we obtain the polynomials
c1 = ω 6 − ω 3 + ω − ω 4 + 1 − ω 4 + ω − ω 3 + 1 − ω 2 + ω 5 − ω 2 + ω 4 − ω 6 + ω 4 −
ω 6 + ω 4 − ω + ω 4 − 1 + ω 3 − ω 6 + ω 2 . Note that c2 = c1 − ω 6 . By simplifying
c1 , we get c1 = 1 + ω − ω 2 − ω 3 + 2ω 4 + ω 5 − 2ω 6 . Then, as multiplying by ω
corresponds to rotating by 2π/7, it is enough to show that Re(ω 2 c1 ) ≥ 1, and
to see this, consider the following.
ω 2 c1 = ω 2 + ω 3 − ω 4 − ω 5 + 2ω 6 + ω 7 − 2ω 8
= ω 2 + ω 3 − ω 4 − ω 5 + 2ω 6 + 1 − 2ω
= ω 2 + ω 3 − ω −3 − ω −2 + 2ω 6 + 1 − 2ω −6
= 1 + (ω 2 − ω −2 ) + (ω 3 − ω −3 ) + 2(ω 6 − ω −6 )
Finally, since (ω 2 − ω −2 ), (ω 3 − ω −3 ), and 2(ω 6 − ω −6 ) are purely imaginary, we
see Re(ω 2 c1 ) = 1. It follows that the intersection of the interiors of R and T1
is empty. The remainder of the distance calculations are given in Section H.1.
For tiles consisting of regular polygons with 8, 9, 13, or 14 sides we give the
bit-reading gadgets and calculations in Section H.1.
Tiles with 10, 11, or 12 sides In the cases where tiles consist of regular
polygons with 10, 11, or 12 sides, bit-reading gadgets are relatively simple to
construct. Figure 20 depicts the configurations that we will use to construct
our bit-reading gadgets for each case. Note that since each polygonal tile of
these configurations is adjacent to another tile, we need only show that for each
configuration depicted in Figure 20, of the two exposed glues, g0 and g1 of the
tile R, a tile can only attach to one of these glues depending on the position
of the tile B in the figure. In other words, for each configuration depicted in
Figure 20, we show that in the top configuration, B prevents a tile from binding
to g1 , and that in the bottom configuration, B prevents a tile from binding to
g0 .
(a) Bit-reading gadget configuration for
decagonal tiles.
(b) Bit-reading gadget
configuration for hendecagonal tiles.
(c) Bit-reading gadget
configuration for dodecagonal tiles.
Fig. 20: (a), (b) and (c) each depict two configurations of polygonal tiles which
represents either a 0 (bottom) or a 1 (top).
Like the bit-reading gadgets themselves, the calculations used to show the
correctness of these bit-reading gadgets are relatively simple when compared
to the previous cases. For example, for decagonal tiles, in top configuration
depicted in Figure 20a, to show that B prevents a tile from binding to g0 , note
that a polygon centered at c2 and a polygon centered at c3 overlap. Let ω be
2πi
the 10th root of unity e 10 . Note that relative to c2 , c3 = ω + ω 9 − 1. Hence,
c3 = ω + ω 9 − 1 = 2 Re(ω) − 1 = 2 cos 2π
10 . Then the distance d from c3
−
1|
<
.62,
and
therefore the intersection of the
to c2 satisfies d = |2 cos 2π
10
interiors of a decagon centered at c3 and a decagon centered at c2 is nonempty.
Hence, a decagonal tile cannot bind to the glue g0 . The remaining calculation
for the decagonal tiles case as well as the calculations for the hendecagonal and
dodecagonal cases are given in Section H.1.
Tiles with 15 or more sides In the cases where tiles consist of regular polygons with 15 or more sides, we give a general scheme for obtaining bit-reading
gadgets for each case. Figure 21 depicts the bit-reading gadgets for each case.
For the top configurations of Figure 21, note that since each polygonal tile of
these bit-reading gadgets is adjacent to another tile, we need only show that for
each top configuration depicted in Figure 21, of the two exposed glues, g0 and g1
of the tile R, B prevents a tile from binding to g0 . In the bottom configurations
of Figure 21, we not only need to show that B prevents a tile from binding to
g1 , but we must also show that B does not prevent a tile (the tile centered at c2
in the bottom configurations for Figure 21) from binding to the tile that binds
to g0 . The latter statement ensures that when we use the bit-reading gadgets
obtained from these configurations to simulate a Turing machine, in the case
that a 0 is read by attaching a tile to g0 , B does not prevent further growth of
an assembly.
Now, consider a polygon Pn with n ≥ 15 sides and let ω be the nth root of
2πi
unity e n . Then, the general scheme for constructing a bit-reading gadget falls
into two cases. First, if n is odd (the cases where n is even are similar), relative
(a) Bit-reading gadget
configuration for pentadecagonal tiles.
(b) Bit-reading gadget
configuration for hexadecagonal tiles.
(c) Bit-reading gadget
configuration for heptadecagonal tiles.
Fig. 21: (a), (b) and (c) each depict two configurations of polygonal tiles which
represents either a 0 (bottom) or a 1 (top).
to a tile with negated orientation (the polygon labeled R in the configurations
in Figure 21), the two configurations that give rise to the bit-reading gadget are
as follows. Let k be such that n = 2k + 1 (n = 2k if n is even). Referring to the
top configurations of Figure 21. To “write” a 1, the configuration is obtained by
centering a blocker tile with negated orientation, labeled B in the top configurations of Figure 21, at −ω n−1 + ω k+1 (whether n is even or odd) relative to
R. Then to “read” a 1, R exposes two glues g1 and g0 such that if a tile binds
to g1 , it will have standard orientation and be centered at −ω n−1 (whether n is
even or odd) and if a tile that binds to g0 , it will have standard orientation and
be centered at −1. We will show that B will prevent this tile from binding. This
gives the configuration depicted in the top figures of Figure 21. Now, referring
to the bottom configurations of Figure 21, to “write” a 0, the configuration is
obtained by centering a blocker tile with negated orientation, labeled B in the
bottom configuration of Figure 21a, at −1 + ω k−1 (−1 + ω k−2 if n is even) relative to R. In this case, we will show that B prevents a tile from binding to g1 .
In addition, we place a glue on the tile that binds to g0 that allows for another
k−1
k−2
tile to bind to it so that its center is at c2 = −1 + ω b 2 c (c2 = −1 + ω 2 if n is
even) relative to R. This gives the configuration depicted in the bottom figures
of Figure 21a and Figure 21c. Moreover, we show that neither R nor B prevent
the binding of this tile.
In order to perform the calculations used to show the correctness of these
bit-reading gadgets, we consider the cases where n is even and where n is odd.
Here we give brief versions of the calculations when n is odd. For more detail
and calculations for the case where n is even, see Section H.1.
Suppose that n = 2k + 1. We now refer to the bottom configurations of
Figure 21a. To show that a polygon centered at c1 and a polygon centered at
c2 do not overlap, consider the case where k is odd (the case where k is even is
k−1
similar). Note that relative to c0 , c1 = 1 and c2 = ω 2 . Then the distance dn
from c1 to c2 satisfies the following equation.
2
(k − 1) π
(k − 1) π
2
2
dn = 1 − cos
+ sin
n
n
3π
Substituting k = n−1
for k and simplifying, we obtain d2n = 2 + 2 sin 2n
.
2
It is well known that for regular polygons with n sides and apothem 12 , the
circumradius is given by cos1 π . Hence, to show that a polygon centered at c1 and
(n)
a polygon centered at c2 do not overlap, we show that d2n > cos21 π for n ≥ 15.
2
( n )
3π
2 π
2 π
To see this,
note
that
cos
d
=
2
cos
1
+
sin
n
n
n
2n . Then for n ≥ 15,
3π
> 2 cos2 π4 = 1. It then follows that dn > cos1 π .
2 cos2 nπ 1 + sin 2n
(n)
Therefore, dn is greater than twice the circumradius of our polygons. Hence, a
polygon centered at c1 and a polygon centered at c2 do not overlap.
To show that a polygon centered at c3 and a polygon centered at c4 overlap,
note that relative to c1 , c3 = −1+ω k−1 and c4 = −ω n−1 . Therefore, the distance
dn from c3 to c4 is satisfies the equation
2
2(n − 1)π
2(k − 1)π
2
+ cos
dn = −1 + cos
n
n
2
2(n − 1)π
2(k − 1)π
+ sin
=
+ sin
n
n
Substituting k =
n−1
2
for k and simplifying, we obtain,
π π d2n = 1 + 2 2 sin2
1 − 2 cos
.
n
n
Note that for each n > 2, d2n < 1. To see this, it suffices to show that
π π 2 sin2
1 − 2 cos
< 0.
n
n
This follows from the fact that 2 sin2 nπ > 0 and 1 − 2 cos nπ < 0 for n > 2.
Now, since for each n > 2, d2n < 1, we see that dn < 1. Since the length of
the apothem for each tile is assumed to be 12 , we can conclude that a polygon
centered at c3 and a polygon centered at c4 must overlap.
F.2
2-shaped systems with regular polygonal tiles
In this section we describe bit-reading gadgets for 2-shaped systems whose tileset consists of two distinct regular polygons. We assume that the edges of all
polygonal tiles have the same length. The bit-reading gadgets that we give here
are normalized on-grid bit-readers.
Lemma 9. Let Pn and Qm be a regular polygons with n and m sides of equal
length. Then, for all n ≥ 3 and m ≥ 3 such that n 6= m, there exists a 2-shaped
system Tn,m = (Tn,m , σn,m ) with shapes Pn and Qm such there a bit-reading
gadget exists for Tn,m .
(a) A 1 is read. This time a 0 cannot
be read by mistake since the tile B prevents growth of a path of tiles that attach via the glue labeled g0 .
(b) A 0 is read, and a 1 cannot be read
by mistake since the tile B prevents a
tile from attaching via the glue labeled
g1 .
Fig. 22: A connected bit-gadget consisting of tiles shaped like a regular triangle
or square.
(a) and (b) of Figure 22 depict bit-reading gadgets which give a scheme for
“writing a bit” as growth proceeds from left to right, and “reading a bit” as
growth proceeds from right to left. To write a bit, we can define unique glues
that enforce the assembly of the path of tiles (light gray tiles in (a) and (b) of
Figure 22) starting from the tile labeled B0 and ending at a tile labeled B2 in
(a) and (b). Assuming that the light gray tiles are part of an existing assembly,
to read a bit, we define unique glues that enforce the (dark gray tiles in (a) and
(b)) starting from the tile labeled R0 and ending with the tile labeled R1 . Then,
R1 exposes two glues labeled g0 and g1 in Figure 22. Now, depending on whether
an assembly which represents a 0 is present or an assembly which represents a 1
is present, either a triangular tile with a glue labeled g1 binds to R1 via the glue
g1 exposed by R1 (depicted in Figure 22a) or a square shaped tile with a glue
labeled g0 binds to R1 via the glue g0 exposed by R1 (depicted in Figure 22b).
In the former case, denote the triangular tile which binds to R1 by R2 ; this
tile is labeled R2 in Figure 22a. Then, we can define glues that allow the tiles Ri
for i = 3, 4, 5, 6 or 7 to bind in that order as depicted in Figure 22a. Finally, we
define a set of tiles that form the path of tiles from R7 to R8 . The latter case,
depicted in Figure 22b, is similar. In this case, a square tile (labeled R2 ) binds
to g0 . We define this tile such that the path of tiles from R2 to R4 assembles.
Note that the square tile labeled R3 ensures that the triangular tiles along this
path of tiles from R3 to R4 are on-grid. In particular, R4 is on-grid. Lastly, we
refer to each configuration in Figure 22 and note that relative to the underlying
grid (shown as dashed lines), B0 , B2 , R0 and R8 in (a) and respectively B0 ,
B2 , R0 and R4 in (b) are on-grid and in the same location. It is straightforward
to see that such configurations can be extended to give a normalized on-grid
bit-reading gadget that conforms to Definition 1.
Constructions for normalized on-grid bit-reading gadgets for pairs of regular
polygons with sides m and n where 3 ≤ m ≤ 6, 5 ≤ n ≤ 6 and m 6= n are similar
and are given in Section H.2.
F.3
Single shaped systems with equilateral polygonal tiles
In this section we describe bit-reading gadgets for single-shaped systems whose
tileset consists of an equilateral polygon. The bit-reading gadgets that we give
here are normalized on-grid bit-readers. Note that for polygons with 7 or more
sides, Lemma 8 implies the following lemma. Hence, we need only show Lemma 10
for equilateral polygons with 4, 5, or 6 sides. Therefore, we give normalized ongrid bit-reading gadgets for all three cases showing the following lemma. It should
be noted that while the general grid construction given in Section 5 pertain to
regular polygons. Similar techniques can be used to obtain grids for the equilateral polygonal tiles in this section. The grids themselves are depicted using
dashed lines in the figures of this section.
Lemma 10. For all n ≥ 4, there exists an equilateral polygon Pn with n sides
and a single-shaped system Tn = (Tn , σn ) shape Pn such a bit-reading gadget
exists for Tn .
(a) and (b) of Figure 23 depict bit-reading gadgets which give a scheme for
“writing a bit” as growth proceeds from left to right, and “reading a bit” as
growth proceeds from right to left. To write a bit, we can define unique glues
that enforce the assembly of the path of tiles (light gray tiles in (a) and (b) of
Figure 23) starting from the tile labeled B0 and ending at a tile labeled B2 in
(a) and (b). Assuming that the light gray tiles are part of an existing assembly,
to read a bit, we define unique glues that allow R0 , R1 and R2 to bind in that
order. Then, R2 exposes two glues labeled g0 and g1 in Figure 23. Now, depending
on whether an assembly which represents a 0 is present or an assembly which
represents a 1 is present, either a quadrilateral tile with a glue labeled g1 binds
to R2 via the glue g1 exposed by R2 (depicted in Figure 23a) or a quadrilateral
tile with a glue labeled g0 binds to R2 via the glue g0 exposed by R2 (depicted
in Figure 23b). In the former case, denote the quadrilateral tile which binds
to R2 by R3 ; this tile is labeled R3 in Figure 23a. Then, we can define glues
that allow the tiles Ri for 3 ≤ i ≤ 10 to bind in that order as depicted in
Figure 23a. Moreover, we note that B1 prevents a tile from binding to g0 . The
latter case, depicted in Figure 23b, is similar. In this case, a quadrilateral tile
(labeled R2 ) binds to g0 . We define this tile such that the path of tiles from R2
to R4 assembles. In the case of Figure 23b, we also note that B1 prevents a tile
from binding to g1 . Finally, we note that relative to the underlying grid (shown
as dashed lines in (a) and (b) of Figure 23) this configuration can then be used
to obtain a normalized on-grid bit-reading gadget.
(a) A 0 is read, and a 1 cannot be read by mistake since the tile B prevents a quadrilateral
tile from attaching via the glue labeled g1 .
(b) A 1 is read. This time a 0 cannot be read
by mistake since the tile B prevents growth
of a path of quadrilateral tiles that attach via
the glue labeled g0 .
Fig. 23: A connected bit-gadget consisting of quadrilateral tiles. This figure also
depicts the tile shape.
Constructions for normalized on-grid bit-reading gadgets for equilateral polygons with sides 5 or 6 sides are similar and are given in Section H.3.
F.4
A single shaped system with triangular tiles
In this section we describe bit-reading gadgets for single-shaped systems whose
tile set consists of a particular obtuse isosceles triangle. We assume that the edges
of all triangular tiles have the same length. The bit-reading gadgets that we give
here are normalized on-grid bit-readers. Again, it should be noted that while the
general grid construction given in Section 5 pertain to regular polygons. Similar
techniques can be used to obtain grids for the triangular tiles in this section. The
grids themselves are depicted using dashed lines in the figures of this section.
Lemma 11. There exists an obtuse isosceles triangle P and a single-shaped
system T = (T, σ) with shape P such a bit-reading gadget exists for T .
(a) A configuration of polygonal tiles which
represents a 0
(b) A configuration of polygonal tiles which
represents a 1.
Fig. 24: Bit-reading gadget configuration for tiles with the shape of an irregular
triangle.
Figure 24 depicts the configurations that give rise to bit-reading gadgets for
single-shaped systems whose tiles have the shape of an obtuse isosceles triangle.
As in Section F.3, one can see that these configurations can be used to obtain a
normalized on-grid bit-reading gadget.
G
Building Normalized Bit-reading Gadgets
Let P be a regular polygon with 7 or more sides, and let gα denote the terminal
assembly of the tile system given in Lemma 4. We now show that given a bitreading gadget from proceeding section corresponding to the regular polygon P ,
we can form an on grid bit-reading gadget (with respect to gα ). In order to show
this, we first show how the individual bit-writers can be grown in an on grid
manner (with the bit reader that reads these writers also on grid), and then we
show how to find positions common to these bit-writers so that up to translation,
the bit writer start and end in the same place. Before we begin our construction,
we introduce a couple of definitions. We denote the location of the center of a
tile P in the complex plane by c(P ). We say that a tile P is x-centered on grid
gα provided that c(P ) = c(P 0 ) and P and P 0 have the same orientation for some
tile P 0 ∈ gα .
At a high-level, we construct a normalized bit-reading gadget from one of the
gadgets presented in Section 6 in the following way. Consider Figures 25 and 26
where normalized bit-reading gadgets are given in the case of heptagonal tiles. In
those figures a bit is written from west to east and read from east to west. When
writing a bit and starting from the southwest-most black tile, assembly proceeds
via attachment of a single tile at a time on some fixed grid gα (shown in the
background in the figures as white heptagons). Then, the blue tiles “shift” off
this grid and onto another grid, gα0 say. This shifting ensures that the tile labeled
R in those figures is on the grid gα . Then, the portion of a bit-reading gadget
which encodes a 0 (Figure 25) or 1 (Figure 26) is assembled. The tiles which
make up this portion are purple in the figures. Call the set of these tiles S. At
this point, we are possibly on a grid gα00 which may or may not be distinct from
gα or gα0 . Finally, we “shift” back onto the grid gα by assembling the remaining
portion of a bit-reading gadget (those tiles of the bit-reading gadget that are not
in S). The tiles which produce this final shift are green in Figures 25 and 26. At
this point, a path of tiles (each of which is on gα ) assemble until the southeastmost black tile in the figures attaches. This bit is read using the orange, red and
yellow tiles. The tile R is on grid gα . The red tiles are the path of unblocked
tiles whose assembly indicates that the appropriate bit is read. The final red tile
that is placed may not be on grid gα . Therefore, the yellow tiles (whose assembly
sequence is essentially that of the red tiles in reverse order) “shift” back onto
grid gα . Note that the black tiles and the end tiles of the reading path of tiles
(the orange, yellow, and red tiles) in Figure 25 have locations that match the
locations of the respective tiles in Figure 26. This ensures that we can “plug”
these gadgets into a zig-zag growth pattern to simulate a Turing machine.
Fig. 25: The completed bit-reading gadget for heptagons when a 0 is “read”.
The grey tiles represent paths which connect the subconfigurations in the bit
writer. The blue tiles represent Cαw , and the dark blue tile represents tww . The
purple tiles represent Cα , and the dark purple tile represents ts . The pink tile
represents tw . The green tiles represent Cαe , and the dark green tile represents
tse . All other color of tiles represent tiles composing the bit reader. In this figure
the bit is written from west to east and read from east to west.
Fig. 26: The completed bit-reading gadget gadget for heptagons when a 1 is
“read”. The grey tiles represent paths which connect the subconfigurations in
the bit writer. The blue tiles represent Cαw , and the dark blue tile represents
tww . The purple tiles represent Cα , and the dark purple tile represents ts . The
pink tile represents tw . The green tiles represent Cαe , and the dark green tile
represents tse . All other color of tiles represent tiles composing the bit reader.
In this figure the bit is written from west to east and read from east to west.
G.1
Constructing On Grid Bit-writer Configurations
The α0 on grid bit writer will consist of three parts which we call: 1) a blocker
subconfiguration, 2) an east shifting subconfiguration and 3) a west shifting
subconfiguration. The three subconfigurations are all formed by modifying a
“base” configuration which we describe now. The base configuration is formed
by modifying the assembly obtained when the bit-reading gadget described in
Section F “reads a 0”.
If the bit-reading gadget for P is simple (e.g. those shown in Figures 20
and 6), we first extend the bit writing portion of the gadget in the following
way. To begin, observe that the bit writer portion of the bit reading gadget will
consist of a tile with negated orientation which we will call B. Note that by the
construction of these simple bit reading gadgets, we can always place a tile which
3k
has standard orientation at a position of ω d 4 e relative to B. After placing this
tile, we continue placing tiles so that we form a path of tiles from B such that
the last tile placed in this path is the northernmost tile in the bit reading gadget
configuration and has standard orientation (see Figure 27b). Next we grow a
path of tiles from B that extends south so that the last tile placed in this path
is the southernmost tile in the bit reading configuration as shown in Figure 27b.
(a) A simple
bit
reading
gadget formed
from a regular
polygon with
10 sides which
has read a 0
(also shown in
Figure 20.
(b) Extending the bit reading gadget to form our base
configuration.
Fig. 27: A simple bit reading gadget (which “read a 0”) and its extension (which
will form our base configuration). The darkly shaded tiles are the bit writer
portion of the bit reading gadget.
We say that the first tile to be placed in the bit-writer subconfiguration of
the bit-reading gadget is the northernmost “end tile” in the path. The other
“end tile” in the path we refer to as the last tile to be placed in the bit-writer
subconfiguration. Also, recall that the tile R in the bit reading gadget is the tile
from which the bit reader grows. To construct the base configuration, we simply
remove the tiles in the configuration which do not lie on either the path from
the first tile in the bit-writer to the tile R or the path from the last tile in the
bit-writer to the tile R. Furthermore, we extend a path from the first tile to be
placed in the bit-writer portion of the bit-reading gadget so that the last tile
placed in this path has negated orientation and is the westernmost tile in the
bit reading gadget configuration. Call this configuration Cα .
Let the tile ts represent the westernmost tile of the set of southernmost tiles
in the bit-writer portion of the configuration Cα . We consider two cases: 1) the
tile ts has negated orientation and 2) the tile ts has standard orientation. In
case 1, we add a tile in standard orientation to the configuration at location
k
−ω b 4 c relative to the tile ts . We know that this is still a valid configuration
by the construction of the bit reading gadgets in the previous section and the
assumption that ts is the westernmost tile of the set of southernmost tiles. Note
that after this modification we are now in case 2. In the case that ts has standard
orientation, we translate Cα so that the tile ts is 1-centered on the grid gα . We
denote the bounding box of Cα by Bα and the dimensions of Bα by mB × nB .
Now, let Cαe be the configuration obtained by taking a copy of Cα and
removing all tiles which do not lie on the shortest path from ts to R. For clarity
we denote the tile ts in Cαe by tse . Translate this configuration so that it has the
following properties: 1) the tile tse is 1-centered on the gird gα , 2) Re(c(tse )) −
Re(c(ts )) ≥ 5, and 3) Im(c(ts )) − Im(c(tse )) ≥ nB .
Define the tile tw to be the westernmost tile of Cα . Translate the configurations Cα and Cαe so that they remain in the same positions relative to each other
and the tile tw is 4-centered on the grid gα . We now make a copy of configuration
Cα , which we call Cαw , and denote the tile tw in Cαw by tww . We translate the
configuration Cαw so that its location meets the following requirements: 1) the
tile tww is 4-centered on the grid gα , 2) Re(c(tw )) − Re(c(tww )) ≥ nB 0 + 5, and
3) Im(c(tw )) − Im(c(tww )) ≥ mB 0 + 5. Call this configuration C 00 .
The blocker subconfiguration consists of a modified version of the configuration Cα . Namely, it consists of the configuration Cα with all the tiles which do
not lie on the minimal path from tw to ts removed. We leave these extra tiles in
the figures in the hopes that it will make the proof of correctness clearer. The east
shifting subconfiguration is given by Cαe and the west shifting subconfiguration
is given by Cαw .
G.2
Connecting the Bit-writer Subconfigurations
Intuitively, we connect the blocker configuration to the east shifting configuration
in the following way. We shift the three configurations so that they remain in
the same positions relative to each other, and the tile ts is 1-centered. Note that
by construction, the tile tse lies at least 5 tiles to the right of ts . Thus, we can
grow an almost straight line of tiles, which all lie on grid, until there is a tile
which lies south of ts in the path. Call this path pse . We then grow a path on
(a) Positioning the configuration αe relative
to the configuration α.
(b) Positioning the configuration αv relative
to the configuration α.
Fig. 28: The three configurations and their positions relative to each other.
grid from the last tile placed in pse that attaches to the southernmost side of
the tile ts . An example of this can be found in Figure 29a.
Similarly, to attach the blocker configuration to the west shifting configuration, we first shift the two unconnected configurations (note there are now only
two unconnected configurations now since the blocker configuration and the east
shifting configuration are now attached) so that they remain in the same positions relative to each other, and the tile tw is 4-centered on the grid. Then we
grow an on grid path of tiles from tn to the west (while keeping the path as
straight as possible) until the path has tiles which lie to the west of tn w at
which time the path turns (while still on grid) and grows south until it attaches
to tn w. An example of this can be found in Figure 29b.
More formally, to connect the configurations Cα to Cαe in the configuration
C 00 , we grow a path in the following manner. The first tile is placed with negated
orientation and 3-centered so that it completely shares a common edge with ts .
We then grow a periodic path of tiles to the south with the tiles in the same
positions and grid locations as the path of tiles in Figure 29a. This repeats until
a 1-centered tile is placed so that it has the same imaginary part as tile tse .
Once this occurs, we grow a periodic path of appropriately positioned tiles to
the east in the same positions and grid locations as the path of east growing
tiles in Figure 29a. We do this until the 2-centered tile completely shares an
edge with the tile tse as shown in Figure 29a. We call this configuration Ce .
To connect the configurations Cα to Cαw in Ce , a path is grown from Cα
to Cαw as follows. First, we shift the configuration Ce so that the tile tw is 4centered. Note that this also means the tile tw w is also 4-centered. We then grow
a periodic path of 1-centered, 2-centered, 6-centered, 4-centered, 1-centered, 3centered, 5-centered, and 4-centered tiles to the west (as shown in Figure 29b)
until a 4-centered tile is placed so that it has the same real part as the tile tww .
Once this occurs, we grow the periodic pattern south shown in Figure 29b until
the 1-centered tile in our path completely shares a common edge with tww . Call
this configuration C 0 .
Now we describe how to grow out “arms” from the bit writer that are on grid
which will allow the bit writers to connect to each other. First, we translate the
configuration C 0 so that the tile R in Cα is 4 centered. Note that this will imply
the R tiles in the configurations Cαe and Cαw are also 4-centered as shown in
Figure 30a. We then place a tile such that it has negated orientation, 3-centered,
and both the southernmost tile and east most tile in the configuration C 0 (call
this tile twb ). Likewise, we also place a tile such that it has standard orientation,
it is 6-centered, and both the southernmost tile and easternmost tile in the
configuration C 0 (call this tile teb ). Next, we place tiles on grid so that a path
of tiles is formed from the R tile in Cαw to the 3-centered tile placed above as
shown in Figure 30b. Similarly, we place tiles on grid so that a path of tiles
is formed from the R tile in Cαe to the 6-centered tile placed above. Call this
configuration C.
(a) Connecting Cαe to Cα .
(b) Connecting Cαw to Cα .
Fig. 29: Connecting the configurations.
(a) Positioning the configurations so that
the R tile is on grid.
(b) Growing the final paths of the bit
writer configuration and removing the nonbit-writer portion of the configuration α. We
refer to this configuration as the α0 bitwriter.
Fig. 30: Completing the bit writer.
We construct α1 in a manner similar to our construction of α0 . The only
difference in our construction of α1 will be that the configuration obtained from
the bit reading gadget “reading a 0” will be used as our base configuration.
G.3
Normalizing Bit-writers
Now that we have constructed on grid bit reading gadgets, we can describe the
construction of normalized bit-writers.
Construction of the normalized bit-writers begins by laying down the configurations Cα0 and Cα1 in the plane so that the tile labeled R in each configuration
(see above for the description of R) lies centered at the same point. Next, we
remove all tiles in the two configurations except for the tiles twb and teb in each
bit writer. We now place two new extremal tiles. The first tile we place should
be both the southernmost and westernmost tile in the configuration as well as
3-centered. Denote this tile tmax w . The location of the second tile’s center should
have the same imaginary part as the location of the center of the tile tmax w . In
addition, this tile, which we denote tmax e should be the easternmost tile in the
configuration. See Figure 32 for an example.
Now, we consider the configuration obtained above with all tiles contributed
by Cα1 removed. We place a connected path of tiles from the tile twb to the tile
tmax w as shown in Figure 33a. Note that this path of tiles is such that none of
the interior points of tiles overlap and every tile is connected to some other tile
in the path by a completely shared edge. Similarly, we place tiles so as to form
a path from the tile teb to the tile tmax w which is also shown in Figure 33a.
These paths of tiles are then attached to configuration Cα0 in the same manner
they are attached to the extremal tiles in the current configuration to form the
configuration for the normalized α0 bit writer (shown in Figure 34a.
We also repeat this same process for the configuration obtained by considering the configuration in Figure 32 with all tiles contributed by Cα0 removed
which yields Figure 33b. After “copying and pasting” these paths, we obtain the
configuration for the normalized α1 bit writer which is shown in Figure 34b.
G.4
Shifting on Grid after the Read
Call the last tile placed by the bit reader T1 . We now describe how the bit
reader shifts back on grid after “reading a bit”. This part of the construction is
very similar to the construction of the on grid bit writers in Section G.1. For our
shifting configuration we will use the configuration obtained by removing all tiles
in the bit reading configuration except for the tiles that lie on the path from the
tile T1 to the tile R (where tiles T1 and R are as described above in Section F.
Without loss of generality, we assume that T1 has standard orientation since if
it is not, we can add one more tile to the path so that the last tile placed in
the bit reader path is in standard orientation. We then construct an on grid bit
reader in a manner similar to the way the on grid bit writers were constructed
in Section G.1.
(a) An example schematic of an α0 bitwriter.
(b) An example schematic of an α1 bitwriter.
Fig. 31: Completing the bit writer.
Fig. 32: The extremal points of the bit writer configurations (lightly shaded) and
the newly created extremal points (darkly shaded).
(a)
(b)
Fig. 33: Growing a path of tiles from the old extremal points to the new ones.
(a)
(b)
Fig. 34: The normalized bit writers.
G.5
Proof of Correctness
To see that the configurations above, are indeed on grid bit reading gadgets
(and thus assemblies) we make three claims: 1) every tile in the configuration
completely shares an edge with another tile in the configuration and the configuration is connected, 2) the interiors of all the tiles in the configurations are
pairwise disjoint, and 3) the beginning and end tiles are on grid as well as the
R tile. After we see that these claims are true, then we can easily give a system
which contains a bit reading gadget.
The first claim follows immediately from our construction. The construction
ensured that every tile placed was next to a pre-existing tile in the assembly and
in the proper orientation. The second claim also follows from the construction
since we were careful to place subconfigurations sufficiently far away from each
other so that there is no overlap and paths can be grown between them without
overlapping.
To see claim 3, observe that the R tiles in all of the subconfigurations lie
in the same position relative to some polyform on the grid (see Figure 30a.
Consequently, once we connect the subconfigurations and shift R so that it is
on grid, all of the R tiles in the subconfigurations are on grid. Thus when the
“arms” of the bit writer are grown, they start and end on grid with respect to
the tile R. Hence, the beginning and end tiles are on grid as well as the R tile.
To see that we can create a system which contains a bit reading gadget using
our normalized bit writers, note that we can grow a path of tiles from the last tile
placed in the normalized bit writer so that it starts the growth of a bit reader at
an appropriate position in relation to the bit writer. Using this notion, Figure 35
shows an example schematic of the complete bit reading gadget which results
from reading a particular bit. The system shown can be constructed by placing
appropriate glues on the tiles so that they come together as shown.
Fig. 35: The complete bit reading gadget reading a particular bit. The arrow in
this picture points to the seed of the system.
H
Technical Appendix
In the following sections we will use this technique for computing the positions
of the centers of polygonal tiles in order to show that the bit gadgets that we
construct are indeed valid bit gadgets.
H.1
Systems with tiles shaped like a single regular polygon
In this section, we present the bit-reading gadgets for tiles shaped like a single
regular polygon and the relevant calculation to show that these bit-reading gadgets are valid. Throughout this section we will use complex number to analyze
configurations of polygonal tiles. This idea is presented in Section 4. Many of
these calculations rely on well known properties of complex numbers and regular polygons. In particular, for a complex number z, we use the equations
2 Re(z) = z + z −1 and 2 Im(z) = z − z −1 . We also apply Euler’s identity
(eiθ = cos (θ)+i sin (θ)) when needed. Moreover, for a regular polygon Pn with n
sides and apothem .5 (which we assume for all of the regular polygons considered
here), the diameter dn of Pn is given by the following equation which will often
be used to show that two polygons do not overlap..
dn =
1
2 cos
π
n
A bit gadget for heptagonal tiles Now that we have a means of computing
the exact positions of the centers of polygonal tiles, we give a bit-reader gadget
that works for heptagonal tiles at temperature-1. Figure 36 gives a depiction of
this bit-reader. Given this bit-reader, the burden of proof is two fold. 1) We must
calculate the distances of the tiles in the bit-reader assembly in order to show
that when a 1 is read, a 0 cannot be read and vice versa, and 2) we must show
that these gadgets assemble in regular (grid-like) positions. In this section we
will handle the first burden of proof, and show the second burden in Section G.
In Figure 36, the gray tiles represent a “written” bit (either 0 or 1), while
the white tiles are “reading” this bit. We ensure that the assembly sequence of a
bit-gadget is such that all of the gray tiles bind before any white tiles. Referring
to Figure 36a, we will first show that the tile labeled R in does not prevent the
binding of the tile labeled T1 or the tile labeled T2 .
Let s denote the center of the tile R, c1 denote the center of T1 , and c2
denote the center of T2 . This is depicted in Figure 37. Then, to calculate c1 and
c2 relative to s, we assume that R is in standard orientation. Following the path
of tiles lying on the dotted line in Figure 37 and summing the appropriate roots
of unity, we obtain the polynomials c1 = ω 6 − ω 3 + ω − ω 4 + 1 − ω 4 + ω − ω 3 +
1 − ω 2 + ω 5 − ω 2 + ω 4 − ω 6 + ω 4 − ω 6 + ω 4 − ω + ω 4 − 1 + ω 3 − ω 6 + ω 2 and
c2 = c1 − ω 6 . By simplifying c1 , we get c1 = 1 + ω − ω 2 − ω 3 + 2ω 4 + ω 5 − 2ω 6 .
First, as multiplying by ω is a rotation by 2π/7, it is enough to show that
Re(ω 2 c1 ) ≥ 1, and to see this, consider the following.
(a) A 0 is read, and a 1 cannot be read by
mistake since the tile B prevents a heptagonal
tile from attaching via the glue labeled g1 .
(b) A 1 is read. This time a 0 cannot be read
by mistake since the tile B prevents growth of
a path of heptagonal tiles that attach via the
glue labeled g0 . Note that some of this path
may form, but B prevents the entire path from
assembling, and thus prevents a 0 from being
read.
Fig. 36: A connected bit-gadget consisting of heptagonal tiles.
Fig. 37: A possible configuration of the bit-reader given in Figure 36. We must
show that the heptagonal tiles centered at c1 and c2 do not overlap the tile
centered at s.
ω 2 c1 = ω 2 + ω 3 − ω 4 − ω 5 + 2ω 6 + ω 7 − 2ω 8
= ω 2 + ω 3 − ω 4 − ω 5 + 2ω 6 + 1 − 2ω
= ω 2 + ω 3 − ω −3 − ω −2 + 2ω 6 + 1 − 2ω −6
= 1 + (ω 2 − ω −2 ) + (ω 3 − ω −3 ) + 2(ω 6 − ω −6 )
Then since (ω 2 − ω −2 ), (ω 3 − ω −3 ), and 2(ω 6 − ω −6 ) are imaginary, we see
Re(ω 2 c1 ) = 1. Therefore, the heptagon with negated orientation centered at c1
and the heptagon in standard orientation centered at s do not overlap. Note that
since Re(ω 2 c1 ) = 1, it may be that these two heptagons partially share an edge,
however, the intersection of their interiors is empty.
To show that the heptagon, Hc2 , with standard orientation centered at c2
and the heptagon, Hs , with negated orientation centered at s do not overlap,
note that c2 = 1 + ω − ω 2 − ω 3 + 2ω 4 + ω 5 − 3ω 6 . Then, one can approximate
|c2 | and observe that |c2 | > 1.11 > cos1 π . Hence the distance from s to c2 is
(7)
greater than twice the diameter of one of these heptagonal tiles. Therefore, Hc2
and Hs do not overlap.
Fig. 38: A possible configuration of the bit-reader given in Figure 36. We must
show that the heptagonal tiles centered at c1 and c2 do not overlap those centered
at b1 and b2 .
Referring to Figure 38, relative to b1 , c1 = −ω + ω 4 − ω + ω 5 − ω 2 + 1 − ω 4 +
ω − ω 4 + ω − ω 6 + ω 2 , and c2 = c1 − ω 6 . Simplifying, c1 = 1 − ω 4 + ω 5 − ω 6 .
To show that a heptagonal tile in negated orientation centered at b1 and a
heptagonal tile in negated orientation centered at c1 do not overlap, it suffices
to show that Re(c1 ) >= 21 + 2 cos1 π . Hence, it is enough to show that Re(c1 ) =
( 7 )
10π
12π
1 − cos 8π
+
cos
−
cos
= 12 + 2 cos1 π . Equivalently, we show 1 −
7
7
7
(7)
10π
12π
1
2 cos 8π
.
To
see this, observe
+
2
cos
−
2
cos
=
7
7
7
cos( π
7)
2 = −2 cos (π)
= − eπi + e−πi
= −eπi − e−πi + e
=e
=e
=e
πi
7
πi
7
− e−πi − e
−πi
7
πi
7
− e−πi − e
13πi
7
πi
7
−e
−πi
9πi
7
−e
−7πi
7
πi
−e 7 +e
+e
−e
−πi
7
−πi
7
− eπi − e
−πi
7
− eπi − e−13 7
+e
+e
−9πi
7πi
−πi
7
πi
7
πi
11πi
7
+e
9πi
−9πi
7
−e
13πi
7
−11πi
−e
−11πi
7
11πi
πi
+ e 7 − e 7 − e 7 + e 7 + e 7 − e 7 − e−13 7
πi
−πi
−8πi
−10πi
−12πi
8πi
10πi
12πi
1−e 7 −e 7 +e 7 +e 7 −e 7 −e 7
= e 7 +e 7
The last equality gives
1−e
8πi
7
−e
−8πi
7
+e
10πi
7
In other words, 1 − 2 cos
+e
8π
7
−10πi
7
−e
+ 2 cos
12πi
7
10π
7
−e
−12πi
7
− 2 cos
=
e
12π
7
2
πi
7
+e
=
−πi
7
1
,
cos( π
7)
which
was what we wanted. Therefore, a heptagonal tile in negated orientation and
centered b1 , and a heptagonal tile in negated orientation and centered at c1 do
not overlap.
From Figure 38, it is now clear that a heptagonal tile in negated orientation
and centered at b1 , and a heptagonal tile in standard orientation and centered
at c2 do not overlap, and that a heptagonal tile in standard orientation and
centered b2 , and a heptagonal tile in standard orientation and centered at c2 do
not overlap.
Fig. 39: A possible configuration of the bit-reader given in Figure 36. We must
show that the heptagonal tile centered at a overlaps the tile centered at b.
Now, referring to Figure 39, we must show that a heptagonal tile, Ha , in
negated orientation and centered a, and a heptagonal tile, Hb , in negated orientation and centered at b overlap. Note that relative to a, b = −ω 4 + ω 6 − ω 3 +
ω − ω4 + 1 − ω4 + ω − ω3 + 1 − ω2 + ω5 − ω2 + ω4 − ω6 + ω4 − ω6 + ω4 − ω +
ω 4 − 1 + ω 3 − ω + ω 4 − ω + ω 4 − 1 + ω 2 − ω 5 + ω − ω 4 + ω. We can simplify b to
obtain b = ω − ω 2 − ω 3 + 2ω 4 − ω 6 . Then we approximate |b| to show that |b| < 1.
Therefore Ha and Hb must overlap. Given these calculations, we can obtain a
bit-reading gadget for systems whose tiles have the shape of a heptagon.
(a) A 0 is read, and a 1 cannot
be read by mistake since the tile
B prevents a octagonal tile from
attaching via the glue labeled g1 .
(b) A 1 is read. This time a 0 cannot be read by mistake since the
tile B prevents growth of a path
of octagonal tiles that attach via
the glue labeled g0 . Note that some
of this path may form, but B prevents the entire path from assembling, and thus prevents a 0 from
being read.
Fig. 40: The configurations for a bit-reading gadget consisting of octagonal tiles.
Octagonal Tile Assembly Figure 40 depicts two possible configurations of a
bit-reading gadget construction for single-shaped systems with octagonal tiles,
the gray tiles represent “bit-writer” tiles (representing either 0 or 1), while the
white tiles are the “bit-reader” tiles. We ensure that the assembly sequence of a
bit-gadget is such that all of the gray tiles bind before any white tiles. Referring
to Figure 40a, we will first show that the tiles labeled R and B do not prevent
the binding of the tile labeled T1 or the tile labeled T2 . Then we will show that
the tile labeled B prevents an octagonal tile from binding to the glue labeled g1 .
When analyzing even sided polygons, note that we can always assume that
each polygonal tile has the standard orientation. Let Tc denote the octagonal
tile centered at c and let Tc1 denote the octagonal tile centered at c1 as shown
2π
in Figure 41. To show that Tc and Tc1 do not overlap, let ω now denote e 8 and
note that relative to c, c1 is given by the following equation.
Fig. 41: A possible configuration of the bit-reader given in Figure 40. We must
show that the octagonal tiles centered at c1 and c2 do not overlap those centered
at b1 and b2 .
c1 = 13ω 7 + ω 5 + 8ω 4 + ω 2 + 2ω 3 + 7ω 2
= 8ω 2 + 2ω 3 + 8ω 4 + ω 5 + 13ω 7
Then, after multiplying by ω we need only show that Im(ωc1 ) ≤ −1. To see
this, note that ωc1 = 8ω 3 + 2ω 4 + 8ω 5 + ω 6 + 13ω 8 . Then, since ω 8 = 1, ω 2 = i,
ω 4 = −1, and ω 3 = ω −5 , we see that ωc1 = 11 + 8(2 Re(ω 3 )) − i, and hence,
Im(ωc1 ) = −1. Therefore, Tc and Tc1 do not overlap.
To show that Tc and Tc2 do not overlap, note that c2 = c1 + ω 2 . Then, after
multiplying c2 by ω we need only show that Re(ωc2 ) ≤ −1. To see that this
inequality holds, consider the following.
Re (ωc2 ) = Re ωc1 + ω 3 = Re 11 − i + 8(2 Re(ω 3 )) + ω 3
√
2
3
= Re 11 + 17 Re(ω ) = 11 − 17
2
1.414
< 11 − 17
< −1
2
Then, since Re(ωc2 ) ≤ −1, we see that Tc and Tc2 do not overlap. Therefore,
Tc does not overlap Tc1 and Tc2 do not overlap. We now show that an octagonal
tile, Tc1 say, with center c1 and an octagonal tile, Tb1 say, with center b1 do
not overlap. It will then also be clear that an octagonal tile with center c1 or
c2 and an octagonal tile with center b1 or b2 do not overlap. To see that Tc1
and Tc1 do not overlap, note that relative to c1 , b1 = 7ω 6 + 2ω 7 + ω 6 + 2ω 4 +
2
+ 1. √
It suffices to
show that Re(b1 ) = −1. Then we see that
3ω 3 + ω + 7ω√
√
Re(b1 ) = 1 + 22 − 3 22 − 2 + 2 22 . Hence, Re(b1 ) = −1, and an octagonal tile
with center c1 and an octagonal tile with center b1 do not overlap.
Now, referring to Figure 42, in remains to be shown that an octagon with
center a and an octagon with center b overlap. That is, an octagonal tile (in an
existing assembly) centered at b prevents the binding of an octagonal tile centered
at a. To see this, note that relative to a, b = 1+13ω 7 +ω 5 +10ω 4 +3ω 3 +ω+7ω 2 +1.
Fig. 42: A configuration of the bit-reader given in Figure 40. We must show that
the octagonal tile centered at a overlaps the tile centered at b.
Simplifying b gives b = 2 + ω + 7ω 2 + 3ω 3 + 10ω 4 + ω 5 + 13ω 7 . Then one can
check that |b| < 1. Given these calculations, we can obtain a bit-reading gadget
for systems whose tiles have the shape of a octagon.
Nonagonal Tile Assembly Figure 43 depicts two possible configurations of a
bit-reading gadget construction for single-shaped systems with nonagonal tiles,
the gray tiles represent a “bit-writer” tiles (representing either 0 or 1), while the
white tiles are the “bit-reader” tiles. We ensure that the assembly sequence of a
bit-gadget is such that all of the gray tiles bind before any white tiles. Referring
to Figure 43a, we will first show that the tiles labeled R and B do not prevent
the binding of the tile labeled T1 or the tile labeled T2 . Then we will show that
the tile labeled B prevents an octagonal tile from binding to the glue labeled g1 .
Referring to Figure 44, let Tc be a nonagonal tile with negated orientation
centered at c and let Tc1 be a nonagonal tile with negated orientation centered
2π
at c1 . We first show that that Tc and Tc1 do not overlap. Let ω now denote e 9 .
Note that relative to c, c1 = −ω 4 + ω 8 − ω 3 + ω 6 − ω 2 + ω 4 − ω 7 + ω 2 − 1 + ω 3 .
Simplifying c1 gives c1 = −1+ω 8 +ω 6 −ω 7 . Then, after multiplying by ω −1 (which
corresponds to rotating the Figure 44 clockwise by 2π
9 ), it suffices to show that
Re(ω −1 c1 ) = − 12 − 2 cos1 π . To see this, first note that ω −1 c1 = ω 5 −ω 6 +ω 7 −ω 8 .
(9)
Therefore, Re ω −1 c1 = cos 10π
− cos 12π
+ cos 14π
− cos 16π
9
9
9
9 . Hence, it
suffices to show that
cos
10π
9
− cos
12π
9
+ cos
14π
9
− cos
To see this, consider the following equations.
16π
9
1
1
=− −
2 2 cos
π
9
.
(a) A 0 is read, and a 1 cannot
be read by mistake since the tile
B prevents a nonagonal tile from
attaching via the glue labeled g1 .
(b) A 1 is read. This time a 0 cannot be read since the tile B prevents growth of a path of nonagonal tiles that attach via the glue
labeled g0 . Note that some of this
path may form, but B prevents the
entire path from assembling, and
thus prevents a 0 from being read.
Fig. 43: The configurations for a bit-reading gadget consisting of nonagonal tiles.
Fig. 44: A possible configuration of the bit-reader given in Figure 43. We must
show that the nonagonal tiles centered at c1 and c2 do not overlap those centered
at c, b1 , and b2 .
−2 = e
=e
=e
πi
9
+ e−
πi
9
πi
9
+ e−
πi
9
πi
9
+e
πi
11πi
9
+ eπi + e−πi − e−
+e
9πi
9
+ e−
9πi
+ e−
9πi
9
−e
11πi
9πi
9
πi
9
−e
13πi
9
17πi
9
− e−
11πi
πi
−e 9
− e−
11πi
9
17πi
9
+e
13πi
15πi
9
+ e−
13πi
9
13πi
−e
15πi
17πi
9
− e−
15πi
15πi
9
17πi
+ e− 9 + e 9 + e− 9 − e 9 − e− 9 + e 9 + e− 9 − e 9 − e− 9
πi
πi
= e 9 + e− 9
10πi
10πi
12πi
12πi
14πi
14πi
16πi
16πi
× 1 + e 9 + e− 9 − e 9 − e− 9 + e 9 + e− 9 − e 9 − e− 9
2
10πi/9
Therefore, − eπi/9 +e
+ e−10πi/9 − e12πi/9 − e−12πi/9 + e14πi/9 +
−πi/9 = 1 + e
iθ
−iθ
e +e
, wecan see that
e−14πi/9 −e16πi/9 −e−16πi/9 . Using the identity
cos(θ) =
2
1
10πi
12πi
14πi
−1 − cos πi = 2 cos 9 − 2 cos 9 + 2 cos 9 − 2 cos 16πi
. Therefore,
9
(9)
Tc and Tc1 do not overlap.
Now we let Tb1 denote a nonagonal tile with negated orientation centered at b1
and show that Tb1 and Tc1 do not overlap. Relative to c1 , b1 = −ω 3 +ω 6 −1+ω 2 .
1
, which we can numerically
It suffices to show that Re(ω −1 b1 ) < − 21 − 2 cos(π/9)
verify is true by approximating each side of the inequality.
Similarly, we let Tb2 denote a nonagonal tile with standard orientation centered at b2 and show that Tb2 and Tc1 do not overlap. Relative to c1 , b2 =
−ω 3 + ω 6 − 1 + ω 2 − ω 7 . Then, it suffices to show that Re(b2 ) = −1. To see this,
note that b2 = −1 − (ω 3 − ω −3 ) + (ω 2 − ω −2 ). Since ω 3 − ω −3 and ω 2 − ω −2 are
imaginary, Re(b2 ) = −1. Therefore, Tc1 and Tb2 do not overlap. Similarly, we
can see that a nonagonal tile centered at c2 that is in standard orientation and
a nonagonal tile centered at b2 that is in standard orientation do not overlap.
Fig. 45: A configuration of the bit-reader given in Figure 43. We must show that
the nonagonal tile centered at a overlaps the tile centered at b.
Now, referring to Figure 45, it remains to be shown that a nonagonal tile,
which we will denote by Ta , centered at a that is in standard orientation and
a nonagonal tile, which we will denote by Tb , centered at b that is in standard
orientation overlap. Relative to a, b = 1 − ω 4 + ω 8 − ω 3 + ω 6 − ω 2 + ω 4 − ω 7 +
ω 2 − 1 + ω 6 − 1 + ω 2 − ω 7 . Simplifying b gives b = −1 + ω 2 − ω 3 + 2ω 6 − 2ω 7 + ω 8 .
Then we can approximate |b| to see that |b| < 1. Therefore, Ta and Tb overlap.
Polygonal Tile Assembly with 10, 11, or 12 Sided Regular Polygonal
Tiles In the cases where tiles consist of regular polygons with 10, 11, or 12
sides, bit-reading gadgets are relatively simple to construct. Figure 46 depicts
the bit-reading gadgets for each case. Note that since each polygonal tile of
these bit-reading gadgets abuts another tile, we need only show that for each
configuration depicted in Figure 46, of the two exposed glues, g0 and g1 of the
tile R, a tile can only attach to one of these glues depending on the position
of the tile B in the figure. In other words, for each configuration depicted in
Figure 46, we show that the intersection of the interiors of a polygon with the
same shape, position and orientation as B and a polygon with the same shape,
position and orientation of the gray tile’s position and orientation.
(a) Bit-reading gadget configuration for
decagonal tiles.
(b) Bit-reading gadget
configuration for hendecagonal tiles.
(c) Bit-reading gadget
configuration for dodecagonal tiles.
Fig. 46: (a), (b) and (c) each depict two configurations of polygonal tiles which
represents either a 0 (bottom) or a 1 (top).
2πi
For decagonal tiles, let ω = e 10 and consider Figure 46a. To show that this
gives a valid bit-reader, we first show that using the top assembly depicted in
the top figure of Figure 46a, a polygon centered at c2 and a polygon centered
at c3 overlap. Note that relative
to c1 , c3 = −1 and c2 = ω 4 + ω 6 . Hence,
4
−4
4
c2 = ω + ω
= 2 Re ω = 2 cos 8π
10 . Then the distance d from c3 to c2
satisfies d = | − 1 − 2 cos 8π
|
<
.62.
10
Secondly, we show that in the bottom figure of Figure 46a, a polygon centered
at c3 and a polygon centered at c4 overlap. Relative to c4 , c3 = ω 9 − 1 +
2
+ cos 18π
+
ω 2 − 1. Hence, c3 = −2 + ω 2 + ω 9 . Then, |c3 | = −2 + cos 4π
10
10
2
4π
18π
sin 10 + sin 10
< .91.
2πi
For hendecagonal tiles, let ω = e 11 and consider Figure 46b. To show
that this gives a valid bit-reader, we first show that using the top assembly
depicted in the top figure of Figure 46b, a polygon centered at c2 and a polygon centered at c3 overlap. Note that relative to c3 , c2 = 1 − ω 10 + ω 6 . Hence,
2
2
12π
12π
+ − sin 20π
< .71
|c2 |2 = 1 − cos 20π
11 + cos 11
11 + sin 11
Secondly, we show that in the bottom figure of Figure 46b, a polygon centered
at c2 and a polygon centered at c1 do not overlap. Relative to c1 , c2 = −1 + ω 2 .
2
1
+ sin2 4π
Then, |c2 |2 = −1 + cos 4π
11
11 > cos( π ) .
11
2πi
For dodecagonal tiles, let ω = e 12 and consider Figure 46c. To show that
this gives a valid bit-reader, we first show that using the top assembly depicted in the top figure of Figure 46c, a polygon centered at c2 and a polygon centered at c3 overlap. Note that relative to c3 , c2 = 1 + ω 5 + ω 7 . Hence,
2
2
14π
14π
|c2 |2 = 1 + cos 10π
+ sin 10π
< .54
12 + cos 12
12 + sin 12
Secondly, we show that in the bottom figure of Figure 46c, a polygon centered
at c2 and a polygon centered at c1 do not overlap. Relative to c1 , c2 = −1 + ω 2 .
Then, it suffices to show that ω 2 c2 = −1. Note that
ω 2 c2 = −ω 2 + ω 4 = ω −4 + ω 4
= 2 Re ω 4 = 2 cos 8π
12
= −1
= 2 cos 2π
3
Tridecagonal Tile Assembly Figure 47 depicts two possible configurations
of a bit-reading gadget construction for single-shaped systems with tridecagonal
tiles, the gray tiles represent a “bit-writer” tiles (representing either 0 or 1),
while the white tiles are the “bit-reader” tiles. We ensure that the assembly
sequence of a bit-gadget is such that all of the gray tiles bind before any white
tiles. Referring to Figure 47a, we will first show that the tiles labeled R and B
do not prevent the binding of the tile labeled T1 or the tile labeled T2 . Then we
will show that the tile labeled B prevents an octagonal tile from binding to the
glue labeled g1 .
2πi
We now refer to Figure 48 and let ω be e 13 . Let Tc denote the tridecagonal
tile with negated orientation centered at c and let Tc1 denote the tridecagonal
tile with negated orientation centered at c1 . To show that Tc and Tc1 do not
overlap, note that relative to c, c1 is given by c1 = −ω 5 + 1 − ω 5 + ω 11 − ω 1 +
ω 11 − ω 2 + ω 5 − ω 12 + ω 5 − ω 12 + ω 6 − ω 9 + ω 2 and c2 = c1 − ω 9 . Simplifying
c1 , we obtain c1 = −2ω 12 + 2ω 11 − ω 9 + ω 6 − ω + 1. Then by approximating |c1 |
we can see that |c1 | > 1.13 > cos 1 π . Therefore, Tc and Tc1 do not overlap.
( 13 )
(a) A 0 is read, and a 1 cannot
be read by mistake since the tile
B prevents a tridecagonal tile from
attaching via the glue labeled g1 .
(b) A 1 is read. This time a 0 cannot be read by mistake since the
tile B prevents growth of a path
of tridecagonal tiles that attach via
the glue labeled g0 . Note that some
of this path may form, but B prevents the entire path from assembling, and thus prevents a 0 from
being read.
Fig. 47: The configurations for a bit-reading gadget consisting of tridecagonal
tiles.
Fig. 48: A possible configuration of the bit-reader given in Figure 47. We must
show that the nonagonal tiles centered at c1 and c2 do not overlap those centered
at c and b.
Now let Tc2 denote the tridecagonal tile with standard orientation centered
at c2 . Since c2 = c1 − ω 9 , we see that c2 = −2ω 12 + 2ω 11 − 2ω 9 + ω 6 − ω + 1.
Then we approximate |c2 | to show that |c2 | > 1.21 > cos 1 π . Therefore, Tc and
( 13 )
Tc2 do not overlap.
Let Tb denote the tridecagonal tile with standard orientation centered at b.
Then, relative to b, c1 = ω 7 −ω 2 +ω 5 −ω 2 +ω 7 −ω 2 +ω 10 −ω 7 +ω−ω 6 +ω 10 −ω 7 +
ω 3 −ω 9 +ω 2 . We can simplify c1 to obtain c1 = 2ω 10 −ω 9 −ω 6 +ω 5 +ω 3 −2ω 2 +ω.
Also note that c2 = c1 − ω 9 .
Then, we approximate |c1 | to show that |c1 | > 1.06 > cos 1 π . Therefore, Tb
( 13 )
1
, and so Tb and
and Tc1 do not overlap. Similarly, |c2 | > 1.04 > 12 + 2 cos(π/13)
Tc1 do not overlap.
Fig. 49: A configuration of the bit-reader given in Figure 47. We must show that
the tridecagonal tile centered at a overlaps the tile centered at b.
Now, referring to Figure 49, it remains to be shown that a tridecagonal tile,
which we will denote by Ta , centered at a that is in standard orientation and a
tridecagonal tile, which we will denote by Tb , centered at b that is in standard
orientation overlap. Relative to b,
a = ω 7 − ω 2 + ω 5 − ω 2 + ω 7 − ω 2 + ω 10 − ω 7 + ω − ω 6 + ω 10 − ω 7 + ω 3 − ω 6 + ω 12 − ω 5
+ ω 12 − ω 5 + ω 2 − ω 11 + ω − ω 11 + ω 5 − 1 + ω 5 − ω 12
= −1 + 2ω − 2ω 2 + ω 3 + ω 5 − 2ω 6 + 2ω 10 − 2ω 11 + ω 12
Then we can approximate |a| to see that |a| < 1. Therefore, Ta and Tb overlap.
Tetradecagonal Tile Assembly Figure 50 depicts two possible configurations
of a bit-reading gadget construction for single-shaped systems with tetradecagonal tiles, the gray tiles represent a “bit-writer” tiles (representing either 0 or
1), while the white tiles are the “bit-reader” tiles. We ensure that the assembly
(a) A 0 is read, and a 1 cannot be
read by mistake since the tile B
prevents a tetradecagonal tile from
attaching via the glue labeled g1 .
(b) A 1 is read. This time a 0 cannot be read by mistake since the
tile B prevents growth of a path of
tetradecagonal tiles that attach via
the glue labeled g0 . Note that some
of this path may form, but B prevents the entire path from assembling, and thus prevents a 0 from
being read.
Fig. 50: The configurations for a bit-reading gadget consisting of tetradecagonal
tiles.
sequence of a bit-gadget is such that all of the gray tiles bind before any white
tiles. Referring to Figure 50a, we will first show that the tiles labeled R and B
do not prevent the binding of the tile labeled T1 or the tile labeled T2 . Then we
will show that the tile labeled B prevents an octagonal tile from binding to the
glue labeled g1 .
2πi
We now refer to Figure 51 and let ω be e 13 . Let Tc , Tc1 , Tc2 , Tb1 , and Tb2
denote the tridecagonal tile with standard orientation centered at c, c1 , c2 , b1 ,
and b2 respectively. Then, to show that Tc and Tc1 do not overlap, note that
relative to c, c1 is given by c1 = c1 = 3ω 12 + ω 10 + ω 8 + ω 6 + 2ω 5 + ω 2 . Then by
approximating |c1 | we can see that |c1 | > 1.2 > cos 1 π . Therefore, Tc and Tc1
( 14 )
do not overlap. Moreover, c2 = c1 + ω 4 . Then, consider the following.
c2 = 3ω 12 + ω 10 + ω 8 + ω 6 + 2ω 5 + ω 4 + ω 2
= (2ω 12 + 2ω 5 ) + (ω 12 + ω 10 + ω 8 + ω 6 + ω 4 + ω 2 )
= (2ω
12
12
− 2ω ) + (ω
12
+ω
10
8
6
4
2
+ ω + ω + ω + ω + 1 − 1)
(1)
(2)
= −1
Equation (1) follows from the following equalities that
ω 5 = e(
10πi
14
14πi
24πi
) = −e( 10πi
14 + 14 ) = −e( 14 ) = −ω 12 .
Equation (2) follows from the fact that ω 12 +ω 10 +ω 8 +ω 6 +ω 4 +ω 2 +1 = 0. To see
this, note that ω 12 +ω 10 +ω 8 +ω 6 +ω 4 +ω 2 +1 = ω 2 ω 12 + ω 10 + ω 8 + ω 6 + ω 4 + ω 2 + 1 ,
Fig. 51: A possible configuration of the bit-reader given in Figure 50. We must
show that the nonagonal tiles centered at c1 and c2 do not overlap those centered
at c, b1 and b2 .
and so,
(ω 2 − 1) ω 12 + ω 10 + ω 8 + ω 6 + ω 4 + ω 2 + 1 = 0.
Then, since ω 2 − 1 6= 0, it follows that ω 12 + ω 10 + ω 8 + ω 6 + ω 4 + ω 2 + 1 = 0.
Therefore, Tc and Tc2 do not overlap.
Now, to show that Tb1 does not overlap Tc1 or Tc2 , note that relative to
b1 , c1 = −1 + 2ω 9 + 2ω 12 + ω 13 + 2ω + 2ω 5 + ω 2 . Simplifying c1 , we obtain
c1 = −1 + ω 9 + ω 13 + 2ω. Then we can approximate |c1 | to see that |c1 | > 1.1 >
1
1
cos(π/14) . Similarly, relative to b1 , |c2 | > 1.06 > cos(π/14) . Therefore, Tb1 does
not overlap Tc1 or Tc2 . This also shows that Tb2 and Tc2 do not overlap since
relative to b2 , c2 = −ω 4 + c1 + ω 4 .
Now, referring to Figure 52, it remains to be shown that a tetradecagonal tile,
which we will denote by Ta , centered at a that is in standard orientation and a
tetradecagonal tile, which we will denote by Tb , centered at b that is in standard
orientation overlap. Relative to b, a = −1 + 2ω 9 + 2ω 12 + ω 13 + 2ω + ω 13 + ω +
2ω 5 +ω 3 +ω 5 +ω 8 . Simplifying a, we see a = −1+3ω +ω 3 +ω 5 +ω 8 +2ω 9 +2ω 13 .
Then we can approximate |a| to see that |a| < 1. Therefore, Ta and Tb overlap.
Polygonal Tile Assembly with Regular Polygonal Tiles with 15 or
More Sides In the cases where tiles consist of regular polygons with 15 or
more sides, we give a general scheme for obtaining bit-reading gadgets for each
case. Figure 53 depicts the bit-reading gadgets for each case. Note that since
each polygonal tile of these bit-reading gadgets abuts another tile, we need only
show that for each configuration depicted in Figure 53, of the two exposed glues,
g0 and g1 of the tile R, a tile can only attach to one of these glues depending
on the position of the tile B in the figure. In other words, for each configuration
depicted in Figure 53, we show that the intersection of the interiors of a polygon
Fig. 52: A configuration of the bit-reader given in Figure 50. We must show that
the tetradecagonal tile centered at a overlaps the tile centered at b.
with the same shape, position and orientation as B and a polygon with the same
shape, position and orientation of the gray tile’s position and orientation.
Now, consider a polygon Pn with n ≥ 15 sides and let ω be the nth root of
2πi
unity e n . Then, the general scheme for constructing a bit-reading gadget falls
into two cases. First, if n is odd (the cases where n is even are similar), relative
to a tile with negated orientation (the polygon labeled R in the configurations
in Figure 53), the two configurations that give rise to the bit-reading gadget are
as follows. Let k be such that n = 2k + 1 (n = 2k if n is even). To “read” a 1, the
configuration is obtained by centering a blocker tile with negated orientation,
labeled B in the top configurations of Figure 53, at −ω n−1 + ω k+1 (whether n
is even or odd). Then R exposes two glues g1 and g0 such that if a tile binds
to g1 , it will have standard orientation and be centered at −ω n−1 (whether n
is even or odd) and if a tile that binds to g0 , it will have standard orientation
and be centered at −1. We will show that B will prevent this tile from binding.
This gives the configuration depicted in the top figures of Figure 53. Similarly, to
“read” a 0, the configuration is obtained by centering a blocker tile with negated
orientation, labeled B in the bottom configuration of Figure 53a, at −1 + ω k−1
(−1 + ω k−2 if n is even) relative to R. In this case, we will show that B prevents
a tile from binding to g1 . In addition, we place a glue on the tile that binds to g0
k−1
that allows for another tile to bind to it so that its center is at c2 = −1 + ω b 2 c
k−2
(c2 = −1+ω 2 if n is even). This gives the configuration depicted in the bottom
figures of Figure 53a and Figure 53c. Moreover, we show that neither R nor B
prevent the binding of this tile.
In order to perform the calculations used to show the correctness of these
bit-reading gadgets, we consider the cases where n is even and where n is odd.
(a) Bit-reading gadget
configuration for pentadecagonal tiles.
(b) Bit-reading gadget
configuration for hexadecagonal tiles.
(c) Bit-reading gadget
configuration for heptadecagonal tiles.
Fig. 53: (a), (b) and (c) each depict two configurations of polygonal tiles which
represents either a 0 (bottom) or a 1 (top).
Case 1: (n is odd) Suppose that n = 2k + 1 for some k. To show that a
polygon centered at c1 and a polygon centered at c2 do not overlap, consider the
k−1
case where k is odd. Note that relative to c0 , c1 = 1 and c2 = ω 2 . Then the
distance dn from c1 to c2 satisfies the following equation.
d2n
=
1 − cos
(k − 1) π
n
2
+ sin
2
(k − 1) π
n
3π
2
Substituting k = n−1
2 for k and simplifying, we obtain dn = 2 + 2 sin 2n . Now
to show that a polygon centered at c1 and a polygon centered at c2 do not overlap, we show that d2n > cos21 π for n ≥ 15. To see this, note that cos2 nπ d2n =
(n)
3π
3π
2 cos2 nπ 1 + sin 2n
. Then for n ≥ 15, 2 cos2 nπ 1 + sin 2n
> 2 cos2 π4 =
1.
It then follows that dn > cos1 π , and therefore dn is greater than twice the
(n)
circumradius of our polygons. Hence, a polygon centered at c1 and a polygon
centered at c2 do not overlap.
In the case where k is even, let m be such that k = 2m. Then relative to c0 ,
c1 = 1 and c2 = ω m−1 . In this case, dn satisfies the following equation.
d2n
2
(2m − 2) π
(2m − 2) π
2
+ sin
= 1 − cos
n
n
5π
2
Substituting m = k2 for m and k = n−1
2 for k we obtain dn = 2 + 2 sin 2n . Now
to show that a polygon centered at c1 and a polygon centered at c2 do not overlap, we show that d2n > cos21 π for n ≥ 15. To see this, note that cos2 nπ d2n =
(n)
5π
5π
2 cos2 nπ 1 + sin 2n
. Then for n ≥ 15, 2 cos2 nπ 1 + sin 2n
> 2 cos2 π4 =
1.
It then follows in the case where k is even, dn > cos1 π , and therefore dn is
(n)
greater than twice the circumradius of our polygons. Hence, a polygon centered
at c1 and a polygon centered at c2 do not overlap.
Now, to show that a polygon centered at c3 and a polygon centered at c4
overlap, note that relative to c1 , c3 = −1 + ω k−1 and c4 = −ω n−1 . Therefore,
the distance dn from c3 to c4 is satisfies the following equation.
2
2(n − 1)π
2(k − 1)π
2
+ cos
dn = −1 + cos
n
n
2
2(k − 1)π
2(n − 1)π
+ sin
+ sin
n
n
Substituting k =
n−1
2
for k and simplifying, we obtain,
π π d2n = 1 + 2 2 sin2
1 − 2 cos
n
n
. Note that for each n > 2, d2n < 1. To see this, it suffices to show that
π π 2 sin2
1 − 2 cos
<0
n
n
. This follows from the fact that 2 sin2 nπ > 0 and 1 − 2 cos nπ < 0 for n > 2.
Now, since for each n > 2, d2n < 1, we see that dn < 1. Since the length of
the apothem for each tile is assumed to be 12 , we can conclude that a polygon
centered at c3 and a polygon centered at c4 must overlap.
Case 2: (n is even) Let k be such that n = 2k. Then, relative to c0 , c1 = 1
k−2
and c2 = ω b 2 c . Then the distance, dn say, from c1 to c2 satisfies the following
equation
2
(k − 2) π
(k − 2) π
dn = 1 − cos
+ sin2
n
n
.
Substituting k = n2 for k and simplifying, we obtain d2n = 2 + 2 sin 2π
n . To
show that c0 and c1 do not overlap, it suffices to show that d2n > cos21 π . To
(n)
2
2π
2 π
2 π
see this, note that cos
d
=
2
cos
1
+
sin
.
Then
for
n
≥ 16,
n
n
n n 2 π 2 cos2 nπ 1 + sin 2π
>
2
cos
=
1.
n
4
As in the case where n is odd, it then follows that in the case where n is
even, dn > cos1 π , and therefore dn is greater than twice the circumradius of
(n)
our polygons. Hence, a polygon centered at c1 and a polygon centered at c2 do
not overlap.
Now, to show that a polygon centered at c3 and a polygon centered at c4
overlap, note that relative to c1 , c3 = −1 + ω k−2 and c4 = −ω n−1 . Therefore,
the distance dn from c3 to c4 is satisfies the following equation.
d2n =
2
2(k − 2)π
2(n − 1)π
+ cos
n
n
2
2(k − 2)π
2(n − 1)π
+ sin
+ sin
n
n
−1 + cos
Substituting k = n2 for k and simplifying, we obtain, d2n = 1−8 sin2 nπ cos 2π
.
n
Note that for eachn ≥ 16, d2n < 1. To see this, it suffices to show that
< 0. This follows from the fact that 8 sin2 nπ > 0 and
−8 sin2 nπ cos 2π
n
cos 2π
> 0 for n > 16.
n
Now, since for each n ≥ 16, d2n < 1, we see that dn < 1. Since the length of
the apothem for each tile is assumed to be 12 , we can conclude that a polygon
centered at c3 and a polygon centered at c4 must overlap.
H.2
2-shaped systems with regular polygonal tiles
The following figures give configurations for normalized on-grid bit-reading gadgets that can be used to obtain bit-reading assemblies for 2-shaped systems
where the tiles of the system have the shape of two different regular polygons.
Note that the grid construction techniques from Section 5 can be used to obtain
the grids shown using dashed lines in the figures below.
(a)
(b)
Table 1: Configurations for normalized on-grid bit-reading gadgets that can be
used for 2-shaped systems using whose tiles have the shape of a regular triangle
and a regular pentagon. (a) represents a 0, and (b) represents a 1.
(a)
(b)
Table 2: Configurations for normalized on-grid bit-reading gadgets that can be
used for 2-shaped systems using whose tiles have the shape of a regular triangle
and a regular hexagon. (a) represents a 0, and (b) represents a 1.
(a)
(b)
Table 3: Configurations of for normalized on-grid bit-reading gadgets that can
be used for 2-shaped systems using whose tiles have the shape of a square and
a regular pentagon. (a) represents a 0, and (b) represents a 1.
(d)
(e)
Table 4: Configurations for normalized on-grid bit-reading gadgets that can be
used for 2-shaped systems using whose tiles have the shape of a square and a
regular hexagon. (a) represents a 0, and (b) represents a 1.
Fig. 54: Bit-reading gadget configuration for tiles with the shape of either a
pentagon or a hexagon. This figure depicts a configuration of polygonal tiles
which represents a 0, while Figure 55 depicts a configuration of polygonal tiles
which represents a 1.
Fig. 55: This figure depicts a configuration of polygonal tiles with the shape of
either a pentagon or a hexagon which represents a 0.
H.3
Single shaped systems with equilateral polygonal tiles
(a)
(c)
(b)
(d)
Table 5: Configurations of for normalized on-grid bit-reading gadgets that can
be used for 1-shaped systems using whose tiles have the shape of a particular
equilateral pentagon ((a) and (b)) or a particular equilateral hexagon ((c) and
(d)).