Design of Low Power Voltage Regulator
for RFID Applications
Josip Mikulić, Niko Bako. Adrijan Barić
1
University of Zagreb, Faculty of Electrical Engineering and Computing, Croatia
1
Abstract
This paper proposes the circuit of a low power onchip voltage regulator. The LDO (low-dropout) voltage regulator
is designed in the UMC 0.18 urn CMOS technology by
using reverse nested Miller compensation (RNMC). The
regulator provides an output DC voltage of 1.455 V with
the load capability of 500 µA and the total quiescent current consumption of less than 4 µA. The line and load
regulation are 1.25 mV/V and 1.08 mV/mA at 500 µA,
respectively. The designed regulator is capable of operating in the temperature range from -20oC to 60oC and it is
specially suitable for RFID applications.
Post-Layout Simulation Results
Loop Gain AC Response
Simulated loop gain with parameter IL
• IL: 0 to 500 µA (log steps)
• VDD : 1.6 V
• GBW: 100 kHz
• PM > 75 deg
Experimental Results
Microphotograph of chip and measurement set-up are presented in figures. The following measurement results are
obtain:
• VOU T =1.49 V, ∆V =60 mV, IQ=4.2 µA,
LiR=3.5 mV/V, LoR=2.4 mV/mA @ 500 µA,
PSRR: -49 dB @ DC and -16 dB @ 1 MHz
Introduction
Cutting-edge low-power RFID solutions are completely onchip. This poses great challenge on design of RFID system
components. In this work the design of voltage regulator is
presented which fulfills the important requirements related
to low-power, scalability to low voltages, full compensation, low cost production, etc.
Poles and Zeros
Voltage Regulator Design
RNMC (Reverse Nested Miller Compensation) error amplifier. Suitable for driving large capacitive loads with low
power.
• 1st stage: differential amplifier
• 2nd stage: common source
• 3rd stage: pass device
• Dominant pole: 0.05 kHz
• Nondominant complex poles (320 kHz to 1.5 MHz)
• Negative zero: 500 kHz
Transient Measurements
Measured transient response of the output voltage VOU T
to the step load current IL from 0 to 500 µA in 100 ns.
Performance Comparison
LDO voltage regulator designed in 0.18 µm CMOS technology. Biasing network and power enabling circuitry not
shown.
Designed topology offers a good line and load regulation
capabilities, together with a relatively fast transient for
the invested power.
PSRR - Power Supply Rejection Ratio
Simulated PSRR with the load current IL as a parameter
• IL: 0 to 500 µA (log steps)
Layout of the designed voltage regulator.
• Area: 0.065 mm × 0.085 mm = 0.0055 mm2
• Output capacitor CL (not shown) 0.0129 mm2
• VDD : 1.8 V
• Low frequencies: -80 dB
• Mid frequencies:
• worse for larger load currents
• influenced by the output resistance of the pass device
• High frequencies:
• Converges to the ratio of CL and CDS of the pass device
Conclusion
The topology based on reverse nested Miller compensation for on-chip voltage regulators, scalable to ultra low
power and voltage is proposed. It provides the solution for
handling large on-chip capacitive loads with low power and
guaranteed stability. Intended for RFID applications, the
LDO voltage regulator is designed in the UMC 0.18 µm
CMOS technology with the total quiescent current consumption of only 3.7 fA. It provides the output voltage of
1.455 V with the maximum load current of 500 fA and
exhibits good performance for temperature range from
-20 oC to 60 oC.