STA530
4 X 50W STEREO
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MONOCHIP BRIDGE QUAD CONFIGURABLE
AMPLIFIER OPTIMIZED FOR BASH®
ARCHITECTURE
4 X 50W OUTPUT POWER @ RL = 8 Ω,
THD = 10% or (2 x 50W @ 8 Ω + 1 x 100W @
4Ω) or (2 x 100W @ 4 Ω)
PRECISION RECTIFIERS TO DRIVE THE
BUCK REGULATOR
ON-OFF SEQUENCE/ TIMER WITH MUTE
AND STANDBY
PROPORTIONAL OVER POWER OUTPUT
CURRENT TO LIMIT THE BUCK REGULATOR
ABSOLUTE POWER BRIDGE OUTPUT
TRANSISTOR POWER PROTECTION
ABSOLUTE OUTPUT CURRENT LIMIT
INTEGRATED THERMAL PROTECTION
POWER SUPPLY OVER VOLTAGE
BLOCK DIAGRAM
GND
+VS
-VS
CD-1&2
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DESCRIPTION
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The STA530 is a BASH® power amplifier where
BASH® means “High Efficiency”.
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-
TURN-ON/OFF
SEQUENCE
CD+3&4
OUT3+
+10
-1
PROTECTION
OUT3-
OUTPUT BRIDGE
CD-3&4
+10
OUT4+
SOA
DETECTOR
+10
-1
-1
OUTPUT BRIDGE
OUT4-
OUTPUT BRIDGE
TRK_2/PAR1&2
ABSOLUTE
VALUE
BLOCK
ABSOLUTE
VALUE
BLOCK
TRK_4/PAR3&4
TRK_1
ABSOLUTE
VALUE
BLOCK
ABSOLUTE
VALUE
BLOCK
TRK_3
PWR_INP2
July 2003
■
CONFIG.
OUT2+
OUT2-
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PROTECTION
FLEXIWATT POWER PACKAGE WITH 27 PIN
BASH® LICENCE REQUIRED
OUTPUT BRIDGE
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PROT
(t s)
+10
OUT1-
FLEXIWATT27
PWR_INP1 STBY/MUTE PWR_INP3
CD+1&2
OUT1+
POWER AMPLIFIER
TRK_OUT
PWR_INP4
D02AU1344
1/17
STA530
DESCRIPTION (continued)
In fact it's permits to build a BASH® architecture amplifier adding only few external components and a variable
Buck regulator tracking the audio signal. Notice that normally only one Buck regulator is used to supply a multichannel amplifiers system , therefore most of the functions implemented in the circuit have a summing output
pin.
The signal circuits are biased by fixed negative and positive voltages referred to Ground. Instead the final stages of the output amplifiers are supplied by two external voltages that are following the audio signal . In this way
the headroom for the output transistors is kept at minimum level to obtain a high efficiency power amplifier.
The circuit contains all the blocks to build a configurable four channel amplifier.
The tracking signal for the external Buck regulator is generated from the Absolute Value Block (AVB) that rectifies the audio signal. The outputs of these blocks are decoupled by a diode to permit an easy sum of this signal
for the multichannel application. The gain of the stage AVB is equal to 70 (+36.9 dB). A sophisticated circuit
performs the output transistor power detector that , with the buck regulator, reduces the power supply voltage .
Moreover, a maximum current output limiting and the over temperature sensor have been added to protect the
circuit itself. The external voltage applied to the STBY/MUTE pin forces the two amplifiers in the proper condition to guarantee a silent turn-on and turn-off.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
uc
Value
+Vs
Positive supply voltage referred to pin 14 (GND)
-Vs
Negative supply voltage referred to pin 14 (GND)
od
27
Pr
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Unit
V
-27
V
20
V
-0.3
V
-20
V
Pin 11, 10, 9, 8 Negative & Positive maximum voltage referred to
GND (pin 14)
-25 to +25
V
VPWR_Imp 3 Pin 17, 18, 19, 20 Negative & Positive maximum voltage referred
VPWR_Imp 4 to GND (pin 14)
VTRK_3
VTRK_4
-25 to +25
V
Pin 12 maximum input current (Internal voltage clamp at 5V)
500
µA
Pin 12 negative maximum voltage referred to GND (pin 14)
-0.5
V
Value
Unit
150
°C
1
°C/W
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VCD+
Positive supply voltage tracking rail referred to pin 14 (GND)
VCD-
Negative supply voltage referred to -Vs (1)
VCD-
Negative supply voltage tracking rail referred to pin 14 (GND)
VPWR_Imp1
VPWR_Imp2
VTRK_1
VTRK_2
)
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ISTBY-max
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VSTBY/
MUTE
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Notes: 1. VCD- must not be more negative than -Vs
THERMAL DATA
Symbol
Tj
Parameter
Max Junction temperature
Rth j_case Thermal Resistance Junction to case .............................. ..max
2/17
STA530
OPERATING RANGE
Symbol
Parameter
Value
Unit
+Vs
Positive supply voltage
+15 to +25
V
-Vs
Negative supply voltage
-15 to -25
V
5V ≤ (Vs+ - VCD+) ≤ 10V
V
∆Vs+
Delta positive supply voltage
VCD+
Positive supply voltage tracking rail
+3 to +15
V
VCD-
Negative supply voltage tracking rail
-15 to -3
V
Tamb
Ambient Temperature Range
0 to 70
°C
200
µA
Pin 12 maximum input current (Internal voltage clamp at 5V)
PIN CONNECTION
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Out3-
Out3+
CD-3&4
CD+3&4
Out4-
Out4+
TRK_4/Par3&4
27
TRK_3
PWR_Inp4
PROT
PWR_Inp3
+Vs
Gnd
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TRK_Out
PWR_Inp1
STBY/MUTE
TRK_1
(t s)
PWR_Inp2
Out2-
Out2+
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TRK_2/Par1&2
bs
CD-1&2
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CD+1&2
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Out1-
Out1+
-Vs
1
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-Vs
Isb_max
D02AU1352
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NOTE
Slug connected to PINs No. 1 & 27
3/17
STA530
PIN CONNECTION
N°
Name
1
-Vs
2
Out1+
Channel 1 speaker positive output
3
Out1-
Channel 1 speaker negative output
4
CD+1&2
Channels 1 & 2 Time varying tracking rail positive power supply
5
CD-1&2
Channels 1 &2 Time varying tracking rail negative power supply
6
Out2-
Channel 2 speaker negative output
7
Out2+
Channel 2 speaker positive output
8
TRK_2/
Par1&2
Absolute value block input for channel 2,and parallel command for channels 1&2
9
TRK_1
Absolute value block input for channel 1
10
PWR_Inp2
Input to channel 2 power stage
11
PWR_Inp1
Input to channel 1 power stage
12
STBY/MUTE
13
TRK_Out
14
Gnd
Analog Ground
15
+Vs
Positive Bias Supply
16
PROT
17
PWR_Inp3
Input to channel 3 power stage
18
PWR_Inp4
Input to channel 4 power stage
19
TRK_3
Absolute value block input for channel 3
20
TRK_4/
Par3&4
Absolute value block input for channel 4,and parallel command for channels 3&4
21
Out4+
Channel 4 speaker positive output
22
Out4-
Channel 4 speaker negative output
24
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4/17
Negative Bias Supply
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Standby/mute input voltage control
Absolute value block output
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Channel Protection signal for STABP01
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CD-3&4
Channels 3 & 4 Time varying tracking rail negative power supply
CD+3&4
Channels 3 & 4 Time varying tracking rail positive power supply
Out3-
Channel 3 speaker negative output
26
Out3+
Channel 3 speaker positive output
27
-Vs
Negative Bias Supply
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Description
STA530
ELECTRICAL CHARACTERISTCS (Test Condition: Vs+ = 25V, Vs- = -25V, V CD+ = 15V, VCD- = -15V, RL =
8Ω, external components at the nominal value f = 1KHz, Tamb = 25°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
66
70
74
VTRK_out Tracking ref. output voltage
0
15
V
ITRK_out Current capability
5
6
mA
1
MΩ
100
mV
TRACKING PARAMETERS
GTRK
Tracking reference voltage gain
ZTRK_in
Input impedance (TRK1/2)
VOFFSET Output traking DC offset
OUTPUT BRIDGE
Gout
Half Output bridge gain
19
20
21
dB
Gch
Output bridge differential gain
25
26
27
dB
∆Gch
Output bridges gain mismatch
-1
1
dB
Pout
Continuous Output Power
THD = 1%
THD = 10%
THD = 10% RL = 4Ω
VCD+ = 11V, VCD- = -11V
THD = 1% RL = 4Ω
Continuous Output Power
Pout
THD
Total harmonic distortion of the
output bridge
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Po = 5W
Pr
so
THD = 10% RL = 4Ω
2 ch par
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50
Output bridge D.C. offset
EN
Noise at Output bridge pins
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Zbr_in
Input impedance
78
W
100
W
Rdson
Output power Rdson
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RdsonMAX Maximum Output power Rdson
OLG
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GB
O
SR
-100
IO = 1A
0.1
%
0.2
%
100
mV
µV
60
100
Tj=25o C
IO = 1A
W
W
0.01
f = 20Hz to 20KHz; Rg = 50Ω
W
40
f = 20Hz to 20KHz; Po = 20W
VOff
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140
180
KΩ
400
500
mΩ
800
mΩ
100
dB
Unity Gain Bandwidth
6
MHz
Slew Rate
8
V/µs
Open Loop Voltage Gain
PROTECTION
VSTBY
Stby voltage range
0
0.8
V
VMUTE
Mute voltage range
1.6
2.5
V
VPLAY
Play voltage range
4
5
V
Th1
First Over temperature threshold
130
°C
5/17
STA530
ELECTRICAL CHARACTERISTCS (continued)
Symbol
Parameter
Th2
Second Over temperature
threshold
Unbal.
Ground
Upper Unbalancing ground
threshold
Unbal.
Ground
Test Condition
Min.
Typ.
Max.
Unit
150
°C
Referred to (CD+ - CD-)/2
5
V
Lower Unbalancing ground
threshold
Referred to (CD+ - CD-)/2
-5
V
Under voltage threshold
|Vs+| + |Vs-|
18
Pd_reg.
Power dissipation threshold for
system regulation
Iprot = 50µA; @ Vds = 8V
18
Pd_max
Switch off power dissipation
threshold
@ Vds = 8V
30
Iprot Pd
Protection current slope
for Pd > Pdreg
400
Iprot Id
Protection current slope
for Id > Idreg
400
UVth
Ilct s
Limiting Current threshold “soft”
Ilct h
Limiting Current threshold “hard”
I+Vs
Positive supply current
Stby (Vstby/mute pin = 0V)
Mute (Vstby/mute pin = 2.5V)
Play (Vstby/mute pin = 5V no signal)
I-Vs
Negative supply current
ICD+
Positive traking rail supply current
ICD-
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µA/W
uc
5
µA/A
5
A
5.5
A
mA
mA
mA
Stby (Vstby/mute pin = 0V)
Mute (Vstby/mute pin = 2.5V)
Play (Vstby/mute pin = 5V no signal)
6
29
33
mA
mA
mA
Stby (Vstby/mute pin = 0V)
Mute (Vstby/mute pin = 2.5V)
Play (Vstby/mute pin = 5V no signal)
200
85
85
µA
mA
mA
Negative traking rail supply current Stby (Vstby/mute pin = 0V)
Mute (Vstby/mute pin = 2.5V)
Play (Vstby/mute pin = 5V no signal)
200
85
85
µA
mA
mA
)
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4.5
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4.5
V
5
TBD
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4
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STA530
FUNCTIONAL DESCRIPTION
The circuit contains all the blocks to build a configurable four channel amplifier.
In fact, only driving properly the TRK_2 (and TRK_4) pins, it’s possible to change the chip configuration:
– 50 Watt x 4
– 50 Watt x 2 + 100 Watt x1 (TRK_2/Par1&2 or TRK_4/Par3&4 at -Vs)
– 100 Watt x 2 (TRK_2/Par1&2 and TRK_4/Par3&4 at -Vs)
Each single channel is based on the Output Bridge Power Amplifier, and its protection circuit. Moreover, a signal rectifier are added to complete the circuit.
The operation modes are driven by The Turn-on/off sequence block. In fact the IC can be set in three states by
the Stby/mute pin:
STANDBY ( Vpin < 0.8V), MUTE (1.6V < Vpin < 2.5V), and PLAY (Vpin > 4V).
In the Standby mode all the circuits involved in the signal path are uninhabited, instead
in Mute mode the circuits are biased but the Speakers Outputs are forced to ground potential.
These voltages can be get by the external RC network connected to Stby/Mute pin.
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The same block is used to force quickly the I.C. In standby mode or in mute mode when the I.C. dangerous
condition has been detected. The RC network in these cases is used to delay the Normal operation restore.
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The protection of the I.C. are implemented by the Over Temperature, Unbalance Ground, Output Short circuit,
Under voltage, and output transistor Power sensing as shown in the following table:
Table 1. Protection Implementation
Fault Type
Condition
Protection strategy
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Action time
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Chip Over
temperature
Tj > 130 °C
Mute
Chip Over
temperature
Tj > 150 °C
Standby
Fast
Slow, Related to
Turn_on sequence
Unbalancing
Ground
|Vgnd| > ((CD+) (CD-))/2 + 5V
Standby
Fast
Slow, Related to
Turn_on sequence
Over Current
Iout > 4.5A
Reducing Buck
regulator output
voltage.
Related to the Buck
regulator
Related to the Buck
regulator
Short circuit
Iout > 5A
Standby
Fast
Slow, related to
Turn_on sequence
|Vs+| + |Vs-|< 20V
Standby
Fast
Slow, related to
Turn_on sequence
Extra power
dissipation
at output transistor
Pd tr. > 18W
Reducing Buck
regulator output
voltage.
Related to the Buck
regulator
Related to the Buck
regulator
Maximum power
dissipation
at output transistor
Pd tr. > 30W
Standby
Fast
Slow, related to
Turn_on sequence
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Under Voltage
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(t s)
Fast
Release time
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Slow Related to
Turn_on sequence
ABSOLUTE VALUE BLOCK
The absolute value block rectifies the signal to extract the control voltage for the external Buck regulator. The
output voltage swing is internally limited, the gain is internally fixed to 70.
The input impedance of the rectifier is very high , to allow the appropriate filtering of the audio signal before the
rectification.
7/17
STA530
OUTPUT BRIDGE
The Output bridge amplifier makes the single-ended to Differential conversion of the Audio signal using two
power amplifiers, one in non-inverting configuration with gain equal to 10 and the other in inverting configuration
with unity gain. To guarantee the high input impedance at the input pins, PWR_Inp1....4, the second amplifier
stages are driven by the output of the first stages respectively.
In 60W x2 channel configuration the "slave" inputs (INPUT 2/4) must be connected to GND.
POWER PROTECTION
To protect the output transistors of the power bridge a power detector is implemented (fig 1).
The current flowing in the power bridge and the voltage drop on the relevant power (Vds) are internally measured. These two parameters are converted in current and multiplied: the resulting current , Ipd, is proportional
to the instantaneous dissipated power on the relevant output transistor. The current Ipd is compared with the
reference current Ipda, if bigger (dissipated power > 18W) a current, Iprot(PD), is supplied to the Protection pin.
The aim of the current Iprot is to reduce the reference voltage for the Buck regulator supplying the power stage
of the chip, and than to reduce the dissipated power. The response time of the system must be less than
200 µSec to have an effective protection. As further protection, when Ipd reaches an higher threshold (when the
dissipated value is higher then 30W) the chip is shut down, forcing low the Stby/Mute pin, and the turn on sequence is restarted. The above description is relative for each channel in 4x30W configuration.
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Figure 1. Power Protection Block Diagram
OUT1p
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-
OPA
OPA
+
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ILIMP
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du
I_pda
+
IPROT(PD)
I_pdp
V/I
I_Pd
x
MULTIPLIER
V/I
RSENSE
IPROT(ID)
I_pd
Iload
I_pd
Ilim
TO PROT
PAD
IPROT
CURRENT
COMP.
SEQUENCE
Pdp1 TO TURN-ON/OFF
CURRENT
COMP.
Oc1
CD+1&2
D02AU1346
8/17
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OUT1n
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SEQUENCE
TO TURN-ON/OFF
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STA530
In fig. 2 there is the power protection strategy pictures. Under the curve of the 18W power, the chip is
in normal operation, over 30W the chip is forced in
Standby. This last status would be reached if the
Buck regulator does not respond quikly enough reducing the stress to less than 30W.
The fig.3 gives the protection current, Iprot(PD), behavior. The current sourced by the pin Prot follows
the formula:
–4
( P d – P d_ av _th ) ⋅ 5 ⋅ 10
I p ro t ( P D) ≡ ------------------------------------------------------------------1.25 V
CURRENT PROTECTION
The chip is also protected by a current detection.
The current ILOAD is compared with the reference
current ILIMP, if bigger (ILOAD> 4,5 A)a current Iprot(IL), is supplied to the Protection pin.
As further protection, when ILOAD reaches an higher
threshold (5 A) the chip is shut down, forcing low the
Stby/Mute pin, and the turn on sequence is restarted.
The above description is relative for each channel in
4x30W configuration.
The fig.4 gives the protection current, Iprot(IL), behavior. The current sourced by the pin Prot follows
the formula:
(for each channel)
( I L O AD – I ict, s )
I p ro t ( IL ) ≡ ---------------------------------------- (for each channel)
2500
for Pd < Pd_av_th the Iprot(PD)= 0.
for IlLOAD < Iict,s the Iprot(IL) = 0.
Figure 2. Power protection threshold
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For the parallel channel Iprot is double.
Ids(A)
Ilim=4.5A
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The chip is also shut down in the following conditions:
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
When the average junction temperature of the chip
reaches 150°C.
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When the ground potential differ from more than 5V
from the half of the power supply voltage, ((CD+)(CD-))/2
Standby
k
Buc
Pd_Max=30W
Li
m
it a
Normal
Operation
0
7.5
ti o
Pd_reg=18W
n
15.0 22.5 30.0 37.5
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-
When the sum of the supply voltage |Vs+| + |Vs-|
<20V
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D02AU1366
Vds(V)
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The output bridge is muted when the average junction temperature reaches 130°C.
Figure 4. Protection current behaviour Iprot (IL)
Figure 3. Protection current behaviour Iprot (P D)
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20
bs
10
Iprot(IL)(µA)
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Iprot (IPd) (mA)
Iprot slope = 0.4 mA/W
O
800
400
:
Pd (W)
5
10
Iprot slope=400µA/A
15
20
25
D02AU1367
5A
4.5A
1
2
3
4
5
6
Id(A)
30
9/17
STA530
Figure 5. Test and Application Circuit (4x50W)
C9
R5
TRK_1
INPUT 1
R1
R9
C1
R13
C16
R14
OUT2P
STBY/MUTE
5V
-VS
R18
-VS
OUT3P
C12
R15
TRK_OUT
R16
PROT
R4
R8
R10
PWR_INP4
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D02AU1347
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Figure 6. Test and Application Circuit (2x50W & 1x100W)
R5
TRK_1
R1
PWR_INP1
C5
C1
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CD+1&2
CD+3&4
R13
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+VS
C17
C15
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GND
C16
R14
C14
C18
-VS
R15
TRK_OUT
R16
PROT
R4
TRK_3
INPUT 3
R8
C8
R12
PWR_INP3
C4
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INPUT 4
C6
C2
TRK_2/PAR1&2
-VS
PWR_INP2
OUT1P
OUT2P
4Ω
OUT2M
OUT1M
STBY/MUTE
5V
R18
OUT3P
C19
CD-1&2
CD-3&4
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C10
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P
R2
-VS
D1
C12
)
s
(
ct
R9
STBY
R19
R6
TRK_4/PAR3&4
C4
C9
MUTE
8Ω
OUT4M
PWR_INP3
INPUT 1
R17
OUT4P
R12
C8
8Ω
OUT3M
TRK_3
INPUT 3
C13
C19
CD-1&2
CD-3&4
10/17
8Ω
OUT2M
C18
D1
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8Ω
C17
GND
C14
C3
OUT1M
+VS
C15
C7
OUT1P
CD+3&4
C13
INPUT 2
PWR_INP2
CD+1&2
C11
R7
R11
PWR_INP1
C5
R3
TRK_2/PAR1&2
8Ω
OUT3M
R17
MUTE
STBY
R19
OUT4P
8Ω
OUT4M
TRK_4/PAR3&4
R10
R6
INPUT 4
R2
C6
PWR_INP4
D02AU1351
C10
C2
STA530
EXTERNAL COMPONENTS
Name
Function
Value
Resistor for tracking input voltage
R1 = R2 =R7 = R8 filter
10KΩ
Resistor for tracking input voltage
R5 = R6 =R3 = R4 filter
56KΩ
Cac
AC Decoupling capacitor
C1 = C2 = C3 = C4
100nF
(fp = 16Hz,
Rac =100KΩ )
R9=R10=R11=R12 Resistor for tracking input voltage filter
C5 = C6 = C7 = C8 Capacitor for Tracking input
voltage filter
10KΩ
1µF
R17
Bias Resistor for Stby/Mute function
R18
Stby/Mute constant time resistor
30KΩ
R19
Mute resistor
30KΩ
C19
Capacitor for Stby/Mute resistor
2.2µF
C17 = C18
Power supply filter capacitor
100nF
R13 = R14
Centering resistor
C13 = C14
Tracking rail power supply filter
680nF
R15
TRK_out
40KΩ
R16
Protection
1KΩ
10KΩ
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330 Ω, 1W
470 µF , 63V
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Power supply filter capacitor
D1
1
Cac = --------------------------------2π ⋅ fp ⋅ Rac
1nF
C9=C10=C11=C12 Dc decoupling capacitor
C15 = C16
Formula
Schottky diode
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-
Figure 7. BASH® module SAM261 6.1 with 2 x STA530 (see Application Note AN1643)
Signal Power Supply
+/-24V DC / mA
50
+50VDC
)
s
(
ct
Dynamic Power Supply
(CD+ & CD-)
Buck
Regulator
u
d
o
r
P
e
STABP01
Controller
t
e
l
o
bs
O
Lines
STA530
4 x 50Watts
AudioInputs
8 Ohm Loads
of
Controls
BASH fi module SAM261
STA530
1 x 100Watts
2 x 50Watts
6.1
+/-24V DC / mA
50
Signal Power Supply
4 Ohm Load
Power - On-Off sequences:
In order to avoid damages to the SAM261 board it is important to follow these sequences:
At Power-On apply in the first the Auxiliary Power Supply (±24V) and after the Main Power Supply
(+50V), in this condition the system is in "Mute state" and it can move in "play state" with the switch present
on the pcb.
At Power-Off is better to bring the SAM module in "Mute state" and after that to follow this order: switchoff the Main Supply Voltage (+50V) and subsequently the Auxiliary Power Supply. (±24V).
11/17
STA530
System Description & Operating Rules
SAM261 is a BASH® 6.1 amplifier ( 6 x 50W, 1 x 100W) implementation utilizing the STA530 Integrated Circuit.
Specifically designed for multi-channel implementation in DVD - HTIB systems, Multi-Media systems, Mini and
Micro systems and Set Top boxes.
SAM261 is dimensioned to provide the maximum Output Power (THD=10 %) on two channels and instantaneously and 1/3 max Pout on the remaining Outputs, or 1/8 of max Pout continuous; this rule is important to
define the main Power Supply size (+50V).
Buck Regulator Description
The function of the buck regulator is to efficient convert efficiently an input voltage to a lower voltage by adjusting the ratio of the switching transistor's on-time to off-time. The resulting waveform is averaged by the output
filter to recover an analog signal.
In the BASH amplifier this output is in effect split in half by centering it on the audio ground to provide CD+ and
CD- rails.
To avoid the need for a high side driver for the transistor switch in the buck regulator the buck circuit recommended has the switch in the return path. Hence the gate drive circuit (part of the STPB01) is referenced to the
negative return of the main supply that provides power for the buck regulator.
c
u
d
Interfacing STA530 to STPB01 (Feedback circuit)
)
s
t(
This circuit produces a control signal current that is fed back to the STPB01 digital controller. The network used
in this example compares the track signal (STA530 track out) to a fixed ratio of buck regulator's output (CD+)
using a transistor. This method is effective because the controller's reference is the negative of the main DC
supply, which is not referenced to audio ground.
The tracking signal is generated inside the STA530 (track out) by taking the absolute value of the pre-amp's
output. The outputs of each channel and of each STA530 are then tied together in a diode-oring arrangement.
This means that the highest of any given output is the output that determines the tracking signal.
The absolute value circuit inside the STA530 has gain. This makes it possible to use an RC network and a resistor divider to create a phase shift in the tracking signal at higher frequencies. This is also useful in optimizing
the alignment of the buck regulator's output with the output signal of the bridge amplifier at high frequency
This circuit first converts the buck switch current to a peak voltage. The control current is then converted to a
voltage (using a resistor) and added to the peak voltage. By doing this, the buck is better able to maintain the
desired headroom over a wide load range and output level.
e
t
le
)
s
(
ct
o
r
P
o
s
b
O
-
u
d
o
Centering Network for CD + & CD- Rails
The power rail of a bridge amplifier has no current flowing through the ground node, as the load is not connected
to ground. However there are several different small sources of dynamic and continuos ground currents flowing
from either CD+ or CD- to support the function of various things such as the control signal to the STABP01 controller. The centering network prevents these currents from shifting the CD+/- rails away from center i.e. away
from a symmetric split of the buck's output about ground. This is critical, even a small centering error requires
an increase in headroom which results in a significant drop in output losses. In its simplest form the centering
network could be a resistor divider from CD+ to CD- with its center tied to ground. As long as the impedance is
low enough (for example 200Ω) this will swamp the smaller offset currents. It is helpful to put this kind of passive
network on the board with the STA530 devices to help when testing this board on its own.
r
P
e
t
e
l
o
s
b
O
Power Amplifier Heatsink requirements
The heatsink requirements are dependent on several design goals. However there are two common references:
Pink noise at 1/8 of full power, all channels loaded. This would approximate a system with all channels reproducing music at full volume with clipping occurring only occasionally. The second would be full power at 1kHz
for 5 minutes after a one hour pre-soak at 1/8 power.
The worse of these two is the full power test. A conservative approach is to assume that the heatsink would
come to thermal equilibrium after 5 minutes. Thus the Rth of the heatsink can be determined by:
12/17
STA530
Tjmax – Tamb
R th = ---------------------------------- – Rth –j
Pd
c ase
– R th
cas e to heatsink
For example in the STA530 the Rth jc is 1°C/W. R case-to-heatsink with grease is about 0.5 °C/W. The maximum operating junction temperature is 130 °C, which for margin should be derated to 120 °C.
Buck Regulator Heatsink
The Buck regulator heatsink can be designed in a similar manner and does not change by varying power supply.
In general the efficiency will be in the order of 85%. The thermal impedances from the junction(s) to the heatsink
may be lower and the maximum operating temperature will be higher. Usually either the sub or the remaining
channels are tested at full power. The result is that usually the Buck heatsink is about ¼ the size of the linear
heatsink, but this can be strongly affected by the design.
Figure 8. PCBs AND COMPONENTS LAYOUT
4 Pins Harness
Power Supply Connections
4 Supply Connections
c
u
d
Main DC
Input
VS DC
Input
Mute
e
t
le
Audio
Inputs
Preamplifier PCB
)
s
(
ct
u
d
o
r
P
e
)
s
t(
o
r
P
o
s
b
O
-
9 Pins Harness
Audio Connections
Amplifier PCB
SAM261 Specification
t
e
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o
Parameter
Output Power
Sensitivity
Crosstalk
Rating
Sats @ 8Ω - 55 Watts @ 10%
Sub @ 4Ω - 100 Watts @ 10%
< 0.05% @ 40 Watts
< 0.05% @ 75 Watts
-102 dB (relative to full power)
-110 dB (A-weighted)
1 VRMS
-87dB (relative to10W)
Main Power Supply Inputs
50Volts @ 2 Amps
Aux Power Supply Inputs
+ 24 Volts @ 100mA
-24 Volts @ 100mA
s
b
O
THD + N
SNR
Notes
See Graphs
Measured @ 1KHZ
Channel 5 terminated
Amplifier
Channel 5 @ 10W 1KHz 8Ω,
Channel 3 input terminated
Maximum Voltage is 50Vdc
Minimum Voltage is 40Vdc
13/17
STA530
Figure 9. THD + N FR Channel
Figure 12. THD + N LF Channel
Audio Precision
Audio Precision
10
10
5
5
2
2
1
1
0.5
0.5
%
%
0.2
0.2
0.1
0.1
0.05
0.05
0.02
0.02
0.01
2.5 5
7.5 10 12.5 15 17.5 20 22.5 25 27.5 30 32.5 35 37.5 40 42.5 45 47.5 50 52.5 55 57.5 60
0.01
5
W
Figure 10. THD + N vs Frequency
Figure 13. Frequency Response
Audio Precision
Audio Precision
10
5
2
1
0.5
%
0.2
0.1
Pout = 30W
0.05
0.02
Pout = 5W
0.01
20
50
100
200
500
1k
Hz
2k
5k
10k
)
s
(
ct
20k
u
d
o
Audio Precision
r
P
e
+0
-10
-20
-30
t
e
l
o
-40
-50
-60
-70
s
b
O
-90
-100
-110
-120
-130
-140
-150
-160
20
14/17
50
100
200
500
Hz
1k
2k
5k
10k
+30
+29
+28
+27
+26
+25
+24
+23
+22
+21
+20
+19
+18
+17
+16
dBr+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
+0 10
c
u
d
e
t
le
o
s
b
O
-
Figure 11. Residual Noise vs Freq - Relative to
full power
dBr -80
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115120
W
20k
20
50
100
)
s
t(
o
r
P
200
500
Hz
1k
2k
5k
10k
20k
40k
STA530
Figure 14. Application Block Diagram
+VS
-VS
MUTE
+VS
S1
-VS
MUTE
J1
MUTE CONTROL
MUTE
+VS
-VS
-VS
IN1
RED
CONNECTOR
IN2
MUTE-BUCK
+VS
WHITE
MUTE-BUCK
TRACK
IN3
RED
CONNECTOR
IN4
BUCK CONTROLLER
GATE-DRIVE
I-SENSE
OUT1+
50W
WHITE
CD-
CDCD+
OUT2+
50W
OUT3+
50W
GATE-DRIVE
200W BUCK
DC++
OUT4+
50W
15µH
CD+
CD-
CDMUTE
1800pF
-VS
-VS
e
t
le
J3
+VS
so
b
O
-
+VS
IN5
RED
IN6
WHITE
J4
OUT4TRACK
PROT
CD+
CD+
J3
OUT3-
I-SENSE
L3
J2
OUT2-
1800pF
DC++
J1
OUT1-
J2
PROT
DC++
STA530
4 CHANNELS
c
u
d
STA530
3 CHANNELS
o
r
P
50W
PROT
)
s
t(
TRACK
OUT5+
OUT5-
J5
OUT6+
50W
J4
OUT6-
J6
OUT7+
IN7
100W
OUT7-
J7
D02AU1444
)
s
(
ct
u
d
o
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P
e
t
e
l
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s
b
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15/17
STA530
DIM.
MIN.
4.45
1.80
A
B
C
D
E
F (1)
G
G1
H (2)
H1
H2
H3
L (2)
L1
L2 (2)
L3
L4
L5
M
M1
N
O
R
R1
R2
R3
R4
V
V1
V2
V3
0.75
0.37
0.80
25.75
28.90
22.07
18.57
15.50
7.70
3.70
3.60
mm
TYP.
4.50
1.90
1.40
0.90
0.39
1.00
26.00
29.23
17.00
12.80
0.80
22.47
18.97
15.70
7.85
5
3.5
4.00
4.00
2.20
2
1.70
0.5
0.3
1.25
0.50
MAX.
4.65
2.00
MIN.
0.175
0.070
1.05
0.42
0.57
1.20
26.25
29.30
0.029
0.014
22.87
19.37
15.90
7.95
0.869
0.731
0.610
0.303
4.30
4.40
0.145
0.142
0.031
1.014
1.139
inch
TYP.
0.177
0.074
0.055
0.035
0.015
0.040
1.023
1.150
0.669
0.503
0.031
0.884
0.747
0.618
0.309
0.197
0.138
0.157
0.157
0.086
0.079
0.067
0.02
0.12
0.049
0.019
MAX.
0.183
0.079
OUTLINE AND
MECHANICAL DATA
0.041
0.016
0.022
0.047
1.033
1.153
0.904
0.762
0.626
0.313
0.169
0.173
c
u
d
5˚ (Typ.)
3˚ (Typ.)
20˚ (Typ.)
45˚ (Typ.)
(1): dam-bar protusion not included
(2): molding protusion included
V
(s)
t
c
u
B
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P
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V3
O
L4
C
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A
H2
R3
t
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l
o
R4
V1
R2
N
L2
R
L3
O
o
r
P (vertical)
Flexiwatt27
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t
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o
H
H1
H3
bs
s
b
-O
)
s
t(
L
L1
V1
V2
R2
D
R1
L5
Pin 1
R1
R1
E
G
G1
F
FLEX27ME
M
M1
7139011
16/17
STA530
c
u
d
e
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le
)
s
(
ct
)
s
t(
o
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P
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s
b
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-
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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17/17