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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 4, APRIL 2005
A 233-MHz 80%–87% Efficient Four-Phase DC–DC
Converter Utilizing Air-Core Inductors on Package
Peter Hazucha, Member, IEEE, Gerhard Schrom, Jaehong Hahn, Bradley A. Bloechel, Associate Member, IEEE,
Paul Hack, Gregory E. Dermer, Member, IEEE, Siva Narendra, Member, IEEE, Donald Gardner, Member, IEEE,
Tanay Karnik, Senior Member, IEEE, Vivek De, Member, IEEE, and Shekhar Borkar, Member, IEEE
Abstract—We demonstrate an integrated buck dc–dc converter
for multi- CC microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was
implemented in a 90-nm CMOS technology. By operating at high
switching frequency of 100 to 317 MHz with four-phase topology
and fast hysteretic control, we reduced inductor and capacitor sizes
by three orders of magnitude compared to previously published
dc–dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%–87% efficiency and 10%
peak-to-peak output noise for a 0.3-A output current and 2.5-nF
decoupling capacitance. A forward body bias of 500 mV applied to
PMOS transistors in the bridge improves efficiency by 0.5%–1%.
Index Terms—Buck converter, CMOS, dc–dc converter.
I. INTRODUCTION
M
ICROPROCESSOR designs with two different supply
voltages are becoming attractive for achieving high performance under stringent power constraints [1]. Speed-critical
circuits operate at high voltage while circuits with delay slacks
operate at low voltage to save power without impacting processor frequency. In addition, large on-chip caches in 90 nm and
beyond require higher voltage to maintain adequate SRAM cell
stability, while lower voltage can be applied to logic cores and
smaller arrays on the chip. Furthermore, on-chip analog circuits
often require larger headroom and higher voltage than logic circuits. An efficient on-die dc–dc converter that delivers high currents with small area overhead and also meets supply noise constraints is desirable to reduce system complexity.
A step-down voltage regulator can be implemented as a
switched-capacitor charge pump, linear regulator, or switching
dc–dc converter. Our feasibility study indicated that a charge
pump with on-chip capacitors implemented in bulk CMOS
achieves only 65% conversion efficiency and requires large
silicon area of 1 mm for 100 mA of output current. A linear
, which
regulator theoretically achieves efficiency
Manuscript received August 30, 2004; revised November 29, 2004.
P. Hazucha, G. Schrom, B. A. Bloechel, T. Karnik, P. Hack,
G. Dermer, S. Narendra, V. De, and S. Borkar are with Circuit Research,
Intel Laboratories, Intel Corporation, Hillsboro, OR 97124 USA (e-mail:
peter.hazucha@intel.com; gerhard.schrom@intel.com; bradley.a.bloechel@
intel.com; tanay.karnik@intel.com; paul.hack@intel.com; greg.dermer@
intel.com; siva.g.narendra@intel.com; vivek.de@intel.com; shekhar.y.borkar@
intel.com).
J. Hahn is with Intel Corporation, Beaverton, OR 97006 USA (e-mail: jaehong.hahn@intel.com).
D. Gardner is with Intel Corporation, Santa Clara, CA 95054 USA (e-mail:
d.s.gardner@intel.com).
Digital Object Identifier 10.1109/JSSC.2004.842837
is 66%–83% in this application. The most important advantage
of a linear regulator is small silicon area and very fast load
regulation. We report on a fast linear regulator in another
paper in this issue [12]. A switching dc–dc converter often has
conversion efficiency above 80% at the cost of bulky off-chip
inductors and a fair amount of decoupling capacitance.
In this paper, we demonstrate a four-phase buck converter
operating at an ultra-high frequency ( 100 MHz) that leads to
a three-orders-of-magnitude reduction in capacitor and inductor
size. The capacitor was integrated on-chip and four size-402
SMT air core inductors were mounted on the package.
In Section II, we describe the details of the dc–dc converter circuits. In Section III, we present dc and transient
response measurements on the test chip. Finally, we compare
performance of our design with previously published dc–dc
converters in Section IV.
II. DC–DC CONVERTER DESCRIPTION
A. Design Requirements
applications with the main voltage of 1.2 V,
For multithe desired output voltage is about 0.8–1.0 V, which results in
of 0.66–0.83. The simplest stepa conversion ratio
down switching converter utilizing just one inductor and two
switches is a buck converter and is typically used for conversion
ratios of 0.1–0.9. For lower conversion ratios, the small duty
cycle significantly degrades efficiency and transformer-based
topologies are preferred. The value of the duty cycle in our application permitted us to use the buck topology, which also eliminated the need for magnetic coupling between the windings.
One of the design goals was to integrate the dc–dc converter
on a single chip. The typical -factor of on-chip air core inductors ranges between 5 and 10, which is not sufficient for power
delivery with efficiency above 80%. Moreover, an on-chip inrating of 0.3 A occupies a substantial silicon
ductor for
area. So implementing the inductor on-chip with present technology did not seem possible. Integrating the output capacitor
would require that the capacitor size be reduced to several nanofarads. Otherwise, the silicon area and the power wasted in oxide
leakage of the capacitor would become prohibitively large. The
size of the capacitor is determined from two requirements.
First, switching operation of the buck converter introduces a
ripple current that flows through the inductor in addition to the
load current. This ripple current is integrated on the output ca. To suppress the
pacitor and produces a voltage ripple on
voltage ripple to several millivolts, the output capacitor has to be
0018-9200/$20.00 © 2005 IEEE
HAZUCHA et al.: A 233-MHz 80%–87% EFFICIENT FOUR-PHASE DC–DC CONVERTER UTILIZING AIR-CORE INDUCTORS ON PACKAGE
large. However, this is only true for a single-phase dc–dc converter. If the converter is divided into phases, each phase deof output current, with their switching times
livering
staggered by 360
, then the switching ripple completely can. In our
cels out for any conversion ratio that is a multiple of
application, the conversion ratios are close to 0.75, which corresponds to a four-phase dc–dc converter. Since the inductor ripple
current is not a limiting factor in a multiphase dc–dc converter,
the inductors can be smaller. This reduces output impedance at
high frequency and improves the transient response for a given
size of output decoupling capacitor.
The second requirement comes from load regulation. If the
load suddenly increases, then the output capacitor has to provide
current to the load until the dc–dc converter adjusts its current
through the inductors. The charge available in a decoupling ca, where
mV for a 10%
pacitor equals
of 0.9 V. For a current step of 50% of
, the
droop at
converter has to adjust the output current within time
For a 1-nF capacitor, the available response time is only 1.2 ns!
Obviously, a dc–dc converter with an extremely fast response
time is required. For a multiphase buck converter, this implies
that the switching frequency has to be in a range of 100 MHz to
1 GHz and the response has to be within less than one switching
cycle. However, the response time of a widely used pulse-width
modulation (PWM) controller is about five to ten switching
cycles.
Hysteretic control techniques have advantages in their immediate response to a load transient and a simple feedback circuit.
However, the lack of synchronization makes them difficult to
apply in multiphase interleaved dc–dc converters. In fact, load
response may be degraded if the output voltage ripple becomes
prohibitively large and forces the inductor size to increase. It is
attractive to develop a multiphase, interleaved dc–dc converter
that would benefit from the fast loop response of a hysteretic
control and still afford small inductor size due to ripple cancellation effect inherent to multiphase design [2]. The proposed
topology enables a multiphase configuration by adding an external synchronization signal to a hysteretic converter.
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Fig. 1. Hysteretic controller with RC network across the inductor.
where
is the switching frequency and
has to match the hysteresis window
is the duty cycle.
which sets the switching frequency
The feedback network
, provides stable operation in
single-phase configuration, especially when the hysteresis
is small.
C. Voltage Positioning
The optimum load response is achieved by designing the
output impedance for a resistive response [3]. When that is the
case and the converter is loaded by current, the output exhibits
a dc error proportional to the output resistance. Since the output
voltage at any time “positions” itself along a load line with the
slope of the output resistance, this concept is called voltage
positioning [4].
. The
The average voltage at the comparator output is
average voltage
at the bridge output is reduced by the
and is given by
drop on the bridge series resistance
is a weighted average of series resistances of high-side
and low-side
switches
B. Hysteretic Controller
Fig. 1 shows a buck converter with a hysteretic controller. The
comparator hysteresis is set by resistors
and . A cascade
of buffers drives a high-side PMOS transistor and a low-side
NMOS transistor of a bridge that switches inductor . The feedback network
, works as a high-pass filter from
to
, and provides fast transient response. Since
is relatively
small and the voltage across is large compared to the ripple
, the voltage across
is an integral of the voltage at
of
the bridge output. Therefore, the RC integrator estimates the inductor current and current sensing is not required.
, is
The voltage variation at the feedback node,
If resistor
is introduced between the comparator output
as shown in Fig. 2, then
and
Since
equals the input reference
due to the action
is given
of the negative feedback loop, the average output
by
By properly choosing
, the dc output impedance can be
adjusted for optimum load response.
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Fig. 2.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 4, APRIL 2005
Hysteretic controller with voltage positioning.
Fig. 4.
Derivation of a synchronization condition.
In order to synchronize, the frequency
angular voltage should be lower than
should satisfy the condition
Fig. 3.
of the injected tri, and the amplitude
Synchronization of the hysteretic controller by injection locking.
Then the injected amplitude is
D. Droop Control
(see Fig. 1)
As mentioned earlier, the feedback network
works as a high-pass filter from
to
, which enables a
very fast response of the controller. Whenever the load current
, the controller will couple the inductor
abruptly changes by
. The inductor needs time
to
either to ground or to
accommodate the current change
for
for
The initial difference between inductor current and load current
causes a droop
The RC time constant is such that the voltage change across
equals
, and
equals
approximately after
time
for
for
E. Synchronization
The hysteretic controller can be synchronized by injection of
, as shown in Fig. 3, so that
a synchronization signal at
the switching instants can follow the envelope of the hysteretic
is
band according to Fig. 4. The free-running frequency
, and the values of and
determined by the hysteresis
where
.
F. Single-Phase Implementation
The complete circuit schematic of a single-phase dc–dc converter module, 1-phase, is shown in Fig. 5. A switched capacwith
itor circuit, subtractor, generates a reference voltage
respect to the local ground by subtracting the external referand
. An integrator
,
ence voltages
compensates for the input offset of comparator
and
and
. Reother offsets induced by the synchronization current
sistors with large values implemented in CMOS usually have
large parasitic capacitance to ground that limits the bandwidth.
in Fig. 3 is about
larger than
. Therefore,
Resistor
, was replaced by resisin Fig. 5, the resistive divider
tors
, and the R-2R ladder
which do not
require high-value resistors. The hysteresis window of comis digitally adjustable by changing the divider ratio
parator
. A sensed output voltage,
, is coupled to
of
via a high-pass filter
, and
for fast response to
, in Fig. 3 was
load current transients. Resistive divider
. By changing the divider
replaced by the R-2R ladder,
, the dc-level of
can be programmed between
ratio of
and
. Buffers
, and
are sized
to minimize the short circuit current through bridge transistors
and
. The rectangular voltage across
creates a tri. Current
creates a staircase
angular waveform at
waveform at
that pulls the free-running oscillation fre. The bridge operates with
quency to the frequency of
independently adjusted, fixed dead times between the turn-off
and turn-on instants of the high-side and low-side switches.
G. Four-Phase DC–DC Converter
The block diagram of the four-phase dc–dc converter is
shown in Fig. 6. The chip contains four single-phase modules
HAZUCHA et al.: A 233-MHz 80%–87% EFFICIENT FOUR-PHASE DC–DC CONVERTER UTILIZING AIR-CORE INDUCTORS ON PACKAGE
Fig. 5.
841
Complete schematic of a single-phase dc–dc converter module (1-phase) featuring hysteretic control, voltage positioning, and synchronization.
Fig. 6. Block diagram of a high-frequency four-phase interleaved dc–dc converter.
that operate as stand-alone converters and receive synchronization signals from block synchronizer. In a multiphase topology,
the switching times of the inductors are staggered to cancel out
the output voltage ripple. For a four-phase design the phase
difference is 90 , allowing a complete ripple cancellation for
duty cycles of 25%, 50%, and 75%. Current reference
generates reference voltage
which is shielded by
and fed differentially to the synchronization circuits inside each
single-phase module. The only output decoupling capacitor
integrated on-chip.
was a 2.5-nF capacitor
H. On-Chip Load
The load current demand is emulated by an on-chip current
, with a programmable dc offset, amplitude, and
source,
ramp time (Fig. 6). The range of ramp times is from 100 to
500 ps. The load can be triggered either by an internal ring os.
cillator or by an external clock
I. Test Chip Layout
The test chip was implemented in a 90-nm CMOS technology
[5]. The dc–dc converter was a part of a 3500 m 4500 m
die out of which it occupied a silicon area of 1280 m 990 m
(see Fig. 7). After subtracting the area of iload, decoupling capacitors, and overhead circuitry used for scanning the config-
Fig. 7. DC–DC converter microphotograph.
uration and internal signal probing, the area occupied by the
140 m. Each singlebridges and controllers is 1000 m
phase module utilized four C4 bumps for bridge output, ground
),
, and
.
(
Fig. 8 shows the chip packaged in a flip-chip BGA package
attached to the circuit board. Four air core surface-mount inductors manufactured by Coilcraft [6] were soldered to pads on
the die side of the package. According to the measurements in
[6], these inductors achieve factors of 20 at 100 MHz, 30 at
300 MHz, and 90 at 2 GHz. For high-frequency measurement
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 4, APRIL 2005
Fig. 8. Photograph of the prototype. Four air core inductors are mounted on
the package.
Fig. 9.
Bridge outputs showing four-phase operation of a dc–dc converter.
of the droop, a probe signal on output
was routed via a
50- series-terminated connection to a dedicated C4 bump, a
50- package trace, and a miniature 50- coaxial cable that
connected directly to the die side of the package. The oscilloscope had a bandwidth of 4 GHz.
III. MEASUREMENT RESULTS
The dc–dc converter test chip was designed to operate at a
switching frequency from 100 MHz to about 600 MHz. Power
loss in charging of the gate capacitance of the bridges increases
with frequency while the resistive loss due to the ripple current
in the inductors and the bridges decreases with frequency. The
optimum frequency is selected such that the total loss is minimized and the efficiency maximized. The optimum point depends on the value of the inductors.
A. Four-Phase Operation
Fig. 9 shows the bridge outputs probed on the leads of the
inductors on top of the package. The bridges operate with a duty
cycle of 75% and are shifted by 90 to cancel out the ripple. For
an inductor of 6.8 nH/phase, the optimum switching frequency
is 233 MHz.
B. Efficiency
Measured efficiencies for 1.2 V/0.9 V and 1.4 V/1.1 V conversion are shown in Figs. 10 and 11, respectively. For a load
current of about 0.2 A, the efficiency improves at larger inductance and lower frequency due to reduced switching loss and
to the resistive loss associated with the ripple current. However,
Fig. 10.
Measured efficiency for 1.2 to 0.9 V conversion with I
= 0:3 A.
Fig. 11.
Measured efficiency for 1.4 to 1.1 V conversion with I
= 0:4 A.
at a larger load current of about 0.3 A, the resistive loss due
to the load current is significant. Inductors with the same form
factor and technology, e.g., air core with copper wires, exhibit
about the same factor at a given frequency. A larger induc. Therefore, the
tance comes with a larger series resistance
efficiency of a dc–dc converter with a larger inductance and
higher peak efficiency degrades faster when the load current increases and eventually becomes worse than the efficiency of a
dc–dc converter with a smaller inductance that runs at higher
frequency.
C. Efficiency With Body Bias
To improve efficiency we applied a forward bias of 500 mV
to the N-well of the PMOS transistors in the bridges. Forward
body bias reduced the series resistance and the resistive loss of
the bridges by about 10%. Since this type of loss contributes
about one-third of the total loss, the overall loss reduction is
about 3%. For a dc–dc converter efficiency of 85%, the total
loss is 15% of the input power. A 3% reduction translates into
about a 0.5% improvement in efficiency, which is in agreement
with the measurements in Fig. 12. At larger load currents, the
improvement is as much as 1%.
D. Transient Response
The transient response of the dc–dc converter was measured by changing the load current between two values with a
100-ps ramp time. From the analysis of typical circuits on a
microprocessor, it was found that the maximum instantaneous
load change is about 50% of the maximum load current. For
1.2 V/0.9 V conversion, the maximum load current is 300 mA.
Fig. 13 shows the response of the converter for a load step from
0 to 150 mA. In all cases, the on-chip decoupling capacitor was
HAZUCHA et al.: A 233-MHz 80%–87% EFFICIENT FOUR-PHASE DC–DC CONVERTER UTILIZING AIR-CORE INDUCTORS ON PACKAGE
Fig. 12. Efficiency with (solid) and without (hollow) a 0.5-V forward body
bias applied to the PMOS transistor of the bridge.
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Fig. 14. Tradeoff between output decoupling requirement, inductor size,
switching frequency, and efficiency.
TABLE I
SUMMARY OF PERFORMANCE
Fig. 13. Output voltage noise for 1.2 to 0.9 V conversion with a 50% load step
from 0 to 150 mA in 100 ps.
2.5 nF. At 3.6 nH, the response time of the converter is limited
both by the delay in the controller and the bridges, and the slew
rate of current in the inductors. As the inductance increases
to 15 nH, the response time becomes dominated by the slew
degrades
rate of the inductor current. Therefore, droop
for larger inductance values. The specified 10% droop is met
for a 3.6 nH and 6.8 nH inductance per phase. The output has
a steady-state error of about 50 mV which was intentionally
introduced by voltage positioning.
TABLE II
PERFORMANCE COMPARISON
E. Design Tradeoffs
It is apparent from Figs. 10 and 13 that higher inductance
improves efficiency and degrades transient response. However,
excessive droop can be corrected by adding more decoupling
capacitance either on-chip or off-chip. So for a constant droop,
there is a tradeoff between the efficiency and the size of the
decoupling capacitance. Fig. 14 illustrates the tradeoffs for a
10% droop. For a 2.5-nF decoupling, the maximum efficiency
is 83.2%. This efficiency is achieved by operating at 233 MHz
with an inductor of 6.8 nH. However, if the decoupling capacitor increases to 6.8 nF, the efficiency improves to 87% if the
converter operates at 100 MHz with 36 nH/phase.
IV. PERFORMANCE COMPARISON
Table I gives a summary of the measured performance for
1.2 V/0.9 V and 1.4 V/1.1 V conversion. Power efficiencies of
82.5% and 83.2% are achieved at bridge current densities of
15 A/mm and 20 A/mm , respectively. These current densities
give the ultimate limit that could be achieved for a large dc–dc
converter with the controller circuits occupying much less area
than the bridges.
Table II shows a comparison with previously reported on-chip
converters [7]–[11]. All the designs had a similar output rating
of about 0.3 A and comparable efficiency. Our dc–dc converter
was implemented in a standard 90-nm low-voltage CMOS
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 4, APRIL 2005
process. The combined switching and resistive losses for these
transistors are about 10% of the output power at frequencies as
high as 100 MHz. The sizes of the inductors and the decoupling
capacitor decrease linearly with frequency resulting in about
100–300 reduction. The combination of four-phase topology
and hysteretic control reduced the decoupling capacitance by
additional 5–10 . At that point, the sizes of the inductors and
the decoupling capacitor were reduced by three orders of magnitude and we could utilize low-cost small-size high-frequency
air-core inductors instead of inductors with magnetic cores that
operate at frequencies of a few megahertz.
V. CONCLUSION
We have demonstrated an integrated dc–dc converter implemented in a 90-nm logic technology with off-chip air-core
inductors soldered to the package. High switching frequency
(100–317 MHz), fast hysteretic control, and four-phase design enable a 1000 reduction in inductor and capacitor size
and elimination of the inductor magnetic core. The die area
overhead of the integrated converter circuits is estimated to
be 3%–4% for a 2-cm microprocessor with an 80-A current
demand and an on-chip decoupling capacitor of 670 nF. Such
a capacitance would be present on the power grid as nonswitching circuit capacitance and decoupling capacitance. To
our knowledge, integration of inductors for 80 A of load current
on the package or on the chip has not been demonstrated yet.
REFERENCES
[1] S. Mathew, M. Anders, B. Bloechel, T. Nguyen, R. Krishnamurthy, and
S. Borkar, “A 4 GHz 300 mW 64 b integer execution ALU with dual
supply voltages in 90 nm CMOS,” in IEEE Int. Solid-State Circuits Conf.
(ISSCC) Dig. Tech. Papers, vol. 519, Feb. 2004, pp. 162–163.
[2] J. A. Abu-Qahouq, N. Pongratananukul, I. Batarseh, and T. Kasparis,
“Multiphase voltage-mode hysteretic controlled VRM with DSP control
and novel current sharing,” in Proc. IEEE Int. Caracas Conf. Devices,
Circuits and Systems, Apr. 2002, pp. P017-1–P017-7.
[3] R. Redl, B. P. Erisman, and Z. Zansky, “Optimizing the load transient response of the buck converter,” in Proc. IEEE Applied Power Electronics
Conf. Expo. (APEC), vol. 1, Feb. 1998, pp. 170–176.
[4] A. Waizman and C.-Y. Chung, “Resonant free power network design
using extended adaptive voltage positioning (EAVP) methodology,”
IEEE Trans. Adv. Packag., vol. 24, no. 3, pp. 236–244, Aug. 2001.
[5] K. Kuhn et al., “A 90 nm communication technology featuring SiGe
HBT transistors, RF CMOS, precision R-L-C RF elements and 1 mm
6-T SRAM cell,” in Int. Electron Devices Meeting (IEDM) Tech. Dig.,
Dec. 2002, pp. 73–76.
[6] Coilcraft. [Online]. Available: http://www.coilcraft.com
[7] M. Mino, K. Tsukamoto, K. Yanagisawa, A. Tago, and T. Yachi, “A compact buck-converter using a thin-film inductor,” in Proc. IEEE Applied
Power Electronics Conf. Expo. (APEC), vol. 1, Mar. 1996, pp. 422–426.
[8] S. Sakiyama, J. Kajiwara, M. Kinoshita, K. Satomi, K. Ohtani, and A.
Matsuzawa, “An on-chip high-efficiency and low-noise DC/DC converter using divided switches with current control technique,” in IEEE
Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 1999, pp.
156–157.
[9] Y. Katayama, S. Sugahara, H. Nakazawa, and M. Edo, “High-powerdensity MHz-switching monolithic DC-DC converter with thin-film inductor,” in Proc. IEEE Power Electronics Specialists Conf., vol. 3, June
2000, pp. 1485–1490.
[10] J. Kim and M. A. Horowitz, “An efficient digital sliding controller for
adaptive power-supply regulation,” IEEE J. Solid-State Circuits, vol. 37,
no. 5, pp. 639–647, May 2002.
[11] K. H. Kim, J. Kim, H. J. Kim, S. K. Han, and H. J. Kim, “A megahertz
switching DC/DC converter using FeBN thin film inductor,” IEEE Trans.
Magn., vol. 38, no. 5, pp. 3162–3164, Sep. 2002.
[12] P. Hazucha, T. Karnik, B. A. Bloechel, C. Parsons, D. Finan, and S.
Borkar, “Area-efficient linear regulator with ultra-fast load regulation,”
IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933–940, Apr. 2005.
Peter Hazucha (M’01) was born in Slovakia. He received the Ph.D. degree in physics from Linkoping
University, Sweden, in 2000.
Since 2001, he has been with the Circuit Research
Laboratory at Intel Corporation. For the past five
years, he has been actively working on neutron soft
error rate characterization of CMOS processes including P1262, and soft error hardening techniques.
Since 2001, he has also been involved in design
of high-frequency voltage regulators and dc–dc
converters.
Gerhard Schrom received the M.S. and Ph.D. degrees from the Technical University Vienna, Austria,
in 1992 and 1998, respectively. His Ph.D. research
work encompassed device and circuit simulation,
device modeling, and low-voltage/low-power CMOS
technology.
After joining Intel Corporation in 1998, he worked
on the development of Intel’s 0.13-m technology.
Since 2001, he has been with Intel Laboratories,
Hillsboro, OR, where he has worked on device parameter variation analysis and the design of on-chip
dc–dc converters. He has authored or co-authored over 20 papers. His research
interests include device and circuit simulation, circuit design and synthesis,
process technology and device design, signal and image processing, and TCAD
framework aspects.
Jaehong Hahn received the B.S. degree from Seoul
National University, Seoul, Korea, in 1989, and the
Ph.D. degree from Texas A&M University, College
Station, in 2002.
From 1989 to 1994, he was a Design Engineer
at the Research and Development Center, Daewoo
Heavy Industries, Incheon, Korea. From 1994 to
1995, he was a Field Application Engineer with
Linear Technology Corporation. From 1995 to 1996,
he was with Maxim Integrated Products, Inc., as
a Senior Field Application Engineer. He joined
the Mobile Platforms Group at Intel in 2002 and is currently working as a
Platforms Engineer. His research interest is power electronics application to
power quality and clean power converters.
Bradley A. Bloechel (M’95–A’96) received the
A.A.S. degree in electronic engineering technology
from Portland Community College, Portland, OR, in
1986.
He joined Intel Corporation, Hillsboro, OR,
in 1987 as a Graphics Design Technician for the
iWarp project supporting the RFU and ILU design
effort. In 1991, he transferred to Supercomputer
Systems Division Component Technology, where he
supported VLSI test/validation effort and extensive
fixturing support for accurate high-speed test and
measurement of the interconnect component used in the Tera ops computer
project (Intel, DOE, and Sandia). In 1995, he joined the Circuits Research Laboratory, Microcomputer Research Laboratory, where he is a Senior Laboratory
Technician specializing in on-chip dc and high-speed I/O measurements and
characterization.
Mr. Bloechel is a member of Phi Theta Kappa.
Paul Hack, photograph and biography not available at the time of publication.
HAZUCHA et al.: A 233-MHz 80%–87% EFFICIENT FOUR-PHASE DC–DC CONVERTER UTILIZING AIR-CORE INDUCTORS ON PACKAGE
Gregory E. Dermer (M’78) received the B.S degree
in electrical engineering from Indiana Institute of
Technology, Fort Wayne, in 1977 and the M.S.
degree in electrical and computer engineering from
the University of Wisconsin, Madison, in 1983.
From 1979 to 1992, he held a variety of processor
architecture, logic design, and physical design
positions at Cray Research, Inc., Nicolet Instrument
Company, Astronautics Corporation of America,
and Tandem Computers, Inc. In 1992, he joined Intel
Corporation’s Supercomputer Systems Division.
While there, he worked on clock system design and reliability modeling for
the Intel ASCI Red supercomputer. For the past six years, he has worked in the
circuits research area of Intel Laboratories, Hillsboro, OR, on physical design
and measurements for high-speed interconnections.
Siva Narendra (M’99) received the B.E. degree
from the Government College of Technology,
Coimbatore, India, in 1992, the M.S. degree from
Syracuse University, Syracuse, NY, in 1994, and the
Ph.D. degree from the Massachusetts Institute of
Technology, Cambridge, in 2002.
He has been with Intel Laboratories since 1997,
where his research areas include low voltage MOS
analog and digital circuits and impact of MOS parameter variation on circuit design. He is an Adjunct
Faculty with the Department of Electrical and Computer Engineering, Oregon State University, Corvallis. He has authored or coauthored 44 papers and has 41 issued and 15 pending patents in these areas.
Dr. Narendra is an Associate Editor for the IEEE TRANSACTIONS ON
VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS and a member of the
ISLPED, ISQED, and DAC/ISSCC Student Design Contest Technical Program
Committees.
Donald Gardner (M’77) received the Ph.D. degree
in engineering from Stanford University, Stanford,
CA.
He has been with Intel Corporation since 1991
and is currently a Senior Research Engineer in
the Circuits Research Laboratory. He is also a
Visiting Scientist at Stanford University. He has
had appointments as a Visiting Research Scientist
at Hitachi Research Laboratories, Japan, and as an
Instructor at Stanford University. He is the inventor
or co-inventor of 38 patents including for Al-Ti
layered metal for interconnections, reflow of copper metal, embedded ground
planes, and high-frequency magnetic materials. He has published and presented
over 100 electrical engineering, materials science and computer science
papers. He enjoys bringing new life to old technologies by blending them with
different technologies or recent science and materials. His current interests
include silicon-based optoelectronic devices, magnetic materials for inductors,
nanostructure design, and process technology.
Dr. Gardner has received three Best Paper and Poster awards at international
conferences and his recent paper on RF inductors was judged the best at the
IEEE IITC conference.
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Tanay Karnik (M’88–SM’04) received the Ph.D.
degree in electrical and computer engineering from
the University of Illinois at Urbana-Champaign in
1995.
From 1995 to 1999, he worked in the Strategic
CAD Laboratory at Intel Corporation working on
RTL partitioning and special circuits layout. Since
March 1999, he has led the power delivery, soft error
rate, and optoelectronics research in the Circuits
Research, Intel Laboratories. He worked at Larsen
and Toubro (India) Ltd. during 1987–1988 and at
AT&T Bell Laboratories during summer 1994. His research interests are in
the areas of power delivery, soft errors, VRM circuits, optoelectronics, and
physical design. He has published over 25 technical papers and has 10 issued
and 25 pending patents in these areas.
Dr. Karnik serves on the ICCAD, ISQED, DAC, and ICICDT committees.
Vivek De (M’89) received the Ph.D. degree in electrical engineering from Rensselaer Polytechnic Institute, Troy, NY, in 1992.
He is a Senior Principal Engineer and Manager
of Low Power Circuit Technology research at Intel
Labs. in Hillsboro, OR. He is an author of 109
technical papers in refereed international conferences and journals, and three book chapters on
low-power design. He has 56 patents issued, with
50 more patents filed (pending) in low-power and
high-performance circuits and devices.
Dr. De has served as General Chair and Technical Program Chair of the
ISLPED, ISQED, and GLSVLSI conferences, and on the technical program
committees of DAC and ISQED. He also served as the guest editor of a special
issue on low-power electronics for the IEEE TRANSACTIONS ON VERY LARGE
SCALE INTEGRATION (VLSI) SYSTEMS. He was the recipient of a Best Paper
Award at the 1996 International ASIC Conference in Portland, OR.
Shekhar Borkar (M’97) received B.Sc. and M.Sc.
degrees in physics from the University of Bombay,
Bombay, India, in 1977 and 1979, respectively, and
the M.S.E.E. degree from the University of Notre
Dame, Notre Dame, IN, in 1981.
He joined Intel Corporation, Hillsboro, OR, in
1981, where he worked on the design of the 8051
family of microcontrollers, high-speed communication links for the iWarp multicomputer, and Intel
Supercomputers. He is an Intel Fellow, and Director
of Circuit Research in the Intel Laboratories, researching low-power high-performance circuits and high-speed signaling. He
is also an Adjunct Faculty Member of Oregon Graduate Institute, Beaverton,
and teaches digital CMOS VLSI.