System Level ESD/EMI Issues
and Protection Design
Dr. Ryan Hsin-Chin Jiang (
Email: Ryan@amazingic.com
Web: www.amazingic.com
)
Nov. 2012
2012 Nov.
Ryan Hsin-Chin Jiang
1
OUTLINE
1. The Influences of the System Level ESD and EMI
on Electronic Products.
2. The Testing of the System Level ESD.
3. The Protection Design for the System Level ESD.
4. The Testing of the EMI.
5. The Protection Design for the EMI.
2012 Nov.
Ryan Hsin-Chin Jiang
2
OUTLINE
1. The Influences of the System Level ESD and EMI
on Electronic Products.
2. The Testing of the System Level ESD.
3. The Protection Design for the System Level ESD.
4. The Testing of the EMI.
5. The Protection Design for the EMI.
Ryan Hsin-Chin Jiang
2012 Nov.
3
ESD Is So Serious !
Electrostatic Voltage
Means of Static Generation
EndEnd-user’
user’s
environment
Factory’
Factory’s
environment
10% R.H.
40% R.H.
55% R.H.
Person walking across Carpet
35,000 V
15,000 V
7,500 V
Person walking across Vinyl Floor
12,000 V
5,000 V
3,000 V
Worker at a Bench
6,000 V
500 V
400 V
Ceramic DIP in Plastic Tube
2,000 V
700 V
400 V
Ceramic DIP in Vinyl Set-up Trays
11,500 V
4,000 V
2,000 V
IC Packs as Bubble Plastic Cover
is removed
26,000 V
20,000 V
7,000 V
IC Packs as Packed in Foam Lined
Shipping Box
21,000 V
11,000 V
5,500 V
2012 Nov.
Ryan Hsin-Chin Jiang
4
Two Kinds of ESD Testing Standards
Component Level:
• To Simulate the ESD events in a well-controlled
environment, such as factory environment.
• To characterize a component’s (e.g. IC’s) electrostatic
discharge (ESD) susceptibility fully.
• It is not alive testing and it uses damage as testing
criterion.
System Level:
• To Simulate the ESD events in an un-controlled
environment, such as end-user’s environment.
• To characterize a system’s (e.g. Electronic Products)
electrostatic discharge (ESD) susceptibility fully.
• It is alive testing and it uses interference, mal-function, and
damage as testing criteria.
2012 Nov.
Ryan Hsin-Chin Jiang
5
Why System ESD Issue Is More Important?
1. The IC’
IC’s are progressing into nm era, e.g. 90nm, 60nm, 45nm
processes. Transistors are very weak for sustaining ESD event.
2. The system operating voltage is going to low voltage, e.g. 5V 3.3V
2.5V 1.8V 1.2V. Signals are easy to be destroyed due to
ESD transient event.
3. The Aspects of Electronic Products are going into Compact and
Light. ESD event is easy to enter the core circuit regions of the
system.
4. The User’
User’s usage behaviors should be more friendlier, e.g. less
limitation. One popular usage behavior is the hothot-plugging action.
ESD event is easy to be generated.
5. High Quality demand is current vogue. ESD testing specifications
are more stricter!
2012 Nov.
Ryan Hsin-Chin Jiang
6
The Affection of ESD on the System Operation
Current will automatically find
the lowest impedance path.
Shell
The electromagnetic
field generated by ESD
電場
The electromagnetic field
generated by ESD 磁場
kV/m
A/m
15
4
3
Hole
Bad Contact
10
2
10 cm
1
20 cm
50 cm
5
2012 Nov.
10
15
5
時間 ns
Ryan Hsin-Chin Jiang
7
ESD Current Enters to IC from I/O Port
Hot plug on/off,
chip IO diode
damaged
C=0.1uF
signal connector
R=75 ohm
damaged
Chip IO
Chip passed HBM 2kV,
MM 200V test
PCB
System Level ESD Protector
should be placed at here!
2012 Nov.
Ryan Hsin-Chin Jiang
8
ESD Current Enters to IC from Shell
System-Level EMC/ESD Test on
LCD Panel of Notebook by An ESD Gun
System-Level EMC/ESD Test
(Standard IEC 61000-4-2)
Driver ICs with
Tape Carrier Package
Ryan Hsin-Chin Jiang
2012 Nov.
9
FA Pictures of CMOS IC after System-Level ESD Test
OM(Substrate):100x
By Air Discharge (-8000V)
1
2
PAD
PAD
Chip fabricated in a 0.18-µm CMOS process.
2012 Nov.
Ryan Hsin-Chin Jiang
10
FA Pictures of CMOS IC after System-Level ESD Test
By Air Discharge (-8000V)
2012 Nov.
Ryan Hsin-Chin Jiang
11
EM Radiation by ESD
Transient Voltage Waveform on VDD Pin
During System-Level EMC/ESD Test
With ESD voltage of +1000V zapping on HCP, the measured VDD transient waveform on
CMOS IC#1 inside the EUT. VDD waveform acts as a bi-polar voltage (with transient
positive peak voltage of +20V) due to the disturbance of the high ESD-coupled energy.
2012 Nov.
Ryan Hsin-Chin Jiang
12
EM Radiation by ESD
System-Level ESD Test Induced Transient Voltage
on VDD to Cause Latchup Event
2.5V
VDD Pin
0A
IDD
~0A
VDD (5V/div.)
0V
VDD
~2V
0V
0V
~60mA
IDD
0A
0A
Time (400ns/div.)
IDD (40mA/div.)
2.5V
IDD (10mA/div.)
VDD (2V/div.)
2.5V
Time (200ns/div.)
Non Latchup
Transient-Induced Latchup
2012 Nov.
Ryan Hsin-Chin Jiang
13
EM Radiation by ESD
Latchup Failure after System-Level ESD Zapping
Output P-N Spacing
Air-Discharge ESD Zapping
~20µm
~150µm
pass 12kV, failed at 15kV
pass 20 kV
ESD Zapping Overshooting/Undershooting trigger current Latchup
Out
VSS
VCC
Out
2012 Nov.
Ryan Hsin-Chin Jiang
14
EM Radiation by ESD
Software Failure after System-Level ESD Zapping
BIOS Fail
2012 Nov.
Ryan Hsin-Chin Jiang
15
EMI Sources and Consequences
Consequences
EMI Sources
2012 Nov.
Ryan Hsin-Chin Jiang
16
Data Stream Produces Noise Spectrum
2012 Nov.
Ryan Hsin-Chin Jiang
17
2012 Nov.
Ryan Hsin-Chin Jiang
18
EMI Consequences
EMI Consequences
Potential Noise Impact to Operating Range
♦Ref: Lecture of Prof. HanHan-Nien Lin, Communications Engineering Department, Feng Chia University
2012 Nov.
Ryan Hsin-Chin Jiang
19
EMI Sources May Be Cables
Bead for Filtering
Bead for Filtering
♦Ref: Lecture of Prof. HanHan-Nien Lin, Communications Engineering Department, Feng Chia University
2012 Nov.
Ryan Hsin-Chin Jiang
20
EMI Sources May Be Cables
2012 Nov.
Ryan Hsin-Chin Jiang
21
OUTLINE
1. The Influences of the System Level ESD and EMI
on Electronic Products.
2. The Testing of the System Level ESD.
3. The Protection Design for the System Level ESD.
4. The Testing of the EMI.
5. The Protection Design for the EMI.
2012 Nov.
Ryan Hsin-Chin Jiang
22
System-Level ESD Testing Standard
♦ IEC 61000-4-2: Electromagnetic Compatibility (EMC)
Part 4: Testing and measurement techniques
Session 2: Electrostatic discharge immunity Test.
2012 Nov.
Ryan Hsin-Chin Jiang
23
System-Level ESD Gun (IEC/EN 61000-4-2)
Contact discharge head
Air discharge head
2012 Nov.
Ryan Hsin-Chin Jiang
24
HBM v.s. IEC61000-4-2 System ESD Gun Comparison
Current Waveform
HBM
HBM
R
A
B
+
V
_
100pF
1.5kΩ
Ω
HBM Ip
2kV 1.3A
8kV 5.3A
12kV 8A
DEVICE
UNDER
TEST
CHBM= 100pF; RHBM= 1.5kΩ
Ω
IEC61000-4-2 ESD Gun
~5X
IEC
Ip
2kV 7.5A
6kV 22.5A
8kV 30A
2012 Nov.
Ryan Hsin-Chin Jiang
25
Electronics System-Level ESD Test Levels
♦IEC 61000-4-2 Test Levels
2012 Nov.
Ryan Hsin-Chin Jiang
26
Set-up of System-Level ESD Test
♦Test Set-up
System is tested
under normal
operation condition!
2012 Nov.
Ryan Hsin-Chin Jiang
27
Electronics System-Level ESD Test Criteria
Class
Criterion
Result
Class A
No abnormal phenomenon
occurs during ESD stress
Pass
More popular
Criterion for High
Quality Products!
Abnormal phenomenon
Class B occurs during ESD stress, but
will recover automatically
Pass
Class C
Abnormal phenomenon
occurs after ESD stress,
manual restart is needed
Pass/
Fail
Class D
Hardware damage
Fail
2012 Nov.
Ryan Hsin-Chin Jiang
28
Hot Plug Could Induce Cable Discharge
Deep submicron & Nano meter
process IC is weak to ESD &
Cable Discharge Event.
2012 Nov.
Ryan Hsin-Chin Jiang
29
Cable Discharge Event
♦ Tribocharging
Cable frictionizes with floor.
♦ Induced charging
Cable carries high voltage signal.
Cable is placed in electric field
♦ Induced voltages
If a cable is subjected by the field of a strong pulse (e.g., a
lightning stroke, ESD close to the cable) a momentary
voltage will be introduced along the cable.
2012 Nov.
Ryan Hsin-Chin Jiang
30
IEEE 802.3 Cable Discharge Ad-Hoc
• Direct Pin Injection Contact
Discharge Test is necessary for
evaluating the immunity to Cable
Discharge Event!
2012 Nov.
Ryan Hsin-Chin Jiang
31
Direct Pin Injection Contact Discharge Test
2012 Nov.
Ryan Hsin-Chin Jiang
32
OUTLINE
1. The Influences of the System Level ESD and EMI
on Electronic Products.
2. The Testing of the System Level ESD.
3. The Protection Design for the System Level ESD.
4. The Testing of the EMI.
5. The Protection Design for the EMI.
Ryan Hsin-Chin Jiang
2012 Nov.
33
ESD Protection Issue in Nanoscale CMOS ICs
(ISCAS’05)
2012 Nov.
Ryan Hsin-Chin Jiang
34
ESD Protection Issue in Nanoscale CMOS ICs
18
16
gate-oxide breakdown voltage
Voltage (V)
14
12
10
8
6
4
2
How to effectively protect the
much thinner gate oxide in the
nanoscale CMOS ICs ?
♦IC
(100-ns Pulse)
?
LNPN trigger voltage
0.1
0.25
0.13
Technology Generation (µ
µm)
Ref: A. A. Salman et al., “ESD-Induced Oxide
Breakdown on Self-Protecting GG-nMOSFET
in 0.1-µm CMOS Technology,” IEEE T-DMR,
vol. 3, pp. 79-84, Sept. 2003.
2012 Nov.
Ryan Hsin-Chin Jiang
35
A Field Return Case
Hot plug on/off,
chip IO diode
damaged
C=0.1uF
signal connector
R=75 ohm
damaged
Chip IO
PCB
Chip passed HBM 2kV,
MM 200V test
System Level ESD Protector
should be placed at here!
This case tells two things:
1. Component level performance can’
can’t guarantee System level performance.
2. Cable Discharge Event exists practically.
2012 Nov.
Ryan Hsin-Chin Jiang
36
Another Field Return Case
• Chip passed Latchup test, but Latchup still happened after
System Level ESD test. So called Transient Latchup Issue.
SCR path stays at ON.
2012 Nov.
Ryan Hsin-Chin Jiang
37
System Level ESD Protector Is Necessary
Shell
Transient Voltage passes to VDD trace on PCB
IC
GND
ESD Protector
VDD
Necessary!
PCB
2012 Nov.
Ryan Hsin-Chin Jiang
38
Two Regions on a System Need ESD Protectors
I/O ports
Critical
Power/Control/Signal
Lines
2012 Nov.
Ryan Hsin-Chin Jiang
39
The Function of ESD Protection Device
I/O port of a Product
♦ Prevent the operation of an Electronic Product from the
disturbance of ESD event. - Bypass the ESD current
and
Clamp the voltage at a low value.
2012 Nov.
Ryan Hsin-Chin Jiang
40
The Operation of TVS Device
System malmal-function threshold
Prevent System from Malfunction!
TVS’s Clamping Voltage is the most important parameter.
Different Systems have different “system malmal-function threshold”
threshold” values.
2012 Nov.
Ryan Hsin-Chin Jiang
41
TVS’s Clamping Voltage
ESD Current waveform
For ESD event:
During TVS is bypassing ESD current,
its terminal voltage is the ESD Clamping
High freq.
Voltage
Lower Clamping Voltage means greater
ESD protection performance.
For Lightning(Surge)
Lightning(Surge) event:
During TVS is bypassing Lightning current,
its terminal voltage is the Lightning
Low freq.
Clamping Voltage
Lower Clamping Voltage means greater
Lightning Current waveform
Lightning protection performance.
2012 Nov.
Ryan Hsin-Chin Jiang
42
How to Measure the Clamping Voltage of TVS Device ? (I)
Not Proper !
2012 Nov.
Ryan Hsin-Chin Jiang
43
How to Measure the Clamping Voltage of TVS Device ? (II)
The Proper
Method:
Transmission
Line Pulsing (TLP)
System
2012 Nov.
Ryan Hsin-Chin Jiang
44
An Example of TLP I-V Curve
♦ When ITLP=IESD= 16A (~ESD
Transmission Line Pulsing (TLP) Measurement
20
5kV), the TVS’
TVS’s ESD clamping
18
voltage VCL = 12V.
16
V_pulse
14
♦ When ITLP=IESD= 6A (~ESD
Pulse from a
transmission line
12
2kV), the TVS’
TVS’s ESD clamping
TLP_I
+
100ns
10
TLP_V
8
voltage VCL = 8.75V.
DUT
-
6
4
I/O to GND
2
0
2
4
6
8
10
12
14
Transmission Line Pulsing (TLP) Voltage (V)
Ryan Hsin-Chin Jiang
2012 Nov.
45
S xxxx
xx
Px
xx x
xx
Cxx x
AZ1015--04S
AZ1015
Sx
Clamping Voltage Comparison by TLP Measurement
TLP: Transmission Line Pulsing
Transmission Line Pulsing (TLP) Current (A)
0
Stress condition:
I/O vs. GND
2012 Nov.
Ryan Hsin-Chin Jiang
46
TLP Clamping Voltage Determines the System ESD Performance
Put ESD Protect IC
@ USB Port
Contact Discharge @ USB ports of PCB
(Class-A)
Self Recover Errors (Class( X: error happened, V: pass))
Parts
±600V
(contact)
±1kV
(contact)
±2kV
(contact)
±4kV
(contact)
Cxxxx
X
---
---
---
Pxxxxxx
X
---
---
---
Sx
V
V
X
---
AZ1015AZ1015-04S
V
V
V
V
2012 Nov.
Ryan Hsin-Chin Jiang
47
Ryan Hsin-Chin Jiang
48
The Clamping Types of TVS Devices
gnd
gnd
Unipolar
Bipolar
2012 Nov.
TVS’s Lightning Clamping Voltage Measurement
TVS’
TVS’s Lightning (8us/20us) Clamping Voltage can be measured by using
oscilloscope. This is because Lightning pulse (<1MHz) is a low freq
freq
noise.
GND
2012 Nov.
Ryan Hsin-Chin Jiang
49
TVS’s Peak Pulse Power (to Lightning Waveform, 8/20us)
TVS’
TVS’s Peak Pulse Power
Ppk = Ipp x Vclamp
Ipp
Vclamp
the max. lightning Current that TVS can bypass
the terminal voltage during TVS is bypassing the max. lightning
Current.
TVS’s Peak Pulse Power is Not an important parameter. It
easily makes users choose wrong TVS.
For example
TVSTVS-1 : Ipp =12 A, Vclamp = 8V, Power = V*I =96W
TVSTVS-2 : Ipp = 12A, Vclamp = 20V, Power = V*I =240W
Do you think which one has better protection performance?
Answer is the TVSTVS-1, which Vclamp is lower.
If you use Power as your selection criterion, you will choose TVS
TVS-2! But,
its protection performance is poor than that of TVSTVS-1.
2012 Nov.
Ryan Hsin-Chin Jiang
50
The Types of ESD Protection devices
♦Transient Voltage Suppressors (TVS)
♦Varistor
♦Zener diode
♦Diode
♦The main function of TVS is to absorb high peak power as a surge device.
♦It also can be an ESD protector.
♦
♦
Advantages
Single channel, 2 terminals, easy to use.
Cheap.
Disadvantages
Clamping Voltage is high.
C load is big, not suitable for high speed
application.
2012 Nov.
Ryan Hsin-Chin Jiang
51
The Types of ESD Protection devices (cont’d)
♦Integrated ESD protection array
♦Zener diode array
♦Regular Diodes array
♦Special designed array
♦ Advantages
Multiple channels.
Small size.
C load could be low, suitable for high
speed applications.
♦ Disadvantages
Cost is a little of higher than TVS.
Board has to be prepre-designed for use.
2012 Nov.
Ryan Hsin-Chin Jiang
52
Varistor Materials
♦ Varistors are made from ceramic materials.
materials. The predominant Varistor
type has a main component which is Zinc Oxide (ZnO
). To this are
(ZnO).
added small amounts of other oxides such as Bismuth, Cobalt,
Manganese and others.
♦ Accordingly, Varistors are sometime known as Metal Oxide Varistors or
MOVs.
MOVs.
♦ A given Varistor specification may be satisfied by a variety of material
formulations.
Ceramic
2012 Nov.
Ryan Hsin-Chin Jiang
53
The Features of Varistor
Positive
♦ Cheap.
♦ Can handle large currents.
Negative
♦ Resistance characteristic is non linear.
♦ The voltage drop across the varistor will increase
dramatically as the current increases.
♦ It ages as the ZnO particles weaken
after conducting current.
♦ Slow in circuit response time, > 35 nsec.
♦ ESD Clamping Voltage is High, hard to help to pass
Class-A test.
2012 Nov.
Ryan Hsin-Chin Jiang
54
The Most Popular Varistor Formates
♦ The Surface Mount (SM) type, which are produced in Multilayer Chip
format, refer as MultiLayer Varistor (MLV).
(MLV).
♦ Industry standard sizes are the same as those for Capacitors and
Resistors, These range are from 0603 (length 1.5 mm x width 0.75 mm)
through 2220 (5.5 mm x 5.0 mm).
♦ The Operating voltages are from 3.5 to 120 volts dc.
dc.
2012 Nov.
Ryan Hsin-Chin Jiang
55
The Characteristics of TVS Diodes (Zener)
♦ Ideally the TVS diode(Zener)
diode(Zener) appears as an open circuit,
circuit, although there is a
small amount of leakage current present. When a transient appears on the
line the TVS Diode(Zener)
Diode(Zener) becomes active,
active, clamping the pulse to level that
will not damage the component it is protecting.
protecting.
+
Protection
working area
V
-
I
2012 Nov.
Ryan Hsin-Chin Jiang
56
The Structure of TVS Diodes
+
V
-
I
♦ The depletion region is only a 100nm thick forcing most
energy dissipation into a very thin region at the surface of
the diode.
2012 Nov.
Ryan Hsin-Chin Jiang
57
The Formats of TVS Diodes
Axial Leads
Surface Mount
Usually for Surge purpose
Usually for ESD protection purpose
2012 Nov.
Ryan Hsin-Chin Jiang
58
The Features of TVS Diodes
Positive
♦ Fast in circuit response time, < 5 nsec.
nsec.
♦ Can conduct their maximum current without any increase in clamp
voltage.
voltage.
♦ No age issue, as long as their parameters are not exceeds.
♦ Dominate in low voltage transient suppressor applications, due to
to
their low clamping voltage.
Negative
♦ Expensive than Varistor.
Varistor.
♦ The handling maximum transient current is less than that of Varistor.
Varistor.
♦ The capacitance is high for high speed applications, typically > 25pF.
♦ Discrete Zener diodes always suffer the high dynamic turnturn-on
resistance which make them have high clamping voltage under high
ESD level stress.
2012 Nov.
Ryan Hsin-Chin Jiang
59
TVS Diodes Array
TVS Diodes Array is an
integrated multi-channels ESD
protection device
♦ Advantages
Multiple channels.
Let System size be small.
C load could be low, suitable for high speed applications.
2012 Nov.
Ryan Hsin-Chin Jiang
60
Application Examples of TVS Diodes Array
Varistors
TVS Arrays
Diodes
TVS Arrays
♦Save Board Area!
♦Save Total System Cost!
Ryan Hsin-Chin Jiang
2012 Nov.
61
Varistor, TVS Diode, and TVS Diode Array
Varistor
TVS Diode
TVS Diode Array
Response Time
Slow
Fast
Fast
Clamp Voltage
High
Low
Low
Peak ESD Current
High
C_load
High
Medium
Low
Heat Sink
Good
Fare
Fare
Individual Cost
Low
Low
High
System Cost
High
High
Low
Lower, but Enough Lower, but Enough
2012 Nov.
Ryan Hsin-Chin Jiang
62
TVS Array in Computer Systems
Card
Reader
South
Bridge
Audio
CPU
North
Bridge
USB 2.0
10M/100M/
1G LAN
IEEE
1394
PS2
Print Port
DVI
VGA
2012 Nov.
HDMI
SATA
Ryan Hsin-Chin Jiang
63
Ryan Hsin-Chin Jiang
64
TVS Array in LCD Display Systems
2012 Nov.
TVS Array in Portable Systems
Mic
LED
Speaker
Ext. Memory
Card
LCD
Interface
Keypad
Volumn Adj/
ON/OFF
Battery
Serial Port
USB/OTG
2012 Nov.
Ryan Hsin-Chin Jiang
65
Single TVS Array for One USB3.0 Port (for 8kV contact ESD)
♦One TVS Array protect whole USB3.0 port with Lower Signal Loss
Typical Variation of CIN vs. VIN
0.50
f = 1MHz, T=25 oC,
0.45
The 5GHz Eye Diagram when
AZ1065-06F is used.
0.40
0.35
VDD=Floated
0.30
Input Capacitance (pF)
0.25
0.20
0.0
VDD=5V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Input Voltage (V)
2012 Nov.
Ryan Hsin-Chin Jiang
66
TVS Arrays for HDMI port (for 8kV contact ESD)
TMDS_D2+
TMDS_D2+
Via hole to GND
TMDS_GND
3
TMDS_D2-
TMDS_D2-
GND
2
1
AZ1045-04SU
TMDS_D1+
4
TMDS_GND
5
+5V
TMDS_D1-
6
TMDS_D1+
Via hole to +5V
C=100nF
(optional)
Via hole to GND
TMDS_D1-
TMDS_D0+
TMDS_D0+
Via hole to GND
TMDS_GND
3
TMDS_D0-
GND
2
1
TMDS_D0AZ1045-04SU
TMDS_CK+
4
TMDS_GND
5
+5V
6
TMDS_CK+
Via hole to +5V
TMDS_CK-
Via hole to GND
C=100nF
(optional)
CE_REMOTE
TMDS_CKCE_REMOTE
Via hole to GND
N/C
3
DDC_CLK
GND
2
DDC_CLK
1
AZC099-04S
DDC_DAT
4
GND
5
+5V
6
DDC_DAT
Via hole to +5V
+5V OUT
Via hole to GND
C=100nF
(optional)
HOTPLUG_DET
HOTPLUG_DET
HDMI
Connector
2012 Nov.
Ryan Hsin-Chin Jiang
67
VDD
5
Green
Red
1
5
11
15
V -Sync
H-Sync
2
3
AZ1015-04S
1
GND
Red
Video
Filter
Green
Green
VCC
Red
6
5
4
DDC DAT
6
5
VDD
VCC
Red
75Ω
Ω
4
Blue
DDC CLK
Video
Filter
Green
Blue
75Ω
Ω
1
Video
Filter
2
Blue
* optional
0.1uF or 0.01uF
chip capacitor for filtering
high-frequency ESD noise DDC_CLK VCC
75Ω
Ω
FB
FB
FB
4
FB
VSYNC
VCC
3
6
Signals From Scaler
2
AZ1015-04S
1
GND
VCC
TVS Arrays for VGA port (for 3kV ~ 8kV contact ESD)
3
VSYNC
Blue
HSYNC
DDC_Data
VSYNC
DDC_CLK
6
5
4
DIG_GND
HSYNC
Red_GND
DDC_Data
Green_GND
DDC_CLK
1
2
3
DDC_Data
HSYNC
Blue_GND
GND
15-pin
VGA connector
♦AZC099AZC099-04S Lower Price
Pick &
Place!
♦AZC002AZC002-04S
♦AZC015AZC015-04S
♦AZ1015AZ1015-04S
♦AZ1045AZ1045-04S
Higher ESD spec.
& Higher Criterion.
TVS arrays
2012 Nov.
Ryan Hsin-Chin Jiang
68
TVS Arrays for DVI port (for 3kV ~ 8kV contact ESD)
3
4
common mode
choke
1
2
TMDS_D2+ VCC
VCC
common mode
choke
1
2
TMDS-D2-
6
5
VCC
CKT24
TMDS_D2+
TMDS-D1-
3
4
2
3
TMDS-D1+
TMDS_D1+
* optional
0.1uF or 0.01uF
chip capacitor for filtering
high-frequency ESD noise
TMDS-D0TMDS-D1+
VCC
TMDS_D0+
TMDS_D1-
VCC
TMDS_D0-
6
5
4
1
2
3
TMDS_D1CKT1
TMDS_D1+
TMDS_D0TMDS_D0+
common mode
choke
1
2
3
4
0.1uF
TMDS_CKTMDS-CKTMDS-CK+
FB
VCC
DDC_Data
6
VCC
5
DDC_CLK
4
DDC_Data
Place!
TMDS DATA 0TMDS DATA 0+
Pick &
TMDS DATA 1TMDS DATA 1+
♦AZC099AZC099-04S Lower Price
TMDS DATA 2TMDS DATA 2+
Detect
DVI_D
connector
+5V Power
3
DDC CLK
2
DDC DATA
GND
1
Hot Plug Detect
Detect
Detect
TMDS DATA CLK+
TMDS DATA CLK-
FB
DDC_Data
0.1uF
AZC099-04S
FB
DDC_CLK
AZC099-04S
TMDS_CK-
TMDS_CK+
DDC_CLK
0.1uF
TMDS_CK+
AZC099-04S
Signals From Scaler
4
4
TMDS_D21
3
common mode
choke
1
2
TMDS_D2-
TMDS-D2+
TVS arrays
♦AZC002AZC002-04S
♦AZC015AZC015-04S
♦AZ1015AZ1015-04S
♦AZ1045AZ1045-04S
Higher ESD spec.
& Higher Criterion.
2012 Nov.
Ryan Hsin-Chin Jiang
69
TVS Arrays for Mobile Phone
♦Mobile Phone Application (pass 12kV Air ESD)
TVS arrays on
Internal Buses
TVS arrays on Low
Speed I/O Port
2012 Nov.
Ryan Hsin-Chin Jiang
70
OUTLINE
1. The Influences of the System Level ESD and EMI
on Electronic Products.
2. The Testing of the System Level ESD.
3. The Protection Design for the System Level ESD.
4. The Testing of the EMI.
5. The Protection Design for the EMI.
Ryan Hsin-Chin Jiang
2012 Nov.
71
EMI
10 m
1-4m
EMI
0.8 m
2012 Nov.
Ryan Hsin-Chin Jiang
72
Spurious emissions Test Set-Up, Frequency Below 1000MHz
2012 Nov.
Ryan Hsin-Chin Jiang
73
Spurious emissions Test Set-UP Frequency Over 1 GHz
2012 Nov.
Ryan Hsin-Chin Jiang
74
EMI
0.8 m
0.8 m
EMI
0.4 m
EMI
EMI
2012 Nov.
LISN
ISN
Ryan Hsin-Chin Jiang
75
Reference Plane
Test Receiver
40cm
EUT
Load
Non-conducted
table
80cm
LISN
LISN
Ground Plane
2012 Nov.
Ryan Hsin-Chin Jiang
76
LISN circuit per line
2012 Nov.
LISN
Ryan Hsin-Chin Jiang
77
Ryan Hsin-Chin Jiang
78
EMI
2012 Nov.
OUTLINE
1. The Influences of the System Level ESD and EMI
on Electronic Products.
2. The Testing of the System Level ESD.
3. The Protection Design for the System Level ESD.
4. The Testing of the EMI.
5. The Protection Design for the EMI.
Ryan Hsin-Chin Jiang
2012 Nov.
−Radio Transmitter (Broadcast,
Communication, Navigation,
Radar)
−Receiver Local Oscillators
−Motors, Switches, Fluorescent
Lights,
Diathermy, Arc Welders
−Engine Ignition, Computer &
Peripherals
−Natural Source; Lightning,
Electrostatic Discharge (ESD)
−Radio Receivers
−Analog Sensors and
Amplifiers
−Industrial Control Systems
−Computer
−Ammunition and
Ordnance
−Human Beings ( Radiation
Hazards)
EMI
(
2012 Nov.
79
)
Ryan Hsin-Chin Jiang
80
Receiver Local Oscillators
radios operate
< 0.5 * clock
SOURCE
cellular phones
2th harmonic
Motors, Switches
Fluorescent Lights
Source =
high technology,
fast microprocessors
e.g. 400 MHz PC’s
Communication,
Navigation, Radar
(350 MHz for workstations)
Engine Ignition
:HP
2012 Nov.
Ryan Hsin-Chin Jiang
81
2012 Nov.
Ryan Hsin-Chin Jiang
82
Core and I/O circuits
Ryan Hsin-Chin Jiang
2012 Nov.
83
Fourier Series Expansion
x(t)
A
τ
A/2
-T
τr
T
τf
t
0 dB / decade
-20 dB / decade
-40 dB / decade
♦
1/πτ 1/πτr
2012 Nov.
f
Ryan Hsin-Chin Jiang
84
Trapezoidal pulse train of 1V, 10 MHz, 50% duty cycle for 20 ns rise/fall time
2012 Nov.
Ryan Hsin-Chin Jiang
85
Measured spectral of trapezoidal pulse train (20 ns rise/fall time)
2012 Nov.
Ryan Hsin-Chin Jiang
86
Trapezoidal pulse train of 1V, 10 MHz, 50% duty cycle for 5 ns rise/fall time
2012 Nov.
Ryan Hsin-Chin Jiang
87
Measured spectral of trapezoidal pulse train (5 ns rise/fall time)
2012 Nov.
Ryan Hsin-Chin Jiang
88
1.
(Spectrum
Management)
4.
(grounding)
5.
(Layout Design)
Field
3.
(shielding)
Conducted
filter
(
)
2.
(Filter)
2012 Nov.
Ryan Hsin-Chin Jiang
89
Ryan Hsin-Chin Jiang
90
Four Ways to Reduce the EMI
1. On-Chip Design
2. PCB Layout Design
3. Shielding Design
4. Placing Filter
2012 Nov.
On-Chip Decouple Capacitors
Vertical, before onon-Chip DeDe-Cap.
Horizontal, before onon-Chip DeDe-Cap.
Vertical, after onon-Chip DeDe-Cap.
Horizontal, after onon-Chip DeDe-Cap.
2012 Nov.
Ryan Hsin-Chin Jiang
91
Ryan Hsin-Chin Jiang
92
On-Chip Slew Rate Control of Clock
No Cext
Cext = 20pF
2012 Nov.
On-Chip Spread Spectrum Clocking
2012 Nov.
Ryan Hsin-Chin Jiang
93
EMI Sources, Consequences, and Solutions
Consequence
EMI Sources
Solution
2012 Nov.
w/ EMI Filter
Ryan Hsin-Chin Jiang
94
EMI Solution by Using Filter
Waveform, with Filter
Using filter on data lines in GSM, Evaluated the
improvement in RF Limit Level (Error Rate > 0%)
w/ Filter
Waveform, no Filter
Bit Error Rate
♦Ref: Lecture of Prof. HanHan-Nien Lin, Communications Engineering Department, Feng Chia University
2012 Nov.
Ryan Hsin-Chin Jiang
95
2012 Nov.
Ryan Hsin-Chin Jiang
96
EMI Solution by Using Filter
EMI Filter Integrated with ESD Protector in Mobile Phone
EMI Filter Integrated
with ESD Protector
EMI Filter Integrated
with ESD Protector
2012 Nov.
Ryan Hsin-Chin Jiang
97
Summary
• ESD event can not be erased from nature.
• To reduce the returned fail rate of a electronic product
and maintain high quality image, ESD testing spec should
go to more stricter.
• Using TVS arrays makes the High ESD protection design
be Easy and Reusable.
• Using TVS arrays can save the total cost of the system
product.
• Using TVS solutions have the best flexibility
regarding to the Trade-off between ESD
Performance and Cost .
2012 Nov.
Ryan Hsin-Chin Jiang
98
-5
(2010/08/01
)
GUTOR
GUTOR
2012 Nov.
Ryan Hsin-Chin Jiang
99