16-bit Pipeline ADC, 150 MSPS XT018 DATA SHEET FEATURES TI-16PI/150M FUNCTIONAL BLOCK DIAGRAM 16-bit resolution Sample rate: up to 180 MSPS Differential input range: up to 1.25 V p-p Effective number of bits at 100 MHz input: 12.7 bits Input signal bandpass: up to 180 MHz HIGHLIGHTS Dual channel fully differential architecture Radiation tolerant implementation Built-in calibration state machine for offset and gain calibration Ability of setting of output data to LVDS (ANSI-644) or CMOS mode Output clock for output data processing Built-in serial peripheral interface (SPI) for parameters tuning including Speed-toPower Consumption ratio trimming Separate analog and digital power supplies (5 V and 1.8 V correspondingly) APPLICATIONS Space applications Communications SDR receivers Test and instrumentation DELIVERABLES Datasheet GDSII database Customer support GENERAL DESCRIPTION This TI-16PI/150M is a dual-channel fully differential 16-bit analog-to-digital converter with pipelined architecture optimized for high dynamic performance at sample rates up to 180 MSPS. The ADC was designed with using of an interleaved channels algorithm providing high speed of the ADC. An internal calibration state machine implementing an algorithm of consequent calibration of offset and gain of pipeline stages and Sample and Hold circuit provides channels accuracy matching and high dynamic and static characteristics of the ADC. An integrated serial peripheral interface allows a user to configure easy the ADC including automatic calibration results control and tuning of main parameters of the state machine and the internal current sources. While operating at lower frequencies the total power consumption of the ADC can be reduced up to 50% by decreasing of current generated by the internal sources and up to additional 50% by using only one of the two conversion channels. CJSC «Thesys-Intechna» 69 Svobody St Voronezh 394006 Russia 1/6 info@thesys-intechna.com thesys-intechna.com TI-16PI/150M ф SHEET DATA LIST OF CONTENTS Features Highlights Functional block diagram Applications Deliverables General description Device parameters Pin configuration Pin functional description CJSC «Thesys-Intechna» 69 Svobody St Voronezh 394006 Russia 1 1 1 1 1 1 3 4 5 2/6 info@thesys-intechna.com thesys-intechna.com TI-16PI/150M ф SHEET DATA DEVICE PARAMETERS VDDA = 4.75..5.25 V; VDDD = 1.62..1.98 V; VREFP = VDDA; VREFM = 0; VCM = 0.5*VDDA; FCLK = 100 MHz; T = -40..110 0 С, unless otherwise noted. Symbol Parameter Min Typ Max Unit Power supplies VDDA Analog supply 4.75 5 5.25 V VDDD Digital supply 1.62 1.8 1.98 V 1.5 2.5 W Power consumption PDD Power consumption 1.4 Accuracy N Resolution 16 Bits INL Integral nonlinearity -3.5 +3.5 LSB DNL Differential nonlinearity -1.5 +1.5 LSB OE Offset error -5 +5 LSB Dynamic parameters FINmax Maximum analog input bandwidth 150 180 MHz FSmax Maximum sample rate 150 180 MSPS DLY ENOB Latency of pipeline 15 Cycles Effective number of bits FIN=100 MHz 12.1 12.7 Bits SNR Signal-to-noise ratio FIN=100 MHz 72 78 dB SINAD Signal-to-noise-anddistortion FIN=100 MHz 72 78 dB SFDR Spurious-free dynamic range FIN=100 MHz 80 85 dB 1.25 Vp-p 6 pF Analog inputs DVIN Input voltage range CIN Equivalent input capacitance RIN Equivalent input resistance 0.5 0.6 5 100 Ohm All the device parameters are guaranteed under the post-layout simulation at all admissible values of power and temperature (-40..+110 0 С) considering possible process deviations in range of 3sigma. CJSC «Thesys-Intechna» 69 Svobody St Voronezh 394006 Russia 3/6 info@thesys-intechna.com thesys-intechna.com TI-16PI/150M ф SHEET DATA VDDA VSSA VDDA VSSA EN_INT_CLK EN_IEXT EN_IEXT_LVDS EN_CMOS 55 SCLK 54 53 52 51 56 MISO 58 N_SS 57 MOSI 60 DONE 59 NRST_I 61 RECAL 62 EN1 63 EN0 65 GNDD 64 n0E 68 VDDD 67 GNDD 66 VDDD 69 IMEAS_120uA 70 IEXT_120uA 71 IEXT_10uA 72 VEXT_IV25 75 VREFPCW 74 VREFMSW 73 VCO_IN PIN CONFIGURATION 76 77 78 79 50 VDD_LVDS 49 VSS_LVDS 48 CLK_OUT47 CLK_OUT+ VDDF 80 46 VSS_LVDS VSSF 81 VDDA 82 45 D-<0> 44 D+<0> 43 D-<1> VSSA 83 VREFP 84 42 D+<1> VREFM 85 VCM 86 41 D-<2> 40 D+<2> 39 D-<3> VINP 87 VCM 88 38 D+<3> VINM 89 90 91 92 93 94 33 D-<5> 32 D+<5> VSSF 95 31 D-<6> VDDF 96 VSSA 97 VDDA 98 30 D+<6> 29 D-<7> 28 D+<7> 27 VSS_LVDS Pin 1 identifier D+<8> 24 D-<8> 25 D-<10> 21 D+<9> 22 D-<9> 23 D+<10> 20 VSS_LVDS 19 D-<11> 17 VDD_LVDS 18 D-<12> 15 D+<11> 16 D-<13> 13 D+<12> 14 D-<14> 11 D+<13> 12 D-<15> 9 D+<14> 10 D+<15> 8 VCO_OUT- 7 26 VDD_LVDS VCO_OUT+ 6 VDD_LVDS 1 VSS_LVDS 2 CLK_IN+ 3 VSSA 99 VDDA 100 36 VDD_LVDS 35 D-<4> 34 D+<4> CLK_IN- 4 VSS_LVDS 5 VCM VREFM VREFP VSSA VDDA 37 VSS_LVDS Figure 1. Pin configuration CJSC «Thesys-Intechna» 69 Svobody St Voronezh 394006 Russia 4/6 info@thesys-intechna.com thesys-intechna.com TI-16PI/150M ф SHEET DATA PIN FUNCTIONAL DESCRIPTION Pin name Description VDD_LVDS Supply for input/output buffers or LVDS receivers/transmitters VSS_LVDS Ground for input/output buffers or LVDS receivers/transmitters CLK_IN+ Clock input (+) CLK_IN- Clock input (-) Comments Typical value: 2.5 V VCO_OUT+ Output for VCO (voltage-controlled oscillator) frequency control (+) Debug output VCO_OUT- Output for VCO frequency control (-) Debug output D+<15:0> Digital output data <15:0> (+) D-<15:0> Digital output data <15:0> (-) CLK_OUT+ Clock output (+) CLK_OUT- Clock output (-) EN_CMOS Digital inputs/outputs mode selecting High level – CMOS active; Low level – LVDS active Debug input; EN_IEXT_LVDS Enable external current source for generating of LVDS receivers/transmitters bias currents active level - high EN_IEXT Enable external current source for generating of pipeline bias currents Debug input; active level - high EN_INT_CLK Debug input; Enable VCO active level - high SCLK Clock input of SPI slave interface MISO SPI slave interface output MOSI SPI slave interface input N_SS SPI slave interface select input Active level - low Reset signal Active level - low DONE «End of calibration» signal output Active level - high RECAL Recalibration signal Active level - high EN1 Enable the accessory pipeline Active level - high EN0 Enable the main pipeline Active level - high nOE Disable outputs (high impedance mode) Active level - high NRST_I CJSC «Thesys-Intechna» 69 Svobody St Voronezh 394006 Russia 5/6 info@thesys-intechna.com thesys-intechna.com TI-16PI/150M ф SHEET DATA PIN FUNCTIONAL DESCRIPTION (continued) Pin name Description GNDD Digital ground VDDD Digital supply IMEAS_120uA IEXT_120uA IEXT_100uA VEXT_1V25 VCO_IN Comments Typical value: 1.8 V Output for VCO current control Input for OPA (operational amplifier) external current source connection Input for OPA (operational amplifier) external current source connection External common-mode voltage for LVDS Voltage for VCO Debug output Debug input; typical value: 120 uA Debug input; typical value: 100 uA Typical value: HighZ Debug input VREFMSW Output for gain tuning control (-) Debug output VREFPSW Output for gain tuning control (+) Debug output VDDA Analog supply VSSA Analog ground VDDF Clock module supply VSSF Clock module ground Typical value: 5 V Typical value: 5 V VREFP High reference voltage Typical value: 5 V VREFM Low reference voltage Typical value: 0 V VCM Common-mode voltage Typical value: 2.5 V VINP Analog input (+) VINM Analog input (-) CJSC «Thesys-Intechna» 69 Svobody St Voronezh 394006 Russia 6/6 info@thesys-intechna.com thesys-intechna.com