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Jameco Part Number 1753768
LTC1744
14-Bit, 50Msps ADC
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FEATURES
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DESCRIPTIO
The LTC ®1744 is a 50Msps, sampling 14-bit A/D converter designed for digitizing high frequency, wide dynamic
range signals. Pin selectable input ranges of ±1V and ±1.6V
along with a resistor programmable mode allow the
LTC1744’s input range to be optimized for a wide variety
of applications.
Sample Rate: 50Msps
77dB SNR and 87dB SFDR (3.2V Range)
73.5dB SNR and 90dB SFDR (2V Range)
No Missing Codes
Single 5V Supply
Power Dissipation: 1.2W
Selectable Input Ranges: ±1V or ±1.6V
150MHz Full Power Bandwidth S/H
Pin Compatible Family
25Msps: LTC1746 (14 Bit), LTC1745 (12 Bit)
50Msps: LTC1744 (14 Bit), LTC1743 (12 Bit)
65Msps: LTC1742 (14 Bit), LTC1741 (12 Bit)
80Msps: LTC1748 (14 Bit), LTC1747 (12 Bit)
48-Pin TSSOP Package
The LTC1744 is perfect for demanding communications
applications with AC performance that includes 77dB
SNR and 87dB spurious free dynamic range. Ultralow jitter
of 0.3psRMS allows undersampling of IF frequencies with
excellent noise performance. DC specs include ±4LSB
maximum INL and no missing codes over temperature.
The digital interface is compatible with 5V, 3V and 2V logic
systems. The ENC and ENC inputs may be driven differentially from PECL, GTL and other low swing logic families or
from single-ended TTL or CMOS. The low noise, high gain
ENC and ENC inputs may also be driven by a sinusoidal
signal without degrading performance. A separate output
power supply can be operated from 0.5V to 5V, making it
easy to connect directly to any low voltage DSPs or FIFOs.
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APPLICATIO S
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Telecommunications
Receivers
Base Stations
Spectrum Analysis
Imaging Systems
The TSSOP package with a flow-through pinout simplifies
the board layout.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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BLOCK DIAGRA
50Msps, 14-Bit ADC with a ±1V Differential Input Range
OVDD
0.1µF
AIN+
±1V
DIFFERENTIAL
ANALOG INPUT
S/H
CIRCUIT
AIN–
CORRECTION
LOGIC AND
SHIFT
REGISTER
14-BIT
PIPELINED ADC
14
OUTPUT
LATCHES
•
•
•
0.5V TO 5V
0.1µF
OF
D13
D0
CLKOUT
OGND
SENSE
BUFFER
VDD
RANGE
SELECT
VCM
1µF
1µF
5V
1µF
DIFF AMP
GND
2.5VREF
CONTROL LOGIC
4.7µF
1744 BD
REFLB
0.1µF
1µF
REFHA
4.7µF
REFLA
0.1µF
1µF
REFHB ENC
ENC
MSBINV
OE
DIFFERENTIAL
ENCODE INPUT
1744f
1
LTC1744
W
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PACKAGE/ORDER INFORMATION
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OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................ 6V
Analog Input Voltage (Note 3) .... – 0.3V to (VDD + 0.3V)
Digital Input Voltage (Note 4) ..... – 0.3V to (VDD + 0.3V)
Digital Output Voltage ................. – 0.3V to (VDD + 0.3V)
OGND Voltage ..............................................– 0.3V to 1V
Power Dissipation ............................................ 2000mW
Operating Temperature Range
LTC1744C ............................................... 0°C to 70°C
LTC1744I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
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ABSOLUTE MAXIMUM RATINGS
ORDER PART
NUMBER
TOP VIEW
SENSE
VCM
GND
AIN+
AIN–
GND
VDD
VDD
GND
REFLB
REFHA
GND
GND
REFLA
REFHB
GND
VDD
VDD
GND
VDD
GND
MSBINV
ENC
ENC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OF
OGND
D13
D12
D11
OVDD
D10
D9
D8
D7
OGND
GND
GND
D6
D5
D4
OVDD
D3
D2
D1
D0
OGND
CLKOUT
OE
LTC1744CFW
LTC1744IFW
FW PACKAGE
48-LEAD PLASTIC TSSOP
TJMAX = 150°C, θJA = 35°C/W
Consult factory for parts specified with wider operating temperature ranges.
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CO VERTER CHARACTERISTICS
The ● indicates specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
MIN
TYP
MAX
UNITS
●
14
●
–4
±1
4
LSB
●
–1
±0.5
1.5
LSB
(Note 7)
– 20
±5
20
mV
Gain Error
External Reference (SENSE = 1.6V)
–3
±1
3
Full-Scale Tempco
IOUT(REF) = 0
Integral Linearity Error
(Note 6)
Differential Linearity Error
Offset Error
Bits
±40
%FS
ppm/°C
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A ALOG I PUT
The ● indicates specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 8)
4.75V ≤ VDD ≤ 5.25V
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
tACQ
Sample-and-Hold Acquisition Time
tAP
Sample-and-Hold Acquisition Delay Time
tJITTER
Sample-and-Hold Acquisition Delay Time Jitter
CMRR
Analog Input Common Mode Rejection Ratio
MIN
●
Sample Mode ENC < ENC
Hold Mode ENC > ENC
●
TYP
UNITS
±1 to ±1.6
V
10
nA
15
8
pF
pF
7.5
0
1.0V < (AIN– = AIN+) < 3.5V
MAX
9.5
ns
ns
0.3
psRMS
80
dB
1744f
2
LTC1744
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DY A IC ACCURACY
The ● indicates specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
SNR
Signal-to-Noise Ratio
5MHz Input Signal (2V Range)
5MHz Input Signal (3.2V Range)
SFDR
S/(N + D)
THD
IMD
Spurious Free Dynamic Range
MIN
TYP
75.5
73.5
77
dBFS
dBFS
25MHz Input Signal (2V Range)
25MHz Input Signal (3.2V Range)
72.5
75.5
dBFS
dBFS
70MHz Input Signal (2V Range)
70MHz Input Signal (3.2V Range)
70
71.5
dBFS
dBFS
●
UNITS
92
87
dB
dB
25MHz Input Signal (2V Range)
25MHz Input Signal (3.2V Range)
87
79
dB
dB
70MHz Input Signal (2V Range)
70MHz Input Signal (3.2V Range)
73
66
dB
dB
73
76
dBFS
dBFS
25MHz Input Signal (2V Range)
25MHz Input Signal (3.2V Range)
72.5
73.5
dBFS
dBFS
70MHz Input Signal (2V Range)
70MHz Input Signal (3.2V Range)
68
64
dBFS
dBFS
5MHz Input Signal, First 5 Harmonics (2V Range)
5MHz Input Signal, First 5 Harmonics (3.2V Range)
– 90
– 85
dB
dB
25MHz Input Signal, First 5 Harmonics (2V Range)
25MHz Input Signal, First 5 Harmonics (3.2V Range)
– 85
– 78
dB
dB
70MHz Input Signal, First 5 Harmonics (2V Range)
70MHz Input Signal, First 5 Harmonics (3.2V Range)
– 72
– 65
dB
dB
Intermodulation Distortion
fIN1 = 2.52MHz, fIN2 = 5.2MHz (2V Range)
fIN1 = 2.52MHz, fIN2 = 5.2MHz (3.2V Range)
– 90
– 80
dBc
dBc
Sample-and-Hold Bandwidth
RSOURCE = 50Ω
150
MHz
Signal-to-(Noise + Distortion) Ratio
Total Harmonic Distortion
5MHz Input Signal (2V Range)
5MHz Input Signal (3.2V Range)
MAX
●
5MHz Input Signal (2V Range)
5MHz Input Signal (3.2V Range)
U U
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I TER AL REFERE CE CHARACTERISTICS
●
76
73
(Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCM Output Voltage
IOUT = 0
2.42
2.5
2.58
V
±30
VCM Output Tempco
IOUT = 0
VCM Line Regulation
4.75V ≤ VDD ≤ 5.25V
3
ppm/°C
mV/V
VCM Output Resistance
1mA ≤ IOUT ≤ 1mA
4
Ω
1744f
3
LTC1744
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DIGITAL I PUTS A D DIGITAL OUTPUTS
The ● indicates specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
VIH
High Level Input Voltage
VDD = 5.25V
●
VIL
Low Level Input Voltage
VDD = 4.75V
IIN
Digital Input Current
VIN = 0V to VDD
CIN
Digital Input Capacitance
MSBINV and OE Only
VOH
High Level Output Voltage
OVDD = 4.75V
VOL
Low Level Output Voltage
OVDD = 4.75V
Hi-Z Output Leakage D13 to D0
COZ
ISOURCE
ISINK
UNITS
●
0.8
V
●
±10
µA
2.4
●
V
1.5
pF
4.74
V
4
IO = 160µA
IO = 1.6mA
IOZ
MAX
IO = –10µA
IO = – 200µA
TYP
V
0.05
0.1
●
V
0.4
V
±10
µA
VOUT = 0V to VDD, OE = High
●
Hi-Z Output Capacitance D13 to D0
OE = High (Note 8)
●
Output Source Current
VOUT = 0V
– 50
mA
Output Sink Current
VOUT = 5V
50
mA
15
pF
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POWER REQUIRE E TS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
VDD
Positive Supply Voltage
5.25
V
IDD
Positive Supply Current
●
245
300
mA
PDIS
Power Dissipation
●
1.2
1.5
W
OVDD
Digital Output Supply Voltage
VDD
V
4.75
0.5
MAX
UNITS
WU
TI I G CHARACTERISTICS
The ● indicates specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
fSAMPLE(MAX)
t1
t2
t3
t4
t5
t6
t7
t8
PARAMETER
Maximum Sampling Frequency
ENC Low Time
ENC High Time
Aperture Delay of Sample-and-Hold
ENC to Data Delay
ENC to CLKOUT Delay
CLKOUT to Data Delay
DATA Access Time After OE ↓
BUS Relinquish Time
Data Latency
CONDITIONS
●
(Note 9)
(Note 9)
●
CL = 10pF (Note 8)
CL = 10pF (Note 8)
CL = 10pF (Note 8)
CL = 10pF (Note 8)
(Note 8)
●
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND
(unless otherwise noted).
Note 3: When these pin voltages are taken below GND or above VDD, they
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above VDD without latchup.
Note 4: When these pin voltages are taken below GND, they will be
clamped by internal diodes. This product can handle input currents of
>100mA below GND without latchup. These pins are not clamped to VDD.
●
●
●
MIN
50
9.5
9.5
1.4
0.5
0
TYP
MAX
10
10
0
4.5
2.3
2.2
10
10
5
1000
1000
8
5
25
25
UNITS
MHz
ns
ns
ns
ns
ns
ns
ns
ns
cycles
Note 5: VDD = 5V, fSAMPLE = 50MHz, differential ENC/ENC = 2VP-P 50MHz
sine wave, input range = ±1.6V differential, unless otherwise specified.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar offset is the offset voltage measured from – 0.5 LSB
when the output code flickers between 00 0000 0000 0000 and 11
1111 1111 1111.
Note 8: Guaranteed by design, not subject to test.
Note 9: Recommended operating conditions.
1744f
4
LTC1744
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Typical INL, 3.2V Range
2.0
Nonaveraged, 8192 Point FFT,
Input Frequency = 2.5MHz, –1dB,
2V Range
Typical DNL, 3.2V Range
1.0
TA = 25°C
0.5
TA = 25°C
0.8
1.5
–20.0
0
–0.5
–1.0
0.4
AMPLITUDE (dBFS)
DNL ERROR (LSB)
–30.0
0.5
0.2
0
–0.2
–0.4
–1.5
0
4000
8000
CODE
12000
–1.0
16000
1744 G01
–60.0
–70.0
–80.0
–110.0
0
4000
8000
CODE
12000
–120.0
16000
1744 G03
Nonaveraged, 8192 Point FFT,
Input Frequency = 2.5MHz, –1dB,
3.2V Range
0.5
TA = 25°C
–10.0
Nonaveraged, 8192 Point FFT,
Input Frequency = 20MHz, –1dB,
3.2V Range
0.5
TA = 25°C
–10.0
–20.0
–30.0
–30.0
–50.0
–60.0
–70.0
–80.0
AMPLITUDE (dBFS)
–20.0
–30.0
AMPLITUDE (dBFS)
–20.0
–40.0
–40.0
–50.0
–60.0
–70.0
–80.0
–50.0
–60.0
–70.0
–80.0
–90.0
–90.0
–100.0
–100.0
–100.0
–110.0
–110.0
–110.0
–120.0
–120.0
0.5
1744 G04
1744 G05
Averaged, 8192 Point 2-Tone FFT,
Input Frequency = 2.5MHz and
5.2MHz, 2V Range
Averaged, 8192 Point 2-Tone FFT,
Input Frequency = 2.5MHz and
5.2MHz, 3.2V Range
0.5
TA = 25°C
–10.0
–120.0
Averaged, 8192 Point FFT, Input
Frequency = 2.5MHz, – 6dB,
2V Range
0.5
TA = 25°C
–10.0
–20.0
–30.0
–30.0
–50.0
–60.0
–70.0
–80.0
AMPLITUDE (dBFS)
–20.0
–30.0
–40.0
–40.0
–50.0
–60.0
–70.0
–80.0
–50.0
–60.0
–70.0
–80.0
–90.0
–90.0
–100.0
–100.0
–100.0
–110.0
–110.0
–110.0
–120.0
–120.0
1744 G07
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
1744 G08
TA = 25°C
–40.0
–90.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
1744 G06
–20.0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–10.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
TA = 25°C
–40.0
–90.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
1744 G02
Nonaveraged, 8192 Point FFT,
Input Frequency = 20MHz, –1dB,
2V Range
AMPLITUDE (dBFS)
–50.0
–100.0
–0.8
–2.0
0.5
–40.0
–90.0
–0.6
–10.0
TA = 25°C
–10.0
0.6
1.0
INL ERROR (LSB)
(Note 5)
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
1744 G10
1744f
5
LTC1744
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TYPICAL PERFOR A CE CHARACTERISTICS
Averaged, 8192 Point FFT, Input
Frequency = 2.5MHz, – 6dB,
3.2V Range
0.5
0.5
–10.0
Averaged, 8192 Point FFT, Input
Frequency = 2.5MHz, – 20dB,
3.2V Range
0.5
TA = 25°C
–10.0
–20.0
–20.0
–30.0
–30.0
–30.0
–40.0
–50.0
–60.0
–70.0
–80.0
AMPLITUDE (dBFS)
–20.0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
Averaged, 8192 Point FFT, Input
Frequency = 2.5MHz, – 20dB,
2V Range
TA = 25°C
–10.0
(Note 5)
–40.0
–50.0
–60.0
–70.0
–80.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
–90.0
–90.0
–100.0
–100.0
–100.0
–110.0
–110.0
–110.0
–120.0
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
1744 G11
0.5
0.5
TA = 25°C
–10.0
Averaged, 8192 Point FFT, Input
Frequency = 20MHz, – 20dB,
2V Range
0.5
TA = 25°C
–10.0
–20.0
–20.0
–30.0
–30.0
–30.0
–50.0
–60.0
–70.0
–80.0
AMPLITUDE (dBFS)
–20.0
–40.0
–40.0
–50.0
–60.0
–70.0
–80.0
–50.0
–60.0
–70.0
–80.0
–90.0
–90.0
–100.0
–100.0
–100.0
–110.0
–110.0
–110.0
–120.0
–120.0
1744 G14
0.5
0.5
TA = 25°C
–10.0
Averaged, 8192 Point FFT, Input
Frequency = 51MHz, – 6dB,
2V Range
0.5
TA = 25°C
–10.0
–20.0
–20.0
–30.0
–30.0
–30.0
–50.0
–60.0
–70.0
–80.0
AMPLITUDE (dBFS)
–20.0
–40.0
–40.0
–50.0
–60.0
–70.0
–80.0
–50.0
–60.0
–70.0
–80.0
–90.0
–90.0
–100.0
–100.0
–100.0
–110.0
–110.0
–110.0
–120.0
–120.0
1744 G17
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
1744 G18
TA = 25°C
–40.0
–90.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
1744 G16
Averaged, 8192 Point FFT, Input
Frequency = 51MHz, – 1dB,
2V Range
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–120.0
1744 G15
Averaged, 8192 Point FFT, Input
Frequency = 20MHz, – 20dB,
3.2V Range
–10.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
TA = 25°C
–40.0
–90.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
1744 G13
Averaged, 8192 Point FFT, Input
Frequency = 20MHz, – 6dB,
3.2V Range
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–120.0
1744 G12
Averaged, 8192 Point FFT, Input
Frequency = 20MHz, – 6dB,
2V Range
–10.0
TA = 25°C
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
1744 G19
1744f
6
LTC1744
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TYPICAL PERFOR A CE CHARACTERISTICS
Averaged, 8192 Point FFT, Input
Frequency = 51MHz, – 20dB,
2V Range
0.5
0.5
Averaged, 8192 Point FFT, Input
Frequency = 70MHz, – 6dB,
2V Range
0.5
TA = 25°C
–10.0
–20.0
–30.0
–30.0
–50.0
–60.0
–70.0
–80.0
AMPLITUDE (dBFS)
–20.0
–30.0
–40.0
–40.0
–50.0
–60.0
–70.0
–80.0
–40.0
–50.0
–60.0
–70.0
–80.0
–90.0
–90.0
–90.0
–100.0
–100.0
–100.0
–110.0
–110.0
–110.0
–120.0
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
1744 G20
0.5
40000
TA = 25°C
78
TA = 25°C
TA = 25°C
77
3.2V RANGE
76
30000
75
–40.0
–50.0
–60.0
–70.0
SNR (dBFS)
25000
COUNT
AMPLITUDE (dBFS)
SNR vs Sample Rate, Input
Frequency = 5MHz, –1dB
35000
–30.0
20000
15000
–80.0
2V RANGE
74
73
72
71
–90.0
10000
70
–100.0
5000
–110.0
69
0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
80
TA = 25°C
TA = 25°C
75
TA = 25°C
–1dBFS
70
– 6dBFS
– 6dBFS
SNR (dBc)
75
70
SNR (dBc)
70
3.2V RANGE
65
65
60
TA = 25°C
60
65
– 20dBFS
60
55
55
– 20dBFS
55
50
100
SNR vs Input Frequency and
Amplitude, 2V Range
75
80
40
60
80
SAMPLE RATE (Msps)
–1dBFS
2V RANGE
85
20
1744 G24
SNR vs Input Frequency and
Amplitude, 3.2V Range
95
90
0
1744 G09
SFDR vs Sample Rate, Input
Frequency = 5MHz, –1dB
100
68
8152 8153 8154 8155 8156 8157 8158
CODE
1744 G23
SFDR (dBc)
1744 G22
Grounded Input Histogram
–20.0
–120.0
0 2 4 6 8 10 12 14 16 18 20 22 24
25.37
FREQUENCY (MHz)
1744 G21
Averaged, 8192 Point FFT, Input
Frequency = 70MHz, – 20dB,
2V Range
–10.0
TA = 25°C
–10.0
–20.0
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
Averaged, 8192 Point FFT, Input
Frequency = 70MHz, – 1dB,
2V Range
TA = 25°C
–10.0
(Note 5)
0
20
40
60
80
SAMPLE RATE (Msps)
100
1744 G25
50
1
10
INPUT FREQUENCY (MHz)
100
1744 G31
50
1
10
INPUT FREQUENCY (MHz)
100
1744 G30
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120
120
TA = 25°C
SFDR (dBFS)
– 6dBFS
90
80
3rd HARMONIC
–70
100
– 6dBFS
90
–1dBFS
80
–1dBFS
70
60
10
INPUT FREQUENCY (MHz)
60
100
1
10
INPUT FREQUENCY (MHz)
100
–60
TA = 25°C
–60
TA = 25°C
–90
1
10
INPUT FREQUENCY (MHz)
–80
–90
–100
100
–120
–80
–90
–110
1
10
INPUT FREQUENCY (MHz)
100
1744 G26
1
10
INPUT FREQUENCY (MHz)
100
1744 G27
1744 G29
SFDR vs Input Amplitude, 2V
Range, 5MHz Input Frequency
110
TA = 25°C
–100
–110
2nd HARMONIC
100
–70
AMPLITUDE (dBc)
AMPLITUDE (dBc)
AMPLITUDE (dBc)
–80
10
INPUT FREQUENCY (MHz)
Worst Harmonic 4th or Higher vs
Input Frequency, 2V Range, –1dB
–70
3rd HARMONIC
1
1744 G28
Worst Harmonic 4th or Higher vs
Input Frequency, 3.2V Range, –1dB
–70
–110
–110
1744 G32
2nd and 3rd Harmonic vs Input
Frequency, 2V Range, –1dB
–100
–90
2nd HARMONIC
1744 G33
–60
–80
–100
70
1
TA = 25°C
– 20dBFS
110
100
–60
TA = 25°C
– 20dBFS
110
SFDR (dBFS)
2nd and 3rd Harmonic vs Input
Frequency, 3.2V Range, –1dB
SFDR vs Input Frequency and
Amplitude, 2V Range
AMPLITUDE (dBc)
SFDR vs Input Frequency and
Amplitude, 3.2V Range
(Note 5)
Power Dissipation vs Sample Rate
1175
TA = 25°C
TA = 25°C
1150
100
1125
SFDR dBc
POWER (mW)
SFDR (dBc AND dBFS)
SFDR dBFS
90
80
70
60
1075
1050
1025
50
40
–60
1100
1000
–40
–20
INPUT AMPLITUDE (dBFS)
0
1744 G34
975
0
10
20
40
30
SAMPLE RATE (Msps)
50
1744 G35
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Input = 5MHz, –25dBFS,
Dither Applied
TA = 25°C
AMPLITUDE (dB)
AMPLITUDE (dB)
Input = 5MHz, –25dBFS, No Dither
0.5
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
0
2
4
6
8 10 12 14 16 18 20 22 24
24.99
FREQUENCY (MHz)
1744 G36
(Note 5)
0.5
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
–150
TA = 25°C
0
2
4
6
8 10 12 14 16 18 20 22 24
24.99
FREQUENCY (MHz)
1744 G37
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SENSE (Pin 1): Reference Sense Pin. Ground selects
±1V. VDD selects ±1.6V. Greater than 1V and less than
1.6V applied to the SENSE pin selects an input range of
±VSENSE, ±1.6V is the largest valid input range.
VCM (Pin 2): 2.5V Output and Input Common Mode Bias.
Bypass to ground with 4.7µF ceramic chip capacitor.
GND (Pins 3, 6, 9, 12, 13, 16, 19, 21, 36, 37): ADC
Power Ground.
AIN+ (Pin 4): Positive Differential Analog Input.
AIN – (Pin 5): Negative Differential Analog Input.
VDD (Pins 7, 8, 17, 18, 20): 5V Supply. Bypass to AGND
with 1µF ceramic chip capacitor.
REFLB (Pin 10): ADC Low Reference. Bypass to Pin 11 with
0.1µF ceramic chip capacitor. Do not connect to Pin␣ 14.
REFHA (Pin 11): ADC High Reference. Bypass to Pin 10 with
0.1µF ceramic chip capacitor, to Pin 14 with a 4.7µF ceramic
capacitor and to ground with 1µF ceramic capacitor.
REFLA (Pin 14): ADC Low Reference. Bypass to Pin 15 with
0.1µF ceramic chip capacitor, to Pin 11 with a 4.7µF ceramic
capacitor and to ground with 1µF ceramic capacitor.
REFHB (Pin 15): ADC High Reference. Bypass to Pin 14 with
0.1µF ceramic chip capacitor. Do not connect to Pin␣ 11.
MSBINV (Pin 22): MSB Inversion Control. Low inverts
the MSB, 2’s complement output format. High does not
invert the MSB, offset binary output format.
ENC (Pin 23): Encode Input. The input sample starts on
the positive edge.
ENC (Pin 24): Encode Complement Input. Conversion
starts on the negative edge. Bypass to ground with 0.1µF
ceramic for single-ended encode signal.
OE (Pin 25): Output Enable. Low enables outputs. Logic
high makes outputs Hi-Z.
CLKOUT (Pin 26): Data Valid Output. Latch data on the
rising edge of CLKOUT.
OGND (Pins 27, 38, 47): Output Driver Ground.
D0-D3 (Pins 28 to 31): Digital Outputs. D0 is the LSB.
OVDD (Pins 32, 43): Positive Supply for the Output Drivers. Bypass to ground with 0.1µF ceramic chip capacitor.
D4-D6 (Pins 33 to 35): Digital Outputs.
D7-D10 (Pins 39 to 42): Digital Outputs.
D11-D13 (Pins 44 to 46): Digital Outputs. D13 is the MSB.
OF (Pin 48): Over/Under Flow Output. High when an over
or under flow has occurred.
1744f
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ANALOG
INPUT
t3
t2
t1
ENCODE
t6
t4
DATA
t5
DATA (N – 3)
DB13 TO DB0
DATA (N – 4)
DB13 TO DB0
DATA (N – 5)
DB13 TO DB0
t5
CLKOUT
t7
t8
OE
DATA N
DB13 TO DB0, OF AND CLKOUT
DATA
1744 TD
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OVDD
0.1µF
AIN+
±1V
DIFFERENTIAL
ANALOG INPUT
S/H
CIRCUIT
AIN–
CORRECTION
LOGIC AND
SHIFT
REGISTER
14-BIT
PIPELINED ADC
14
OUTPUT
LATCHES
•
•
•
0.5V TO 5V
0.1µF
OF
D13
D0
CLKOUT
OGND
SENSE
BUFFER
VDD
RANGE
SELECT
VCM
1µF
1µF
5V
1µF
DIFF AMP
GND
2.5VREF
CONTROL LOGIC
4.7µF
1744 BD
REFLB
0.1µF
1µF
REFHA
4.7µF
REFLA
0.1µF
1µF
REFHB ENC
ENC
MSBINV
OE
DIFFERENTIAL
ENCODE INPUT
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DYNAMIC PERFORMANCE
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio [S / (N + D)] is the
ratio between the RMS amplitude of the fundamental input
frequency and the RMS amplitude of all other frequency
components at the ADC output. The output is band limited
to frequencies above DC to below half the sampling
frequency.
Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is the ratio between the
RMS amplitude of the fundamental input frequency and
the RMS amplitude of all other frequency components
except the first five harmonics and DC.
Total Harmonic Distortion
Total harmonic distortion is the ratio of the RMS sum of all
harmonics of the input signal to the fundamental itself. The
out-of-band harmonics alias into the frequency band
between DC and half the sampling frequency. THD is
expressed as:
THD = 20Log
V22 + V32 + V 42 + ...Vn2
V1
where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. The THD calculated in this
data sheet uses all the harmonics up to the fifth.
2, 3, etc. The 3rd order intermodulation products are 2fa
+ fb, 2fb + fa, 2fa – fb and 2fb – fa. The intermodulation
distortion is defined as the ratio of the RMS value of either
input tone to the RMS value of the largest 3rd order
intermodulation product.
Spurious Free Dynamic Range (SFDR)
Spurious free dynamic range is the peak harmonic or
spurious noise that is the largest spectral component
excluding the input signal and DC. This value is expressed
in decibels relative to the RMS value of a full scale input
signal.
Input Bandwidth
The input bandwidth is that input frequency at which the
amplitude of the reconstructed fundamental is reduced by
3dB for a full scale input signal.
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
SNRJITTER = – 20log (2π) • FIN • TJITTER
Intermodulation Distortion
CONVERTER OPERATION
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused by
the presence of another sinusoidal input at a different
frequency.
As shown in Figure 1, the LTC1744 is a CMOS pipelined
multistep converter. The converter has four pipelined
ADC stages; a sampled analog input will result in a
digitized value five cycles later, see the Timing Diagram
section. The analog input is differential for improved
common mode noise immunity and to maximize the input
range. Additionally, the differential input drive will reduce
even order harmonics of the sample-and-hold circuit. The
encode input is also differential for improved common
mode noise immunity.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer
function can create distortion products at the sum and
difference frequencies of mfa ± nfb, where m and n = 0, 1,
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The LTC1744 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For brevity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
the first stage produces its residue which is acquired by
the second stage. At the same time, the input S/H goes
back to acquiring the analog input. When ENC goes back
high, the second stage produces its residue which is
acquired by the third stage. An identical process is repeated for the third stage, resulting in a third stage residue
that is sent to the fourth stage ADC for final evaluation.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
Each ADC stage following the first has additional range to
accommodate flash and amplifier offset errors. Results
from all of the ADC stages are digitally delayed such that
the results can be properly combined in the correction
logic before being sent to the output buffer.
SAMPLE/HOLD OPERATION AND INPUT DRIVE
When ENC is low, the analog input is sampled differentially
directly onto the input sample-and-hold capacitors, inside
the “Input S/H” shown in the block diagram. At the instant
that ENC transitions from low to high, the sampled input
is held. While ENC is high, the held input voltage is
buffered by the S/H amplifier which drives the first pipelined
ADC stage. The first stage acquires the output of the S/H
during this high phase of ENC. When ENC goes back low,
AIN+
AIN–
VCM
INPUT
S/H
Sample Hold Operation
Figure 2 shows an equivalent circuit for the LTC1744
CMOS differential sample-and-hold. The differential analog inputs are sampled directly onto sampling capacitors
(CSAMPLE) through CMOS transmission gates. This direct
capacitor sampling results in lowest possible noise for a
FIRST STAGE
SECOND STAGE
THIRD STAGE
FOURTH STAGE
5-BIT
PIPELINED
ADC STAGE
4-BIT
PIPELINED
ADC STAGE
4-BIT
PIPELINED
ADC STAGE
4-BIT
FLASH
ADC
2.5V
REFERENCE
4.7µF
SHIFT REGISTER
AND CORRECTION
RANGE
SELECT
REFL
SENSE
REFH
INTERNAL CLOCK SIGNALS
OVDD 0.5V TO
5V
OF
REF
BUF
DIFFERENTIAL
INPUT
LOW JITTER
CLOCK
DRIVER
DIFF
REF
AMP
D13
CONTROL LOGIC
AND
CALIBRATION LOGIC
OUTPUT
DRIVERS
•
•
•
D0
CLKOUT
1744 F01
REFLB REFHA
4.7µF
REFLA REFHB
0.1µF
1µF
0.1µF
1µF
ENC
ENC
MSBINV
OE
OGND
Figure 1. Block Diagram
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the change in voltage between samples will be seen at this
time. If the change between the last sample and the new
sample is small the charging glitch seen at the input will be
small. If the input change is large, such as the change seen
with input frequencies near Nyquist, then a larger charging
glitch will be seen.
LTC1744
VDD
AIN+
CSAMPLE
7pF
CPARASITIC
8pF
VDD
CSAMPLE
7pF
Common Mode Bias
AIN–
The ADC sample-and-hold circuit requires differential
drive to achieve specified performance. Each input should
swing ±0.8V for the 3.2V range or ±0.5V for the 2V range,
around a common mode voltage of 2.5V. The VCM output
pin (Pin 2) may be used to provide the common mode bias
level. VCM can be tied directly to the center tap of a
transformer to set the DC input level or as a reference level
to an op amp differential driver circuit. The VCM pin must
be bypassed to ground close to the ADC with 4.7µF or
greater.
CPARASITIC
8pF
5V
BIAS
2V
6k
ENC
ENC
Input Drive Impedance
6k
2V
1744 F02
Figure 2. Equivalent Input Circuit
given sampling capacitor size. The capacitors shown
attached to each input (CPARASITIC) are the summation of
all other capacitance associated with each input.
During the sample phase when ENC/ENC is low, the
transmission gate connects the analog inputs to the sampling capacitors and they charge to and track the differential input voltage. When ENC/ENC transitions from low to
high the sampled input voltage is held on the sampling
capacitors. During the hold phase when ENC/ENC is high
the sampling capacitors are disconnected from the input
and the held voltage is passed to the ADC core for
processing. As ENC/ENC transitions from high to low the
inputs are reconnected to the sampling capacitors to
acquire a new sample. Since the sampling capacitors still
hold the previous sample, a charging glitch proportional to
As with all high performance, high speed ADCs the dynamic performance of the LTC1744 can be influenced by
the input drive circuitry, particularly the second and third
harmonics. Source impedance and input reactance can
influence SFDR. At the falling edge of encode the sampleand-hold circuit will connect the 7pF sampling capacitor to
the input pin and start the sampling period. The sampling
period ends when encode rises, holding the sampled input
on the sampling capacitor. Ideally the input circuitry
should be fast enough to fully charge the sampling capacitor during the sampling period 1/(2FENCODE); however,
this is not always possible and the incomplete settling may
degrade the SFDR. The sampling glitch has been designed
to be as linear as possible to minimize the effects of
incomplete settling.
For the best performance, it is recomended to have a
source impedence of 100Ω or less for each input. The
source impedence should be matched for the differential
inputs. Poor matching will result in higher even order
harmonics, especially the second.
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Input Drive Circuits
Figure 3 shows the LTC1744 being driven by an RF
transformer with a center tapped secondary. The secondary center tap is DC biased with VCM, setting the ADC input
signal at its optimum DC level. Figure 3 shows a 1:1 turns
ratio transformer. Other turns ratios can be used if the
source impedence seen by the ADC does not exceed 100Ω
for each ADC input. A disadvantage of using a transformer
is the loss of low frequency response. Most small RF
transformers have poor performance at frequencies below 1MHz.
VCM
4.7µF
5V
SINGLE-ENDED
INPUT
2.5V ±1/2 RANGE
18pF
+
LTC1744
37Ω
AIN+
1/2 LT1810
–
18pF
100Ω
+
AIN–
1/2 LT1810
37Ω
–
500Ω
18pF
500Ω
1744 F04a
VCM
Figure 4a. Differential Drive with Op Amps
4.7µF
0.1µF
1:1
ANALOG
INPUT
100Ω
37Ω
100Ω
18pF
AIN+
18pF
AIN
37Ω
VCM
LTC1744
5V
RIN
402Ω
–
18pF
0.01µF
1744 F03
VIN
Figure 3. Single-Ended to Differential
Conversion Using a Transformer
Figure 4a demonstrates the use of operational amplifiers
to convert a single ended input signal into a differential
input signal. The advantage of this method is that it
provides low frequency input response; however, the
limited gain bandwidth of most op amps will limit the
SFDR at high input frequencies.
Figure 4b shows the LT6600, a low noise differential
amplifier and lowpass filter, used as an input driver. The
LT6600 provides two functions: it serves as a 4th order
lowpass filter and as a single-ended to differential converter. Additionally it can be programmed with one external resistor to provide a gain from 1 to 4. Three versions
of this device are available having lowpass filter bandwidths of 2.5MHz, 10MHz or 20MHz.
The 37Ω resistors and 18pF capacitors on the analog
inputs serve two purposes: isolating the drive circuitry
from the sample-and-hold charging glitches and limiting
the wideband noise at the converter input. For input
RIN
402Ω
1µF
0.1µF
1
2
–
3
4
49.9Ω
LTC1744
AIN+
VOCM +
18pF
LT6600-20
7
49.9Ω
AIN–
VMID –
8
5
+ 6
GAIN = 402Ω/RIN
MAXIMUM GAIN = 4
1744 F04b
Figure 4b. Using the LT6600 as a Differential Driver
frequencies higher than 40MHz, the capacitors may need
to be decreased to prevent excessive signal loss.
Reference Operation
Figure 5 shows the LTC1744 reference circuitry consisting
of a 2.5V bandgap reference, a difference amplifier and
switching and control circuit. The internal voltage reference can be configured for two pin selectable input ranges
of 2V(±1V differential) or 3.2V(±1.6V differential). Tying
the SENSE pin to ground selects the 2V range; tying the
SENSE pin to VDD selects the 3.2V range.
The 2.5V bandgap reference serves two functions: its
output provides a DC bias point for setting the common
mode voltage of any external input circuitry; additionally,
the reference is used with a difference amplifier to generate the differential reference levels needed by the internal
ADC circuitry.
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An external bypass capacitor of 4.7µF or larger is required
for the 2.5V reference output, VCM. This provides a high
frequency low impedance path to ground for internal and
external circuitry. This is also the compensation capacitor
for the reference. It will not be stable without this capacitor.
Other voltage ranges in between the pin selectable ranges
can be programmed with two external resistors as shown
in Figure 6a. An external reference can be used by applying
its output directly or through a resistor divider to SENSE.
It is not recommended to drive the SENSE pin with a logic
device since the logic threshold is close to ground and
VDD. The SENSE pin should be tied high or low as close to
the converter as possible. If the SENSE pin is driven
externally, it should be bypassed to ground as close to the
device as possible with a 1µF ceramic capacitor.
The difference amplifier generates the high and low reference for the ADC. High speed switching circuits are
connected to these outputs and they must be externally
bypassed. Each output has two pins: REFHA and REFHB
for the high reference and REFLA and REFLB for the low
reference. The doubled output pins are needed to reduce
package inductance. Bypass capacitors must be connected as shown in Figure 5.
LTC1744
VCM
2.5V
4Ω
2.5V BANDGAP
REFERENCE
4.7µF
1.6V
TIE TO VDD FOR 3.2V RANGE;
TIE TO GND FOR 2V RANGE;
RANGE = 2 • VSENSE FOR
1V < VSENSE < 1.6V
1µF
1V
RANGE
DETECT
AND
CONTROL
SENSE
REFLB
0.1µF
REFHA
BUFFER
INTERNAL ADC
HIGH REFERENCE
4.7µF
DIFF AMP
1µF
REFLA
0.1µF
REFHB
INTERNAL ADC
LOW REFERENCE
1744 F05
Figure 5. Equivalent Reference Circuit
2.5V
VCM
2.5V
VCM
4.7µF
4.7µF
14k
1.1V
11k
SENSE
LTC1744
5V
0.1µF
1µF
1744 F06a
Figure 6a. 2.2V Range ADC
4
LT1790-1.25
1, 2
6
1.25V
SENSE
LTC1744
1µF
1744 F06b
Figure 6b. 2.5V Range ADC with an External Reference
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Input Range
Driving the Encode Inputs
The input range can be set based on the application. For
oversampled signal processing in which the input frequency is low (<10MHz), the largest input range will
provide the best signal-to-noise performance while maintaining excellent SFDR. For high input frequencies
(>10MHz), the 2V range will have the best SFDR performance but the SNR will degrade by 3.5dB. See the Typical
Performance Characteristics section.
The noise performance of the LTC1744 can depend on the
encode signal quality as much as on the analog input. The
ENC/ENC inputs are intended to be driven differentially,
primarily for noise immunity from common mode noise
sources. Each input is biased through a 6k resistor to a 2V
bias. The bias resistors set the DC operating point for
transformer coupled drive circuits and can set the logic
threshold for single-ended drive circuits.
LTC1744
5V
BIAS
VDD
ANALOG INPUT
2V BIAS
TO INTERNAL
ADC CIRCUITS
6k
ENC
0.1µF
1:4
CLOCK
INPUT
50Ω
VDD
2V BIAS
6k
ENC
1744 F07
Figure 7. Transformer Driven ENC/ENC
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Any noise present on the encode signal will result in
additional aperture jitter that will be RMS summed with the
inherent ADC aperture jitter.
In applications where jitter is critical (high input frequencies) take the following into consideration:
1. Differential drive should be used.
2. Use as large an amplitude as possible; if transformer
coupled use a higher turns ratio to increase the
amplitude.
3. If the ADC is clocked with a sinusoidal signal, filter the
encode signal to reduce wideband noise.
4. Balance the capacitance and series resistance at both
encode inputs so that any coupled noise will appear at
both inputs as common mode noise.
The encode inputs have a common mode range of 1.8V to
VDD. Each input may be driven from ground to VDD for
single-ended drive.
Maximum and Minimum Encode Rates
The maximum encode rate for the LTC1744 is 50Msps. For
the ADC to operate properly the ENCODE signal should
have a 50% (±5%) duty cycle. Each half cycle must have
at least 9.5ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise
50% duty cycle is easy with differential sinusoidal drive
using a transformer or using symmetric differential logic
such as PECL or LVDS. When using a single-ended
ENCODE signal asymmetric rise and fall times can result
in duty cycles that are far from 50%.
At sample rates slower than 50Msps the duty cycle can
vary from 50% as long as each half cycle is at least 9.5ns.
The lower limit of the LTC1744 sample rate is determined
by droop of the sample-and-hold circuits. The pipelined
architecture of this ADC relies on storing analog signals on
small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency for the LTC1744 is 1Msps.
3.3V
MC100LVELT22
ENC
VTHRESHOLD = 2V
3.3V
130Ω
Q0
ENC
D0
2V ENC
130Ω
LTC1744
ENC
Q0
0.1µF
83Ω
LTC1744
83Ω
1744 F08a
1744 F08b
Figure 8a. Single-Ended ENC Drive,
Not Recommended for Low Jitter
Figure 8b. ENC Drive Using a CMOS-to-PECL Translator
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DIGITAL OUTPUTS
Lower OVDD voltages will also help reduce interference
from the digital outputs.
Digital Output Buffers
Figure 9 shows an equivalent circuit for a single output
buffer. Each buffer is powered by OVDD and OGND, isolated from the ADC power and ground. The additional
N-channel transistor in the output driver allows operation
down to low voltages. The internal resistor in series with
the output makes the output appear as 50Ω to external
circuitry and may eliminate the need for external damping
resistors.
Output Loading
As with all high speed/high resolution converters the
digital output loading can affect the performance. The
digital outputs of the LTC1744 should drive a minimal
capacitive load to avoid possible interaction between the
digital outputs and sensitive input circuitry. The output
should be buffered with a device such as an ALVCH16373
CMOS latch. For full speed operation the capacitive load
should be kept under 10pF. A resistor in series with the
output may be used but is not required since the ADC has
a series resistor of 43Ω on chip.
Format
The LTC1744 parallel digital output can be selected for
offset binary or 2’s complement format. The format is
selected with the MSBINV pin; high selects offset binary.
Overflow Bit
An overflow output bit indicates when the converter is
overranged or underranged. When OF outputs a logic high
the converter is either overranged or underranged.
Output Clock
The ADC has a delayed version of the ENC input available
as a digital output, CLKOUT. The CLKOUT pin can be used
to synchronize the converter data to the digital system.
This is necessary when using a sinusoidal ENCODE. Data
will be updated just after CLKOUT falls and can be latched
on the rising edge of CLKOUT.
LTC1744
VDD
OVDD
VDD
0.5V TO
VDD
0.1µF
OVDD
DATA
FROM
LATCH
PREDRIVER
LOGIC
43Ω
TYPICAL
DATA
OUTPUT
OE
OGND
1744 F09
Figure 9. Equivalent Circuit for a Digital Output Buffer
1744f
18
LTC1744
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APPLICATIO S I FOR ATIO
Output Driver Power
Separate output power and ground pins allow the output
drivers to be isolated from the analog circuitry. The power
supply for the digital output buffers, OVDD, should be tied
to the same power supply as for the logic being driven. For
example if the converter is driving a DSP powered by a 3V
supply then OVDD should be tied to that same 3V supply.
OVDD can be powered with any voltage up to 5V. The logic
outputs will swing between OGND and OVDD.
Output Enable
The outputs may be disabled with the output enable pin,
OE. OE low disables all data outputs including OF and
CLKOUT. The data access and bus relinquish times are too
slow to allow the outputs to be enabled and disabled
during full speed operation. The output Hi-Z state is
intended for use during long periods of inactivity.
GROUNDING AND BYPASSING
The LTC1744 requires a printed circuit board with a clean
unbroken ground plane. A multilayer board with an internal ground plane is recommended. The pinout of the
LTC1744 has been optimized for a flowthrough layout so
that the interaction between inputs and digital outputs is
minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track, an
encode signal track or underneath the ADC.
High quality ceramic bypass capacitors should be used at
the VDD, VCM, REFHA, REFHB, REFLA and REFLB pins as
shown in the block diagram on the front page of this data
sheet. Bypass capacitors must be located as close to the
pins as possible. Of particular importance are the capacitors between REFHA and REFLB and between REFHB and
REFLA. These capacitors should be as close to the device
as possible (1.5mm or less). Size 0402 ceramic capacitors
are recomended. The large 4.7µF capacitor between REFHA
and REFLA can be somewhat further away. The traces
connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC1744 differential inputs should run parallel and
close to each other. The input traces should be as short as
possible to minimize capacitance and to minimize noise
pickup.
An analog ground plane separate from the digital processing system ground should be used. All ADC ground pins
labeled GND should connect to this plane. All ADC VDD
bypass capacitors, reference bypass capacitors and input
filter capacitors should connect to this analog plane. The
LTC1744 has three output driver ground pins, labeled
OGND (Pins 27, 38 and 47). These grounds should connect to the digital processing system ground. The output
driver supply, OVDD should be connected to the digital
processing system supply. OVDD bypass capacitors should
bypass to the digital system ground. The digital processing system ground should connected to the analog plane
at ADC OGND (Pin 38).
HEAT TRANSFER
Most of the heat generated by the LTC1744 is transferred
from the die through the package leads onto the printed
circuit board. In particular, ground pins 12, 13, 36 and 37
are fused to the die attach pad. These pins have the lowest
thermal resistance between the die and the outside environment. It is critical that all ground pins are connected to
a ground plane of sufficient area. The layout of the evaluation circuit shown on the following pages has a low thermal resistance path to the internal ground plane by using
multiple vias near the ground pins. A ground plane of this
size results in a thermal resistance from the die to ambient
of 35°C/W. Smaller area ground planes or poorly connected
ground pins will result in higher thermal resistance.
1744f
19
C1
4.7µF
•
•
C29
TBD
R21
100Ω
•
R23
3k
•
R11
50Ω
T2
MINICIRCUITS T1-1T
R3
100Ω
E3
GND
E4
GND
E5
GND
R2
37Ω
R1**
0Ω
R9**
10Ω
C11
1µF
5V
R22
100Ω
JP3
C5
18pF
C9
0.15µF
C26
0.15µF
C14
0.15µF
JP4
R5
1Ω
5V
R Y*
R X*
C3
10µF
C27
C15 0.15µF
0.15µF
C7
0.15µF
C18
4.7µF
C13
0.15µF
C6
2.2µF
C24**
18pF
INPUT
TWO
RANGE COMPLEMENT
SELECT
SELECT
C8
4.7µF
C25**
18pF
R10**
0Ω
R7
37Ω
R4
100Ω
R24
2k
C2
4.7µF
T1
MINICIRCUITS T1-1T
GND
VDD VOUT
*RX, RY = INPUT RANGE SET
**DO NOT INSTALL C24, C25, R1, R9 AND R10
5V
J5
ENCODE
INPUT
J4
J3
J1
ANALOG
INPUT
5V
R8
0Ω
4
3
OUT
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SENSE
C17
4.7µF
ENC
ENC
MSBINV
GND
VDD
GND
VDD
VDD
GND
REFHB
REFLA
GND
GND
REFHA
REFLB
GND
VDD
VDD
GND
AIN–
AIN+
GND
VCM
2
1
OF
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
C4
4.7µF
C16
10µF
OE
CLKOUT
OGND
D0
D1
D2
D3
OVDD
D4
D5
D6
GND
GND
OGND
D7
D8
D9
D10
OVDD
D11
D12
D13
OGND
U5
LTC1744
TAB GND
IN
U3
LT1521-3
3V
45
RN4C 33Ω
E2
C23
PGND 0.1µF
E1
5V
RN4D 33Ω
44
RN4B 33Ω
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
C20
0.1µF
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
U4
P174VCX16373V
C19
0.1µF
48
47
46
43
RN4A 33Ω
42
41
C10 0.1µF
RN3D 33Ω
40
39
38
37
36
RN3C 33Ω
RN3B 33Ω
RN3A 33Ω
34
RN2D 33Ω
35
33
32
RN2C 33Ω
31
RN2B 33Ω
30
29
28
27
26
25
RN2A 33Ω
C12 0.1µF
RN1C 33Ω
RN1B 33Ω
RN1A 33Ω
R6
33.2Ω
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
JP2
C21
0.1µF
RN8B 33Ω
RN8A 33Ω
RN7D 33Ω
RN7C 33Ω
RN7B 33Ω
RN7A 33Ω
RN6D 33Ω
RN6C 33Ω
RN6B 33Ω
RN6A 33Ω
RN5D 33Ω
RN5C 33Ω
RN5B 33Ω
RN5A 33Ω
1744 TA01
C22
0.1µF
U2
10T74ALVC1G86
3V
C28
0.1µF
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
J2
3201S-40G1
U
U
20
W
U1
LT1460-2.5
APPLICATIO S I FOR ATIO
U
DC345B Evaluation Circuit Schematic of the LTC1744
LTC1744
1744f
LTC1744
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APPLICATIO S I FOR ATIO
Topside Silkscreen
Topside Copper Layer
Ground Plane, Layer 2
1744f
21
LTC1744
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APPLICATIO S I FOR ATIO
Split Power Plane, Layer 3
Bottom Side Copper, Layer 4
1744f
22
LTC1744
U
PACKAGE DESCRIPTIO
FW Package
48-Lead Plastic TSSOP (6.1mm)
(Reference LTC DWG # 05-08-1651)
12.4 – 12.6*
(.488 – .496)
0.95 ±0.10
8.1 ±0.10
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
6.2 ±0.10
7.9 – 8.3
(.311 – .327)
0.32 ±0.05
0.50 TYP
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
RECOMMENDED SOLDER PAD LAYOUT
1.20
(.0473)
MAX
6.0 – 6.2**
(.236 – .244)
0° – 8°
-T.10 C
-C0.09 – 0.20
(.0035 – .008)
0.45 – 0.75
(.018 – .029)
0.50
(.0197)
BSC
0.17 – 0.27
(.0067 – .0106)
0.05 – 0.15
(.002 – .006)
FW48 TSSOP 0502
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE
**DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
1744f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1744
RELATED PARTS
PART NUMBER
®
DESCRIPTION
COMMENTS
LT 1019
Precision Bandgap Reference
0.05% Max Initial Accuracy, 5ppm/°C Max Drift
LTC1196
8-Bit, 1Msps ADC
3V to 5V, SO-8
LTC1405
12-Bit, 5Msps, Sampling ADC with Parallel Output
Pin Compatible with the LTC1420
LTC1406
8-Bit, 20Msps ADC
Undersampling Capability Up to 70MHz Input
LTC1411
14-Bit, 2.5Msps ADC
No Pipeline Delay, 5V, 80dB SINAD
LTC1410
12-Bit, 1.25Msps ADC
±5V, 71dB SINAD
LTC1412
12-Bit, 3Msps, Sampling ADC with Parallel Output
±5V, No Pipeline Delay, SINAD = 72dB at Nyquist
LTC1414
14-Bit, 2.2Msps ADC
±5V, No Pipeline Delay, 80dB SINAD, 95dB SFDR
LTC1415
Single 5V, 12-Bit, 1.25Msps with Parallel Output
55mW Power Dissipation, 72dB SINAD
LTC1419
14-Bit, 800ksps ADC
±5V, 95dB SFDR, 150mW
LTC1420
12-Bit, 10Msps ADC
71dB SINAD and 83dB SFDR at Nyquist
LT1460
Micropower Precision Series Reference
0.075% Accuracy, 10ppm/°C Drift
LTC1604/LTC1608
16-Bit, 333ksps/500ksps ADCs
16-Bit, No Missing Codes, 90dB SINAD, –100dB THD
LTC1668
16-Bit, 50Msps DAC
87dB SFDR at 1MHz fOUT, Low Power, Low Cost
LTC1741
12-Bit, 65Msps Low Noise ADC
Pin Compatible with the LTC1744
LTC1742
14-Bit, 65Msps Low Noise ADC
Pin Compatible with the LTC1744
LTC1743
12-Bit, 50Msps Low Noise ADC
Pin Compatible with the LTC1744
LTC1745
12-Bit, 25Msps Low Noise ADC
Pin Compatible with the LTC1744
LTC1746
14-Bit, 25Msps Low Noise ADC
Pin Compatible with the LTC1744
LTC1747
12-Bit, 80Msps Low Noise ADC
Pin Compatible with the LTC1744
LTC1748
14-Bit, 80Msps Low Noise ADC
Pin Compatible with the LTC1744
1744f
24
Linear Technology Corporation
LT/TP 0803 1K • PRINTED IN THE USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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 LINEAR TECHNOLOGY CORPORATION 2002