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Physics Seminars
Physics
2-12-2013
Plastic Low-Cost Circuits Enabled Through
Nanotechnology
Paul R. Berger
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Berger , P. R. (2013). Plastic Low-Cost Circuits Enabled Through Nanotechnology. .
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Plastic Low-Cost Circuits Enabled
Through Nanotechnology
“Quantum Functional Circuitry”
Paul R. Berger
Department of Electrical and Computer Engineering
Department of Physics
The Ohio State University
Columbus OH, 43210 USA
PDL
Wight State Univ. visit (Berger)
Feb. 12, 2013
Research at OSU
 Nanoelectronics and
Optoelectronics Lab
 OSU Campus Electron Optics
Facility
 Nanotech West Lab
 5000 square foot class 100 cleanroom
The Ohio State University
 Largest Single-Campus University in USA (~7 km2)
 Largest University by Enrollment (63,217 as of 2010)
 5 Campuses including Main Campus in Columbus
175 undergrad majors; 12,000 courses, 465,000 living alums
 Space
Grant
 Ohio Space Grant
Consortium
 OSU Airport
 Land
Grant
 ATI
 OARDC
 Sea
Grant
 Stone
Lab.
ECE at OSU
 48 faculty members and 14 researchers are active in the areas of:
 Communication, Electromagnetics, Computer Systems, Computer Networks,
Computer Vision, Control Systems, Electro-Mechanical Systems, Electronic
Materials and Devices (EMDL, EMNLAB, NOEL, PDL) , High Performance
Networking and Computing, Intelligent Transportation Systems, Mixed-Signal VLSI
Circuit Design, Power Engineering, Signal Processing, and Wireless
Communication.
 Our annual external funding is about $17M.
 17 are IEEE fellows and 3 National Academy of Engineering members.
 In the last three years, six of our faculty won the prestigious NSF CAREER award.
 Our research laboratories are housed in four buildings: Dreese Labs, Caldwell
Labs and the Electro Science Lab (I & II).
 Undergraduate ECE enrollment is ~1200 students.
 Graduate enrollment is ~400 students.
 About 20 Ph.D. and 70 M.S. degrees awarded every year.
Solid State Electronics at OSU
Institute of Materials Research
 More than 120 faculty members, including 9 ECE professors
 Research groups from 19 departments
Notable OSU ECE Alumni in Solid State Area
 John L. Moll (Ph.D, ‘52)
 Dawon Kahng (Ph.D, ‘59)
 Ebers-Moll Transistor model
 Invented the First Practical
MOSFET
 Intel Senior Fellow
 Invented Floating Gate Memory
Cell
 Director of Transistor
Research and Nanotechnology,
Intel
 Robert S. Chau (Ph.D, ‘89)
Ohio Wright Center for Photovoltaics Innovation
and Commercialization (PVIC)





Funded by Ohio Department of Development Third Frontier Program
$18.6M initial State funding with $29.7M in cost-share from members
 Approximately half of ODOD funding is capital
 OSU portion of PVIC State funding is $6.8M
A major focus is on technology brought to the marketplace instead of
exclusive academic research
Initial team: three universities (OSU, U. Toledo, Bowling Green State
U.), three not-for-profits (Battelle, EMTEC, Green Energy Ohio), and
sixteen industry members (Founding Members)
Membership now open to new companies for low annual fees
Selected Labs at OSU
 Nanotech West Lab
 5000 square foot class 100 cleanroom
 Vistec EBPG-5000 20 / 50 / 100 keV
electron beam nanolithography tool
 Zeiss Ultra 55 Plus field emission
scanning electron microscope
(FESEM)
 Campus Electron Optics Facility
 4 transmission electron
microscopes (TEMs),
 3 scanning electron microscopes
(SEMs),
 2 Dual-Beam FIBs, and
 4 X-ray diffractometers (XRDs).
 FEI’s Titan S/TEM is a state-of-theart STEM with an aberrationcorrected probe-forming system,
monochromator and highresolution spectrometer capable of
Angstrom scale nanoanalysis.
New PVIC Equipment at Nanotech West - I

Picosun® atomic layer deposition (ALD)
• Capable of atomically precise deposition on samples and wafers
up to 150mm
• This tool can utilize solid source precursors
• Currently capable of depositing Al2O3, ZnO, Ta2O5 , TiO2
• Currently developing deposition procedures with conjugated polymers
New PVIC Equipment at Nanotech West - II

Aixtron Swan® metalorganic chemical vapor deposition
(MOCVD) tool grew first epi layers in 3Q09




Industry-style tool capable of fast growth of arsenides, phosphides, and [future] antimonides
3x2” close-coupled showerhead (CCS) design
$1.6M installation
Already have 3 industrial customers for epitaxial growth with this
tool, including 2 Ohio customers, one with non-PV product
application
New PVIC Equipment at Nanotech West - III

AJA International Orion® five-gun RF/DC sputter
deposition tool



Commissioned in November 2009
Load-locked system with UHV gun option from AJA
Intended for general use sputter depositions (W, Pd, Ti, Ni, Cr,
Ti/W, Al, Cu, …) filling a need for the OSU materials research
community
Moore’s law
Intel’s Core i7
6T SRAM cache memory dominates footprint
and power consumption, operates about 1 volt
(→ 8T SRAM)
Power consumption related to voltage squared
(~1 volt state-of-the-art)
NOEL
2005 ITRS – Emerging Research Devices
Introduction to Advantages of
Tunnel Diodes
•
How to characterize tunnel diode?
“N-shaped”
negative differential
resistance (NDR)
Ip
– Peak-to-valley current ratio
PVCR = Ip / Iv
– Peak current density
– Speed index
s = J p / Cj
•
Why use TD with transistors?
–
–
–
–
Increases circuit speed
Reduces circuit complexity
Lowers circuit power
Simple integration with transistor
Current
Jp = Ip / Area
Iv
Voltage
NOEL
Opportunity: Tunnel Diode Memory
• One Transistor 2-Tunnel Diode SRAM (1T TSRAM)
• Robust operation at low voltages
• Refresh-free – Low active and standby power Consumption
• J. P. A. van der Wagt, A. C. Seabaugh, and E. A. Beam, III, “RTD/HFET low standby power SRAM
gain cell,” IEEE Electron Dev. Lett. 19, pp. 7-9 (1998).
• J. P. A. van der Wagt, “Tunneling-Based SRAM,” Proc. of IEEE, 87, pp. 571-595 (1999).
LATCHED COMPARATOR 25 GHz DESIGN
(Courtesy A. Seabaugh, formerly Raytheon Systems)
Conventional
Quantum • Latching behavior is inherent to RTD
VDD
• Settling time is determined by RTD
switching speed
VDD2
CLK
OUT
VREF
•Regenerative feedback gives latching
• Feedback loop has long settling time
IN
GND
Quantum
2
2
Conventional
VSS
25 GHz clock
V out
CLK
GND
V out
Voltage
1
Voltage
VDD2
OUT
IN
OUT
2 RTDs
2 HFETs
Area=1
VDD
1
clk
V
V ref
VSS
in
0
25 GHz clock
V in
0
0
0 10
clk
400 10
Time
-12
800 10
-12
-1
0
0 10
400 10
SPICE Simulations
Time
-12
800 10
-12
12 HFETs
6 Schottky
Diodes
Area=6
NOEL
MOBILE Logic
VCLOCK
• MOBILE (Monostable-Bistable) Logic
– Two serially connected Tunnel Diodes driven by a clock
– Self Latching action of tunnel diodes
– When clock high, final state latched depending on relative peak
current of the two tunnel diodes. Device with lower peak
current switches from on to off state (controlled quenching).
Low State Latch
Monostable
TD
VOUT
TD
Device with
lower peak
current - off
state
Bistable (low)
VOUT
High State Latch
VCLOCK
VOUT
VCLOCK
VOUT
Device with
lower peak
current - off
Monostable
VLOW
VCLOCK
Bistable (high)
state
VOUT
VCLOCK
VOUT
VCLOCK
VOUT
VHIGH VCLOCK
Boolean Logic
• Inverter
– Peak current is proportional to
device area. Device with larger
area has higher current (assuming
constant current density). Here
AreaTDL>AreaTDD
– Peak current of driver tunnel diode
varied by addition of parallel tunnel
diode. Currents in parallel branches
add
– Transistor acts as a switch to
TD
activate parallel branch
VIN
– When VIN =‘0’, ITDL>ITDD output=1,
when VIN=‘1’ ITDD+ITD>ITDL output=0
VCLOCK
TDL
VOUT
TDD
• Output changes only on
positive clock edge
– Nanopipelining: each logic gate is
clocked enabling very high clock
frequencies without the need of
additional circuitry for pipelining
“Threshold Logic Circuit Design of Parallel Adders Using Resonant Tunneling Devices”, C. Pacha et.al., IEEE Trans. On VLSI
Systems, 8(5), 558, 2000
Multi-value Logic
•
•
Stacked NDR Devices
Same principle can be extended to obtain multi-value logic inverter
Normalized
peak current
value
y= 2-x1
Logic levels ‘0’, ‘1’, ‘2’
3 valued inverter circuit
clock
Input
Inverted
output
“Multiple-Valued Logic Circuits Design using Negative Differential Resistance Devices”, K. S. Berezowski et.al., ISMVL, 2007
Reconfigurable Logic
Same circuit can be configured to act as different logic gates depending on
control bit values
Reconfigurable AND/XOR gate
Control c = 0,
AND gate
Control c = 1,
XOR gate
“Reconfigurable RTD-based Circuit Elements of Complete Logic Functionality”, Y. Zhang et.al., ASPDAC, 2008
The Payoff: TDs Integrated with Transistors
More computational power per unit area
 Fewer devices required
 Faster circuits and systems
 Reduced power consumption
Result: Extension of CMOS if a
Si-Based TD is available that is
compatible with CMOS!
NOEL
Outline
 Motivation & Circuit Application
 Epitaxy constraints on Si-based NDR
devices
 Our MBE-grown RITD device
 CVD-grown RITDs with IMEC
 TSRAM memory array
 Future: TFETs?
NOEL
Basic Physics: Esaki Tunnel Diode (Interband)
E
E
E
E
E
E
E
E
E
E
E
V
n(E)
p(E)
n(E)
p(E)
p(E)
p(E)
I
I
I
(a)
I
V
V
(b)
Thermal diffusion current
I
I
V
(c)
p(E)
p(E)
Peak
Excess current
Tunneling current
Tunneling current
E
n(E)
n(E)
n(E)
n(E)
V
V
V
V
V
(d)
V
(e)
V
(f)
Degenerate Doping Required – Difficult with conventional epitaxy
For more info see L. Esaki, “New phenomenon in narrow Germanium p-n junctions,” Phys. Rev., vol. 109, p. 603, 1958.
Prior Art: Lack of Si-Based TDs that can be Monolithically Integrated with Si transistors
Ge Esaki Diode
Si Esaki Diode
• Vintage 1960’s alloy technology prevents large-scale batch processing
• Discrete Esaki diodes are ideal for niche applications.
• However the alloy process does not lend itself to an integrated circuit.
Basic Physics: Resonant Tunneling Diode (Intraband)
intrinsic
V
emitter
I
collector
Tunneling current
I
V
(a
)
For more info see L. L. Chang, L. Esaki
and R. Tsu, “Resonant tunneling in
semiconductor double barriers,” Appl.
Phys. Lett., vol. 24, pp. 593-595, 1974.
V
V
Excess current
I
V
(b
)
Thermal diffusion current
I
V
(c
)
V
(d
)
Large Band Offset Required
Si/SiGe heterojunction has limited band offset
without a thick relaxed buffer
Alternative barriers (i.e. SiO2) present difficult
heteroepitaxy of single crystal Si quantum well
atop amorphous barrier
Basic Physics: Resonant Interband
Tunneling Diode
n ‐delta doping
V
V
V
p‐ delta doping
Excess current
Tunneling current
I
I
I
V
(a)
I
V
(b)
For more info see M. Sweeny and J. Xu,
“Resonant interband tunnel diodes,” Appl. Phys.
Lett., vol. 54, pp. 546-548, 1989.
Thermal diffusion current
V
(c)
V
(d)
δ-doping to form quantum wells;
eliminates need for degenerately doped junctions
High Peak-to-Valley Current Ratios
7
MBE Heterostructure
PVCR: 4.03
2
PCD: 142 A/cm
Si/Si0.6Ge0.4/Si RITDs
Grown at 320 oC
100 nm n+ Si
P -doping plane
4 nm undoped Si
4 nm undoped Si0.6Ge0.4
B -doping plane
1 nm p+ Si0.6Ge0.4
Tunnel
Barrier
Current (mA)
6
5
4
100 nm p+ Si
p+ Si substrate
3
1
2
0
0.0
X
0 .5
Energy (eV)
1
V = 0 .4 V
OSU/NRL RITDs (#050322.2)
o
800 C, 1-min anneal
etched by HBr
0.4
0.6
Voltage (V)
0.8
X
xy
|H H >
|L H >
0
Courtesy
R. Lake (UC
Riverside)
|X >
-0 .5
xy
|X >
z
-1
0.2
z
HH
LH
SO
1.0
-1 .5
45
50
55
P o s itio n (n m )
60
Greater defect annihilation leads to less excess
current in valley region and therefore higher PVCRs
NOEL
First Si-Based Resonant Interband Tunnel Diodes
Approach
EC
(eV)
Upper
Barrier
Crystalline
Quantum
Well
Crystalline
Lower
Barrier
Crystalline
Production
Potential
SiO2/a-Si/SiO2
3.2
No
No
No
High
Abandoned -H igh scattering in quantum,
no room temperature PVR
CaF2/Si/CaF2
2
Yes
Yes
Yes
Low
Abandoned - Tendency for island growth,
defect-assisted transport below 10 nm
ZnS/Si/ZnS
1
Yes
Yes
Yes
Med.
ZnS on Si growth established, Si quantum well
growth under study
SiO2/Si/SiO2
Lateral overgrowth
3.2
No
Yes
No
Med.
Process for forming oxide islands established,
overgrowth process under development
ZnS/Si/ZnS
Lateral overgrowth
1
Yes
Yes
Yes
Med.
ZnS islands have been prepared for first
overgrowth experiments
SiO2/SiGe(C)/SiO2
Lateral overgrowth
3.2
No
Yes
No
Med.
Oxide islands have been prepared for first
overgrowth experiments
Si/SiGe
resonant interband
tunnel diode
-
-
-
-
High
World’s first demonstration on Si;
room temperature peak-to-valley
current ratio of 1.6
Status
980505
A paradigm shift from other approaches was spearheaded
by a team of researchers lead by Berger (then at the
University of Delaware), Naval Research Laboratory and
Raytheon Systems.
• DARPA Award of Excellence (1998)
• Late News at International Electron Devices Meeting
(1998)
• Best Science/Engineering Dissertation (2000)
• Special Invitation to 2003 ITRS Meeting
• IEEE Fellow (2011)
NOEL
Front page of the Wall
Street Journal
(October 1, 1998).
High Peak-to-Valley Current Ratios
7
MBE Heterostructure
PVCR: 4.03
2
PCD: 142 A/cm
Si/Si0.6Ge0.4/Si RITDs
Grown at 320 oC
100 nm n+ Si
P -doping plane
4 nm undoped Si
4 nm undoped Si0.6Ge0.4
B -doping plane
1 nm p+ Si0.6Ge0.4
Tunnel
Barrier
Current (mA)
6
5
4
100 nm p+ Si
p+ Si substrate
3
1
2
0
0.0
X
0 .5
Energy (eV)
1
V = 0 .4 V
OSU/NRL RITDs (#050322.2)
o
800 C, 1-min anneal
etched by HBr
0.4
0.6
Voltage (V)
0.8
X
xy
|H H >
|L H >
0
Courtesy
R. Lake (UC
Riverside)
|X >
-0 .5
xy
|X >
z
-1
0.2
z
HH
LH
SO
1.0
-1 .5
45
50
55
P o s itio n (n m )
60
Greater defect annihilation leads to less excess
current in valley region and therefore higher PVCRs
NOEL
Tampere visit (Berger)
Oct. 28, 2010
10
3
10
2
10
1
10
0
Current densities can be
engineered over ~8 orders of
magnitude by controlling RITD
spacer thickness between the δ­
doping pair from 1 nm up to 16 nm.
8 nm
10 nm
10
-1
10
-2
10
-3
10
2
12 nm
14 nm
15 nm
16 nm
o
825 C annealed, 1 min
-4
0.0
0.2
0.4
Peak Current Density (A/cm )
10
4
2
Current Density (A/cm )
Tailorable Peak Current Densities
0.6
Voltage (V)
0.8
1.0
10
5
10
4
10
3
10
2
10
1
10
0
Red data points
indicated occur at
maximum PVCR
Mixed signal
Logic
10
-1
10
-2
Memory
0
2
4
6
8
10
12
14
Spacer Thickness (nm)
By widening spacer, below 20 mA/cm2 current density!
Low current densities valuable for memory and low power consumption
NOEL
Tampere visit (Berger)
Oct. 28, 2010
16
10
3
10
2
10
1
10
0
Quantum Memory
8 nm
Word (V)
2
10 nm
12 nm
-1
10
-2
10
-3
10
-4
Bit (V)
10
14 nm
15 nm
o
825 C annealed, 1 min
0.0
0.2
-2
-4
1
0
Write into "1"
Write into "0"
16 nm
SN (V)
Current Density (A/cm )
10
4
0.4
0.6
0.8
Voltage (V)
I–V characteristics of Si-based
RITDs annealed at 825 ◦C with the
spacer thickness varied from 8 to
16 nm on a semilog plot.
1.0
0.5
0.3
0.0
-10
-8
-6
-4
-2
0
2
4
6
8
Time (sec)
Oscilloscope capture of the
waveform with Word, bit and SN
showing write functionality.
"The Effect of Spacer Thickness on Si-based Resonant Interband Tunneling Diode Performance and their
Application to Low-Power Tunneling Diode SRAM Circuits," Niu Jin, Sung-Yong Chung, Ronghua Yu, Roux
M. Heyns, Paul R. Berger, and Phillip E. Thompson
IEEE Transactions on Electron Devices, 53, pp. 2243-2249 (September 2006).
NOEL
Tampere visit (Berger)
Oct. 28, 2010
10
Monolithic Quantum Memory
Binary 2TD-1T
Word
• Low voltage operation down to 0.37 V
and %VSWING up to 53.5%.
NFET
VSN
Bit
RITD Drive
Bit (V)
Ground
RITD Load
20 m
VH = 0.59V
0.0V - 1.0V
1.0V - 0.0V
0.44V
0.4 0.36V
0.3
VSN (V)
VSN (V)
0.5
051003.3
Word (V)
0.6
VDD
VL = 0.21V
0.2 0.13V
0.12V
0.57V 0.78V
0.47V
0.1
0.2
0.3
0.4
0.5
0.6
VDD(V)
S.L. Rommel
0.7
0.8
0.9
1.0
1.0
0.8
0.6
0.4
0.2
0.0
3.0
VDD = 0.57V
WL SB WH SB WL
SB WH SB WL
2.0
1.0
0.0
0.5
0.4
0.3
0.2
0.1
0.0
"1"
"1"
0.43 V
0.30 V
"0"
0.13 V
"0"
Time
S. Sudirgo, et al., Proc. 64th Annual Device Research
Conference, pp. 265-6, (2006)
Quantum Logic
0.8
0.7
VSN (volts)
0.6
0.5
VH
0.4
0.3
0.2 V
L
VG = 0 V
VG = 3.5 V
0.1
Circuit schematics of a MOBILE
logic
circuits
using
TDs.
Latching
properties
of
a
MOBILE circuit realized using
Si-based
RITDs
with
modulation.
0.0
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VCLK (volts)
“Monolithically Integrated Si/SiGe Resonant Interband Tunnel Diode/CMOS Demonstrating Low Voltage
MOBILE Operation,” S. Sudirgo, R.P. Nandgaonkar, B. Curanovic, J.L. Hebding, R.L. Saxer, S.S. Islam,
K.D. Hirschman, S.L. Rommel, S.K. Kurinec, P.E. Thompson, N. Jin, and P.R. Berger,
Solid State Electronics, 48, pp. 1907-1910 (2004).
NOEL
Tampere visit (Berger)
Oct. 28, 2010
Multi-valued Quantum Logic For Compact
and Energy Efficient Circuitry
Vpulse (V)
10
6
P1
P2
P3
4
Vout (V)
Current (mA)
8
2
10
8
6
4
2
2.5
8
p
Sw
eep
U
Current (mA)
"0"
2
4
6
Time (ms)
8
Reduced device count potential.
However, there is a large series resistance
created by the vertical stacking and a lower
noise margin from P2 → P3 than P1 → P2
Do
wn
Lower RITD
Sw
ee
p
2
Integrated RITD Pair
0
-1.0
-0.5
0.0
0.5
1.0
1.5
Voltage (V)
NOEL
"1"
Backward diode
Upper RITD
6
4
"1"
1.5 "0"
1.0
0.5
0
0.0 0.5 1.0 1.5 2.0 2.5
Voltage (V)
"2"
2.0
Tampere visit (Berger)
2.0
2.5
“Tri-State Logic Using Vertically Integrated Si Resonant
Interband Tunneling Diodes with Double NDR,” Niu Jin, SungYong Chung, Roux M. Heyns, Paul R. Berger, Ronghua Yu,
Phillip E. Thompson, and Sean L. Rommel, IEEE Elect. Dev.
Lett., 25, pp. 646-648 (September 2004).
Oct. 28, 2010
Si-Based RITD Results Summary
Device Optimization
•High PVCR (4.0)
•High PCD (≥ 218 kA/cm2)
•Low PCD (≤ 20 mA/cm2)
Hybrid Circuit Prototyping
• Vertically stacked back-to-back RITDs for
symmetric NDR
• Tri-state logic with vertically stacked RITDs
• Low voltage MOBILE latches (CMOS-RITD)
Device Integration
NOEL
Monolithic Circuits
•Monolithic integration with CMOS
•Low power/low voltage TSRAM
•Monolithic Integration with SiGe HBTs
•Low power/low voltage MOBILE
•CVD Integration
•Adjustable PVCR (HBT-RITD)
For Further Reading
 Paul R. Berger, Anisha Ramesh “Negative Differential Resistance Devices and Circuits” in
Comprehensive Semiconductor Science and Technology, Elsevier, Volume 5, Chapter 13, pp.
176–241 (2011).
 A. C. Seabaugh, B. Brar, T. Broekaert, G. Frazier, and P. van der Wagt, “Resonant tunneling
circuit technology: has it arrived?” 1997 GaAs IC Symposium, pp. 119-122.
 A. Seabaugh and R. Lake, “Tunnel diodes,” Encyl. Appl. Phys., vol. 22, pp. 335-359 (1998).
 J.P. Sun, G.I. Haddad, P. Mazumder, J.N. Schulman, “Resonant tunneling diodes: Models and
properties,” Proc. of IEEE, vol. 86, pp. 641-661 (1998).
 P. Mazumder, S. Kulkarni, Bhattacharya M, J.P. Sun, G.I. Haddad, “Digital circuit applications of
resonant tunneling devices, Proc. IEEE, vol. 86, pp. 664-686 (1998).
 J. P. A. van der Wagt, “Tunneling-Based SRAM,” Proc. of IEEE, vol. 87, pp. 571-595 (1999).
 A. Seabaugh, B. Brar, T. Broekaert, F. Morris, P. van der Wagt, and G. Frazier, “Resonant­
tunneling mixed-signal circuit technology,” Solid State Electronics, vol. 43 pp. 1355-1365 (1999).
 K. Maezawa, T. Akeyoshi, and T. Mizutani, “Flexible and reduced-complexity logic circuits
implemented with resonant tunneling transistors,” International Electron Devices Meeting
Technical Digest, pp. 415-418 (1993).
NOEL
NDR in an Organic System
Now let’s turn our attention to organic
systems.
First, let’s review some prior art.
PDL
SmartCards – Flexible Electronics
Memory
Lithium
Battery
Logic
Connectors
keyslot
Edge Connector
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NDR in an Organic System (Reed and Tour)
Large On-Off Ratios and Negative Differential Resistance in a Molecular Electronic Device
J. Chen, M. A. Reed, A. M. Rawlett, J. M. Tour
Science, vol. 286, pp. 1550-1552 (November 19, 1999).
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Abstract
● A significant discovery for fashioning strong room temperature
negative differential resistance (NDR) devices using organic
semiconductors was made.
● NDR devices enable compact, low power consumption logic
and memory circuits with fewer devices, exploiting their
quantum functionality that would be ideal for distributed
computing needs on flexible substrates, such as Smartcards
and portable displays.
● The work which appeared in Applied Physics Letters (Nov.
2005) reports on a robust process that utilizes simple solution
processing and large area devices, circumnavigating the need
for molecular-sized junctions for NDR.
● The Key: Controlled oxidation and crystallinity of a thin (<
10 nm thick) TiO2 layer.
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Polymer material and device
structure with its associated energy
band diagram
poly[2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylenevinylene]
(MEH-PPV)
Energy (eV)
O
-4
-5
-6
LUMO
-3.0 eV
TiO2
-3
Indium tin oxide (ITO) coated glass
substrates with a sheet resistance (Rs)
below 10 Ω-cm. (A=0.19 cm2)
MEH-PPV
ITO
EF=-4.8 eV
HOMO
-5.1 eV
Al
EF=-4.2 eV
-7
O
TiO2
(+)
Al
ITO
Glass Substrate
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(–)
A thin layer of Ti metal (2-20 nm)
electron beam evaporated was oxidized
using oxygen plasma at an RF power of
80 W at room temperature.
Thin films of MEH-PPV were then spin
coated atop the TiO2 layer from a 0.5%
MEH-PPV solution in 80% toluene and
20% THF.
The devices were completed by a
shadowmask evaporation of an Al
cathode, about 250 nm thick.
Surface image of room-temperature
plasma-oxidized thin TiO2 film
1.0µm
AFM image (5m5m) of O2
plasma-oxidized TiO2 layer on ITO
SEM image of O2 plasma-oxidized TiO2
layer on ITO
 AFM data indicates that the as-deposited metallic Ti layer with a grain structure
converted to a smoother surface after oxygen plasma oxidation , root mean
square roughness (RMS) ~ 1 nm.
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Current-voltage characteristics with
large and reproducible NDR
0.3
2 nm thick TiO2
0.2
PVCR = 35
2
0.1
0.0
-0.1
-0.2
-0.3
-8
-6
c
-4
-2
0
2
0 .1
0 .0
-0 .1
-0 .2
-0 .3
-10
-8
-6
2
6 nm thick TiO2
PVCR = 12
0.1
0.0
-0.1
-0.2
-4
-2
0
2
4
Vo ltage (V )
0.0
 5 adjacent devices for
each TiO2 thickness –
reproducible
-0.1
-0.2
4 nm thick TiO2
PVCR = 53
-8
-6
-4
-2
0
2
4
 Forward and backward
sweep – lack of
hysteresis
Voltage (V)
0.4
ITO/TiO2/MEH-PPV/Al
 4 different TiO2
thicknesses – tracks
as expected
ITO/TiO2/MEH-PPV/Al
0 .2
d
Current density (A/cm )
2
Current density (A/cm )
0.1
0 .3
-10
0.4
0.2
0.2
4
Voltage (V)
0.3
0.3
-0.3
-10
0 .4
2
0.4
ITO/TiO2/MEH-PPV/Al
Current density (A/cm )
2
Current density (A/cm )
0.4
C u rrent density (A /cm
)
b
a
0.3
0.2
ITO/TiO2/MEH-PPV/Al
8 nm thick TiO2
PVCR = 1.2
0.1
 Thicker TiO2 –
incomplete oxidation –
residual metallic Ti
0.0
-0.1
-0.2
-0.3
-0.4
-0.3
-10
-8
-6
-4
-2
0
Voltage (V)
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2
4
-10
-8
-6
-4
-2
0
Voltage (V)
2
4
 PVCR up to 53!
Summary of current-voltage characteristics
Tunneling
barrier
(nm)*
Jpeak
(A/cm2)
Vpeak
(V)
Jvalley
(A/cm2)
Vvalley
(V)
PVCR
2
-0.13
-3.3
-0.004
-6.4
34.5
4
-0.29
-4.4
-0.006
-7.4
53.4
6
-0.16
-3.5
-0.013
-6.1
12.4
8
-0.23
-5.6
-0.199
-5.6
1.20
* The thickness of the as-deposited titanium layers before the plasma process is referred to as the
thickness of the final TiO2 layers.
The lack of the measured peak current density to exponentially decrease with
increasing TiO2 layer thickness suggests that the observed reverse-biased
NDR behavior does NOT occur via tunneling across the thin-TiO2 layer acting
as a traditional tunneling barrier.
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Current-voltage characteristic of a
control device (ITO/PEDOT:PSS/
MEH-PPV/Al)
0.08
ITO/PEDOT:PSS/MEH-PPV/Al
2
Current Density (A/cm )
2
Current Density (A/cm )
0.4
0.3
0.2
0.1
0.06
0.04
0.02
With TiO2 removed,
the previously
observed NDR effect
disappears
0.00
-0.02
-0.04
-10
-8
-6
-4
-2
0
2
4
Voltage (V)
0.0
-0.1
-0.2
-0.3
-10
ITO/PEDOT:PSS/MEH-PPV/Al
-8
-6
-4
-2
0
Voltage (V)
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2
4
Robust stability after 30 days
2
Current Density (A/cm )
0.00
-0.05
-0.10
ITO/TiO2/MEH-PPV/Al
2 nm thick TiO2
-0.15
As-fabricated
After 30 days
-0.20
-10
-8
-6
-4
-2
0
Voltage (V)
After testing, the devices were stored (un-encapsulated) in an inert glove box
for 30 days with little variation in their peak current density and peak current
position.
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Monostable-bistable Transition
Logic Element (MOBILE) operation
0
VG=-3 V
VG= 1.5 V
0
-10
VSN (V)
Ithru (mA)
-5
VDD
-15
PD1
VH
-2
VCLK
-4
-6
VL
Ithru
-20
PD2
PD1
VD
VSN
PD2
-8
VG
-25
-16
-14
-12
-10
-8
-6
VDD (V)
-4
-2
0
-10
-16
-14
-12
-10
-8
-6
-4
-2
0
VCLK (V)
 Two polymer tunnel diodes (a 2 nm thick TiO2 layer) were serially connected
and ramped in bias from -16 V to 0 V, showing multiple NDR regions.
 Voltage at the sense node as a function of clock voltage of JFET-polymer
tunnel diodes MOBILE latch with 51% voltage swing of the applied VCLK at -8 V.
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Questions?
Science and Vie (France's Scientific American): “
Plastic diodes promise low cost memory" (July 2006).
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The NDR effect in the polymer tunnel
diode is hypothesized to occur due to
local defect sites within the TiO2 film?
 Results suggest that the NDR seems to occur as a result of tunneling
through localized defect sites within the thin TiO2 layers that are confined to a
small range of energies within the TiO2 bandgap near the TiO2 conduction
band.
- The lack of the measured peak current density to exponentially
decrease with increasing TiO2 layer thickness
- Switching effect in the current-voltage curves
- Using 380°C with the O2 plasma treatment resulted in more
thorough conversion to a thin TiO2, and diodes built using this
layer did not exhibit the significant NDR effect.
 The mechanism for NDR under reverse bias in these ITO/TiO2/MEH-PPV/Al
tunnel diodes is speculated to occur via electrons emitted from the n-type
ITO, tunneling through defect states in the TiO2, which are then collected by
the lowest unoccupied molecular orbital (LUMO) level in the MEH-PPV.
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I-V characteristics with high
temperature plasma-oxidized TiO2
2
Current Density (A/cm )
0.4
ITO/TiO2/MEH-PPV/Al
0.3 4 nm thick TiO2
High-tmeperature plasma-oxidation of TiO film
2
0.2 (at 380 C)
o
0.1
0.0
-0.1
-0.2
-0.3
-10
-8
-6
-4
-2
0
2
4
Voltage (V)
As the conversion of Ti to TiO2 takes place at higher temperatures, the TiO2
crystallinity is improved. Therefore, fewer defects. Observed NDR behavior
diminishes, indicative of defect related tunneling.
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The schematic of band diagram for NDR under reverse
bias in these ITO/TiO2/MEH-PPV/Al tunnel diodes
Diagram of photoconductivity model. The
diagram represents the conduction and
valence bands in a nanoparticle of TiO2 and
the energy levels of a trap state, and an
electron scavenging state, S/S− on the
surface of the nanoparticle. The arrows
represent the different possible electron
transitions. (1) photogeneration, (2) band-to­
band recombination, (3) electron trapping,
(4) hole trapping, (5) electron scavenging.
Charge transport in porous nanocrystalline titanium dioxide
Eppler, Anuradha M.; Ballard, Ian M.; Nelson, Jenny
Physica E vol.14 pp. 197-202 (2002)
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Applied
VR
EC 4.2 eV LUMO
3.0 eV
ITO
Carrier tunneling?
4.8eV
4.8eV
MEH-PPV
Al
++
++
HOMO
5.1 eV
Reverse bias
TiO2
Ev 7.4 eV
4.2eV
Forward Bias NDR
Forward bias
LUMO
3.0 eV
Al
4.2eV
MEH-PPV
2
Current Density (A/cm )
0.10
0.08
EC 4.2 eV
TiO2 (6 nm)
ITO
0.06
0.02
Carrier tunneling?
4.8eV
4.8eV
0.04
PVCR (~2.6)
PVCR (~73)
0.00
HOMO
5.1 eV
TiO2
-0.02
-0.04
-10 -8 -6 -4 -2
0
2
Voltage (V)
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4
6
8
Applied
VF
10
Ev 7.4 eV
UV-VIS Absorption Spectrometry
for Plasma Oxidized TiO2 thin film
ITO/glass
Ti (2 nm)/ITO/glass
TiO2 (2 nm, 100 sec)/ITO/glass
Ti/ITO/glass Substract ITO/glass
TiO2/ITO/glass Substract ITO/glass
TiO2/ITO/glass Substract Ti/ITO/glass
0.30
Absorbance
0.25
0.20
0.15
Optical absorption
0.10
0.05
0.00
-0.05
300
400
500
600
Wavelength (nm)
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700
800
 Using a standard double
beam instrument recording
UV Visible spectrum (Perkin
Elmer Lambda 20 UV-vis
spectrometer), the defect level
characterization of plasma
oxidized TiO2 thin film is
conducted.
 Advantages of a double beam
instrument:
 It compensates for most
short-term fluctuation in
the radiant output sources
as well as for drift in the
transducer and amplifier.
 It compensate for wide
variations in source
intensity with wavelength.
UV-VIS absorption spectrometry for
plasma oxidized TiO2 thin film
0.15
TiO2 (2 nm)/ITO/glass Substract ITO/glass
1400 TiO2 (2 nm)/ITO/glass Subtract ITO/glass
1/2
0.10
(h)
Absorbance
1200
1000
800
600
400
200
0.05
0
2.0
2.5
3.0
3.5
4.0
4.5
h (eV)
0.00
300
400
500
600
700
800
Wavelength (nm)
Localized defect sites within the thin TiO2 layers that are confined to a small
range of energies within the TiO2 bandgap near the TiO2 conduction band was
estimated to be about 2.57 eV.
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Conclusions
 A significant discovery for fashioning strong room temperature
negative differential resistance (NDR) devices [PVCR up to 53]
using organic semiconductors was developed and applied
towards a latching circuits.
 Room temperature NDR operation, large area, bulk-like
thicknesses and simple solution processable platform are key
advantages.
 The mechanism for NDR under reverse bias in these polymer
tunnel diodes is speculated to occur by tunneling through defect
states in the TiO2.
 Organic NDR devices enable compact, possible low power
consumption logic and memory circuits with fewer devices,
exploiting their quantum functionality that would be ideal for
distributed computing needs on flexible substrates, such as
Smartcards and portable displays.
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Si-Based Work - Collaborators
Naval Research Laboratory
Phillip E. Thompson, Karl Hobart, and Brad Weaver
IMEC
Roger Loo, Ngoc Duy Nguyen (now Univ-Liege), Shotaro Takeuchi
(now Covalent Silicon), and Matty Caymax
Rochester Institute of Technology
Sean L. Rommel, Santosh K. Kurinec, and Karl D. Hirschman
University of California, Riverside
Roger Lake
NIST, Gaithersberg
David Simons
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Si-Based Work - Students
Current Graduate Students & Researchers
Tyler Growden
Former Graduate Students
Ms. Anisha Ramesh (Ph.D. 2012)
Si-Young Park (Master’s Thesis 2006, Ph.D. 2009)
Ronghua Yu (Ph.D. 2007)
Sung-Yong Chung (Master's Thesis 2002, Ph.D. 2005)
Sandro Di Giacomo (Master's Thesis 2005)
Niu Jin (Master's Thesis 2001, Ph.D. 2004)
Anthony Rice (Master's Thesis 2003)
Sean L. Rommel (Ph.D. 2000)
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Si-Based Work - Past and Current Support
This work was financially supported by:
 National
Science
Foundation
[ECS-9624160
(CAREER); ECS-9622134 (REG); DMR-0103248
(NIRT); ECS-0196054 (w/ RIT); ECS-0196208 (GOALI
w/ Raytheon); DMR-0216892 (IMR); ECS-0323657
(GOALI w/ Motorola); ECS-1028650 (GOALI w/
Traycer) ]
 DARPA/AFOSR (F49620-96-C-0006).
 Naval Research Laboratory (N00173-99-1-G010).
This work is indebted to the MBE sample exchanges by:
Phillip E. Thompson (Naval Research Laboratory)
And the CVD sample exchanges by:
Roger Loo (IMEC)
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Polymer Work - Students
Current Students
Sarah Al-Issa (Undergrad Researcher)
Nadia Ahlborg (Undergrad Researcher)
Minjae Kim (Ph.D. Candidate @ IMEC)
Fomer Students
Woo-Jun Yoon (Ph.D. 2009)
Sita Asar (Physics Undergrad Researcher)
Ohio State University
Prof. Richard L. McCreery & Andrew P. Bonifas
Prof. Steven A. Ringel & Maria Gonzalez
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Acknowledgements
This work was supported by the National
Science Foundation
(ECCS-1002240).
And
the authors wish to thank
Gary Farlow (WSU); Don Lupo (TUT); Ioan
Stamatin (UB); Filip Tuomisto (Aalto)
for technical discussions and collaborations.
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STOP!
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