Master Thesis/Internship
Topic Guide
2013-2014
Information.............................................................................................................................................................................................5
I.
CMOS Scaling (sub-22 nm) ............................................................................................... 6
Electrical evaluation and reliability assessment of local interconnects...................................................................... 6
Time-Dependent Dielectric Breakdown (TDDB) reliability of advanced CMOS gate dielectrics....................... 6
Conductive Atomic Forc e Microsc opy (C-AFM) for memory devices characterization ...................................... 7
Investigation and optimization of the electrical switching properties of scaled Ta2O5-based resistive RAM
memory cells ........................................................................................................................................................................ 7
Measurement and circuit modeling of advanced interconnect reliability ................................................................. 9
Evaluation of MgO as tunnel barrier in material stacks for MRAM applications..................................................... 9
Thermo-compression bonding of fine-pitch micro-bumps for 3D integration of ICs .........................................10
Study of chipping mechanisms in the dicing of thin silicon wafers ...........................................................................10
Evaluation of photoresist outgassing for Extreme Ultraviolet Lithography ...........................................................11
Deposition, characterization and application of dielectric films...............................................................................11
Development, characterization and application of pore sealing treatments..........................................................12
Hot carrier reliability on advanced logic/DRAM devices...........................................................................................13
Modeling and extraction of TSV characteristics: resistance, capacitance and inductance...................................13
Characterization of capacitance vs. voltage in TSV capacitors.................................................................................15
Investigation of advanced self-rectifying resistive switching memory cells (SRC-RRA M) ...................................16
Self-assembled monolayers as enabling technology for microelectronics ..............................................................17
Advanced barrier CMP slurry development ................................................................................................................17
Development of a ramped voltage BTI procedure for fast gate dielectric testing ...............................................18
Compact modeling of advanced transistors.................................................................................................................19
Modeling of temperature effects in advanced devices ...............................................................................................19
Characterization and modeling of oxide border traps in Ge/III-V MOSFETs........................................................20
Interface stability and reliability of high-mobility channel MOSFETs.......................................................................20
Carbon nanotube contacts: electrical characterization of CNT – damascene contacts ....................................21
Carbon nanotube growth and its catalyst nanoparticle deposition for future contact applications .................22
Bottom-up fill of deep holes with nanowires for future contact schemes.............................................................23
Energy spectrum of a cylindrical superlattice nanowire ............................................................................................23
Modeling of tunable band gap bilayer structures and devices...................................................................................24
Design of an reliability characterization package for future generation high-performance CMOS
transistors ...........................................................................................................................................................................24
Design and simulation of on-chip circuits for parallel characterization of ultra-scaled transistors and
SRAM cells for BTI reliability ..........................................................................................................................................25
Master Thesis/Internship Topics 2013-2014
1
Graphene: device fabrication for optoelectronics ......................................................................................................26
Graphene: device fabrication and characterization.....................................................................................................27
Plasma etching and characterization of novel materials for advanced patterning.................................................28
Low damage plasma processing: new materials for pore stuffing of 2.0 porous SiOCH materials ...................28
Depth loading study in STI ..............................................................................................................................................29
Advanced materials characterization using ion beam scattering ..............................................................................30
Development of an accelerator based metrology application ..................................................................................31
Analysis of surface preparation for HV and UHV-SSRM ...........................................................................................32
Active dopant characterization with micro-probes on advanced ultra-shallow high-mobility CMOS
semiconductor structures ...............................................................................................................................................33
Development of a professional data analysis package for the micro-four point probe (M4PP).........................34
Fundamentals of nanoscopic materials removal ..........................................................................................................35
Strain characterization in advanced transistor structures using Raman .................................................................35
Non-destructive assessment of electrical properties of nanoscale probe tips ....................................................36
Nickel damascene process for MEMS ...........................................................................................................................36
Defectivity monitoring of directed self-assembly ........................................................................................................37
Modeling of leakage in very high permittivity dielectrics for DRAM applications ................................................38
II.
Heterogeneous Integration............................................................................................. 39
Calibration of stress sensors for 3D-IC applications .................................................................................................39
III. Electronics for Healthcare and Life Sciences ................................................................ 40
Studying the function of neural circuits.........................................................................................................................40
Measurement of nanomaterial exposure in air............................................................................................................41
Sensors for weight management and energy expenditure ........................................................................................41
How to detect dehydration with body area networks? ............................................................................................42
Ionic fluidic study of metallic nanopores.......................................................................................................................43
Exploration of efficient electroporation protocols for intracellular recording of action potentials using
configurations of microelectrod es on chip...................................................................................................................43
Characterization of optical waveguides for optogenetic stimulation of in vitro and in vivo neurons..................44
High-density carbon nanotube electrod es for recording and stimulating electrogenic cells ..............................44
Controlling light-matter interactions with plasmonic nanoantennas.......................................................................45
Engineering micro-structures for an optimized lens-free image ..............................................................................46
Measuring electrical properties of cancer cells ...........................................................................................................47
Gram staining using spectroscopy..................................................................................................................................47
Gold nanostars for imaging and photothermal treatmen t of cancer.......................................................................48
Master Thesis/Internship Topics 2013-2014
2
Antibody stabilizers for lateral flow assays...................................................................................................................48
Multiplex ligation polymerase amplification on chip ...................................................................................................49
TNFα detection in cell-culture medium of activated cells ........................................................................................49
Detection of single protein molecules in microwells on a digital lab-on-a-chip for point-of-care
diagnostics ..........................................................................................................................................................................50
Quantitative protein kinetics analysis using a refractometric LSPR sensor with an improved figure of
merit ....................................................................................................................................................................................50
High quality-factor resonators in silicon nitride waveguides ....................................................................................51
Noise characterization and modeling of electrodes for in vivo and in vitro neural recording ..........................52
Characterization of the light-sensitivity of CMOS-ICs for life science applications.............................................52
Multimodal integration of EEG and functional Near Infrared Spectroscopy for ambulatory brain imaging.....53
IV. Imaging Systems............................................................................................................... 55
Dynamic current steering in active pixel sensors .......................................................................................................55
V.
Organic Electronics.......................................................................................................... 56
Degradation mechanisms in organic solar cells...........................................................................................................56
Organic photodetectors ..................................................................................................................................................56
Contact resistance optimiza tion in organic thin film transistors .............................................................................57
Bias stress stability study of a-IGZO TFTs...................................................................................................................58
VI. Wireless Communication................................................................................................ 59
Radio-frequency communication with metal-oxide electronics on plastic.............................................................59
Algorithm and architecture co-optimizations for cost and power constrained signal processing system.......60
Digital assistance and digital frontend for deep submicron analog circuits............................................................60
Algorithm development for automated tuning of cellular duplexer module in CMOS .......................................61
VII. Energy................................................................................................................................ 62
Hydrogen generation through water photoelectrolysis using semiconductor photoanodes .............................62
Electrical characterisation of amorphous Si layers for solar cell applications .......................................................62
Dielectric ablation by laser processing for photovoltaic applications .....................................................................63
Development of assembly technology for next-generation c-Si PV modules........................................................63
Optimization of the porosification of silicon for application in thin-film crystalline silicon solar cells.............64
Master Thesis/Internship Topics 2013-2014
3
Optimization of the bonding and detachment process of epitaxial silicon foils for application in thin-film
crystalline silicon solar cells ............................................................................................................................................65
Development and validation of an optical model for PV modules...........................................................................66
Degradation mechanisms in organic solar cells...........................................................................................................66
Large area coating of organic photovoltaic modules..................................................................................................67
2D and 3D modeling of high efficiency back junction solar cells .............................................................................68
Photonic nanostructures for light management in novel thin silicon solar cells and modules ...........................68
VIII. Sensor Systems for Industrial Applications .................................................................. 70
Opto-acoustic micro-resonator for sensing applications ..........................................................................................70
MEMS-based compass: optimization of magnetometers enabled by MEMS resonators ......................................71
Cost-effective photonic sensor for point-of-care medical diagnostics ...................................................................72
IX. Microelectronics Design .................................................................................................. 73
Visualisatie van DfX analyse feedback in een elektronisch ontwerp .......................................................................73
Design van een 3.3V digitale standaardcelbibliotheek in UMC 180 nm technologie voor
ruimtetoepassingen ...........................................................................................................................................................73
Ontwerp van radiatie-tolerante flipflopsvoor imec’s DARE bibliotheken..............................................................75
Design prediction tool development for solder joint reliability for printed board assemblies, including
the flexibility of components/boards .............................................................................................................................76
X. NERF.................................................................................................................................. 77
Design and construction of automated environmen ts to study spatial memory function in rodents ..............77
Closed-loop real-time read out and control of memory processing in behaving rats.........................................77
Scale-space based segmentation and identification of cells in microscopic images ..............................................78
Optogenetic dissection of dopamine function for learning from reward and punishment .................................79
Using superparamagnetic nanoparticles as force actuators in cells and tissues ....................................................79
Design, prototyping and testing of miniaturized brain implants...............................................................................80
Inferring population network dynamics from cellular imaging data in behaving animals .....................................81
Master Thesis/Internship Topics 2013-2014
4
Information
Students from universities and engineering schools can apply for a master thesis and/or internship project at imec.
Imec offers topics in engineering and (industrial) sciences in different fields of research.
The internship and thesis projects currently available are collected in this topic guide and are classified according to
the imec research domains. You can find more detailed information on each research domain under the heading
‘Research’ on www.imec.be.
Should you require more information, you can send an e-mail to student@imec.be.
How to apply?
Send an application e-mail with your motivation letter and detailed resume to the responsible scientist(s)
mentioned at the bottom of the topic description of your preference.
The scientist(s) will screen your application and let you know whether or not you are selected for a project at
imec.
It is not recommended to apply for more than three topics.
For more information, go to the Internship and Master Thesis page under the heading Academy on our website.
Master Thesis/Internship Topics 2013-2014
5
I.
CMOS Scaling (sub-22 nm)
Electrical evaluation and reliability assessment of local interconnects
In future CMOS technologies the individual transistors will be connected through local interconnects in order to
increase the device density and to reduce the metal one complexity. These local interconnects however have to
fulfill the same strict reliability specification as the other chip components and a thorough understanding of the
potential degradation mechanisms is needed.
The main task of this thesis/internship is the electrical characterization of these local interconnects. This includes
the evaluation of various newly designed test structures, the comparison of different local interconnect processes
and the investigation of potential reliability issues.
Type of project: Thesis or internship project (preferred duration is 6 months)
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering
Responsible scientist:
For further information or for application, please contact Thomas Kauerauf (Thomas.Kauerauf@imec.be).
Time-Dependent Dielectric Breakdown (TDDB) reliability of advanced CMOS gate
dielectrics
CMOS scaling is not only concerned with the reduction of the channel length and channel width, but also the
scaling of other transistor parameters such as the gate dielectric thickness. Recently high-k gate dielectric were
introduced and the long-term reliability of these ultra-thin layers is of major concern. The time-dependent
dielectric breakdown (TDDB) is one of the critical mechanisms, where the generation of individual defects in the
dielectric leads to an increase in gate leakage current and eventually to device failure. Although there has been a
lot of learning on TDDB in the recent years, there are still many open questions waiting to be answered.
The main task of this thesis/internship is to study the effect of electrical stress at the gate on key transistor
parameters. Since the degradation does not occur abrupt but gradually, testing and analyzing the shift of these
parameters over time is required. A second aspect will be to evaluate whether these parameter shifts are actually
critical to the device performance and if additional effects such as self-heating can be expected.
Type of project: Thesis or internship project (preferred duration is 6 months)
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering
Responsible scientist:
For further information or for application, please contact Thomas Kauerauf (Thomas.Kauerauf@imec.be).
Master Thesis/Internship Topics 2013-2014
6
Conductive Atomic
characterization
Force
Microscopy
(C-AFM)
for
memory
devices
Conductive bridging resistive memory CBRAM, based on resistance switching mechanisms, is emerging as a
potential replacement for Flash and/or DRAM applications, due to its high scalability potential, for future 20 nm
technology nodes and beyond (fig. A).
Conductive atomic force microscopy C-AFM (fig. B) is a scanning probe microscopy technique, relying on a normal
atomic force microscope equipped with a current sensor capable to measure ultra low currents. C-AFM
represents an invaluable tool in two ways. First it allows examining very small features with nm-scale spatial
resolution (nanoscopic electrical probing), and secondly the tip can be used as a nano sized electrode.
This internship/thesis fits into the characterization framework for OXRRAM/CBRAM using C-AFM. You will be
trained in the use of the tool and you will intensively use it focusing on device characterization methodologies.
During the period of the internship the student will focus particularly on material characterization and
environmental conditions .The data analysis and interpretation will cover an important part of the work; you will
apply statistical principles in data collection and will be asked to rule out your results. You will work in an
international R&D team; a good command of English language is required.
The detailed content of the work will be defined in detail at the moment of starting this project.
Type of project: Thesis or internship project of 6 months
Degree: Master in Science or Master in Engineering majoring in physics, electrical engineering, material science,
chemistry
Responsible scientist:
For further information or for application, please contact Umberto Celano (Umberto.Celano@imec.be).
Investigation and optimization of the electrical switching properties of scaled
Ta2O5-based resistive RAM memory cells
The Resistance RAM (RRAM) is a new class of memories emerging as serious candidate for future memory
replacement. Resistance RAM cells typically consist of an insulator material sandwiched between two metal
electrodes, and exhibiting resistive-switching properties, that is to say the application of an electrical
current/voltage to the cell induces reversible changes of the cell resistance, which allows thus programming
different memory states.
For metal/oxide/metal RRAM devices, the switching to the low resistance state (LRS) is understood as the
formation of oxygen-vacancy chain through the oxide while the return to the high resistance state (HRS) is due to
partial recovery of these defects, the two operations being electrically induced.
Ta2O5 materials have recently drawn a lot of attention due to excellent set of RRAM memory properties
demonstrated recently on scaled cells (see Fig.1). Not only controlled memory operation, low programming
power, and good data retention were demonstrated, but also in particular longer write-programming endurance
results were obtained on such material (Fig.1c) than on other switching oxides.
Master Thesis/Internship Topics 2013-2014
7
(a)
(b)
(c)
Fig1: examples of scaled Ta2O5-based RRAM cell (a), switching I-V traces (b), and excellent write endurance properties (c), as extracted from “M.-J. Lee et
al., Nature Materials, vol.10, 2011, p165”
However, little is known yet with respect to the switching mechanisms and improvement potentials in Ta2O5based RRAM. We recently undertook the integration development of scaled Ta2O5 RRAM memory cells stacked
on memory-select transistors. The purpose of the internship will be to study the effect of processing and cell-stack
material combinations (including electrodes) on the electrical-switching properties. To this aim, the following
methods will be used:
• Standard I-V measurements
• Constant voltage stress tests
• Above methods at different temperatures
• Pulse programming using sub-10ns wide electrical pulses
• Possible C-V measurements
• Possible modeling activity
The study will be carried out within a project team consisting of experts in different fields (processing, integration,
physical characterization, modeling ...), so that the understanding and modeling of the electrical results can be
facilitated.
The study will also be realized in close collaboration with industrial partners. The gained understanding of the
switching will allow defining an optimum stack configuration satisfying the industrial specification for memory
operation.
Type of project: Internship project of minimum 5 months
Degree: Master in Science or Master in Engineering majoring in material science, physics, electronics
Responsible scientist:
For further information or for application, please contact Ludovic Goux (Ludovic.Goux@imec.be).
Master Thesis/Internship Topics 2013-2014
8
Measurement and circuit modeling of advanced interconnect reliability
Deep submicron interconnect scaling leads to severe issues with reliability of the wires. Both electromigration and
TDDB (Time-dependent dielectric
breakdown) play a major role.
In this thesis, we want to measure the characteristics of deeply scaled interconnect schemes to evaluate the
degradation mechanisms and to characterize them under different conditions.
Moreover, based on these measurements we want to build a SPICE-level model which allows to model the effects
in a parametric way for use in circuit level simulations of data-path or memory structures.
We are looking for a student with a strong interest in measurement setups and hardware, basics of electrical
SPICE-level modeling, basics of reliability degradation.
Type of project: Thesis project of minimum 6 months
Degree: Master in Engineering majoring in micro- or nano-electronics
Responsible scientists:
For further information or for application, please contact Kristof Croes (Kristof.Croes@imec.be) and Francky
Catthoor (Francky.Catthoor@imec.be).
Evaluation of MgO as tunnel barrier in material stacks for MRAM applications
Magnetic random access memory (MRAM) is a non-volatile memory having the information stored in the
magnetization direction. In order to realize next generation of high density non-volatile memory a lower switching
current density and high thermal stability are needed. A promising solution to achieve these requirements in
MRAM relies on MgO based magnetic tunnel junctions (MTJs) with perpendicular magnetic anisotropy. Crystalline
MgO with (001) texture is needed to achieve perpendicular magnetic anisotropy in CoFeB/MgO/CoFeB based
MTJs. Parameters that are believed to have an important impact on performance are: texture, interface, B-content
of CoFeB, seed and capping layers or post-deposition anneals conditions. In this project basic understanding of the
stacks is being built up. MgO will be deposited via MgO RF sputtering or Mg post-oxidation. A comparison with
MgO ALD (atomic layer deposition) properties could be performed. The project will comprise beside stack
deposition, extensive physical analysis such as XRD, AFM, TEM, SIMS, XPS and magnetic properties such as
evaluation of magnetoresistance ratio and magnetization saturation.
1. S. Ikeda, K. Miura, H.Yamamoto, K. Mizunuma, H.D. Gan, M. Endo, S. Kanai, J. Hayakawa, F. Matsukura, and H. Ohno, Nature Materials, 2010, 9,
721.
2. K. Yakushiji, K. Noma, T. Saruya, H. Kubota, A. Fukushima, T. Nagahama, S. Yuasa and K. Ando, Applied Physics Express, 2010, 3, 053003.
3. D.C. Worledge, G. Hu, D.W. Abraham, J.Z.Sun, P.L. Trouillard, J. Nowak, S. Brown, M.C. Gaidis, E.J. O'Sullivan and R.P. Robertazzi, Applied Physics.
Letters, 2011, 98, 022501.
4. Y.S. Choi, K. Tsunekawa, Y. Nagamine, and D. Djayaprawira, Journal of Applied Physics, 2007, 101, 013907.
Type of project: Thesis and/or internship project of 3 up to 6 months
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in material science,
physics, electronics, chemistry
Responsible scientist:
For further information or for application, please contact Mihaela Popovici (Mihaela.Ioana.Popovici@imec.be).
Master Thesis/Internship Topics 2013-2014
9
Thermo-compression bonding of fine-pitch micro-bumps for 3D integration of ICs
Three-dimensional integration of ICs is a major driving technology for future size shrinkage and performance
improvement of electronic products. One of the key elements in 3D integration is to build reliable fine pitch
interconnects between the vertically stacked ICs.
At imec, we are working on thermo-compression bonding technology to make interconnection joints between the
micro-bumps on the ICs. In this master thesis, you will work on both the theoretical and experimental aspects of
thermo-compression bonding to deepen the understanding of this process and to further develop it towards finer
pitch requirements. You will focus on the investigation of actual physical conditions and resulting micro-scale
changes applied on the bonding interfaces between micro-bumps under different process conditions, and their
influence on the final bonding quality. In the implementation of this work, you will be involved in model building,
planning of experiments, processing, characterization, and finally the analysis of results. You will have access to
cutting-edge tools with the guidance from experienced researchers and engineers.
Type of project: Thesis project of 6 months
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in physics, applied
mechanics, material science or relevant fields
Responsible scientist:
For further information or for application, please contact Teng Wang (Teng.Wang@imec.be).
Study of chipping mechanisms in the dicing of thin silicon wafers
Chipping of silicon wafers during their dicing is an important factor which limits the throughput and yield of the
dicing process. Chipping also plays a significant role in determining the reliability of ICs. The recent development of
3D integrated ICs and ultra-thin packages have strongly driven the need of thinning silicon wafers to a thickness
range of below 100 µm, which has made the
In this thesis work, your focus will be on the understanding of chipping mechanisms on both front sides and back
sides of thin silicon wafers. The target is to identify different chipping mechanisms under different dicing conditions
and on wafers with different passivation layers through carefully designed experiments and microscopic inspection
using both optical and scanning electron microscopes. You will be involved in design and execution of experiments,
characterization, and analysis of experimental results. You will have access to cutting-edge processing and
metrology tools, assisted by experienced researchers and engineers.
Type of project: Thesis project of 6 months
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in physics, material
science, mechanical engineering or relevant fields
Responsible scientists:
For further information or for application, please contact Teng Wang (Teng.Wang@imec.be) and Kenneth Rebibis
(Kenneth.June.Rebibis@imec.be).
Master Thesis/Internship Topics 2013-2014
10
Evaluation of photoresist outgassing for Extreme Ultraviolet Lithography
Extreme Ultraviolet (EUV) light is currently of increased interest in semiconductor processing. EUV Lithography
(EUVL) is the leading candidate for 15nm half-pitch device manufacturing and beyond. One of the concerns of this
process technology is related to outgassing of materials in the vacuum environment – e.g. from photoresists –,
which, enhanced by the EUV irradiation, can result in a reflectivity decrease of the optical elements and in other
decrease of exposure tool performance.
In this field the student would work at imec on an experimental outgassing set-up (Fig. 1) to evaluate the EUV
related outgassing and contamination and is involved in outgassing analysis of various photoresist materials. This
will contribute significantly to the understanding how materials and process conditions can impact contamination in
the EUV scanners, and lead to procedures to qualify resist materials before they are used on the EUV scanners.
Fig.: Experimental EUV outgassing set-up at imec for investigation of outgassing of lithography materials.
Type of project: Preferably internship project of minimum 6 months
Degree: Master in Science or Master in Engineering majoring in physics, material science, chemistry
Responsible scientist:
For further information or for application, please contact Ivan Pollentier (Ivan.Pollentier@imec.be).
Deposition, characterization and application of dielectric films
New dielectric films are being developed for many applications in integrated circuits. Dielectric films are, in
general, used to form an electrical insulator between active devices-transistors and/or electrically conducting metal
lines. Their main characteristics are:
• good uniformity over the wafer
• high resistivity
• controlled stress
• hardness and Young’s modulus
Master Thesis/Internship Topics 2013-2014
11
The deposition process also has the following needs:
• reproducibility and compatibility with other process steps in the manufacturing of the integrated circuit
• the adhesion of the film to films below and above has to be assured
• a good reliability of the IC, which is strongly dependent on the quality of the dielectric films
The characterization of thin dielectric films consists of several phases. At imec, we start with the determination of
thickness, refractive index, density, chemical composition through Fourier Transform Infrared spectrometry,
stress, Young’s modulus, hardness, porosity, hydrophilicity and dielectric constant of the films. If this
characterization looks promising, a second series of tests which simulate other (former and later) process steps,
are performed; this also includes tests to determine the adhesion to other films, mainly by 4 point bending analysis.
Also, a more detailed chemical analysis, e.g. through XPS and TOFSIMS, will be performed. If all tests are positive,
finally, the material is used in an integration process, resulting in a real test chip and the final electrical
characterizations (including reliability characterizations) are made.
The student will be very strongly involved in the detailed characterization of the basic film properties. Hereby
(s)he will use state of the art analysis equipment, such as ellipsometers, a Fourier Transform Infrared
spectrometer, a high precision mass measurement system, and others. Furthermore (s)he will also be involved in
the next phase of the characterization cycle, as setting up the processes for the simulation of integration aspects
and the electrical characterization on test chips.
Academic and industrial results will be reported in meetings where both imec staff and industrial affiliates
participate.
Type of project: Internship project of 6 months
Degree: Master in Science or Master in Engineering majoring in material science, chemistry
Responsible scientist:
For further information or for application, please contact Patrick Verdonck (Patrick.Verdonck@imec.be).
Development, characterization and application of pore sealing treatments
New low-k dielectric films are being developed for many applications in integrated circuits. The new low-k films
are quite porous and have large pores. During the integration of these low-k films into an integrated circuit, it is
necessary to seal these pores in order to obtain structures with a high reliability.
The pore sealing process has to obey demanding requirements, such as:
• the final thickness of the pore sealing films should be as low as possible, of the order of a few nm
• the dielectric constant of the pore sealing film should be as low as possible, below 4
• during the deposition of the pore sealing film, the pores in the bulk of the low-k film have to remain open
• the pore sealing treatment should damage the low-k film as little as possible
At imec, we have already started to explore different routes for these pore sealing treatments. The deposition of
both dielectric and metal films is being studied. Also the combination of different treatments (plasma, application of
self assembled monolayers etc.) are being investigated. Pore sealing of different materials is being tested, as well on
films with a dielectric constant of less than 2.0 and very large pores, with a pore diameter up to 4 nm, as on films
with a dielectric constant of 2.4 with a pore diameter of less than 1 nm.
Different characterization techniques are applied. Ellipsometric porosimetry is very important to detect the sealing
of the treatments. Also determination of the final dielectric constant by C-V measurements is essential. Besides
these, the most interesting film stacks are also being characterized by other techniques such as: Fourier Transform
Infrared spectrometry, XPS and TOFSIMS. If these tests yield positive results, the new treatment is used in an
integration process, resulting in a real test chip and the final electrical characterizations (including reliability
characterizations) are made.
Master Thesis/Internship Topics 2013-2014
12
The student will be very strongly involved in the detailed characterization of the film-stack properties. Hereby
(s)he will use state of the art analysis equipment, such as ellipsometers, a Fourier Transform Infrared
spectrometer, a high precision mass measurement system, C-V meters and others.
Academic and industrial results will be reported in meetings where both imec staff and industrial affiliates
participate.
Type of project: Internship project of 6 months
Degree: Master in Science or Master in Engineering majoring in material science, chemistry
Responsible scientist:
For further information or for application, please contact Patrick Verdonck (Patrick.Verdonck@imec.be).
Hot carrier reliability on advanced logic/DRAM devices
The continuous device scaling down allows the integration of a large number of transistors on a chip and increases
the speed. However since the 65 nm node, the VDD is saturating at a level around 1V due to the non-scaling subthreshold slopes of the MOSFET’s. And this increases electric fields with scaling, makes hot carrier reliability an
very important issue.
In this study, hot carrier degradation in very thin EOT regime will be investigated by exploring defects in the gate
oxide/ junction. Also, the impact of the process conditions including different high-k stacks and/or device structure
will be studied. For the applicant, a good knowledge of semiconductor physics is required. During the project, the
student will have the opportunity to participate and interact with the researchers of the Logic/DRAM program.
Type of project: Thesis and/or internship project
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in material science,
physics, electronics
Responsible scientist:
For further information or for application, please contact Moon Ju Cho (Moon.Ju.Cho@imec.be).
Modeling and extraction of TSV characteristics: resistance, capacitance and
inductance
3-D INTEGRATED (IC) stacking technology consists of stacking and connecting ICs one on top of the other, as
shown in Fig.1.
a)
b)
Fig. 1a): 3D stacking concept; b) Stacking of 2 dies containing test structures for 3D technology assessment
The potential advantages of this technology are in system integration, in terms of reduced footprint, possibility of
integrating in 3D ICs with different technologies and lower cost with respect to traditional 2-D ICs.
Master Thesis/Internship Topics 2013-2014
13
Electrical connections between dies are vertical; in the so-called back-to-face approach, they are obtained by
etching large vias in the substrate of the top die, with diameter in the range of few microns. These vias are then
filled with a conductor material, usually copper (Cu), after putting a dielectric layer in the via cavity, to insulate the
conductor from the substrate, as shown in Fig. 2a).
TSV Landing pad
TSV top
Substrate
M1_T
IMD
PMD
p+ ring
Top die
TSV
TSV insulator
M2_B
P-SUBSTRATE
Glue layer
IMD
a)
Bottom die
Fig. 2a): TSV in cross section; b) Typical CV curve of TSV capacitor
The obtained connections are named Through-Silicon Vias or TSVs. During the stacking phase, the TSV lands on a
specific contact pad (or landing pad) on the surface of the bottom die and is permanently welded to it by a
thermo-compression process. The vertical connection between top and bottom die must serve the typical
functions supported by standard 2-D interconnects: signal propagation (analog and/or digital), clock distribution,
power supply and ground. Therefore, the electrical characteristics of the TSV, essentially resistance R, capacitance
C and inductance L play an essential role in defining the propagation speed and the power consumption of the
vertical connections.
Predicting the TSV electrical characteristics require the availability and the use of models for calculating R, C and L.
These models already exist and are based on analytical formulas; however, they are limited to the TSV as a
cylinder structure and do not take into account the presence of the connections to the TSVs, as the landing pad,
the metal layers on top of the TSV and possible Cu pillars, as illustrated in Fig.2b).
The purpose of this thesis/internship is to define parametric models, based on geometry and material parameters
of the TSV and of the other connection elements attached to it, to be given as input to electrostatic solvers for
extracting resistance and capacitance of the entire TSV connection assembly, which would be too complex to
model with analytical formulas. In particular, the following activities are foreseen:
1. Implementation of parametric 3D models based on dimensions and material parameters of the entire TSV
assembly;
2. Calibration of the models with measured data on test structures including real TSVs;
3. Definition of experiments for exploring in simulation the impact of dimensions and material parameters on
extracted TSV R and C characteristics;
4. Reporting and discussing the results with Imec experts in 3D processing, reliability and characterization.
Type of project: Internship or thesis project
Degree: Master in Electrical Engineering or Master in Physics
Responsible scientists:
For further information or for application, please contact Michele Stucchi (Michele.Stucchi@imec.be) and Kristof
Croes (Kristof.Croes@imec.be).
Master Thesis/Internship Topics 2013-2014
14
Characterization of capacitance vs. voltage in TSV capacitors
3-D INTEGRATED (IC) stacking technology consists of stacking and connecting ICs one on top of the other, as
shown in Fig.1.
a)
b)
Fig. 1a): 3D stacking concept; b) Stacking of 2 dies containing test structures for 3D technology assessment
The potential advantages of this technology are in system integration, in terms of reduced footprint, possibility of
integrating in 3D ICs with different technologies and lower cost with respect to traditional 2-D ICs. Electrical
connections between dies are vertical; in the so-called back-to-face approach, they are obtained by etching large
vias in the substrate of the top die, with diameter in the range of few microns. These vias are then filled with a
conductor material, usually copper (Cu), after putting a dielectric layer in the via cavity, to insulate the conductor
from the substrate, as shown in Fig. 2a).
TSV Landing pad
TSV top
Substrate
M1_T
IMD
PMD
p+ ring
Top die
TSV
TSV insulator
M2_B
a)
P-SUBSTRATE
Glue layer
IMD
Bottom die
Fig. 2a): TSV in cross section; b) Typical CV curve of TSV capacitor
The obtained connections are named Through-Silicon Vias or TSVs. During the stacking phase, the TSV lands on a
specific contact pad (or landing pad) on the surface of the bottom die and is permanently welded to it by a
thermo-compression process. The vertical connection between top and bottom die must serve the typical
functions supported by standard 2-D interconnects: signal propagation (analog and/or digital), clock distribution,
power supply and ground. Therefore, the electrical characteristics of the TSV, essentially resistance, capacitance
and inductance play an essential role in defining the propagation speed and the power consumption of the vertical
connections.
The TSV capacitance is due to the Metal Insulator Semiconductor (MIS) capacitor formed by the Cu conductor,
the insulator and the substrate around the TSV. MIS capacitors are well known for being voltage-dependent; the
typical capacitance vs. voltage characteristics (CV curve) measured at 100kHz is in Fig.2 b), where the
accumulation, transition and depletion zones are indicated. The 3D stacking process may cause anomalies in the
CV curve of TSVs. For example, the depletion region in which the TSV capacitance is lower than in accumulation,
may result identical to the accumulation region, due to defects in silicon induced by some processing steps.
The purpose of this thesis/internship is to investigate the causes of this anomalous CV curves in Imec TSVs and
possibly find a solution to avoid them. In particular, the following activities are foreseen:
Master Thesis/Internship Topics 2013-2014
15
1. Measure of CV curves on specific TSV test structures at different phases of the stacking process; different
process conditions, measurement techniques and measurement parameters will be applied for this purpose;
2. Analysis of the measurement results, reporting and discussion in brainstorming sessions with imec experts
in 3D processing, reliability and characterization;
3. Collaboration in determining the causes and the process step(s) responsible of anomalous CV curves;
4. Propose and verify possible solutions, together with imec experts in 3D processing, reliability and
characterization.
Type of project: Internship or thesis project
Degree: Master in Electrical Engineering or Master in Physics
Responsible scientists:
For further information or for application, please contact Michele Stucchi (Michele.Stucchi@imec.be) and Kristof
Croes (Kristof.Croes@imec.be).
Investigation of advanced self-rectifying resistive switching memory cells (SRCRRAM)
Resistive Random-Access-Memory (RRAM), based on resistance switching mechanisms, is emerging as a potential
nonvolatile memory candidate for below-20nm technology nodes, due to its better scalability, beyond the limits
currently predicted for NAND Flash. 10nm-small RRAM cells are shown to have low voltage operation, very fast
switching time, in the order of ns and below, small energy consumption per switching and good reliability. To take
on the benefits of these excellent attributes to circuit level and enable high density memory array implementation,
additional self-rectifying functionality is required for the resistive switching stack and needs to be achieved within a
two-terminal, 10nm scalable structure.
The main task of this internship/thesis is to screen new resistive switching memory concepts with the aim of
assessing their potential for self-rectifying memory cells and/or investigate RRAM cells that show self-rectifying
characteristics, with the aim of understanding the switching behavior, relate it to intrinsic performance and identify
paths for further improvement/optimization.
You will be involved in electrical characterization, focusing on performance and/or reliability aspects. You will be
using state-of-the-art instrumentation and you will apply statistical principles in data collection using in-house
developed characterization methodologies, so as to ensure a short response time in characterization. You will
process data and assist in their interpretation. Feedback for process improvement is a key point.
You must have a good background in semiconductor physics and knowledge of CMOS technology. You must be
fluent in at least one programming/data analysis environment such as Matlab or similar and familiar with LabView
and basic instrumentation for electrical testing. You will work in an international R&D team; a good command of
English language is required.
The detailed content of the work will be defined at the moment of starting this project, in line with latest research
priorities.
Type of project: Internship or thesis project of 6 months
Degree: Master in Science or Master in Engineering majoring in electronics, electrical engineering, physics
Responsible scientist:
For further information or for application, please contact Bogdan Govoreanu (Bogdan.Govoreanu@imec.be).
Master Thesis/Internship Topics 2013-2014
16
Self-assembled monolayers as enabling technology for microelectronics
As the total transistors and interconnect sizes come down to few tens of nanometers a shift in paradigm for the
manufacturing and integration of microelectronics components becomes apparent. Organic molecules - owing to
their size, mechanical flexibility and chemical tunability - fit well in this slot and, thus, are expected to play a key
role in IC downscaling. In this respect, self-assembled monolayers (SAMs) seem the best candidates. SAMs are a
prototypical form of nanotechnology: the SAM precursor molecules carry the “instructions” required to generate
an ordered, nanostructured material without external intervention. SAMs demonstrate that molecular-scale design,
synthesis, and organization can generate macroscopic materials properties and functions. Although the details of
the thermodynamics, kinetics, and mechanisms of assembly will differ significantly, these monomolecular films
establish a model for developing general strategies to fabricate nanostructured materials from individual
nanometer-scale components. Because SAMs can assemble onto surfaces of any geometry or size, they provide a
general and highly flexible method to tailor the interfaces between nanometer-scale structures and their
environment with molecular (i.e., subnanometer scale) precision. SAMs can control the wettability and
electrostatic nature of the interfaces of individual nanostructures and thus their ability to organize into large
assemblies adding chemical functionality, thermodynamic stability (e.g., improving the adhesion at the
dielectric/metal interface).
In particular, metallization of SAMs, i.e. the formation of metallic or barrier overlayers or clusters on top of
monomolecular organic films, is of great importance for many areas of fundamental and applied research. Albeit
this problem was actively addressed in the last years, reliable methods to the deposition of metal on top of the
SAM are continuing to be a topic of intense research. This task is challenging since most of the studies show an
undesirable metal penetration through the SAM. It is generally believed that this is caused by structural defects in
the monolayer. Cu is the interconnect material of choice in the metallization step for advanced semiconductor
device manufacturing. The current approaches to Cu metallization include chemical vapor deposition (CVD),
physical vapor deposition (PVD), selective electroless deposition (ELD) and electroplating.
The purpose of this work is to characterize and benchmark the thin SAM organic films deposited both in liquid
phase and vapor phase on full 300mm wafer scale as a function of the ELD films quality. The effects of the SAMs
chemistry (functional groups, vapor vs. liquid phase deposition, deposition solvents etc...) and ELD experimental
conditions on the deposition mechanism and efficiency of the electroless Cu bath (e.g. in terms of Cu thickness
and roughness control, adhesion at the interfaces dielectric/SAMs/Cu..., which will be characterized by the student)
will be investigated.
Type of project: Thesis and/or internship project of minimum 6 months
Degree: Master in Science or Master in Engineering majoring in chemistry, material science
Responsible scientist:
For further information or for application, please contact Silvia Armini (Silvia.Armini@imec.be).
Advanced barrier CMP slurry development
In order to build even smaller devices, very narrow structures have to be filled with copper to achieve advanced
interconnects. The aspect ratio of these lines makes them hard to fill without defects and voids. One of the
approaches that helps the deposition of copper into narrow structures is to vary the underlying barrier-seed layer.
The choice of this layer improves copper electroplating and can make ELD Cu deposition possible.
In the subsequent processing steps, the copper as well as the underlying barrier-seed layer needs to be removed in
the field area, leaving conducting material only within the interconnect structures. This is achieved through a Cu
Chemical Mechanical Polishing (CMP) step followed by a barrier CMP step (which removes the barrier-seed layer).
When polishing these barrier layers using CMP, there are several process issues that can occur. First of all, the
barrier metal needs to be removed quickly and evenly, which can be hard due to native oxides on the surface.
Second, it is necessary to keep corrosion issues under control during the CMP process.
Master Thesis/Internship Topics 2013-2014
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The goal of this project is to optimize barrier-seed layer removal rates on blanket wafers while limiting (galvanic)
corrosion using model slurries which are optimized for barrier CMP. In order to achieve a good removal rate,
different oxidizers and complexing agents are added to model slurries while surfactants/inhibitors are added to
protect the surface against corrosion and improve planarity. Static etch rates for these slurries need to be
determined to estimate extent of static corrosion. Other CMP parameters (e.g. pressures, flow rates) can be
adjusted to further improve the process. Basic electrochemical measurements can be done as well to determine
the effect on the corrosion currents in the Cu-barrier CMP system for different slurry additives.
For the best performing slurries, it needs to be ascertained that the defectivity and planarity of the polished surface
is good. Performance with respect to other device materials needs to be checked. Time permitting, these slurries
may be tested on patterned wafers as well as on other advanced barrier materials.
Applied techniques include CMP on our experimental polisher, sheet resistance measurements, defectivity analysis,
electrochemical tests, etc.
A basic knowledge of chemistry is necessary, some experience in electrochemistry is a plus.
Type of project: Internship or thesis project of minimum 3 months
Degree: Master in Industrial Sciences or Master in Science majoring in chemistry, chemical technology, materials
science, physics
Responsible scientist:
For further information or for application, please contact Lieve Teugels (Lieve.Teugels@imec.be).
Development of a ramped voltage BTI procedure for fast gate dielectric testing
As the vertical scaling of the conventional poly-Si/SiO2/Si field effect transistors (MOSFET) reached the nanometric
scale, the high electric field dropping in the oxide resulted in an intolerable gate leakage current. At that point,
industry opted for replacing the conventional SiO 2/poly-Si structure by high-k/metal gate stacks that tolerate
physically thicker oxide while keeping or even increasing the oxide capacitance. Once the leakage current issue
was circumvented, the so-called bias temperature instability (BTI) is becoming one of the most critical factors,
complicating the qualification of the future technology nodes [ 1, 2, 3]. Furthermore, the number of stochastically
behaving gate oxide defects in each device decreases to a numerable level due to the lateral downscaling, while
their relative impact on the device characteristics increases. For all these reasons, BTI lifetime cannot be described
any longer by a unique number, and BTI lifetime distribution has to be taken into consideration. As a consequence,
even in the ideal case of the average BTI lifetime meeting the ITRS [ 4] specifications, a fraction of nanoscaled devices
will fail at low overdrives.
The main task of this thesis/internship is to develop a fast methodology to assess NBTI lifetime distributions. A
ramped voltage BTI procedure is proposed as fast alternative to the time consuming current methodology. This
includes the adaptation of the test software, the demonstration of the finished routine, the benchmark with the
classical BTI routine and eventually the electrical testing of advanced gate stacks.
[1] E. Cartier, A. Kerber, T. Ando, M. M. Frank, K. Choi, S. Krishnan, B. Linder, K. Zhao, F. Monsieur, J. Stathis and V. Narayanan “Fundamental aspects of
HfO2 -based high-k metal gate stack reliability and implications on tinv -scaling,” in Proc.: IEDM 2011, pp. 441-444.
[2] M. Cho, M. Aoulaiche, R. Degraeve, B. Kaczer, J. Franco, T. Kauerauf, Ph. J. Roussel, L. Å. Ragnarsson, J. Tseng, T.Y. Hoffmann and G. Groeseneken,
“Positive and negative bias temperature instability on sub-nanometer EOT high-k MOSFETs,” in Proc.: IRPS 2010, pp. 1095-1098.
[3] J. Franco, B. Kaczer, G. Eneman, J. Mitard, A. Stesmans, V. Afanas'ev, T. Kauerauf, Ph.J. Roussel, M. Toledano-Luque, M. Cho, R. Degraeve, T. Grasser,
Master Thesis/Internship Topics 2013-2014
18
L.-Ǻ. Ragnarsson, L. Witters, J. Tseng, S. Takeoka, W.-E. Wang, T.Y. Hoffmann, G. Groeseneken, “6Å EOT Si0.45 Ge0.55 pMOSFET with optimized reliability
(V DD =1V): Meeting the NBTI lifetime target at ultra-thin EOT,” in Proc.: IEDM 2010, pp.70-73.
[4] International Technology Roadmap for Semiconductors available at http://public.itrs.net.
Type of project: Internship or thesis project of 6 months preferably
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering
Responsible scientist:
For further information or for application, please contact Maria Toledano Luque (Maria.ToledanoLuque@imec.be).
Compact modeling of advanced transistors
As CMOS technology is entering the 10nm and sub-10nm technology era, important innovations are introduced in
the device design and even in the device concepts. New constraints are also appearing such a layout dependent
effects. To enable circuit design based on these new transistors and behaviors, the compact models used for circuit
simulations must evolve accordingly.
Working on compact modeling allows to have a very broad view on the field of semiconductors, from fabrication
constraints towards device physics, and taking into account system level requirements.
The goal of this project is to model modern devices (FinFETs) fabricated at imec. This work will imply reviewing
the standard methodology used in transistor compact modeling, setup the required experiments to extract key
transistor model parameters, perform the measurements, and use the results to build compact models based on
Silicon data. Industry standard software for compact model extraction will be available, as well as access to all
technical information required to perform compact model extraction. The student will be part of the compact
modeling team and interact with device developers and circuit designers.
Type of project: Internship or thesis project of 6 months
Degree: Master in Engineering majoring in (micro)electronics
Responsible scientists:
For further information or for application, please contact Morin Dehan (Morin.Dehan@imec.be) and Marie Garcia
Bardon (Marie.GarciaBardon@imec.be).
Modeling of temperature effects in advanced devices
As technology feature sizes are reduced, temperature becomes an important parameter in devices and in circuit
design. Temperature impacts strongly the speed, the power and the reliability of circuits. Massive amounts of heat
are generated by the higher and higher density of power with lower access to cooling. The low access to heat
dissipation can even generate "self-heating" effects, for example in FinFETs. In parallel, the use of advanced
materials stacks change the sensitivity of devices to temperature and can even reverse well-known trends used to
design circuits.
These effects have to be understood and captured in device compact models to be transferred at circuit design
level, where their impact will be evaluated and solutions could be found.
The goal of this project is to understand and model how temperature affects device functionality in bulk and SOI
FinFETs, as well as to understand the impact of scaling on temperature variations. The study will be based on
measurements of imec devices. The modeling and understanding will be mainly based on use of industry standard
compact models such as BSIM to produce model cards for circuit simulation. The student will be part of the
compact modeling team but also interact with the device characterization engineers and circuit designers.
Master Thesis/Internship Topics 2013-2014
19
Type of project: Internship or thesis project of 6 months
Degree: Master in Engineering majoring in (micro)electronics
Responsible scientists:
For further information or for application, please contact Morin Dehan (Morin.Dehan@imec.be) and Marie Garcia
Bardon (Marie.GarciaBardon@imec.be).
Characterization and modeling of oxide border traps in Ge/III-V MOSFETs
Recent developments on CMOS-driven III-V and Ge MOS (Metal-oxide-semiconductor) technologies provide new
opportunities in advancing the performance envelope of logic devices as well as lowering the operating power. The
quest of high speed/low power post-Si CMOS with heterogeneous integration calls for in-depth studies on various
aspects including device modeling and characterization, performance benchmarking, reliability/passivation/contact
studies and ultimately, scaling beyond 10nm node. Recently, the impact of oxide traps (border traps) on device
performance has been demonstrated [1] on III-V and Ge MOSFETs.
The proposed research activities for the internship include (but not limited to):
1. Electrical characterization of III-V/Ge planar MOS- and FIN- FETs for gate stack performance, and oxide and
interface evaluation (Admittance analysis, AC-transconductance, charge pumping... ), paired to device
benchmarking.
2. Modeling and simulation: relating the border traps and electrical results measured on devices with different
channel materials, gate stacks and layer structures.
[1] D. Lin, et al, p. 645 IEDM 2012
Type of project: Internship or thesis project
Degree: Master in Science or Master in Engineering majoring in electrical engineering, physics, materials science
Responsible scientists:
For further information or for application, please contact Koen Martens (Koen.Martens@imec.be) and Dennis Lin
(Dennis.Lin@imec.be).
Interface stability and reliability of high-mobility channel MOSFETs
After the end of conventional CMOS scaling era, unabated enhancement of the device performance has been
guaranteed by materials and architecture innovation. Three main technological breakthroughs have been
introduced in recent CMOS nodes: strain engineering (90nm node), high-k/metal gate technology (45nm) and trigate (finFET) architectures (22nm). A new innovation will be soon needed for continued equivalent scaling in future
nodes.
One of the most promising options currently under consideration is the introduction of high-mobility channel
materials, namely Ge-based channels for pMOS and III-V compounds for nMOS. However, significant technological
challenges remains to be solved. In particular, interface passivation of non-Si channel materials is a critical issue
which severely impacts the device performance and reliability. Moreover, further challenges derive from the need
of integrating such novel materials in the novel finFET architecture and in combination with previously introduced
innovations (strain-engineering, high-k/metal gate stacks).
The main task of this thesis/internship is the electrical characterization of high-mobility channel device prototypes.
This includes the use of several measurement approaches (I-V, C-V, pulsed I-V, Charge Pumping, Measure-StressMeasure techniques) with both manual and semi-automatic computer-controlled measurement setups.
Master Thesis/Internship Topics 2013-2014
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Type of project: Internship or thesis project of 6 months preferably
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering
Responsible scientist:
For further information or for application, please contact Jacopo Franco (Jacopo.Franco@imec.be).
Carbon nanotube contacts: electrical characterization of CNT – damascene
contacts
Carbon Nanotubes (CNT) have remarkable electrical, thermal and mechanical properties that make them
interesting candidates as a metal in future contact applications where conventional metals cannot meet the
required specs that come with the extreme scaling in nanotechnology. At imec, CNT interconnects are being
created and electrically evaluated inside 150nm diameter contact holes. All steps for the CNT integration, the
steps for patterning the Cu damascene top contact, and the mask set used are compatible with 130nm device
technologies on 200mm wafers.[1,2] Our new platform is designed for automatic electrical testing using Kelvin
vias, parallel vias or other probing pads.
This project is focusing on improving the CNT quality to reduce the contact resistance [1-3]. In parallel, splits in
the integration module on the top contact are included to obtain more insight in the CNT-to-metal contact. The
electrical performance studies have the objective to obtain a detailed understanding of the CNT interconnect and
find ways to improve the CNT interconnect performance.
The purpose of the project is: (1) Obtaining a better understanding of the behavior of the CNT interconnect
under stressed conditions (high frequency, breakdown, aging, reliability...), supported by theoretical modeling. (2)
Developing a theoretical model that can be validated experimentally to distinguish the resistance from the CNT
and bottom and/or top contact.
The CNT growth and integration work is realized in a
cross-functional team bridging the two groups of Prof. Dr.
S. De Gendt and Dr. Zs. Tökei (team InterConnect
Integration).
[1] van der Veen et al., IEEE IITC conf. proc. (2012) 14.2
[2] van der Veen et al., “Electrical Characterization of CNT contacts with Cu
damascene Top Contact” Microelectron Eng. (2013)
http://dx.doi.org/10.1016/j.mee.2012.09.004
[3] Chiodarelli et al. Nanotechnology 22 (2011) 085302.
Cross-section of the electrical structure showing four 150nm contact holes
filled with CNT and metallized with Cu single damascene top contact
Type of project: Internship or thesis project of minimum 4 months
Degree: Master in Science or Master in Engineering majoring in physics, electronics, material science,
nanotechnology
Responsible scientists:
For further information or for application, please contact Yohan Barbarin (Yohan.Barbarin@imec.be) and Marleen
van der Veen (Marleen.vanderVeen@imec.be).
Master Thesis/Internship Topics 2013-2014
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Carbon nanotube growth and its catalyst nanoparticle deposition for future contact
applications
Due to their remarkable electrical, thermal and mechanical properties, carbon
nanotubes (CNT) have been considered for various applications in different
fields of research. One particular application, situated in the world of
integrated circuits, is a CNT based interconnect and CNT contacts.
Various reports exist in literature where the growth of CNT with a high
quality is demonstrated. However, most of these results are obtained under
process conditions that are not fully CMOS compatible and hence cannot be
used in nanoelectronic applications in CMOS.
The aim of this project is to investigate and develop a CMOS compatible
growth process that results in high quality CNTs.
The CNTs need to be grown in very small via features (sub 22 nm) or
structures with a high aspect ratio (diameter with respect to depth of the
hole), as is projected for future generations of interconnects and other contact
applications (Figure 2). The most important boundary conditions for this CNT
growth are:
1) Catalyst placement on the bottom of the deep hole.
2) Achieve CNT growth directly on conductive substrates.
Figure 1: Schematic view of CNTs in small via
features (<60nm diameter)
The first part of the project focuses on the fundamental
aspect of catalyst deposition and choosing the
nanoparticle deposition process for CNT growth in
high aspect ratio features. After a good understanding
has been obtained on the catalyst deposition process, a
fixed catalyst will be chosen to study the CNT growth
with the objective to achieve sufficient CNT growth for
electrical characterization.
The work will start from earlier findings within the
CNT team in the group of Prof. Dr. S. De Gendt.
Figure 1: Scanning Electron Image of CNT growth in small vias
Type of project: Internship or thesis project of minimum 6 months
Degree: Master in Science majoring in chemistry, material science, nanotechnology
Responsible scientists:
For further information or for application, please contact Johannes Vanpaemel (Johannes.Vanpaemel@imec.be)
and Marleen van der Veen (Marleen.vanderVeen@imec.be).
Master Thesis/Internship Topics 2013-2014
22
Bottom-up fill of deep holes with nanowires for future contact schemes
Nanowires are expected to play a key role in the transistor and interconnect down scaling as the paradigm for
integration of microelectronics components is entering the sub-22nm scale. Conventional metals will no longer
simply meet the requirements needed for the performance and conventional depositions methods are no longer a
filling solution at sub-14nm dimensions.
The aim of this project is to realize CMOS compatible nanowire deposition
in extreme small dimensions at the nanoscale. The focus is to deposit the
metals like Cu and W, or alloys, using a void-free and preferably from
bottom-up growth process. Techniques that can be considered for the
metallic nanowire growth are chemical vapor deposition, atomic layer
deposition, or selective electroless or electrochemical deposition. The
bottom-up growth will be studied on metallic contacts or barrier layers.
Several test vehicles for the bottom-up growth will be available for the growth
tests.
The characterization of the vertical nanowires grown on a conductive
substrate will focus on the relation between the structural properties and the
electrical properties. The ultimate goal is to identify metallic nanowires that
can show ballistic transport on a sub-10nm scale. For this, it’s needed to study
and understand how the electrical conduction through the nanowires is influenced by the dimensions (diameter
and length), and whether optimization of the growth can improve the nanowires performance. Successful grown
nanowires can be tested further in full integration schemes using the advanced imec pilot line on 300mm full wafer
level.
The work will start from earlier findings within the cross-functional metallization teams bridging the group of H.
Struyf and the InterConnect Integration program of Dr. Zs. Tökei.
Type of project: Internship or thesis project of minimum 6 months
Degree: Master in Science or Master in Engineering majoring in chemistry, material science, nanotechnology
Responsible scientist:
For further information or for application, please contact Marleen van der Veen (Marleen.vanderVeen@imec.be).
Energy spectrum of a cylindrical superlattice nanowire
In this thesis the energy spectrum for a cylindrical nanowire consisting either out of heterostructure superlattice
or periodic gate configurations or periodic width fluctuations will be calculated. In first instance the student will
consider a simple periodic potential profile along the axis of the nanowire to understand the formation of the
miniband spectrum as a function of periodicity and potential energy heights. Once this problem is solved we will
consider periodic all-around gates and study the energy spectrum as a function of the applied gate voltages, wire
radius, spacing between the gates. Finally, the case of a periodic superlattice heterostructure and an infinite array
of periodically spaced width fluctuations will also be considered.
The research is situated in the broader quest for devices that can be fabricated in future sub-10 nm nodes.
Amongst other challenges, one problem to overcome is to suppress unwanted currents that remain present when
transistors are in sub-threshold mode (‘off’). One approach to this problem is the use of minibands to filter out the
electrons that contribute to this unwanted current. Hence a good understanding of the influence of wire
geometry, superlattice parameters, etc. on the formation of minibands is necessary. Since the usual semi-classical
approximations for semiconductors are no longer useful on this length-scale, calculations will start from solving the
Schrödinger equation itself, a paradigm called wavefunction engineering that is becoming increasingly more
important as devices continue shrinking.
Master Thesis/Internship Topics 2013-2014
23
The student will perform the aforementioned calculations by making acceptable approximations which will render
the problem tractable. If necessary the student can also rely on available software to numerically solve the
problem. The student will make an analysis of the energy spectrum and draw preliminary conclusions with respect
to the transport properties of the charge carriers in the nanowire.
The candidate should have a strong background/interest in solid-state physics, quantum mechanics and
computational physics.
Type of project: Thesis project
Degree: Master in Science or Master in Engineering majoring in physics, nanoscience, nanotechnology
Responsible scientist:
For further information or for application, please contact Bart Soree (Bart.Soree@imec.be).
Modeling of tunable band gap bilayer structures and devices
It is possible to tune the band gap in bilayer graphene and transition-metal dichalcogenides by external electric
fields applied perpendicular to the layers. The band gap of bilayer graphene increases while the band gap of MoS2,
MoSe2, MoTe2, and WS2 bilayer structures continuously decreases with increasing applied electric field. This field
effect suggests potential directions for the fabrication of novel electronic and photonic devices.
The focus of this master thesis will be on the modeling of the bilayer graphene tunneling field effect transistor
either in the P-N or P-I-N configuration. The possibility of tuning the band gap (electric field) by sweeping the gate
voltage offers a new path towards switching transistor devices on or off. Preliminary simulations have already
shown that sub-60 subthreshold slope current-voltage characteristics with reasonable Ion/Ioff ratios can be
achieved.
The student will make use of an existing simulation program based on the Non-Equilibrium Green’s Function
(NEGF) formalism. The purpose is to model, understand and investigate the device characteristics as a function of
gate voltage, insulator thickness and multiple gate configurations.
The candidate should have a strong background/interest in solid-state physics, quantum mechanics and
computational physics.
Type of project: Thesis project
Degree: Master in Science or Master in Engineering majoring in physics, nanoscience, nanotechnology
Responsible scientist:
For further information or for application, please contact Bart Soree (Bart.Soree@imec.be).
Design of an reliability characterization package for future generation highperformance CMOS transistors
Continuously shrinking the device size and device dielectric thickness results in changes of physical and electrical
properties which imposes limits on their usefulness, in particular a broad range of as-fabricated and stressgenerated defects strongly affect the device performance. It is important to characterize these defects on the basis
of extent of performance degradation caused by them in the CMOS devices. In particular, scaling the equivalent
oxide thickness (EOT) has tremendous impact on failure mechanisms like bias-temperature instability (BTI), timedependent dielectric breakdown (TDDB), hot carrier injection (HCI), stress-induced leakage current (SILC) and
random telegraph noise (RTN). Therefore, based on these degradation studies it is desired to introduce variants in
the deposition strategies to reduce the defect density or to mitigate their harmful effects.
Master Thesis/Internship Topics 2013-2014
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Since measuring strategies are tailored to each different failure mechanism, it is time-consuming to gather device
parameters for each of these failure mechanisms. The focus of this internship/thesis would be the development of a
software tool which combines a systematical and uniform approach for basic device parameter extraction in
combination with existing device reliability characterization packages. The gathered information should then be
extracted and processed to be stored in a central database.
The candidate will be given the opportunity to co-work with state-of-the art semiconductor reliability researchers
and scientists where he provides a generic software framework for future characterization of high performance
CMOS transistors. The candidate is required to have competent programming skills in general purpose
programming languages, preferably in Perl, C++. Knowledge of semiconductor components is recommended.
Type of project: Thesis project, possibly in combination with internship of 6 months
Degree: Master in Industrial Engineering majoring in computer sciences, electronics
Responsible scientists:
For further information or for application, please contact Erik Bury (Erik.Bury@imec.be), Pieter Weckx
(Pieter.Weckx@imec.be) and Ben Kaczer (Ben.Kaczer@imec.be).
Design and simulation of on-chip circuits for parallel characterization of ultrascaled transistors and SRAM cells for BTI reliability
It is well established that with the size of CMOS devices decreasing to atomic dimensions, the number of dopant
atoms in each device reduces to numerable levels, resulting in increased time-zero (i.e., as-fabricated) variability. At
the same time also the number of defects is decreasing to literally single-digit numbers, resulting in further
variability increase with time (i.e., increased time-dependent variability and thus, further reduced reliability). This
trend has recently lead to a shift in our perception of reliability: the “top-down” approach (deducing the
microscopic mechanisms behind the average degradation in large devices) is being replaced in deeply-scaled devices
by the “bottom-up” approach, in which the time-dependent variability is understood in terms of individual defects.
The small ensembles of stochastically behaving individual defects are then responsible for the wide time-dependent
distributions of CMOS device parameters. Understanding these distributions requires electrical measurements on
a large number of devices, necessitating in turn parallel evaluation schemes. Moreover, the impact of these defect
on circuit performance has barely been studied, except for simulations.
Parallel evaluation of device reliability and circuits to monitor the effect of these degradation mechanisms is of
crucial importance to gather enough statistical information. For this on-chip stressing and monitoring circuits,
capable of capturing the degradation effects on ultra-scaled transistors, (reduced drain current, threshold voltage
shift, ..) are required.
In this thesis project such on-chip circuits will be created where the candidate is given the chance to undertake
each step in the development process, from designing, simulating and (optionally) lay-outing of the circuit. The
candidate will be required to have a solid knowledge of semiconductor components with experience in both digital
and analog circuit design. Recommended skills include SPICE circuit simulation and Cadence (optional).
Type of project: Thesis or internship project of 5 up to 6 months
Degree: Master in Electronical Engineering or Nanoscience
Responsible scientists:
For further information or for application, please contact Erik Bury (Erik.Bury@imec.be), Pieter Weckx
(Pieter.Weckx@imec.be) and Ben Kaczer (Ben.Kaczer@imec.be).
Master Thesis/Internship Topics 2013-2014
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Graphene: device fabrication for optoelectronics
Graphene, an atomically-thin sheet of carbon atoms arranged in a sp 2 honeycomb lattice, has been successfully
isolated for the first time only in 2004 [Novoselov et al, Science 306 (2004) 666 .]. The peculiar electronic
properties of graphene arise mainly from the configuration of its energy band structure, which, combined with the
intrinsically low occurrence of defects and the stiffness of its lattice, allows for the featuring of intriguing 2-D
physical phenomena. With respect to optoelectronic device performances, the high transparency in the visible-light
range and the low resistivity of graphene sheets are the most attractive features, which makes graphene an ideal
candidate to explore further its potential as a transparent electrode.
The goal of this project is to study the layer interactions between substrate, graphene and optical active materials
(e.g. quantum dot interactions), to characterize device performances and by molecular fine-tuning increase the
optoelectronic device performance.
(a)
(b)
(c)
Figure: (a) Schematic of the QD-treated graphene transistor in the typical measurement configuration employed in this work. (b) Transfer
characteristics Ids vs. Vg of a SLG FET in pristine conditions, after QD deposition, and during QD excitation (532 nm laser). The inset shows an
optical microscope image of the 2-probe graphene device (scale bar: 2 μm). (c) Energy level diagram of the CdSe/ZnS QDs in contact with
SLG.[Pictures taken from: Klekachev et al, Physica E: Low-dimensional Systems and Nanostructures (2011) 43(5) 1046-1049]
During the internship/master thesis you will learn how to manipulate and functionalize graphene, to characterize
the doping level and the bandgap formation. Therefore, you will be involved in the design, fabrication, and
characterization of graphene optoelectronic devices. The challenges involved are:
• the study of the interfacial reactions between the substrate, graphene and doping layer
• post-processing of as-grown graphene (e.g., transfer, modification, device design)
• device fabrication by lithography
• electrical and optical device characterization
The work will start from earlier findings within the graphene team and is conducted in the group of Prof. Dr. S. De
Gendt.
Type of project: Thesis or internship project
Degree: Master in Science or Master in Engineering majoring in material science, nanotechnology, chemistry,
physics
Responsible scientist:
For further information or for application, please contact Inge Asselberghs (Inge.Asselberghs@imec.be).
Master Thesis/Internship Topics 2013-2014
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Graphene: device fabrication and characterization
Graphene, an atomically-thin sheet of carbon atoms arranged in a sp2 honeycomb lattice, has been successfully
isolated for the first time only in 2004 [Novoselov et al, Science 306 (2004) 666.]. The peculiar electronic
properties of graphene arise mainly from the configuration of its energy band structure, which, combined with the
intrinsically low occurrence of defects and the stiffness of its lattice, allows for the featuring of intriguing 2-D
physical phenomena. Graphene has been proposed as a candidate for CMOS and post-CMOS electronics.
However, in order to make electronic applications of graphene realistic, one has to necessarily tune its electronic
properties, so that, for example, a bandgap is introduced. The realization of a proper bandgap is critical for the
device performance. Most recently, the research team has demonstrated the tuning of single-layer graphene by pand n- doping due to engineering the interactions with the SiO2 support [Nourbakhsh et al, PSS 6 (2012) 53.].
Figure: (a) Transfer characteristics and (b) transconductance of SLG-FETs fabricated on pristine and silanized Si/SiO2 substrates. The latter sample is then
treated in basic (red) and acidic (blue) solutions to turn the behavior from n- to p-type.[Figure taken from: Nourbakhsh et al, PSS 6 (2012) 53.] (c) image
of a graphene device.
The candidate will learn how to manipulate and functionalize graphene, to characterize the doping level and the
bandgap formation. Therefore, he/she will be involved in the design, fabrication, and characterization of graphene
devices. Part of the work will entail the manipulation and functionalization of graphene produced by both
mechanical exfoliation and synthetically grown graphene, for benchmarking purposes. The challenges involved are:
• the study of the interfacial reactions between the substrate, graphene and doping layer;
• post-processing of as-grown graphene (e.g., transfer, modification, device design);
• device fabrication by lithography;
• electrical device characterization.
The work will start from earlier findings within the graphene team and is conducted in the group of Prof. Dr. S. De
Gendt.
Type of project: Thesis or internship project
Degree: Master in Science or Master in Engineering majoring in material science, nanotechnology, chemistry,
physics
Responsible scientist:
For further information or for application, please contact Inge Asselberghs (Inge.Asselberghs@imec.be).
Master Thesis/Internship Topics 2013-2014
27
Plasma etching and characterization of novel materials for advanced patterning
Continuation of CMOS scaling, following Moore’s law, is a key challenge for the IC industry. Nowadays, the 22 nm
node is on production (Intel), 14 and 10, 7 nm nodes are being explored at R&D level. From a patterning
perspective, i.e. the ability to print and etch such structures on the wafer, 193i and EUV lithography coupled to
self-aligned double or quadruple patterning will enable the patterning down to 15-20 nm line/space features.
Besides this, direct-self-assembly (DSA) polymers offer the possibility to print sub-15 nm line/space structures.
For building advanced CMOS devices, reaching small dimensions at lithography stage is a must, but also pattern
transfer into the target substrate must be done in a well controlled and reproducible manner. The current
materials used for patterning transfer are reaching their limits. Thus, novel materials in the field need to be
explored. These materials should allow to pattern smooth structures since the ITRS roadmap suggest that a line
with a critical dimension of 10 nm should have a line width roughness (LWR) of less than 10 Angstroms. The
patterning of smooth sub-15 nm features within specifications (LWR, CD, etc.) will be a milestone for the IC R&D
and industry.
The general objective of this Master work is to evaluate potential new materials that can be used in a CMOS
integration scheme. 1) Evaluate etch rates using plasma processes, 2) measure thickness, stress and optical
properties by means of Spectroscopic ellipsometry, 3) evaluate mechanical properties of the materials when they
are exposed to different thermal cycles, 4) evaluate the performance of the selected materials in a real patterned
device (Profile and LWR).
Type of project: Internship project of 6 up to 12 months
Degree: Master in Engineering majoring in chemistry, electronics, physics (materials, plasma)
Responsible scientists:
For further information or for application, please contact Efraín Altamirano-Sánchez
(Efrain.AltamiranoSanchez@imec.be) and J.-F. de Marneffe (Jean-Francois.deMarneffe@imec.be).
Low damage plasma processing: new materials for pore stuffing of 2.0 porous
SiOCH materials
In order to cope with device scaling, inter-line crosstalk and interconnect delays, chip manufacturers are
introducing since a few years low dielectric constant materials (low-k’s) as insulating material separating conducting
Cu lines. Currently, targeted k values for 2020 are of the order to 2.0 and below, to be compared with 4.2 for
bulk SiO2 (reference dielectric for the semiconductor industry). In order to achieve such a low k value, Si-based
CVD materials are favored, where methyl groups are introduced (less polarizables) together with substractive
porosity. Those materials are referred as p-SiOCH, hybrid dielectrics, or organo-silicon glass (OSG). Current
state-of-the-art synthesis methods allow to reach k values ~ 2.0, with porosity ~ 45% and average pore size ~
2.4nm. Recent studies indicate that those materials are damaged by plasma processing, leading to methyl group
suppression and loss of hydrophobicity. The source of damage is twofold; first, active radicals do penetrate the
interconnected porous structure and react with pore sidewalls, leading, through various reaction pathways, to the
replacement of hydrophobic Si-CH3 terminations by hydrophilic Si-OH; second, vacuum-ultra-violet (VUV)
photons emitted by the plasma, due to their high-energy (> 6eV) do break the Si-CH3 bonds as well, causing
chemical and structural re-organization of the material, with appearance of high-polarity bonds and densification.
Master Thesis/Internship Topics 2013-2014
28
Both together, plasma radicals and VUV act synergetically, leading to even higher damage. An option to overcome
these issues is the so-called pore stuffing approach, where, once formed, interconnected pores of the p-SIOCH
are temporary filled with another material. Right now, conventional polymers have shown good filling and decent
protection properties, however on one hand their VUV absorption spectrum is weak, while on the other hand
they are easily thermally decomposed which poses some issues for subsequent process steps, namely TaN/Ta
barrier deposition. There is therefore a need to study other type of filler materials, showing a higher optical
absorption in the VUV range and better thermal stability, but still being removable later in the process flow
(typically after metal CMP).
The details of the proposed internship are therefore as follows:
1. The research will follow an intense in-house training allowing him to get familiar with the cleanroom tools
and working environment (safety), then with the different experimental techniques required by the project.
2. Starting from the in-house 2.0 p-SiOCH dielectric film (called ALKB+), and the physico-chemical properties
of the envisioned filler material, the researcher will optimize the filling conditions so as to obtain the best
possible filling, i.e. > 85% of the free volume. At this stage, numerous thin film characterization methods will
be intensively used.
3. Once the best filling conditions will be found, the researcher will characterize the plasma-damage
characteristics of the resulting hybrid film, looking especially at the impact of VUV, and comparing it to
more conventional fillers. Bulk k-value will be evaluated, as well as chemical & structural modifications
caused by plasma exposure. Simultaneously, the thermal stability of the hybrid film will be checked up to
350°C, and removal (burn-out) approaches will be investigated.
Techniques for such a study are broad and represent a significant part of the stay: deep understanding of 300mm
etch tool usage, work with coupons and optical filters, thin film characterization (ellipsometry for thickness-n&k,
FTIR or ATR-FTIR for bulk composition, WCA for film hydrophobicity, XRR for density, k-value extraction by C-V
measurements on metal dots, porosity by ellipsometric porosimetry). More specific material characterization (XPS,
TOF-SIMS) may be requested to the Material Characterization & Analysis (MCA) group.
Type of project: Internship or thesis with internship project of 6 up to 12 months
Degree: Master in Science or Master in Engineering majoring in materials sciences, physics, chemistry, electronics
Responsible scientists:
For further information or for application, please contact Mikhail Baklanov (Mikhail.Baklanov@imec.be) and J.-F. de
Marneffe (Jean-Francois.deMarneffe@imec.be).
Depth loading study in STI
It has been shown that the fluorocarbon-based-passivation STI has some benefits in the profile control for the
current small generation nodes , see PESM 2012 (Fluorocarbon-Based Passivation in STI Plasma Etching). Though it
can provide a single sidewall slope, required CD, and CDU there is one parameter that would still be interesting
to optimize --- it is an ISO /Dense depth loading.
Master Thesis/Internship Topics 2013-2014
29
The objective of the work is to perform various plasma experiments on a SA3 patterned lot in order to reduce the
difference in depth of ISO and Dense structures. The experiments are planned to be performed in Kiyo-E
chamber. The effect of pressure-power and gas composition is to be studied. Also, the activity can include
cooperation with the modeling group, if the new model of STI is ready.
Type of project: Internship project of minimum 3 months
Degree: Master in Engineering majoring in chemistry, electronics, physics (materials, plasma)
Responsible scientists:
For further information or for application, please contact Alexey Milenin (Alexey.Milenin@imec.be) and Kaidong
Xu (Kaidong.Xu@imec.be).
Advanced materials characterization using ion beam scattering
This work will be executed at imec, the leading European micro-electronics research center. Imec does research
on a wide variety of front edge micro-electronic devices and applications (transistors, memories, solar cells...). To
verify the correct fabrication of these extremely challenging new devices (sub-22 nm technology) also high-end
characterization tools are essential. In this framework, accelerator based tools are recognized as versatile solutions
for thin film (sub-nm scale) characterization.
This topic is an opportunity to learn about fundamental materials characterization techniques in a state-of-the-art
nanoelectronics research center. You will be exposed to challenges in current and future CMOS technology.
Novel materials processing techniques and characterization approaches have boosted the nanoelectronics industry
dramatically. We have witnessed the introduction of high-k materials (e.g. HfO2) replacing the SiO2 insulator in
advanced transistors, and metals (e.g. TiN) replacing poly-Si as a gate material. Yet, the introduction of novel
materials is expected to be even more essential in the future. Research is ongoing to replace Si by alternative
materials that exhibit a higher mobility. Finally, new materials are also needed for the realization and optimization
of new devices such as Magnetic memory cells (MRAM), resistive memory (RRAM) cells, conductive bridge
resistive memory (CBRAM), photovoltaic(PV) cells, nano-batteries, micro-electromechanical systems (MEMS), light
emitting diodes (LEDs) etc.
The development of new materials at imec builds also upon the experience and expertise of the materials and
component analysis (MCA) department. One of our major tools is an ion accelerator (maximum 2 Mega Volt) with
two dedicated end stations; one for Rutherford Backscattering spectrometry (RBS), and another for Elastic Recoil
Detection (ERD) experiments. In RBS, essential information from the sample is gained from the residual energy of
the scattered projectiles. In ERD, the information comes from the energy of the recoiled target atoms. To attain
Master Thesis/Internship Topics 2013-2014
30
the best possible detection resolution, the acceleration voltage and the projectile species need to be properly
chosen in relation with the nominal sample structure and the known detection schemes.
The focus of your work will be to investigate novel materials, e.g. Lithium-containing materials for battery
applications, using Elastic Recoil Detection experiments. Till now, at imec, we have been employing mostly a 6 MeV
Cl beam for the ERD analysis of thin films. It may be expected that projectile beams other than Cl (e.g. Cu, Br, I)
and primary energy other than 6 MeV are more effective in the analysis of certain thin films. Through practical
experiments and supported with simulations (software available), you will investigate the capabilities of various ion
species and acceleration voltages towards the analysis of new materials.
Type of project: Thesis and/or internship project of minimum 6 months
Degree: Master in Science or Master in Engineering majoring in materials science, physics, chemistry, electronics
Responsible scientist:
For further information or for application, please contact Johan Meersschaut (Johan.Meersschaut@imec.be).
Development of an accelerator based metrology application
This work will be executed at imec, the leading European micro-electronics research center. Imec does research
on a wide variety of front edge micro-electronic devices and applications (transistors, memories, solar cells,...). To
verify the correct fabrication of these extremely challenging new devices (sub-22 nm technology) also high end
characterization tools are essential. In this framework accelerator based tools are recognized as versatile solutions
for thin film (sub-nm scale) characterization.
This subject involves the development and implementation of an object-oriented control application within a Visual
C++ based programming environment. In particular, the software will have to communicate with various
instruments through Ethernet (TCP/IP) and RS232/RS485 (via Serial-Ethernet gateways) and with the user through
an extremely user-friendly graphical interface (GUI) as well as support for a flexible scripting language capability.
The goal is to achieve this functionality by developing a high quality object-oriented program, paying attention to
optimal class structures, efficient usage of polymorphism, re-usability aspects, etc.
This project aims at the development of a new software package for the control of an accelerator-based
measurement system in a graphical, object oriented, Microsoft Visual C++ programming environment (dialog
boxes, menu’s, toolbars, property sheets, etc.). This package will most likely be developed based on the Qt4
(http://qt.digia.com/ ) class library in order to allow the final application to run on any operating system (Windows,
Linux, Apple,...).
The main tasks will be as follows:
• Analyze the present operational system, and design a completely new high-level class diagram for the
envisaged multi-threading metrology application.
• To implement the necessary communication protocols (with stepper motors, data acquisition, counters)
into the Visual C++ environment, with an initial user-interface for testing purposes.
• To design and implement a user-friendly graphical user interface (GUI) and scripting capability to interact
with the hardware.
The software will be designed such that new devices can be connected and disconnected dynamically during the
operation, and should appear as virtual instruments on the screen. The signals from various virtual instruments are
accessible to both virtual super-instruments as well as scripts that can be run in a command-like environment. The
various instruments should be accessed in parallel, i.e. multiple threads may be needed. Ideally, the software allows
access to the control application from various locations (locally and remotely) and by various users (multi-user).
This subject is a challenge for those who wish to specialize themselves in all aspects and capabilities of objectoriented programming within a Visual C++ based environment.
Master Thesis/Internship Topics 2013-2014
31
Type of project: Thesis project of 1 year with a 4 weeks internship
Degree: Master in Industrial Sciences majoring in electronics/ICT
Responsible scientists:
For further information or for application, please contact Johan Meersschaut (Johan.Meersschaut@imec.be) and
Trudo Clarysse (Trudo.Clarysse@imec.be).
Analysis of surface preparation for HV and UHV-SSRM
The SSRM technique is an AFM-based technique used to obtain 2D carrier maps of electronic devices (MOS,
bipolar transistors, FinFets, TFETs,…) with (sub)-nm resolution. Samples therefore need to be cross-sectioned
(polishing or cleaving). The latter may lead to artifacts such as Fermi-level pinning, surface states, native oxide,…
High Vacuum-SSRM, and recently Ultra High Vacuum-SSRM, versions have been introduced with improved
performances relative to the ambient version, due to water layer removal, as well as reduced/suppressed native
oxide growth, contamination and anodic oxidation during the measurements.
In order to fully benefit from the vacuum, a more detailed understanding of the impact of the measurement
environment is required as well as the role of eventual passivation procedures and cleaning/heating treatments
after cross section preparation.
Task of the student(s) will be to study these effects and to correlate the electrical (HV-SSRM and UHV-SSRM)
performance with existing models for the high pressure SSRM-contact. The latter will involve studies on spatial
resolution, ohmic contact formation (through studies of I-V curves), tip and sample erosion, and life time (regrowth, oxidation,..) of the sectioned surface.
Type of project: Internship project of 6 months
Degree: Master in Engineering majoring in chemistry, physics
Responsible scientist:
For further information or for application, please contact Pierre Eyben (Pierre.Eyben@imec.be).
Master Thesis/Internship Topics 2013-2014
32
Active dopant characterization with micro-probes on advanced ultra-shallow highmobility CMOS semiconductor structures
As CMOS devices get smaller with each technology node, the processes needed to fabricate and characterize
these also become more and more complex. Moreover, the fast introduction of new high mobility materials (Ge,
SiGe, III-V) additionally complicates the electrical analysis of these new structures. Ultimately one is interested in
the characterization of the electrically active portion of the implanted dopant species, either in extremely shallow
blanket layers (sub-20 nm) or small structures (50x50 um pads down to 20-100 nm wide trenches) or layers with
carriers of different mobility signature (interface versus bulk behavior)
On blanket layers the active dopant portion can in principle be determined by combining Secondary Ion Mass
Spectrometry (SIMS) profiles (for depth information) with surface sheet resistance or conventional Hall
measurements. The latter give additionally information about the sheet carrier (= active dose) and exact mobility
of the surface layer. Conventional Hall, however, suffers from contact penetration issues and needs quite large
areas (cm). Recently a new virtually zero-penetration micro-probe (10 um pitch) based tool (CIPT), from Capres,
has been installed at imec, which allows micro-Hall measurements close to the edge of a blanket sample (5 um
distance) in the presence of a 600 mT magnetic field. The accuracy of these measurements on many of the new
materials, however, still needs to be further investigated. Among others, values for the Hall scattering factor need
to be determined.
Subsequently, one needs to be able to extract the active dopant information on ever smaller structures (50x50
um) and thinner 250 nm deep trenches (20 nm wide), taking into account two-dimensional and side-wall effects.
For some of these challenging structures new extraction algorithms will need to be developed based on the
understanding obtained through Synopsis/Sentaurus device simulations. For trenches also specialized reference
(calibration) characterization structures will be developed and fabricated.
Besides the study of ever shrinking structures, another issue is being able to discriminate between carriers with
different mobility’s in the same layer, for instance in the neighborhood of an interface or in the bulk of the layer.
For such a characterization a variable magnetic field will be considered giving rise to a field dependent mobility
spectrum. Measurement procedures and physical understanding for such types of measurements will have to be
developed.
The major steps in this work will be: (i) Familiarizing oneself with the CIPT (and micro-four point probe M4PP)
tools and related software and underlying theoretical publications, (ii) Extending the capabilities of micro-Hall
measurements on blanket films in different new materials, (iii) Explore the capabilities of micro-Hall on different
types of small structures and develop a theoretical framework for the obtained results, (iv) Investigate the behavior
of micro-Hall measurements in the presence of a variable magnetic field.
Type of project: Internship or thesis project of minimum 6 months
Degree: Master in Science or Master in Engineering majoring in physics, electrical/electronic engineering, material
science
Responsible scientist:
For further information or for application, please contact Trudo Clarysse (Trudo.Clarysse@imec.be).
Master Thesis/Internship Topics 2013-2014
33
Development of a professional data analysis package for the micro-four point probe
(M4PP)
The micro-four point probe (M4PP) is an electrical technique that allows for the very accurate measurement of the
(sheet) resistance of a very thin (sub-100 nm) highly conductive semiconductor layer on top of a substrate of
opposite impurity type (n- or p-type) (by pushing a current through the outer two probes and measuring the
resulting voltage difference between the inner two probes). In 2009 such a M4PP tool has been installed at Imec.
The tool came with commercial software (from Denmark) for the sheet resistance raw data collection, but not for
the data manipulation of the many different data files or consequent data interpretation.
When applying this technique to a bevelled surface (slanted), one can generate a sheet resistance versus depth
profile, from which the underlying carrier depth profile can be extracted. The latter is of crucial importance for the
development of future state-of-the art transistors. In 2010-2011 an initial version of a brand new M4PP data
treatment software package named “Tivoli” has been implemented. During the next (second) academic year Tivoli
was enhanced among others with improved smoothing capabilities, a graphics overlay module and printing
capability.
The goal of the third working year of this project is, to continue the development of the Tivoli package for both
surface sheet resistance+mobility and carrier depth profiling analysis. The programming environment is Microsoft
Visual C++, with the Qt4 class libraries (http://qt.digia.com/) and Qwt graphics libraries
(http://qwt.sourceforge.net/ ). Issues involved in this work will be: (i) For surface analysis, making different types of
result plots/maps (resistance/voltage versus position, two-dimensional 200- and 300 mm resistance contour maps,
etc.) and implementing support for a new micro-probe CIPTech tool allowing to extract mobility data from the
measurements, (ii) For carrier depth profiling, implementing probe pitch correction algorithms and adding support
for two point (so called spreading resistance) measurements, which have a smaller sampling volume, (iii) Adding
further support for making overlays with profiles from other dopant and carrier characterization techniques, (iv)
Eventually semi-automatically generation of analysis results reports (in MS Word or PDF format).
It is not the aim of this work to develop new data treatment “algorithms’. This subject is, however, a challenge for
those who wish to specialize themselves in all aspects and capabilities of object-oriented Windows programming
within the Visual C++ environment with a signal-slot architecture (Qt) environment, focusing on a truly userfriendly graphical user interface (GUI).
Type of project: Thesis project of minimum 6 months with 1 month internship
Degree: Master in Industrial Sciences majoring in electrical/electronic engineering, ICT
Responsible scientist:
For further information or for application, please contact Trudo Clarysse (Trudo.Clarysse@imec.be).
Master Thesis/Internship Topics 2013-2014
34
Fundamentals of nanoscopic materials removal
The high potential of three-dimensional (3D) electrical atomic force microscopy (AFM) has recently been
demonstrated; for example by probing the electrical properties of carbon nanotube based interconnects. Our
method uses scanning spreading resistance microscopy (SSRM) and applies
a slice-and-view approach where material is removed on the nanometer scale by successive tip scanning. In-house
made boron-doped diamond tips are used for both continuous material removal by successive scanning and for
the actual electrical measurements. By stacking and interpolating between the individual 2D SSRM resistance maps,
one can obtain an electrical tomogram. The further development of this 3D electrical AFM method crucially
depends on understanding the fundamentals of nanoscale material removal using doped diamond tips.
This topic investigates the basics of nanoscopic material removal using in-house developed full diamond tips. It is
the aim to develop procedures allow for adjustable scan removal rates of about 1-10 nm/scan on hard materials
like silicon, germanium and silicon oxide. Three different tip configurations are evaluated in this work: pyramidal
tips, knife-shaped tips (45° rotated on cantilever) and in-plane tips (triangular shape with tapered end). The latter
configuration strongly facilitates locating the region of interest as the tip region is clearly visible in the optical
microscope of the AFM. Operating such diamond probes in slicing motion only, can be exploited for nanomachining purposes as well. The student will optimize the tip performance for making reference marks and
removing passivation layers. The final outcome of this work are probe concepts and scanning approaches enabling
the nanoscopic controlled removal of semiconductor materials.
The student will work in a state-of-the-art materials characterization lab. He/she will be trained in working with
AFM and in particular with SSRM. For probe tip inspection, scanning electron microscopy (SEM) is used. The
student will be part of the materials and component analysis (MCA) department.
Type of project: Internship project of 6 months
Degree: Master in Science or Master in Engineering majoring in physics, electrical engineering, material science
Responsible scientist:
For further information or for application, please contact Thomas Hantschel (Thomas.Hantschel@imec.be).
Strain characterization in advanced transistor structures using Raman
Strain engineering is used as a concept in most advanced nanoelectronics transistor structures to enhance the
mobility of electrons (or holes) in the channel region and thereby increasing the channel conductivity. This is
achieved by various approaches (e.g. strain-inducing capping layers, using a silicon-rich solid solution such as SiGe).
PMOS and NMOS respond differently to the applied strain. PMOS benefits from applied compressive strain
whereas NMOS performance is supported by tensile strain. The use of such stress-engineering implies also the
possibility to measure locally the stress inside the channel region. In this topic, the use and optimization of the
Raman method is investigated for measuring the local stress in state-of-the-art FinFET transistor structures.
Raman is an optical technique and relies on inelastic scattering of photons which means that the energy of photons
in monochromatic light changes upon interaction in a sample. The student will learn to work with a micro-Raman
system using different laser wave lengths. The experimental focus is on using the nanometer-scale dimension of the
device to locally increase the Raman signal originating from the channel region. The student will be trained in
working with a Raman system and characterize advanced device structures. He/she will be part of the materials
and component analysis (MCA) department.
Master Thesis/Internship Topics 2013-2014
35
Type of project: Internship project of 6 months
Degree: Master in Science or Master in Engineering majoring in physics, electrical engineering, material science
Responsible scientist:
For further information or for application, please contact Thomas Hantschel (Thomas.Hantschel@imec.be).
Non-destructive assessment of electrical properties of nanoscale probe tips
Doped diamond tips have been developed for carrier profiling of state-of-the-art semiconductor devices with a
spatial resolution of 1nm. They are mainly used for scanning spreading resistance microscopy (SSRM) which uses a
high pressure in the GPa range to establish a good electrical contact to the silicon. Despite the high resolution of
such tips, their overall fabrication yield is still limited to about 30-50%. A tip evaluation procedure does exist to
determine the yield for a particular probe wafer but the actual testing affects the tip properties and can hence not
be used for tip qualification (predicting the tip performance without tip wear). Therefore, in this topic a nondestructive approach is developed and optimized based on local I-V measurements at low forces. Moreover, it is
the aim of this internship to better understand the mechanism behind the formation of the nanoscale electrical
contact and to link the observed high tip resolution in SSRM to the physical properties of the apex of the diamond
tip. For this, the obtained I-V tip characteristics are compared to the actual tip performance in SSRM (resolution,
conductivity) and to the physical shape/geometry of the diamond tip apex. The final outcome is a non-destructive
tip qualification procedure and gaining better insight into the diamond tip to substrate interaction. For this, the
student is going to working a modern materials characterizations lab and will be trained to operate an atomic
force microscopy (AFM) system, to perform SSRM measurements and to collect I-V measurements for tip
evaluation. After the training period, the student will independently perform the electrical and physical tip
assessment. He/she will be part of the materials and component analysis (MCA) department.
Type of project: Internship project of 6 months
Degree: Master in Science or Master in Engineering majoring in physics, electrical engineering, material science
Responsible scientist:
For further information or for application, please contact Thomas Hantschel (Thomas.Hantschel@imec.be).
Nickel damascene process for MEMS
In a previous project, we have started to investigate the properties of electrodeposited nickel (Ni), which is a very
interesting candidate for making structures that could be used in a MEMS (Micro ElectroMechanical System).
Advantages of Ni are that it has a low electrical resistivity and it is mechanically more robust than most other
metals. Therefore, it can be an important metal for building MEMS structures.
For building transistors, copper is extensively used in the so-called “Damascene process”, in which various layers
are stacked during processing by sequences of patterning-metallization-planarization, in order to build more
complex structures (see figure). For this student project, we are going to develop a process in which Ni is
deposited inside a patterned structure (e.g. photoresist, oxide) and the student will be executing many of these
processing steps.
Master Thesis/Internship Topics 2013-2014
36
Figure - Cross section of a 3-layer Damascene stack, which consists of metal (brown), dielectric (yellow) and stopping layer required for planarization
(green), on a silicon substrate.
In the first phase of the project, the student will get familiar with the processing steps, focusing on
electrodeposition of Ni and chemo-mechanical polishing (CMP). Initially, the student will work on thin films and
investigate the deposition and removal properties of Ni. In the next phase, a patterned structure will be used for
which the results obtained during the first phase will be applied. Analysis, interpretation and presentation of the
results will be important activities in which the student participates.
Execution of experiments on silicon wafers in the IMEC cleanroom. Analysis of samples (e.g. optical microscopy,
Atomic Force Microscopy (AFM), Focused Ion Beam (FIB), cross-sectioning, Scanning Electron Microscopy (SEM),
resistivity), characterization of deposition and removal uniformity. Project can be done by student as a Master
thesis, or as ‘industrial internship’. Background by education: Chemistry, Physics, Engineering.
Type of project: Internship project of 6 months
Degree: Master student in chemistry, physics, engineering
Responsible scientists:
For further information or for application, please contact Harold Philipsen (Harold.Philipsen@imec.be) and Lieve
Teugels (Lieve.Teugels@imec.be).
Defectivity monitoring of directed self-assembly
In this project the patterning reliability (or defectivity) of our chemo-epitaxy directed self-assembly process will be
monitored over time. The initial goal is to demonstrate long term stability of the process and to implement
improvements as these are developed in parallel projects. The ultimate goal of the study is to demonstrate the
ability of the process to reproducibly deliver low defectivity on full 300mm wafers.
X-PS cross-linking
Lithography
OH-Brush grafting
O2 plasma etch
Chemical Pattern
Master Thesis/Internship Topics 2013-2014
Rinse
BCP annealing
37
In our directed self-assembly process (see cartoon above) we use a number of process steps (including optical
lithographic patterning, dry etch and spin coating of dedicated polymer materials) to obtain a so-called ‘chemical
pattern’. At this stage there is no wafer topography, but only well controlled domains of different chemical surface
energies. When a block copolymer of appropriate composition is coated on such a surface, spontaneous frequency
multiplication is obtained (see microscope images below). The left image shows the low frequency pre-pattern.
The 1 st image on the right is the desired result. In some cases, however a defective self-assembly result is obtained
(2 nd image on the right). In this project the number of such defects on a full 300mm wafer will be quantified.
4
or
Initially the work will mainly focus on metrology, including defect inspection and SEM (scanning electron
microscope) defect review in the advanced 300mm imec wafer fab. Depending on skills and interest, wafer
processing may be included in a later phase of the project.
Type of project: Thesis with internship project of 12 up to 18 months
Degree: Master in Science or Master in Engineering majoring in material science, physics, chemistry, chemical
engineering
Responsible scientist:
For further information or for application, please contact Roel Gronheid (Roel.Gronheid@imec.be).
Modeling of leakage in very high permittivity dielectrics for DRAM applications
Future dynamic random access memories (DRAM) require metal-insulator-metal capacitors (MIMcaps)
with equivalent oxide thicknesses (EOT) ≤ 0.4 nm, necessitating the introduction of dielectrics with very
high dielectric constant (k~100). Furthermore, low leakage current densities (≤ 1e-7 A/cm2) are required
for sufficient retention of charge. Regrettably, high-throughput industrial deposition techniques can result
in dielectric films with defects that can facilitate electronic conduction. Reducing the leakage thus requires
thorough understanding of the role of the defects.
The general aim of the thesis is to interpret the measured leakage and capacitance characteristics (IV and
CV at varying temperature). This will be achieved by modeling trap-assisted leakage mechanisms in MIM
structures with non-uniform electric field due to charge trapped inside the dielectric. Requirements
therefore include understanding of the physics of various conduction mechanisms, self-consistent solving
of the Poisson equation, and optionally electrical IV and CV measurements.
Type of project: Thesis project
Degree: Master in Science or Master in Engineering majoring in physics, electronics, nanoscience/technology,
material science
Responsible scientist:
For further information or for application, please contact Ben Kaczer (Ben.Kaczer@imec.be).
Master Thesis/Internship Topics 2013-2014
38
II.
Heterogeneous Integration
Calibration of stress sensors for 3D-IC applications
The 3D-IC technology enables the high density integration of integrated circuits resulting in the smaller footprint
of the chip and at the same time improving the signal integrity and to some extend the power consumption. It also
enables integration of different CMOS technologies in one functional 3D module. However the 3D-IC integration
introduces an extra complexity into the micro-system thus affecting its reliability and thermo-mechanical stability.
To quantify these effects the set of temperature and stress sensors has been developed. The response of these
devices has also been measured at different temperatures and at different levels and kinds of the mechanical
stresses.
The objective of this master thesis is to get more systematic experimental and theoretical information on the
sensitivities of the sensors which are available on the different 3D test vehicles. In particular the work will be
focused on the calibration of stress sensors at vertical (out-of-plane) stresses and at the calibration of stress
sensors at different temperatures.
The work will include:
• literature study
• developing the experimental techniques and the methodology to enable the calibration of different sensors
• performing the experiments
• analyzing the results and drawing the conclusions
Type of project: Thesis project
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in material
science, physics, electronics
Responsible scientist:
For further information or for application, please contact Vladimir Cherman (Vladimir.Cherman@imec.be).
Master Thesis/Internship Topics 2013-2014
39
III.
Electronics for Healthcare and Life Sciences
Studying the function of neural circuits
Investigating the computations performed by the brain requires simultaneous recordings from many individual
neurons. Moreover, it is essential to dissect and perturb genetically defined functional components of neural
circuits to test the effects of these perturbations. Neuroscience is currently constrained by a limited ability to
make specific perturbations in neural circuits. Yet, neural circuits are perturbed in various ways during
development. As the brain develops, not only the numbers of neurons increase drastically but also the composition
of the neural circuits change. Constant spatial and functional reorganization of the developing brain also affects the
connectivity between the components of neural circuits. Yet, the brains of both developing and adult animals
function properly and generate behaviours essential for life.
Zebrafish is a rising model organism for studying the function and development of neural circuits. First, zebrafish
brain development and organizational principles are highly similar to the mammalian brain. Zebrafish larvae are
optically transparent and posses a small and easily accessible brain for electrophysiology, imaging and optogenetic
manipulations. The molecular toolbox associated with zebrafish is well developed, easily accessible and expanding
rapidly.
The main aim of the proposed research is to understand the fundamental principles underlying the function and
development of neural circuits. Towards this overarching goal the successful student candidate will investigate how
sensory information is processed along the brain pathways; how this information is stored and recalled in the
process of learning and memory; how neural circuits are established in development and which cells give rise to
the necessary components of this system; how the neural circuits change throughout development of the embryo
and how this relates to the behaviour of the organism.
To accomplish these goals, the successful candidate will be trained in functional imaging, electrophysiology,
computer based analytical methods and genetics. Using these techniques we will study the activity of thousands of
neurons in response to odor stimulation and perturb the genetically defined components of these neural circuits
to understand their function in olfactory information processing. Moreover we will develop and use anatomical and
physiological methods to trace the functional connectivity of olfactory circuits in both adult and larval zebrafish
brain. Ultimately, the experiments that are designed by using these new tools will help us to understand the
fundamental principles of sensory information processing in the brains of vertebrates, including humans.
Type of project: Internship or thesis project
Degree: Master student majoring in engineering, physics, bio-engineering, mathematics
Responsible scientist:
For further information or for application, please contact Emre Yaksi (Emre.Yaksi@nerf.be).
Master Thesis/Internship Topics 2013-2014
40
Measurement of nanomaterial exposure in air
Nanomaterials contain objects smaller than 100 nm in at least one dimension, for example, particles, filaments, or
sheets. They represent an increasingly important product of nanotechnologies having a wide range of applications
from medicine to energy storage. On the other hand, nanomaterials have different chemical and toxicological
properties compared to bulk materials and can introduce different environmental and occupational hazards.
Important properties determining their biological effect are their aspect ratio and surface area. The literature on
measurement strategies for assessing exposure to manufactured nanomaterials is currently very limited, especially
regarding airborne exposures. The information base for exposure assessment in workplaces is currently built on a
limited database which has to be improved in volume, comparability and reproducibility.
This student topic will combine a literature search regarding the toxicological properties of nanomaterials and
laboratory work (scanning electron microscopy SEM, X-ray photoelectron spectroscopy, XPS) eventually
determining airborne exposure. We are looking for a candidate with enthusiastic attitude and basic knowledge of
physical chemistry.
The objectives of this project are to
• get familiar with the nanomaterials produced and used in imec;
• conduct a literature search about the current literature about measurement strategies;
• develop an experimental setup providing controlled release of nanomaterials in the air;
• perform physical and chemical characterization of nanomaterials.
Type of project: Internship or thesis project of 6 months
Degree: Master in Industrial Sciences or Master in Science, majoring in material science, physics, chemistry
Responsible scientist:
For further information or for application, please contact Dimiter Prodanov (Dimiter.Prodanov@imec.be).
Sensors for weight management and energy expenditure
The development of novel sensors and the deployment of personal body area networks with these sensors are
driven by microsystem integration technologies. These wireless networks provide assisted living, sports or
increased wellbeing functions for the user, without visible interference with their active lives. Prevention rather
than detection and cure will be the future paradigm. In imec's imHealthy program, these body area networks
(BAN) with several different types of sensors are currently under development: ECG signals, skin conductance,
motion and many more signals can be monitored, recorded and wirelessly transmitted to a personal mobile device
during longer periods of time. With the growing availability and acceptance of these sensor networks for
improving our life quality, it is becomes attractive to use their information in a multitude of applications.
Master Thesis/Internship Topics 2013-2014
41
Overweight is a growing concern in our society and monitoring it together with tracking our energy (or calorie)
burning with BAN based sensors can help us to give timely warning signals, since people are tending to neglect
there body signals. In this thesis work, the aim is to study and compare several strategies for monitoring people’s
weight and energy expenditure from the signals produced by the sensors in the BAN: e.g. measuring a persons’
activity with a accelerometer on the body together with monitoring the heartrate can give a solid figure for the
amount of calories that were dissipated. At the start of this thesis, a study of weight and energy expenditure
monitoring methods that are compatible with imec's available BAN sensors systems will be made. After getting
acquainted with the BAN hard- and software, an experimental monitoring tool will be developed for the BAN
sensors by analyzing the readout signals (from 3D accelerometer, skin conductance sensor for sweat estimation,
heart rate sensor) and combining them in a user app that allows informing a person about his/her energy balance.
Type of project: Thesis project
Degree: Master in (Bio)Engineering, majoring in nanotechnology, (bio)electronics
Responsible scientists:
For further information or for application, please contact Walter De Raedt (Walter.DeRaedt@imec.be) and Chris
Van Hoof (Chris.VanHoof@imec.be).
How to detect dehydration with body area networks?
Microsystem technologies are currently stimulating the development and deployment of personal body area
networks. These wireless networks provide lifestyle, assisted living, sports or entertainment functions for the user,
without visible interference with their active lives. Prevention rather than detection and cure will be the future
paradigm. In imec’s imHealthy program, such body area networks (BAN) with several different types of sensors
are currently under development: ECG signals, skin conductance, ions in sweat, motion and many more signals
can be monitored, recorded and wirelessly transmitted to a hub during longer periods of time.
The aim of this thesis work is to study how these sensor networks can be used for detecting dehydratation of
persons, this is particularly of interest for sports and elderly people. Dehydration can have various causes: not
only serious illnesses (diarrhea, vomiting, excessive consumption of alcoholic beverages…) but also prolonged
physical activity with sweating , stress, prolonged exposure to dry air can cause a dehydration that is not readily
recognized. Enhancing BAN networks with dehydration detection and timely warning thus is a very worthwhile
and challenging feature.
This thesis work will start with a study of dehydration detection methods that are compatible with imec’s BAN
sensors systems that are under development. Next a monitoring tool for dehydrtation will be developed for these
sensors by analyzing sensor readout signals and combining them in a user app that allows warning the user about
his dehydration status.
Type of project: Internship or thesis project
Degree: Master in (Bio)Engineering, majoring in nanotechnology, (bio)electronics
Responsible scientists:
For further information or for application, please contact Walter De Raedt (Walter.DeRaedt@imec.be) and Chris
Van Hoof (Chris.VanHoof@imec.be).
Master Thesis/Internship Topics 2013-2014
42
Ionic fluidic study of metallic nanopores
Downscaling is a trend not only seen in the field of electronics, but even in the field of fluidics. This has given rise
to the field of microfluidics, which allowed the manipulation of very small quantities of reagents, and recently to
the field of nanofluidics, where completely new phenomena come into play. Solid-state nanopores, nanometersized holes in a thin synthetic membrane, are a versatile fluidic device for the detection and manipulation of
charged biomolecules. An external electric field drives a biomolecule through the nanopore, producing a
characteristic transient change in the trans-pore ionic current. This approach can be used for sensitive singlemolecule biosensing platforms, and much current research is directed toward nanopore sequencing of DNA.
An understanding of the conductance of a nanopore is the basis for any nanopore experiment. To date, however,
models for conductance through metallic nanopores are under developed. In most previous studies of dielectric
pores, it was usually assumed that (a) the potential drop occurs predominantly across the pore and (b) the pore
has a cylindrical shape. However, in many cases, particularly when the pore is highly charged, the surface
conductance significantly contributes to the corresponding potential drop. At the meantime, the specific chemical
interactions on metal surfaces are critical but not integrated into the modeling of the conductance.
This thesis will focus on a fundamental study of the nanopore fluidics and build the conductance model for metallic
nanopores. For this purpose, the size of nanopore, different metal surfaces will be systematically studied. Further
surface modification experiments with different electrolyte buffer will be also applied to connect the metallic
nanopore with dielectric ones. Modeling of nanopore conductance will be derived to interpret the nanofluidics
inside.
Type of project: Thesis project
Degree: Master in Science or Master in Engineering, majoring in physics, electronics, physical chemistry
Responsible scientists:
For further information or for application, please contact Yi Li (Yi.Li@imec.be) and Chang Chen
(Chang.Chen@imec.be).
Exploration of efficient electroporation protocols for intracellular recording of
action potentials using configurations of microelectrodes on chip
Multi-electrode arrays are an elegant and fast technique to sense electrical activity of in vitro electrogenic cells
such as neurons and cardiac cells. Despite the ability to record from many cells at the same time, the signal quality
and the resolution of this technique are still not optimal. Recently, imec developed a technique that makes it
possible to record intracellular action potentials using on-chip electroporation (Braeken et al., Lab Chip, 2012).
Such intracellular signals are 500 times larger in amplitude and preserve the original shape of the action potential,
improving the quality of the recording drastically.
The project aims to further investigate the principle of electroporation using on-chip electrical stimulation. The
student will make use of a novel experimental platform designed for testing different electrode configurations,
topologies and materials, such as three-dimensional electrodes, carbon nanotubes, etc. Effects of electroporation
protocols will be evaluated using fluorescent imaging techniques and recording of the spontaneous electrical
activity of cardiac and neuronal cells using the multi-electrode array platform of imec.
Type of project: Internship or thesis project
Degree: Master in Science or Master in Engineering, majoring in (bio)electronics, (bio)physics, biomedics,
nanotechnology
Responsible scientists:
For further information or for application, please contact Andim Stassen (Andim.Stassen@imec.be) and Dries
Braeken (Dries.Braeken@imec.be).
Master Thesis/Internship Topics 2013-2014
43
Characterization of optical waveguides for optogenetic stimulation of in vitro and in
vivo neurons
Since the first reports in literature only a few years ago, optogenetics is one of the fastest growing and most
promising fields in neuroscience. Optogenetic stimulation is based on optical activation or inhibition of neurons
that have been genetically modified to express light-sensitive opsins in their membranes. Today, optical stimulation
in vivo is mainly performed using bulky optical fibers with limited selectivity. Imec is investigating optical stimulation
of cells using a novel type of devices that make use of waveguide technology to guide visible light into in vitro and
in vivo probes. By positioning multiple light entry and exit sites we want to ensure selective stimulation of single
cells is feasible.
The student will be involved in characterizing on-chip waveguides to investigate optical losses in the substrate, the
efficiency of coupling of light into and from the substrate, and the efficiency of optogenetic stimulation of single
cells in vitro and in vivo. Parameters of efficient stimulation and the effect on single cells will be studied using
optical imaging and electrical recording techniques.
Type of project: Thesis and/or internship project
Degree: Master in Science or Master in Engineering majoring in electronics, physics, biomedics, optics
Responsible scientists:
For further information or for application, please contact Luis Hoffman (Luis.Diego.Leon.Hoffmann@imec.be) and
Dries Braeken (Dries.Braeken@imec.be).
High-density carbon
electrogenic cells
nanotube
electrodes
for
recording
and
stimulating
Electrogenic cell types, such as heart or brain cells, rely on electrical signals to communicate with one another. In
order to gain insights in the fundamental processes of brain cell communication, unravel the cause of brain
disorders, or validate the effect of certain drugs on heart cells, it is important to record these signals in a minimally
invasive and long-term manner. Our imec research group developed a state-of-the-art chip which is smaller than
the size of a fingernail, but yet contains tens of thousands of subcellular-sized electrodes, each individually
addressable and able to record and stimulate cells on top. Obviously, the quality of the signal depends highly on the
properties of the electrode material. Prerequisites are a good biocompatibility and a high recording and stimulation
efficacy. Recently, carbon nanomaterials – such as carbon nanotubes – have attracted considerable interest due to
their exceptional electronic, thermal and structural properties. Different and independent studies show that the
interface created between carbon nanomaterials and the cellular membrane can yield a high-quality electrical
coupling. Using a technique called ‘capillary forming’, complex three-dimensional structures such as overhanging
wells, inward or outward bending ‘flower petals’ and intricate microhelices can be fabricated, which can
dramatically increase the intimate coupling between the cell and the electrode. The student will be involved
fabricating and characterizing different flavors of carbon structures using electrochemical, electrophysiological and
optical techniques.
Master Thesis/Internship Topics 2013-2014
44
Type of project: Thesis and/or internship project
Degree: Master in Science or Master in Engineering majoring in biomedics, biology, nanotechnology, bioelectronics
Responsible scientists:
For further information or for application, please contact Jordi Cools (Jordi.Cools@imec.be) and Dries Braeken
(Dries.Braeken@imec.be).
Controlling light-matter interactions with plasmonic nanoantennas
Plasmonic nanoantennas are metallic nanoparticles that can be considered as classical oscillators at the nanoscale.
They act as antennas, converting electromagnetic waves at optical frequencies into localized fields. As such, they
provide an effective way to study light-matter interactions at the nanoscale by coupling photons in and out of
nanoscale volumes and manipulate them.
Applications of surface plasmon resonances are widespread, nurtured by nanotechnology, and already approaching
a level of maturity that gives them a prominent position to contribute to some of today’s most important
challenges: energy harvesting, cancer treatment, disease diagnostics, DNA sequencing, and optical computing.
In our group we explore plasmonic antennas for their potential use in innovative biomedical technologies. For
instance, directional antennas are designed to route specific light colors emitted by luminescent molecules. High
quality factor antennas with very high near-field enhancements in combination with a gain medium can even act as
plasmonic nanolasers, paving the way towards highly integrated on-chip biological experiments.
In this master thesis, the interaction of plane light waves, as well as local quantum emitters, with new plasmonic
antenna designs will be studied. The student will gain hands-on experience with sample preparation in the imec
cleanroom, scanning electron microscopy (SEM), and optical experiments (in close collaboration with the KU
Leuven Department of Physics. The experimental results will be verified and complemented by full-field 3D
electromagnetic simulations.
Type of project: Thesis project of 1 year
Degree: Master in Science or Master in Engineering majoring in
physics, electric engineering, nanotechnology
Responsible scientists:
For further information or for application, please contact Niels
Verellen (Niels.Verellen@imec.be) and Dries Vercruysse
(Dries.Vercruysse@imec.be).
Master Thesis/Internship Topics 2013-2014
45
Engineering micro-structures for an optimized lens-free image
Lens-free imaging has the potential to generate high-resolution microscope images without the need of expensive
and bulky optical components. In lens-free imaging the small objects are illuminated with coherent light and the
interference pattern of the diffracted light is captured by an image sensor. As these patterns can be mathematically
described, the inverse formula can be used to reconstruct the original object from the recorded interference
pattern (see figure 1). As such, traditional microscopy is replaced by computational algorithms that allow us to
generate microscopic images using a portable, inexpensive device.
Figure 1: recorded interference pattern of a marker (left) as well as the reconstructed image
(right)
To further explore the full potential of this technique, the aim of this thesis is to engineer micro-structures whose
features are directly visible in the recorded interference pattern, eliminating the need to do full image
reconstruction for image region selection. Hereto the student will devise micro-structures whose interference
pattern has a minimal footprint and a maximal signal-to-noise ratio. Novel concepts will be proposed and their
interference patterns simulated. Finally several micro-structures will be fabricated and tested in real-life working
conditions.
This project is ideal for master students who want to explore the intricate relationship between concept
simulation, device fabrication and experimental validation.
Type of project: Internship or thesis with internship project
Degree: Master in Engineering or Master in Physics
Responsible scientist:
For further information or for application, please contact Frederik Colle (Frederik.Colle@imec.be).
Master Thesis/Internship Topics 2013-2014
46
Measuring electrical properties of cancer cells
It has been known that around 90% of cancer death cases are not due to primary cancer, but metastasis, i.e. tumor
cells migrate from the primary tumor and reside at other part of the body. Circulating tumor cells (CTCs) are cells
shed from primary tumors and circulate in the peripheral blood. CTCs have been known to be one of the most
important pathways for cancer metastasis. The identification & isolation of CTCs are an extremely challenging task
because of the low abundance (down to 1 CTCs per mL) and high similarity to blood cells. State-of-the-art
techniques are suffering from low specificity & efficiency, the loss of cell viability and high subjectivity.
This project work aims to characterize the physical properties of cancer cells (various cell lines as model system)
in order to distinguish and thus isolate them from blood cells. This non-invasive method may provide cell
information without jeopardizing the cell viability, which allows follow-up genetic study on these cells. Two
approaches will be combined in this work: electrical cancer characterization by dielectrophoresis and optical
characterization by fluorescent staining. For both approaches, early studies have already implied clear difference
between cancer cells and blood cells. In the course of this work, an imec proprietary device will be used to
capture cells in a microfluidic chip which allows both electrical & optical characterizations for fixed cancer cell and
leukocytes.
Type of project: Thesis project of 1 year
Degree: Master in Science or Master in Engineering majoring in physics, electric engineering, nanotechnology
Responsible scientists:
For further information or for application, please contact Chengjun Huang (Chengjun.Huang@imec.be) and
Chengxun Liu (Chengxun.Liu@imec.be).
Gram staining using spectroscopy
Gram staining is a widely used method to differentiate bacteria on the chemical and physical properties of their cell
walls into Gram-positive or Gram-negative. Gram positive bacteria stain violet due to the presence of a thick layer
of peptidoglycan in their cell walls, which retains the crystal violet these cells are stained with. A standard
procedure typically takes three steps: staining with a water-soluble dye called crystal violet, decolorization, and
counterstaining.
The gram stain is one of the most frequently used stains in a clinical microbiology laboratory, but as this procedure
is time-consuming, a simple spectroscopic method to replace this method would largely be beneficial. Raman
scattering is an optical spectroscopy method and allows to differentiate chemical biomolecules based on their
vibrational or rotational modes. It has been shown to be allow for differentiation of cells and may allow as well to
spectroscopically differentiate bacteria.
You will combine state-of-the-art confocal Raman spectroscopy with advanced signal processing using principal
component analysis to image and differentiate both gram-positive and –negative bacteria.
Type of project: Thesis and/or internship project
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in bio-engineering,
nanotechnology, (bio)chemistry, biomedics
Responsible scientist:
For further information or for application, please contact Evelien Mathieu (Evelien.Mathieu@imec.be).
Master Thesis/Internship Topics 2013-2014
47
Gold nanostars for imaging and photothermal treatment of cancer
Cancer is still one of the most leading death causes in the world and the demand for more precise and sensitive
imaging and therapy techniques remains high. In the latest decennium, nanoparticles have been opted as a contrast
agent to improve the detection limit for optical tumor imaging or even to treat cancer.
During this thesis, gold nanoparticles will be examined as they can be both used for cell therapy upon irradiation
and for imaging based on surface enhanced Raman scattering (SERS). More specifically, gold nanostars will be
coated with a SERS label and subsequently coupled with biological ligands to target specific receptor molecules on
the tumor cells. Using multiple SERS labels, each with a specific spectrum, multiplexing is possible allowing to
visualize different cell types or molecules. Besides imaging, the treatment will occur by photothermal therapy since
the particles will absorb light at a specific wavelength and convert it into heat. This heat is deadly for tumor cells
since they are more temperature sensitive compared to normal cells.
The thesis student will be strongly involved in the different aspects of this topic, including the chemical synthesis of
nanoparticles, Raman spectrometry, in vitro studies and microscopy techniques.
Type of project: Thesis project
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in (bio)chemistry,
bio-engineering, nanotechnology or related
Responsible scientist:
For further information or for application, please contact Antoine D’Hollander (Antoine.DHollander@imec.be).
Antibody stabilizers for lateral flow assays
Lateral flow immunoassays are especially designed for single use at a point of care/need. The best-known lateral
flow system today is the pregnancy test. In all lateral flow systems, antibodies are immobilized on a solid support
or on a transducer for selective detection of their analyte. However, when an antibody comes into contact with a
solid support, the folding conformation can change to a partially unfolded or totally unfolded state. Unfolded
antibodies show a reduced or even a total loss of their activity. Therefore, immobilized antibodies must be stored
in an environment beneficial to stabilize their conformation. Furthermore, guaranteed stability of immobilized
antibodies on a solid support is an important key to achieve reliability and stable interfaces for lateral flow
immunoassay commercialization.
This thesis aims to characterize different commercial stabilizers and methods to preserve the 3D conformation of
the antibody for application in lateral flow systems. Hereto different characterization methods will be used. This
research should lead to robust and reliable biointerfaces for lateral flow detection schemes.
Type of project: Thesis and/or internship project
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in bio-engineering,
(bio)chemistry, biomedicine or related
Responsible scientist:
For further information or for application, please contact Karolien Jans (Karolien.Jans@imec.be).
Master Thesis/Internship Topics 2013-2014
48
Multiplex ligation polymerase amplification on chip
Since its introduction, the polymerase chain reaction (PCR) has become an indispensable tool in clinical diagnostics.
In recent years, significant advancements emerged in the area of miniaturization of PCR using microfabricated
structures with clear benefits. Not only the speed and the efficiency of the amplification can be improved, also the
assay costs are largely reduced by downscaling due the lower consumption of expensive reagents. A further benefit
in developing complete lab-on-a-chip systems is the possibility to integrate both sample preparation and
amplification in a single disposable cartridge.
At imec, we recently designed and developed a silicon based miniaturized PCR system. This on-chip PCR chamber
showed to be very promising, but its use for multiplexing has not been demonstrated. Therefore, the scope of this
research topic is to transfer and optimize this 3-step multiplex PCR based reaction, more particularly a multiplex
ligation polymerase amplification (MLPA) reaction, for on chip analysis. To make this project a success, a broad
interest in molecular biology, chemistry and basic engineering is required.
Type of project: Thesis and/or internship project
Degree: Master in Industrial Sciences of Master in Science or Master in Engineering majoring in bio-engineering,
(bio)chemistry, biomedicine or related
Responsible scientist:
For further information or for application, please contact Tim Stakenborg (Tim.Stakenborg@imec.be).
TNFα detection in cell-culture medium of activated cells
Cytokines (e.g. IL6, IL10, TNFα and many others) are an important class of secreted proteins that play a key role
in the immune response. They are secreted by many cell types like macrophages, monocytes, T-cells, B-cells, etc.
This secretion is often in very small amounts with a peak of only a few hours after activation of the cells. In
literature, the detection of cytokines is mainly done by RT-PCR or ELISA, which are both sensitive techniques, but
they do not allow real-time detection. Therefore, a need remains for real-time detection methods that allow rapid,
quantitative, close-to-the-cell (to reduce dispersion effects) cytokine analysis. A type of biosensor that can meet
these requirements are silicon waveguide ring resonators.
Silicon waveguide ring resonators are based on the total internal reflection properties of silicon. Silicon waveguide
ring resonators contain a bus waveguide, for the input of the light, a silicon ring shape close to the bus waveguide
and an output waveguide to the detector. When the ring is close enough to the bus waveguide, the light can
couple into the ring and positive interference of discrete wavelengths can occur. These wavelengths are dependent
on the total length of the ring, but also the refractive index near the ring surface. This property results in a
detectable wavelength shift when for example proteins bind to the ring, which makes it ideal for real-time, labelfree sensing.
As a proof-of-principle we will make use of the U-937 cell line which is known to secrete elevated levels of TNF-α
when stimulated with for example phorbol myristate acetate (PMA). The cells will be trapped in cellular
bioreactors near the sensor surface for real-time detection of the secreted TNF-α. These results will be compared
to results obtained with the BIAcore tool and Enzyme-Linked Immunosorbent Assay (ELISA).
This topic is a collaboration between imec and the MeBIOS group of Jeroen Lammertyn at KULeuven.
Type of project: Thesis and/or internship project
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in bio-engineering,
(bio)chemistry, biomedicine or related
Responsible scientist:
For further information or for application, please contact Jef Ryken (Jef.Ryken@imec.be).
Master Thesis/Internship Topics 2013-2014
49
Detection of single protein molecules in microwells on a digital lab-on-a-chip for
point-of-care diagnostics
Detecting low protein concentrations in blood samples has the potential to improve early-stage detection of many
diseases. Most immunoassays detect protein concentrations in the range 10 -12 M. However, most proteins relevant
for early detection in cancer and early stages of infection (f.e. HIV) require detection of protein biomarkers in a
much lower concentration range of 10 -16 to 10 -12 M. The most common assay format for detecting these proteins
in serum is ELISA. This thesis will focus on the detection of single protein biomarkers by developing an integrated
lab-on-a-chip that allows ELISA to be executed in femtoliter-sized reaction chambers (i.e. digital ELISA).
In a first step, sandwich antibody complexes will be formed on microscopic spheres. After this, the
immunocomplexes will be labeled with an enzyme-reporter as in standard ELISA tests. When the ratio of proteins
to microscopic spheres is very low, as is the case for low protein biomarker concentrations in serum, beads will
either carry a single protein in an immunocomplex or none. Next, the captured immunocomplexes will be
confined to very small reaction chambers. As such, the fluorophores that are generated by each single
immunocomplex are very concentrated, ensuring a high local concentration of fluorescent product that can be
detected with standard fluorescence microscopy.
This approach relies on the accurate fabrication of femtoliter-sized reaction chambers to confine these
fluorophores. In a first phase, a fabrication process will be developed that enables the creation of arrays of
hydrophilic microwells surrounded by a hydrophobic material. Therefore, a thin layer of hydrophobic Teflon will
be coated on a glass substrate. Subsequently, microwells will be etched through the Teflon layer and the glass
substrate, thereby generating large arrays of micron-sized glass wells in a Teflon matrix.
In a next phase, this array of microwells will be used for a digital ELISA assay for detecting the protein tumor
necrosis factor-α (TNF-α) on a lab-on-a-chip. Microscopic spheres used for capturing TNF-α in serum are loaded
inside the microwell arrays by transporting droplets containing these beads over the array by using a digital lab-ona-chip. Wells containing a single TNF-α molecule will be quantified by counting the fluorescent microwells.
This topic is a collaboration between the MeBIOS group of Jeroen Lammertyn at KULeuven and imec.
Type of project: Thesis and/or internship project
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in nanotechnology,
(bio)physics, bio-engineering or related
Responsible scientist:
For further information or for application, please contact Frederik Colle (Frederik.Colle@imec.be).
Quantitative protein kinetics analysis using a refractometric LSPR sensor with an
improved figure of merit
Proteins are vital parts of living organisms, and it’s important to explore their structures and functions. The
interactions between proteins, from transient, low-affinity to stable, high-affinity, define much of cellular behavior,
and analysis of their interaction networks will help to assign functions to uncharacterized proteins. Furthermore,
during the development of therapeutics, such as antibodies, molecules are frequently selected based on their
binding kinetics and selectivity for a target ligand, as this single parameter is often predictive of activity in in-vitro
and in-vivo assays. The standard analysis method, surface plasmon resonance (SPR), suffers from the fact that its
decay length is much larger than the protein size and thus might not provide an optimum sensing ability. However,
its nanoscale counterpart, localized surface plasmon resonance (LSPR) is very promising to solve this problem.
LSPR is a resonantly excited coherent electron oscillation at a metal nanoparticle surface, and its wavelength
position is highly sensitive to local refractive index changes within the electromagnetic near-field of the
nanoparticles. This effect forms the basis of LSPR biosensors. The electromagnetic field decay length has the same
length scale as proteins, making biomolecules an ideal analysis target. In addition, it provides the possibility of
miniaturization and multiplexing, as well as the compatibility with microfluidics for point-of-care personalized
diagnostics.
Master Thesis/Internship Topics 2013-2014
50
At imec, we have recently developed a LSPR sensing platform with the spectral linewidth as narrow as ~10nm,
offering a supreme figure of merit to potentially reduce the limit of detection. The thesis student will compare its
sensing ability to that of the conventional SPR platform, and take advantage of the sensing system to investigate the
protein-protein interactions and their binding/unbinding kinetics in real time.
Type of project: Thesis and/or internship project
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in bio-engineering,
(bio)chemistry, biomedical or related
Responsible scientist:
For further information or for application, please contact Jiaqi Li (Jackie.Li@imec.be).
High quality-factor resonators in silicon nitride waveguides
Dielectric waveguides consisting of a high-index core surrounded
by lower-index cladding layers allow low-loss guiding of light. For
photonic integrated circuits, the focus still lies on silicon photonic
waveguide structures for 1300 and 1550 nm wavelengths.
However for several applications in biology and chemistry,
waveguides for short wavelength operation are desirable. Silicon
nitride is a promising material for optical waveguides due to its
low non-linearity and its transparency in the visible and infrared
spectrum. Last year, a low-loss silicon nitride waveguide platform
was developed. By an extensive materials study in the 200 mm
line of imec, the propagation losses were reduced below 0.5
dB/cm at a wavelength of 532 nm while maintaining a low
autofluorescence. In the picture, the coupling from a fiber to a
250 nm wide waveguide on chip is shown.
For integrated biosensing applications, the development of compact, high-quality factor resonators at visible
wavelengths is of paramount importance. In this thesis project, the student will start from the developed silicon
nitride waveguide technology and design novel high quality-factor waveguide resonators. Initially, two types of
resonators will be considered: linear 1D photonic crystal resonators and ring resonators. The main focus will be
on the linear photonic crystal resonators, for which both the Bragg gratings and the resonant cavity will have to be
designed and optimized on the working frequency of 532 nm. This will be done by performing FDTD or FEFD
simulations, followed by experimental confirmation of the simulated properties on the fabricated samples by means
of waveguide transmission spectroscopy.
The student will gain hands-on experience with optical experiments. Sample preparation will be handled by the
student in the imec III-V cleanroom in cooperation with the daily advisor. The student will obtain experience in
optical and electron beam lithography and master various deposition and etching techniques. Further sample
characterization will be done by optical microscopy, scanning electron microscopy and waveguide transmission
spectroscopy. The candidate should have a strong interest in photonics and nanofabrication.
Type of project: Thesis project of 1 year
Degree: Master in Science or Master in Engineering majoring in material science, physics, nanotechnology
Responsible scientist:
For further information or for application, please contact Pieter Neutens (Pieter.Neutens@imec.be).
Master Thesis/Internship Topics 2013-2014
51
Noise characterization and modeling of electrodes for in vivo and in vitro neural
recording
Imec develops state-of-the-art CMOS-active Si neural probes and multi-electrode arrays (MEAs) for large-scale
neural recording. One of the most important sub-components of such devices is the electrode that transduces the
neural signals into measurable voltages. In addition to the wanted signal, electrodes (and integrated circuits) also
pick-up unwanted noise originating from different sources: thermal, biological, electrode-electrolyte interface,
electronic, and crosstalk. Understanding the contribution of these noise sources to the overall recorded neural
data is crucial for developing better and smaller electrodes and more efficient algorithms to recover the encoded
neural information.
In this research project, the student will perform an in-depth study of the non-biological noise recorded with
electrodes of different sizes from passive and CMOS-active Si probes and multi-electrode arrays. The student will
develop the required setups for accurate measurements of small noise amplitudes. Hands-on experience in building
PCBs using discrete components (low-noise amplifiers, R C components, etc.) and good understanding of their
properties is a pre-requisite. Moreover, knowledge in handling spectrum/network/impedance analyzers & Matlab is
advantageous. The overall goal will be to identify the causal links between electrode noise and intrinsic/extrinsic
electrode properties including electrode-electrolyte impedance, area, material roughness, material composition,
etc.
Type of project: Thesis project of min. 6 months full-time
Degree: Master in Electrical Engineering, Master in Material Engineering/Sciences majroing in device physics,
electrical engineering, physics, physical chemistry, electrochemistry, material science
Responsible scientist:
For further information or for application, please contact Andim Stassen (Andim.Stassen@imec.be) and Carolina
Mora Lopez (Carolina.MoraLopez@imec.be).
Characterization of the light-sensitivity of CMOS-ICs for life science applications
For many life sciences applications, monolithic integration of analog CMOS ICs with MEMS, photonics, and
microfluidics is essential to enable multimodal, high-performance diagnostic, therapeutic, and scientific instruments.
Analog CMOS ICs are required amongst others to amplify and filter small bio-signals, multiplex large sensor arrays,
and actuate and manipulate cells or other micro-objects.
In most cases, such chips need to be operated under ambient light conditions or may even be exposed to laser
light for fluorescence microscopy. On the other hand, Si CMOS is innately sensitive to light (from near IR to near
UV) causing leakage currents in the transistors that alter the overall circuit performance. It is hence crucial to
properly shield the circuits.
In this research project, the student will do an in-depth investigation of the light-sensitivity of implantable CMOS
neural probes and multi-electrode arrays for in vitro applications. These two technology platforms have recently
been developed at imec. The student will do extensive IC characterization (on wafer and single die level) under
various light conditions and, if necessary, develop appropriate experimental setups to study the observed effects in
more detail.
The student will also explore and identify new solutions for light shielding or sensitivity suppression: deposition of
thin metal layers (imec processing), chip/setup packaging, layout techniques, circuit design techniques, etc.
Furthermore, electrical modeling of the light effects may serve as an additional tool to further understand the
observed phenomena.
Master Thesis/Internship Topics 2013-2014
52
Type of project: Thesis project of min. 6 months full-time
Degree: Master in Electrical Engineering, Master in Sciences majoring in electronics, device physics, material
science
Responsible scientist:
For further information or for application, please contact Carolina Mora Lopez (Carolina.MoraLopez@imec.be)
and Luis Hoffmann (Luis.Diego.Leon.Hoffmann@imec.be).
Multimodal integration of EEG and functional Near Infrared Spectroscopy for
ambulatory brain imaging
Research on low power, portable EEG recording devices have recently gained huge momentum. These devices are
already being used for continuous monitoring of brain activity for both therapeutic and neuroscientific research.
Active-electrode based, comfortable, gel-free EEG headsets have made it possible to use these in home
environment with minimal professional supervision. Near Infrared Spectroscopy (NIRS), a brain imaging technique
of growing interest, however, lags far behind while ambulatory monitoring is concerned. It has been recently
shown that EEG combined with functional-NIRS (fNIRS) has far greater prospect in decoding brain activity. EEG
measures post synaptic potentials associated with neural activation while fNIRS measures local haemodynamic
changes associated to the same. These two modalities complement each other in their ability to resolve
information about the spatial and temporal characteristics of neural activity.
Analog circuits live at the heart of these medical systems, extracting relevant biomedical signals in presence of
various unwanted artifacts . As one of the key building blocks of such medical systems, constrains on these analog
circuits are strict: Low power dissipation, high signal quality, reliability, and miniature size. Combining EEG and
fNIRS in a portable headset requires both electrical and optical monitoring, preferably on the same IC. These
battery operated systems have to low power and the two modalities should have minimal interference. The sensor
nodes should be optimally placed and proper algorithms need to be developed to extract maximal information on
neural activity.
The focus of this MS topic will be to first start with literature search of the existing fNIRS system and how they are
combined with EEG measuremnt. She/he will next validate the efficacy of EEG+fNIRS with existing EEG headset
and off-the-shelf components. The candidate will recognize the key challenges in combining these two modalities
and will also be involved in developing algorithms to extract maximal information from this mutimodal system.
Existing custom EEG+fNIRS system used in lab
environment.
Future multimodal EEG+fNIRS
ambulatory monitoring.
Master Thesis/Internship Topics 2013-2014
system
for
53
Type of project: Thesis project with internship of 6 months
Degree: Master in Engineering majoring in electronics
Responsible scientist:
For further information or for application, please contact Srinjoy Mitra (Srinjoy.Mitra@imec.be).
Master Thesis/Internship Topics 2013-2014
54
IV.
Imaging Systems
Dynamic current steering in active pixel sensors
Most CMOS image sensors use ’active pixels’ to reduce the readout noise. Being ‘active’ in this case means they
contain a transistor in source-follower operation that acts as a buffer between the sensitive pixel photo-sensitive
node and the output line that is shared between all pixels in the same column of the imager array.
With ever-increasing imager pixel count, both parasitic resistance and capacitance of these output lines increase,
while at the same time higher frame rates require increased sample rates. The settling time of the pixel sourcefollower including all interconnect parasitics becomes the bottleneck for large imagers at high-speed operation.
While the standard solution to this problem involves an increase of the operating current, there are alternative
options suggested in literature as well as new ideas, that could improve on this speed-power trade-off.
In this thesis, the target is to investigate to what extent the speed/power-ratio of this imager readout could be
improved; this involves
• literature study
• quantitative comparison by spectre simulations on the available options for a representative imager
• (if possible) a more generic modeling of this trade-off to deduce guidelines for an optimal solution,
depending
• on the imager parameters
Type of project: Thesis project
Degree: Master in Engineering majoring in electronics
Responsible scientists:
For further information or for application, please contact Steven Terryn (Steven.Terryn@imec.be) and Jonathan
Borremans (Jonathan.Borremans@imec.be).
Master Thesis/Internship Topics 2013-2014
55
V.
Organic Electronics
Degradation mechanisms in organic solar cells
Organic photovoltaic devices are one of the most promising applications of organic semiconductors. As organic
semiconductors can be manufactured by low temperature processes, such as printing from solution based inks,
these materials are compatible with flexible plastic substrates resulting in a lightweight, inexpensive and very
practical product. Over the last years impressive progress has been achieved in organic photovoltaic device
efficiency and promising roll-to-roll compatible deposition techniques have been also reported. This rapid
technological development brings applications close-by, and consequently also the importance of device reliability.
Cost evaluations suggest that a lifetime of 5-10 years is necessary with current power conversion efficiencies to
achieve low prices. Nevertheless, currently only 1 year of outdoor lifetime was reported on polymer solar cells,
other studies in accelerated conditions estimated the device lifetime to 2-3 years.
Currently, organic solar cells are comprised of a multilayer stack of a transparent anode, an organic or oxide
interlayers, a photoactive bulk heterojunction composed at least two organic compounds capped with an
evaporated cathode. Reaction with oxygen and humidity as well as light induces degradation both in the volume
and at the interfaces of these layers leading to multiple concurrent degradation mechanisms. Therefore
discriminating between the parallel mechanisms is one of the biggest challenges in reliability research. The focus of
this master thesis/internship lies in the investigation of the degradation of exciton separation, charge transport and
charge extraction in organic solar cells. Implementation of new device architectures, complementary electrical
measurements and eventually material characterization techniques will assist the distinction between the
simultaneously occurring degradation mechanisms.
Most of the work will be done in the state-of-the-art organic device processing lab of imec. The student will
receive a broad training on full device processing and characterization tools. After a short training period it is
expected that the student can work independently and focusing on his/her investigation. This thesis/internship will
mostly consist of practical work.
Type of project: Internship or thesis project of minimum 6 months
Degree: Master in Science or Master in Engineering majoring in physics, material science, nanosciences, electrical
engineering
Responsible scientist:
For further information or for application, please contact Eszter Voroshazi (Eszter.Voroshazi@imec.be).
Organic photodetectors
Organic semiconductors are used in many fields of photonics. Displays fabricated using organic light emitting
diodes (OLED) can be found in modern smartphones and tablets, whereas organic solar cells (OPV - organic
photovoltaics) are emerging with demonstrated efficiencies above 10%. Organic photodetectors (OPD) are
another very interesting domain, with ultrathin active layers (order of tens of nanometers) providing performance
comparable to bulk inorganic devices. Thanks to a multitude of possible compounds, parameters such as response
spectrum, cut-off wavelength etc. can be easily tuned.
Because of very high absorption coefficient and low refractive index, issues such as reflection or crosstalk can be
minimized. Another exciting feature is the low processing temperature and thus feasibility of using a flexible foil as
substrate, leading to rollable or curved photodetector arrays.
The focus of this internship will be optimization of the fabrication process of advanced organic photodetectors and
investigation of their performance with respect to given specifications. Active layers will be deposited by spincoating (solution processed polymers) or thermal evaporation (evaporated small molecules).
Master Thesis/Internship Topics 2013-2014
56
The student will be involved in the entire fabrication cycle, performed in the state-of-the-art facilities including
imec's dedicated organic line. Initially, the student will receive training on the relevant processing and
characterization tools. After a short introduction to the facilities, an independent investigation is expected with the
focus on short-term research goals.
Type of project: Internship or thesis project of 4 up to 6 months
Degree: Master in Science or Master in Engineering majoring in nanotechnology, material sciences or electrical
engineering.
Responsible scientists:
For further information or for application, please contact Pawel Malinowski (Pawel.Malinowski@imec.be) and
Soeren Steudel (Soeren.Steudel@imec.be).
Contact resistance optimization in organic thin film transistors
Flexible electronics have drawn many attentions for its applications in large area electronics, such as flexible
display. To realize the complex circuits on foil, high performance thin film transistors (TFTs) with low process
temperature are required. Metal oxide n-type transistors have been demonstrated in industry with average
mobility around 15 cm2/V∙s for back-plane applications in flexible display and OLED TV. However, there is no ptype TFTs demonstrated with the process temperature lower than 150 ˚C in metal oxide TFTs. Instead, organic
TFTs have also been widely studied for its advantages, such as low process temperature and nice p-type TFTs
performance. Record high p-type mobility up to 30 cm2/ V∙s has been demonstrated in large area electronic by
solution proceed single crystal organic TFTs. Thus OTFTs has its potentials in high performance p-type logic
circuits and also CMOS application in cooperation with n-type metal oxide transistors.
To realize high performance TFTs in large area electronics, contact resistance of the TFTs is a very important
factor that limits the performance of the OTFT circuits. With the improvement in contact resistance in OTFTs,
many performance issues would be improved e.g. speed of circuits, noise margin in CMOS logic gates and selfheating induced instability.
In the project, you will be part of the transistor team and you will process and characterize the organic thin-film
transistors independently with some initial training. You will start with device fabrication by working with vacuum
deposition system and photolithography for different process steps. Different device structures would be
investigated for the contact resistance analysis. You will electrically characterize the TFTs and interpret the data to
define follow-up experiments. The morphologies of the devices maybe characterized by different technologies
such as optical microscopy, atomic force microscopy (AFM) and x-ray diffraction (XRD).
This project is very practical and process oriented. Fundamental knowledge of TFT device physics is necessary.
A good sense of experimental design and discipline to execute the plan are required. Persons with hands-on
experience in labs or cleanrooms are preferred. Independent working style and good communication abilities in
English are highly appreciated.
Type of project: Internship project
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in electrical
engineering, material science, chemical engineering
Responsible scientist:
For further information or for application, please contact Tung-Huei Ke (Tung.Huei.Ke@imec.be).
Master Thesis/Internship Topics 2013-2014
57
Bias stress stability study of a-IGZO TFTs
In recent years, amorphous oxide semiconductors (AOSs) are of great interest for thin-film transistor (TFT)
channel layer applications. They have been studied due to their superior characteristics, such as high uniformity,
high electron mobility between 10-50 cm2/V‧s, and their fabrication at low temperatures on plastic substrates.
These advantages of a-IGZO thin-film transistors are promising for next-generation large & flexible backplanes for
displays.
Among AOSs, amorphous indium gallium zinc oxide (a-IGZO) is leading the display industry because of its high
performance. Issue of bias instability of these TFTs under light & at higher temperature still not completely
understood. The semiconductor possesses a high optical band gap and is transparent but the TFTs still exhibit a
photo response to visible light when illuminated. Some studies have reported that illumination can enhance the
negative gate bias stress effect. However, a study involving the full spectrum of colors and overall gate bias
conditions under various temperatures has not yet been conducted on our devices.
The objective of the research on this topic is to provide detailed assessments of our a-IGZO TFT’s bias stress
instabilities under illumination and at higher temperatures. Positive and negative gate bias stress instabilities with
and without light (red, blue & green spectra) exposure together with temperature range between 25oC to 120oC
need to be studied extensively. The time dependence behavior of stress and recovery under various stress
conditions needs to be established. From the results a conclusion need to be drawn for both positive and negative
gate bias stress in relation to device structure, interface & material defects of the TFTs. This activity also includes
the measurements of the manufactured devices with various process splits. If time allows, the student will also
investigate the devices on the flexible substrates.
Type of project: Internship or thesis project of 6 months
Degree: Master in Science or Master in Engineering majoring in material physics, electronics, nanotechnology
Responsible scientist:
For further information or for application, please contact Manoj Nag (Manoj.Nag@imec.be).
Master Thesis/Internship Topics 2013-2014
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VI.
Wireless Communication
Radio-frequency communication with metal-oxide electronics on plastic
In recent years, fast progress was made in the technology of thin-film semiconductor devices based on organic
semiconductors (such as pentacene and derivatives) and oxides, such as Indium-Gallium-Zinc-Oxide (GIZO). In
particular this latter semiconductor offers over amorphous silicon the advantages of a much higher carrier
mobility, of the order of 10 cm2/Vs, and room temperature processing, making it fully compatible with plastic
substrates. This new technology opens the way to circuits and systems fabricated directly on flexible plastic foil.
RFID transponders and tags are one type of application that will greatly benefit from this opportunity.
RFID is an important technology in logistics, to transmit an identification code between a transponder and a
reader. The crucial components of a passive RFID tag are the antenna and the rectifier. The antenna must be
isotropic and have the largest gain possible, while the rectifier must operate at HF (13.56MHz) or more preferable
at UHF (868MHz). In the rectifier, the diodes must follow the high-frequency input signal and provide enough
power for the tag circuitry. Large Area Electronics technologies allow strong cost reductions compared to Si chips
and simultaneously offer true mechanically flexibility, required for tag integration onto items. The diodes can have
mainly two topologies: the Schottky and transistor connected diodes. Transistor-diodes are based on a shorted
gate-drain transistor configuration. In this configuration, the gate-drain electrode and the source act as the injector
and the blocking electrode, respectively. The main advantage of such topology is the integration with other
circuitry, as the same process technology for standard transistors can be used for its fabrication. Their main
drawback, on the other hand, is the relatively long minimal channel length that can be achieved with standard
photolithographic processes. Schottky diodes offer the possibility of extremely small charge transient time and are
normally chosen as rectifying element. However, as GIZO is an amorphous material with a high defect density, it is
difficult to achieve high Schottky barriers and low leakage currents.
The main task of the student is to investigate the effects of GIZO deposition on the transistor-diode
characteristics, in order to achieve high on/off drain currents and high electron mobility, targeting mainly the
transistor onset voltage control. This activity includes the fabrication of devices within imec clean room and our
laboratories using mainly two deposition techniques: RF sputtering and thermal evaporation. The second step will
be to integrate these single devices in a rectifier with integrated capacitances and characterize its frequency
response. Initially, the devices will be fabricated on a hard substrate such as silicon, but the final device should be
completely realized on a flexible plastic carrier. If time allows, the student will also tackle the Schottky barrier
formation on GIZO and its characterization. In order to develop insightful ideas about the diode performance, all
experimental work will be followed by analytical and SPICE models.
Type of project: Internship or thesis project of 6 months
Degree: Master in Science or Master in Engineering majoring in material physics, electronics, nanotechnology
Responsible scientist:
For further information or for application, please contact Adrian Chasin (Adrian.Chasin@imec.be).
Master Thesis/Internship Topics 2013-2014
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Algorithm and architecture co-optimizations for cost and power constrained signal
processing system
Many fundamental innovations in ICT are driven by advanced signal processing systems and their efficient
implementations. As an example, wireless baseband signal processing is one of the key enablers for affordable Gbps
wireless communications.
As one of the key challenges in such innovation, cost and power of signal processing implementations need to be
minimized whereas application level requirements are not scarified. To achieve this goal, co-optimizations of the
following two will be essential:
• Signal processing algorithms that extract useful information from raw data via various mathematical
transformations and searching operations.
• Signal processing architectures that execute the above mathematical transformations and searching
operations.
In the proposed thesis, the student will work on concrete cases such as:
• MIMO detectors optimized for LTE and LTE-Advanced radio systems
• Channelization for software defined radio receivers
For each of the topics, the work will consist first of an extensive literature study of the involved algorithms. Next,
algorithms will be selected with the help of the experienced imec researchers in the field. Finally, an efficient
implementation should be derived. To achieve this, possible algorithm or architecture optimizations will be
needed. The student will learn the respective application domain (e.g., MIMO detectors for LTE) as well as
embedded software design and computer architectures. As a result, this topic provides a good training for
industry-relevant skills as well as innovative algorithms and architectures.
Type of project: Internship project of 6 up to 12 months
Degree: Master in Electrical Engineering majoring in signal processing, telecommunication, embedded systems
Responsible scientist:
For further information or for application, please contact Min Li (Min.Li@imec.be).
Digital assistance and digital frontend for deep submicron analog circuits
CMOS is scaling down to deep-submicron technologies (28nm, 22nm, 14nm) pushed by benefits obtained in digital
design (speed is increasing and area per function is decreasing). From analog design point of view the benefits of
scaling are less clear (parasitics are lower, time resolution is increased but voltage resolution is decreased), but it
has to follow digital design. On the other side, modeling of MOS transistor in deep submicron technologies is less
accurate. Spread with respect to nominal corner is larger in deep- submicron technologies. There is a clear trend
to correct (or assist) functions implemented in analog domain in the digital domain.
The master student may work on the following aspects:
• Calibration, compensation and healing algorithms and digital implementations for practical deep submicron
analog circuits
• Power and performance optimized controlling algorithms and digital implementations for practical deep
submicron analog circuits
This topic will offer an exciting challenge on the boundaries of analog circuits, signal processing and digital circuits.
Type of project: Internship project of 6 up to 12 months
Degree: Master in Electrical Engineering majoring in signal processing, telecommunication, circuit design
Responsible scientists:
For further information or for application, please contact Min Li (Min.Li@imec.be) and Vojkan Vidojkovic
(Vojkan.Vidojkovic@imec.be).
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Algorithm development for automated tuning of cellular duplexer module in
CMOS
Imec’s reconfigurable radio research focuses on scalable transceivers in cost-effective digital CMOS technology,
targeting low power, low cost, high linearity and multimode–operation.
In modern cellular phones, higher data rates are required to stream live media content to the end-user. 4G
standards such as LTE are used to achieve high data rates. These standards require the usage of Frequency
Division Duplexing (FDD) operation, in which the transmitter and receiver communicate at a small frequency
distance, using the same antenna, at the same time. A duplexer is placed between antenna, receiver and
transmitter to filter the transmitter leakage to the receiver, where a very low-power signal must still be
distinguished from noise.
Currently, surface acoustic wave (SAW) technology is commonly used to implement such duplexers off chip.
These duplexers are large, cost-ineffective and only work in one frequency band. In practice, many cellular
handsets support up to 5 bands already, while many more must be supported in the future. In imec, we are
working on a solution which may allow several fixed-frequency SAW-based duplexers to be replaced with a single
reconfigurable duplexer.
Automated tuning is required to guarantee that sufficient isolation between the transmitter and the receiver is
achieved. Variations in the environment of the antenna require the filtering circuit to be adaptively tuned in an online manner. Although optimal algorithms can always estimate all related variations and calculate the right
operation point, the implementation of such optimal algorithms in digital CMOS is a complex challenge, due to
power, area and speed constraints. Hence, practical low complexity but smart algorithms need to be designed to
achieve required performance, and this will eventually translate into feasible CMOS implementations.
In this project, we are looking for a top-notch motivated MSc student to perform his/her thesis work on the
development of practical automated tuning algorithms on CMOS for tunable duplexers in 4G cellular handsets.
During this project, the student will investigate system-, circuit- and component level issues related to the
automated tuning of duplexers. Furthermore, the student will develop and implement an automated-tuning
algorithm (e.g. using an FPGA). The student is expected to verify/prove the operation of said algorithm using
prototype duplexers and antennas in imec’s RF laboratory.
Besides knowledge of analog circuits, RF and signal processing, good communicative and planning skills are a must
to complete the project within time.
Type of project: Internship project of 6 up to 12 months
Degree: Master in Electrical Engineering majoring in DSP/Embedded Systems (or micro-electronics with affinity for
algorithms)
Responsible scientists:
For further information or for application, please contact Barend van Liempd (Barend.vanLiempd@imec.be), Min Li
(Min.Li@imec.be) and Jan Craninkx (Jan.Craninckx@imec.be).
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VII.
Energy
Hydrogen generation through water photoelectrolysis using semiconductor
photoanodes
Hydrogen receives tremendous attention as a renewable energy source in the future. Water photoelectrolysis is a
direct approach to generate hydrogen using solar energy. Due to adjustable bandgap and proper band edge
potential, III-Nitride semiconductor is considered as a promising material in photoelectrolysis. In this project, some
important challenges in III-Nitride system will be focused. To enhance the photocarrier separation and migration,
metal particles/films are introduced at sample surface to manipulate surface potential and band bending. The
corresponding changes in photocatalytic property will also be investigated. Moreover, sample corrosion during
photoelectrolysis is commonly observed. A thin metal oxide layer by atomic layer deposition will be employed to
separate the electrode from direct contact to solution during photoelectrolysis. Third, chemical reactive sites play
an essential role in carrier transfer to solution. Nanostructuring treatment will be applied to the sample surface for
a larger surface area.
In this project, the student will be responsible for device fabrication and (photo)electrochemical characterization.
The device fabrication part includes different metal deposition, annealing and electrode preparation. The
experiments include mainly cyclic voltammetry, chronometry and impedance spectroscopy.
Type of project: Thesis or internship project of 6 months, preferably starting between May-June 2013.
Degree: Master in Science or Master in Engineering majoring in (electro)chemistry, material science, physics,
electronics
Supervising scientists:
For further information or for application, please contact Peter Tseng (tsengp@imec.be) and Ruben Lieten
(Ruben.Lieten@imec.be).
Electrical characterisation of amorphous Si layers for solar cell applications
Amorphous silicon layers offer several advantages for the production of cost-effective, high efficiency Si solar cells.
These advantages stem from the presence of an ultra-thin intrinsic amorphous silicon passivation layer between
the doped (amorphous silicon) emitter region and the crystalline silicon base material. The presence of this
heterojunction, where the interface defect density can be very low, and with favourable band alignment to repel
minority carriers, enables achieving very high open circuit voltage values, and resulting high efficiency cells. To
maximize the solar cell efficiency, minimizing the resistive losses in the electrical contact to a doped amorphous
silicon layer is also critical. Previous works have shown the significance of the amorphous layer processing
conditions on the layers resistivity, and its link to the contact resistance.
The presence of an heterojunction requires careful passivation, and an analysis of this passivation layer/doped layer
stack is one of the aims of this proposed research. It is foreseen that capacitance-voltage and conductance
measurements of a-Si layers, with varying layer thickness, processing conditions, substrate doping etc, will form the
basis for this research. Analysis of the measured data can yield information on defect densities in the layers, the
energy of these defects in the silicon bandgap. The impact of processing on these parameters will be examined. It is
envisaged that this work will focus on electrical characterisation of amorphous silicon layers, and interpretation of
the data generated from this analysis. We are looking for a student who has experience in electrical
characterisation, preferably capacitance-voltage/ conductance-voltage measurements.
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Type of project: Internship project (of 8 months preferably)
Degree: Master in Physics or Master in Engineering majoring in physics, electronic engineering
Supervising scientist:
For further information or for application, please contact Barry O’Sullivan (Barry.Osullivan@imec.be).
Dielectric ablation by laser processing for photovoltaic applications
Laser processing has long been used in photovoltaic solar cell manufacture, but recently it is receiving considerably
research interest as a method of rapidly and accurately ablating dielectric layers. This enables a pattern to be
defined on a solar cell, in an industrially viable process. In this application, a laser process is used to ablate thin
SiO2 layers, used as passivation layers in interdigitated back contact solar cells. In the envisaged process flow, it is
foreseen that two ablation steps will be required: firstly to define the n+ and p+ doped regions, and secondly to
open the points at which the metal layer contacts these doped layers. This work will involve optimising the laser
parameters for such applications, and in designs that correlate with either lithography or screen printing masks.
As the ablation process itself involves melting of the underlying silicon, which then expands, and ruptures the SiO2
layer above, there is a risk of surface damage of the remaining silicon. However, by performing chemical
treatments on this layer, this damage can be minimized. The aim of this project is to develop suitable laser and
subsequent chemical treatment combinations to accurately define the required pattern, and avoid degradation of
the underlying layers.
Type of project: Internship project of minimum 8 months
Degree: Master in Physics or Master in Engineering majoring in physics, chemistry, electronic engineering
Supervising scientist:
For further information or for application, please contact Barry O’Sullivan (Barry.Osullivan@imec.be).
Development of assembly technology for next-generation c-Si PV modules
Photovoltaics have always been mainly (over 80%) based on c-Si solar cells, and this will continue to be the case for
the foreseeable future. The module technology used for connecting and protecting these cells likewise has been
established already quite some time ago and has proven its worth with operational lifetimes exceeding 20 years in
harsh outdoor conditions. However, cost (and other) considerations are continuously pushing technology
development towards higher performance, longer lifetimes and cheaper materials and processing. But while this
pressure has in the past mostly been focused on cell development, also module technology is now being pushed
towards such improvements.
With this in mind, imec is developing module concepts (i-module and i2-module), that provide an alternative for
the currently standard technology for making modules. The standard technology is based on stringing of cells for
electrical interconnection and subsequent EVA lamination for encapsulation of these strings between a
(transparent) front- and backsheet, whereas the i-module targets bonding of the cells to the superstrate using a
silicone adhesive, early on in the process, and then further build up the module. In all of the proposed module
concepts, silicone bonding plays a crucial role, and many aspects of it are still under investigation.
In this topic, the idea is to focus on this silicone bonding technology. In first instance we want to develop and
characterize it further, while at the same time implementing and evaluating it in the different module concepts.
Later on, we would like to investigate the possibilities and limitations of the technology to expand the module
concepts further and test a few ideas we have in mind (intermediate concepts, additional components, alternative
module materials). Of course, even though the focus is on the silicone bonding technology, also its impact on
previous and subsequent processing has to be taken into account, and therefore close interaction with students
and other people working in those fields is needed.
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Type of project: Thesis or internship project of minimum 9 months
Degree: Master in Industrial Sciences or Master in Engineering majoring in material science, physics, electronics
Supervising scientist:
For further information or for application, please contact Jonathan Govaerts (Jonathan.Govaerts@imec.be).
Optimization of the porosification of silicon for application in thin-film crystalline
silicon solar cells
Thanks to its peculiar properties, porous silicon has been extensively employed in different fields of science and
technology, from MEMS technology to biosensors. Within silicon solar cells technology, porous silicon layers can
fulfill various functions, such as those of light reflector or anti-reflector, sacrificial layer for patterning, or structureweakening layer. At imec, we are developing an advanced process for thin solar cells in which porous silicon plays
a double and key role: first, as seed layer it enables the growth of a high-quality thin film (few tens of micrometers)
of silicon, and second, as weakening layer it enables the detachment of this film for transfer onto a low-cost
substrate. The object of this research topic is to optimize the fabrication of this porous layer in order to improve
the reproducibility of the process.
Fabrication of porous silicon is done by electrochemical etching (anodization) of a highly-doped silicon substrate.
The etching process takes place in a solution containing water, HF and an alcohol. The porosity of the layer, a
crucial property for detachment, is determined by processing parameters like the anodization current density and
the electrolyte composition (cf. the figure below, where a double layer of low and high porosities was successively
grown). But other secondary parameters, such as temperature or metal contamination can also impact the porous
layer quality. Your task will be to investigate the impact of various parameters on the detachment yield of the
silicon films, identify which ones are essential for our process, and gain control on them.
This work will be experimental and will take place at a wetbench, in cleanroom environment. For this application
you should therefore have a hands-on attitude and be cautious. A background in semiconductor sciences and/or
(electro)chemistry is preferred.
Type of project: Thesis or internship project of minimum 9 months
Degree: Master in Science or Master in Engineering majoring in material science, physics, chemistry
Supervising scientists:
For further information or for application, please contact Valerie Depauw (Valerie.Depauw@imec.be) and Roberto
Martini (Roberto.Martini@imec.be).
Master Thesis/Internship Topics 2013-2014
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Optimization of the bonding and detachment process of epitaxial silicon foils for
application in thin-film crystalline silicon solar cells
To limit the use of ultra-pure silicon in the fabrication of thin-film crystalline silicon solar cells, a procedure to
create foils is established at imec. This concept consists of the formation of an epitaxial layer on top of a weak
porous silicon layer. After this epitaxial layer underwent the front-side solar cell processing, the cells are separated
from each other by laser grooving. At the same time, the laser groove is used to be able to detach a specific part
of the epitaxial foil from its parent substrate. Afterwards, it is bonded to a quartz plate by a permanent silicone
bond. Many different separation processes (like heat treatment, ultrasonic waves, mechanical force, …) can be
used to detach the epitaxial foils from the parent substrate. The object of this research topic is to help us
screening the possible separation processes to obtain tiles of silicon on a quartz plate. In a second step optimize
the most promising candidate in order to improve the yield of this specific process sequence. This will be done by
starting from a currently used process sequence that is used to glue a single foil of silicon onto a quartz plate.
However, many additional problems (like formation of micro-cracks on the edges, stress and bowing of the foils
during and after gluing, …), occur when tiles of 40µm-thick foils need to be glued to a single quartz plate in an
accurate manner.
Your task will be to investigate the impact of various parameters on the detachment and bonding yield of those
silicon films, identify which ones are essential for our process, and gain control on them.
This work will be experimental and will take place in a lab and cleanroom environment. For this application you
should therefore have a hands-on attitude. You should be able to work accurate and consistent. Since you will
depend also on other persons for processing, you should be a real team player. A background in engineering is
preferred.
Bonded epitaxial foil of 40µm-thick onto a quartz substrate
Type of project: Thesis or internship project of minimum 9 months, starting September 2013
Degree: Master in Science or Master in Engineering majoring in material science, physics, chemistry
Supervising scientist:
For further information or for application, please contact Kris Van Nieuwenhuysen
(Kris.VanNieuwenhuysen@imec.be).
Master Thesis/Internship Topics 2013-2014
65
Development and validation of an optical model for PV modules
It is well known that photovoltaic (PV) modules have a lower performance in the field than measured directly after
production under “Standard Test Conditions”. The resulting energy yield losses can be mainly attributed to:
• reduced illumination resulting in lower current
• increased cell temperature during operation resulting in lower voltage (not compensated by slightly higher
current)
nNon-uniform illumination conditions (shading, clouds,...) leading to current mismatch in serially connected
cells
• performance degradation over time
In order to predict either the energy production of PV modules or to identify energy yield loss within the module,
it is necessary to develop a suitable model to calculate the optical absorption, cell temperature and electrical
output as a function of ambient temperature, wind direction and total irradiance. With this in mind, imec develops
a model for module that incorporates optical, thermal and electrical properties and behavior and is suitable for
simulating non-steady-state and non-uniform illumination conditions.
Thermal and electrical properties of PV modules were investigated and have been correctly integrated into the
opto-electro-thermal model. However, more insight into optical properties of PV module is needed to improve
the accuracy of the energy yield simulations.
In the first place, the goals of this topic is to characterize the optical properties of PV modules and to develop an
optical model suitable to simulate non-steady-state and non-uniform illumination conditions. The optical model has
to fit into the opto-electro-thermal model, therefore close interaction with students and other people working in
those fields is needed. Later on, we would like to validate the opto-(electro-thermal) PV module model.
Type of project: Thesis or internship project of minimum 9 months
Degree: Master in Industrial Sciences or Master in Engineering majoring in material science, physics (optics)
Supervising scientists:
For further information or for application, please contact Hans Goverde (Hans.Goverde@imec.be) and Ounsi El
Daif (Ounsi.ElDaif@imec.be).
Degradation mechanisms in organic solar cells
Organic photovoltaic devices are one of the most promising applications of organic semiconductors. As organic
semiconductors can be manufactured by low temperature processes, such as printing from solution based inks,
these materials are compatible with flexible plastic substrates resulting in a lightweight, inexpensive and very
practical product. Over the last years impressive progress has been achieved in organic photovoltaic device
efficiency and promising roll-to-roll compatible deposition techniques have been also reported. This rapid
technological development brings applications close-by, and consequently also the importance of device reliability.
Cost evaluations suggest that a lifetime of 5-10 years is necessary with current power conversion efficiencies to
achieve low prices. Nevertheless, currently only 1 year of outdoor lifetime was reported on polymer solar cells,
other studies in accelerated conditions estimated the device lifetime to 2-3 years.
Currently, organic solar cells are comprised of a multilayer stack of a transparent anode, an organic or oxide
interlayers, a photoactive bulk heterojunction composed at least two organic compounds capped with an
evaporated cathode. Reaction with oxygen and humidity as well as light induces degradation both in the volume
and at the interfaces of these layers leading to multiple concurrent degradation mechanisms. Therefore
discriminating between the parallel mechanisms is one of the biggest challenges in reliability research. The focus of
this master thesis/internship lies in the investigation of the degradation of exciton separation, charge transport and
charge extraction in organic solar cells. Implementation of new device architectures, complementary electrical
measurements and eventually material characterization techniques will assist the distinction between the
simultaneously occurring degradation mechanisms.
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Most of the work will be done in the state-of-the-art organic device processing lab of imec. The student will
receive a broad training on full device processing and characterization tools. After a short training period it is
expected that the student can work independently and focusing on his/her investigation. This thesis/internship will
mostly consist of practical work.
Type of project: Internship or thesis project of minimum 6 months
Degree: Master in Science or Master in Engineering majoring in physics, material science, nanosciences, electrical
engineering
Responsible scientist:
For further information or for application, please contact Eszter Voroshazi (Eszter.Voroshazi@imec.be).
Large area coating of organic photovoltaic modules
Organic photovoltaics (OPV) are evolving within the field of renewable energy production from lab-scale devices
to industrial-scale modules. OPVs differ from traditional silicon based solar cells in their carbon-based light
absorbing material. These organic materials are processable in two manners: vacuum evaporation and solution
based deposition. Roll-to-roll compatible processing techniques like spray coating and slot-die coating can be used
within the solution processed domain to achieve high-throughput production. This, in combination with the low
process temperature required, creates opportunities for processing on many types of substrates, including foils or
textile. To enable the transition from lab- to industrial- scale production, patternable coating techniques need to
be investigated.
Recent OPV developments have focused on efficiency enhancement on single cell levels, with active areas below 1
cm². However, due to the inherently low mobility’s of organic materials, the upscaling poses serious problems.
One of the more promising approaches for upscaling connects several smaller cells together in a monolithic series
connection. In order to create the interconnection of these subcells, several patterning steps are normally
required. Recently established in-house patterning techniques have enabled the reduction in material wastage and
the number of patterning steps required, but modifies the coating characteristics.
In this project, the researcher will investigate scalable coating techniques for large area OPV production and the
effects of patterning methods on the coatings. Initially, conventional sheet-based processing methodologies will be
used, followed by the transferal of the process to roll-to-roll applicable tools. Once coating and patterning have
been developed, complete OPV modules will be fabricated, and their performance will be benchmarked against
more conventional fabrication techniques.
Type of project: Internship or thesis project of minimum 6 months
Degree: Master in Industrial Engineering or Master in Science or Master in Engineering majoring in material
science, nanotechnology, electrical engineering, chemical engineering, physics, chemistry
Responsible scientist:
For further information or for application, please contact Jeffrey Tait (Jeffrey.Tait@imec.be).
Master Thesis/Internship Topics 2013-2014
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2D and 3D modeling of high efficiency back junction solar cells
This project is part of a further collaboration between MCA and the PV department, for the development of 2D
and 3D modeling of high efficiency back junction solar cells (IBC, Interdigitized Back Contact).
IBC solar cells stand as the workhorse of imec’s PV technology vehicle, aiming in high efficiency values (above 22%)
and simplification of the fabrication process in order to reduce the associated costs.
The overall operation of the IBC cells is governed by the combination of a large number of fabrication features and
parameters (i.e. doping, passivation, antireflection coating, contact placement, etc.). In order to maximize the
electrical output of the cell, it is necessary to optimize both its optical and electrical properties so as to achieve
high optical absorption and efficient trapping of the photogenerated electron-hole pairs. In this respect, the ability
to model the overall cell operation is of paramount importance, as it offers in – depth understanding of the effect
of each parameter / feature, and most importantly, a cost effective test vehicle for the optimization of the cell
performance.
In this direction, imec has already developed both 2D and 3D modeling platforms for the cell simulation, which are
based both on Process and Device simulation tools. At this point, we are in the final stage of the development and
evaluation of these platforms, and we are focusing on the optimization of the Device modeling (optical and
electrical). In particular, we are using several tools from Synopsys (SProcess, SDevice, SDE, Sentaurus Workbench
etc.)
The main work of this project will be the optimization of the device simulations, first by calibrating cells with
simpler geometries and then, the most updated cell types. One additional goal is the link of Process simulation
results with the observed device behavior of solar cells that have been fabricated by means of ion implantation.
Both topics are in close conjunction with current research activities on modeling, within MCA.
The student will work on close collaboration with researchers both from MCA and PV. Depending on the overall
progress of the work, he might have to focus more either to optical or the electrical aspect of the modeling.
Type of project: Internship project of 6 months
Degree: Master in Science or Master in Engineering majoring in physics, electrical engineering, material science
Responsible scientists:
For further information or for application, please contact Pierre Eyben (Pierre.Eyben@imec.be) and Antonios
Florakis (Antonios.Florakis@imec.be).
Photonic nanostructures for light management in novel thin silicon solar cells and
modules
Context
Silicon based solar photovoltaic cells represent more than 90% of the photovoltaic panels presently sold in the
world; silicon is one of the most abundant materials on earth. In such cells, more than 1/3 of the cost is due to the
silicon itself. Indeed, its purification and crystallisation have an important energetic and economical cost. This is
why the photovoltaic research community is presently looking for ways to have solar cell structures based on
thinner and thinner silicon layers. There are nevertheless limitations, existing for thick cells and becoming crucial
for thin cells: the thinner the material, the lower its light absorption, in particular at long wavelengths (near
infrared), due to the low absorption of Silicon. Thus, in order to keep the light absorption high, it is necessary to
find light scattering and trapping techniques inside the absorbing silicon layer.
Imecframe
Imec is developing novel approaches to decrease the cost of silicon solar cells, including going to thinner silicon
layers (40 to one micron). For such thin cells, the regular light scattering approach used for today’s thick cells (>
150 µm) by texturisation of the silicon surface) will not be sufficiently effective anymore. We propose therefore to
develop light scattering and light trapping techniques to compensate for these losses.
Master Thesis/Internship Topics 2013-2014
68
This means concretely:
Understanding the optical losses of such structures thanks to home-made optical simulations. (Simulation tool:
CAMFR based on Python, possibly Lumerical) as well as various optical characterisation techniques.
Exploring schemes to enhance the light trapping in order to enhance absorption, while keeping good electrical
properties.
For this 2nd point the imec Photovoltaics group is exploring several approaches:
• Nanopatterned diffractive structures: we are developing nanopatterning techniques based on novel
lithography techniques: nanoimprint lithography, hole-mask colloidal lithography (pseudo-random) and
plasma or solution-based etching techniques, allowing to strongly modify the optical properties of a solar
cell stack.
• Dielectric Bragg reflector that increase the reflection to almost 100 % in the near-IR.
• Metallic or dielectric nanoparticles to scatter light into the layers.
Internship description
In this frame, it is proposed to interns (between 3rd and 5th year of Master or equivalent) to participate to the
numerical modelling of solar cells with and without light-management features, as well as to some aspects of the
experimental part, in particular nanoimprint lithography and solar cell characterisation.
Type of work: experimental and simulations
Type of project: Thesis or internship project
Degree: Master in Science or Master in Engineering majoring in physics, electrical engineering, material science,
chemistry
Responsible scientist:
For further information or for application please contact Ounsi El Daif (Ounsi.ElDaif@imec.be).
Master Thesis/Internship Topics 2013-2014
69
VIII.
Sensor Systems for Industrial Applications
Opto-acoustic micro-resonator for sensing applications
In the past decades, Micro-ElectroMechanical resonators made their way in a vast amount of applications. They are
used nowadays as clocks and timing devices, inertial sensors, gas sensors, energy harvesters, ... The vast majority of
these resonators rely on electrostatic, piezoelectric, thermal or piezoresistive transduction mechanisms for their
function. Indeed, these mechanisms are relatively easily implemented in typical microelectronic platforms.
The development of photonic platforms, like the ones available at imec, allow considering to use optical
interactions, e.g. radiation pressure, as transduction mechanisms. Optical forces are well known for example in
bio- or life science contexts where optical tweezers have been demonstrated for a long time. In this project we
will investigate the possibilities offered by optical (hyper)sensing and actuation to define opto-acoustic resonators
for applications in gas sensing. To be more specific, the candidate will have to design and characterize novel types
of opto-acoustic resonators with enhanced robustness, in one of the photonic platforms from imec.
Optical and acoustic ring resonators to be combined for sensing applications
For this purpose, the student will
1. design and model the device analytically and numerically in FEM packages (COMSOL or ANSYS) for which
previous experience is wished for but definitely not required
2. lay-out the structures to make these processable
3. fully characterize the device (electrically, optically, acoustically)
4. use the processed devices as sensor or propose an enhanced design improving on the simulated sensing
performance of the first one
Through this work, the student will learn about state-of-the-art optical sensing of acoustic waves while enhancing
his/her engineering skills and learning simulation tools and characterization facilities.
Type of project: Thesis project
Degree: Master in Science or Master in Engineering majoring in physics, electronics
Responsible scientists:
For further information or for application, please contact Bruno Figeys (Bruno.Figeys@imec.be) and Xavier
Rottenberg (Xavier.Rottenberg.imec.be).
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70
MEMS-based compass: optimization of magnetometers enabled by MEMS
resonators
MEMS-based inertial measurement units (IMUs) have gained the status of mainstream commodities for consumer
electronics in the past years and find use in guidance, navigation, attitude control, smart metering, etc.. From the
simple 1-axis accelerometer, IMUs have evolved to 3 degrees-of-freedom (DOFs) acceleration sensing and
eventually to 6DOFs modules, including angular rate sensors. In particular, the synergy of multi-DOF inertial
sensors turned out to be key in improving the navigation capabilities of inertial modules. This trend of adding more
functionality to existing units goes on. On-chip magnetometer, barometer, thermometer, electronic nose and
clocks, are seen as further improvements of current IMUs, but moreover to enable novel smart multi-sensor units.
The goal of this master thesis is to characterize and compare the performance of different MEMS resonators
fabricated at imec in the Poly-SiGe MEMS platform that were designed to be used in magnetometers for compass
applications. You will further build a magnetometer system around at least one of these resonators selected for his
promising capabilities.
Different standard and novel types of resonant MEMS devices have been designed and fabricated for compass
applications. One of these, the Xylophone Bar Magnetometer (XBM), is shown in the figure below. It consists of a
free-free beam supported at the nodal points of its fundamental transverse mode of vibration. For its function, it is
excited via its nodal supports with a sinusoidal current at its natural vibration frequency. In the presence of an
external B, this current results in a sinusoidal Lorentz force (F) that puts the XBM in vibration. The vibrations
amplitude, in direct relation with the magnetic field intensity, is capacitively measured through a set of electrodes
placed under the beam.
Microphotograph of a Xylophone Bar Magnetometer (XBM) fabricated in Poly-SiGe MEMS technology at imec
For this thesis, you will have to:
- understand the working principle of each type of MEMS magnetometer and derive simple models for each
of these, i.e. analytical, numerical (COMSOL) and equivalent circuit,
- perform experimental characterization of produced devices, first with a Laser Doppler Vibrometer (LDV)
to observe vibration modes and identify the working frequencies, then with a 2-port network analyzer to
assess the electrical response of the resonators,
- update the model with the experimental data,
- compare the performance of each type of magnetometer,
- breadboard a dedicated circuit around a selected resonator to allow an integrated magnetic field
measurement.
Type of project: Thesis project
Degree: Master in Science or Master in Engineering majoring in physics, electronics
Responsible scientists:
For further information or for application, please contact Veronique Rochus (Veronique.Rochus@imec.be) and
Xavier Rottenberg (Xavier.Rottenberg.imec.be).
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71
Cost-effective photonic sensor for point-of-care medical diagnostics
In the past decade, physicians’ insight in the biomolecular causes of several diseases has grown tremendously.
Although this knowledge provides a very rich basis for fast and accurate medical diagnoses, it is currently only
applied at limited scale due to a lack of efficient methods to measure biologically relevant molecules in a urine or
blood sample from a patient. Where nowadays an analysis can take weeks, and can only be done in big clinical
laboratories, one ideally would want a system that can perform molecular diagnostics in real-time at the point-ofcare, e.g. at the patient’s bed-side.
Integrated photonic sensors lately receive a lot of attention for this type of applications. Indeed, in analogy to
electronic integrated circuits, photonic integrated circuits combine and miniaturize optical functions, such as (laser)
sources, detectors and filters, on a chip. Such photonic integrated circuits, mass manufactured at high quality using
optical lithography and etching, are already commonly applied in optical fiber communication networks that form
the basis of the internet.
Imec has developed a state-of-the-art technology in its CMOS-fab that enables the fabrication of integrated
photonic chips on a large scale in a cost-effective way. Using this technology, sensors for biomedical applications
have already been developed. They consist of on-chip waveguide interferometers or resonators. When
biochemical receptor molecules placed on the waveguide walls selectively capture target molecules, a phase shift is
induced in the light propagating through the waveguide. This phase shift then results in a measurable output change
of the interferometer or resonator. Using this technique, sensor chips with hundreds of different sensors have
been demonstrated. However, although the sensor chips can be fabricated cost-effectively, the interface
instrumentation, that interrogates the chip, is still prohibitively expensive (in the order of 100 000 euro) for
application at the bed-side of the patient. Therefore, there is a strong drive towards developing low cost
interrogation instrumentation.
Recent progress in imec’s technology enables just that, and now you have the opportunity to contribute to the
development of a new prototype instrument! The goal is straightforward, but challenging at the same time: develop
a photonic chip and instrument that allows biomolecular measurements, but at a fraction of the instrument cost.
Your challenges:
1. design a cost-effective interrogation scheme
2. design your own photonic chip
3. build a prototype instrument
4. characterize your photonic chip
5. perform a proof-of-concept measurement of your chip with the instrument you built
Your gains:
1. work in a multidisciplinary team
2. acquire hands-on experience with optical components
3. learn about on-chip photonics, such as waveguiding and interference
4. learn lithographic mask design for a CMOS-fab
Type of project: Thesis project
Degree: Master in Engineering majoring in electronics, photonics, applied physics or related
Responsible scientist:
For further information or for application, please contact Tom Claes (Tom.Claes@imec.be).
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IX.
Microelectronics Design
Visualisatie van DfX analyse feedback in een elektronisch ontwerp
Onder Design-for-X worden alle ontwerpaspecten van een elektronisch product verstaan die buiten het zuiver
elektrische ontwerp vallen. Hieronder vallen zaken zoals de maakbaarheid van het product (DfManufacturing), de
bedrijfszekerheid (DfReliability), de testbaarheid (DfTest), enz.
Het eindwerk kadert binnen de onderzoeksactiviteiten van het EDM programma van imec (www.edmp.be) dat zich
richt op het uitwerken van ontwerp- en kwalificatierichtlijnen voor Printed Board Assemblies (PBA) voor de
Vlaamse elektronica-industrie en elektronica-implementatoren. Binnen dit programma is er een PBA simulatie tool
ontwikkeld (Visual studio 2010 – visual basic & excel integratie) die analyses doet op elektronische ontwerpen. De
resultaten van deze tool worden nu in Excel voorgesteld aan de gebruikers.
Het eindwerk richt zich op het grafisch visualiseren van de gerichte analyse feedback naar de gebruiker:
• Studie van de gebruikte CAD formaten en selectie van een formaat. Dit formaat wordt nadien gebruikt om
data van een elektronisch ontwerp in te lezen en te visualiseren.
• Importeren van de CAD Data: extraheren van gegevens en opslaan in de gebruikte datastructuur van de
PBA simulatie tool.
• Grafische visualisatie van deze CAD data.
• Visualisatie van diverse feedback gegevens
− testanalyses: defect rates, meest falende componenten
− betrouwbaarheidsgegevens
− thermische analyses
− mechanische vibratie analyses
• Optioneel: 3D voorstelling van de CAD gegevens.
• Ontwerp van een applicatie en/of custom control in MS Visual Basic 2010.
Project: Thesis project
Degree: Master in Industrial Sciences majoring in electronics-ICT
Responsible scientist:
For further information or for application, please contact Wesley Van Meensel (Wesley.VanMeensel@imec.be).
Design van een 3.3V digitale standaardcelbibliotheek in UMC 180 nm technologie
voor ruimtetoepassingen
Imec ontwikkelt in samenwerking met het Europese Ruimteagentschap ESA celbibliotheken die toelaten
stralingstolerante chips te ontwerpen in commerciële technologieën. Deze aanpak biedt als voordeel dat er niet
gekozen moet worden voor dure stralingsharde processen met beperkte functionele flexibiliteit in het analoog
domein.
Momenteel ondersteunt imec een 180 nm bibliotheek in UMC technologie. We noemen die stralingstolerante
bibliotheken DARE, een acroniem voor Design Against Radiation Effects. De bibliotheken worden gratis ter
beschikking gesteld van de Europese ruimtevaartindustrie. Op dit moment wordt er actief gebruik gemaakt van
DARE om ASICs (Application Specific Integrated Circuits) voor kritische ruimtetoepassingen te ontwikkelen.
Het uitdoven van oudere chipproductieprocessen leidt tot een grotere vraag naar cel bibliotheken die enkel met
3.3V voeding werken. Dit eindwerk heeft als doel een functioneel volledige stralingsharde standaard cel bibliotheek
te maken om de nood vanuit de ruimtevaartindustrie te beantwoorden.
Via dit ontwerpeindwerk worden de studenten vertrouwd met het concept van stralingsharde elektronica, vanuit
zowel digitaal als analoog standpunt. Eerst krijgen ze inzicht in de werking en de transistorimplementatie van de
Master Thesis/Internship Topics 2013-2014
73
essentiële basisblokken van digitaal chipontwerp (latch, flipflop, adder, exor...). De extreme condities (temperatuur,
straling...) in de ruimte vragen een grondige verificatie van elke basiscel. Hiervoor doen we beroep op
gespecialiseerde CAD software, waarmee de studenten stap voor stap vertrouwd worden gemaakt.
De figuur toont de verschillende ontwerpaspecten van een typisch basisblok. Elk basisblok wordt op
transistorniveau uitvoerig gesimuleerd om de performantie onder veranderende produktie- en omgevingsfactoren
te analyseren en bij te sturen. Het gefinaliseerde ontwerp wordt daarna volledig uitgetekend in een ‘layout’ en met
extractie- en karakterisatiesoftware worden de nodige formaten gegenereerd om de cel voor te stellen in
verschillende stappen van het digitale ontwerpproces (synthese, timing analyise, layout...) .
Dit eindwerk vereist toegang tot Cadence ontwerptools en de Calibre verificatie tools. Dit kan gebeuren door
regelmatig naar imec (Leuven) te komen of door remote in te loggen op het imec-netwerk. Een constante
communicatie met de begeleider op imec is vereist.
Software tools (state-of-the-art):
• Cadence: Virtuoso, Composer, Analog Design Environment, Ocean, Spectre simulator
• Metor Graphics: Calibre (DRC, LVS, LPE)
• Linux/Unix
Tijdsindeling: 10% technologie, 50% ontwerp/simulatie, 30% layout., 10% scripting
Project: Thesis project
Degree: Master in Industrial Sciences majoring in (micro)electronics
Responsible scientist:
For further information or for application, please contact Geert Thys (Geert.Thys@imec.be).
Master Thesis/Internship Topics 2013-2014
74
Ontwerp van radiatie-tolerante flipflopsvoor imec’s DARE bibliotheken
Via dit ontwerpeindwerk worden studenten vertrouwd met CMOS ontwerp op transistor niveau. Concreet
woden radiatie-tolerante flipflops ontworpen.
Imec ontwikkelt in samenwerking met de Europese ruimtevaartorganisatie (ESA) standaardcelbibliotheken die
gebruikt worden in radiatie-tolerante chips. In de ruimte zijn chips onderhevig aan verschillende soorten
hoogenergetische straling die hun oorsprong vinden in de kosmische straling. Het betreft deeltjes (alfa, ionen,
neutronen etc.); niet elektromagnetische straling.
Momenteel ondersteunt imec celbibliotheken in 180 nm CMOS technologie van UMC (Taiwan). We noemen die
bibliotheken DARE, een acroniem voor Design Against Radiation Effects. De bibliotheken staan ter beschikking van
de Europese ruimtevaartindustrie en worden vandaag actief aangewend in ASIC ontwikkeling.
Wanneer een energetisch deeltje door een CMOS chip ‘vliegt’, wordt in het silicium een hoeveelheid lading achter
gelaten. Deze stoorlading kan in de elektronische schakeling leiden tot een niet-destructieve functionele fout. De
chip dient dan zodanig ontworpen te worden, dat hij ongevoelig wordt voor de stoorlading.
De stoorlading kan resulteren in verschillende elektrische fenomenen. Flipflops zijn bijvoorbeeld onderhevig aan
SEU (Single Event Upset). De inslag veroorzaakt een niet gewilde toestandsverandering van de flipflop. Klassieke
CMOS flipflops zijn zeer gevoelig. Deeltjes met een beperkte energie kunnen reeds een SEU veroorzaken. De HIT
flipflop (Heavy Ion Tolerant), die
we nu gebruiken in onze radiatietolerante bibliotheken, heeft een
architectuur die robuuster is wat
SEU betreft. Uiteraard is het
transistorschema van de flipflop
complexer. De cel wordt dus
groter en verbruikt meer. Een
alternatief is de DICE (Dual
Interlocked
Storage
Cell)
architectuur. DICE heeft een aantal
bijkomende voordelen t.o.v. de
HIT cel.
De opzet van de thesis bestaat erin
analoge simulaties op te zetten om
de SEU-robuustheid van flipflops te
bepalen
in
verschillende
technologieën
(UMC
180nm,
XFAB 180nm, UMC 65nm).
Vervolgens kunnen verschillende
SEU-tolerante flipfloptopologieën
met elkaar worden vergeleken, waarbij ook andere parameters (vermogen, oppervlakte, snelheid) in rekening
dienen gebracht. De meest performante SEU flipflop kandidaten kunnen daarna uitgetekend worden (layout) en
gekarakeriseerd, zodat de nieuwe cellen kunnen worden opgenomen in de bibliotheek. Ontwerp van een testchip
is mogelijk afhankelijk van het tijdsbestek.
Dit eindwerk vereist toegang tot Cadence en Mentor Graphics ontwerp-tools. Regelmatige aanwezigheid op imec
voor ontwerpondersteuning en het gebruik van de specifieke software tools is aangeraden. Remote inlogen op het
imec netwerk biedt de aanvullende mogelijkheid om van thuis uit te werken.
Software tools (state-of-the-art) en omgeving:
• Cadence: Virtuoso (Schematic Composer + Layout), Analog Design Environment, Spectre simulator
• Mentor Graphics: Calibre (DRC, LVS, LPE)
• Linux/Unix
Tijdsindeling: 10% technologie, 60% ontwerp/simulatie, 30% layout.
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Project: Thesis project
Degree: Master in Industrial Sciences majoring in (micro)electronics
Responsible scientist:
For further information or for application, please contact Geert Thys (Geert.Thys@imec.be).
Design prediction tool development for solder joint reliability for printed board
assemblies, including the flexibility of components/boards
The working heart of any electronic system is the (green-coloured) printed circuit board with many electronic
components assembled to it. The material which makes the electrical, but also the mechanical and thermal
connection between the component and the board is tin (Sn) based solder. This material is suitable thanks to its
low melting temperature allowing to make the connection at acceptable temperatures for board and components.
Solder is also a very ductile material, meaning having a low yield stress, allowing to compensate for a thermal
expansion mismatch between the component and the board. Where this ductility minimises the stress in board
and component in a positive way, it becomes vulnerable for mechanical fatigue fracture occurring under repeated
deformations. A proper design and good knowledge of life time for each component helps to avoid these solder
joint failures. In the recent years, poor solder joint life time has resulted in major field returns for laptop
computers, gaming consoles and even failing electronics in cars.
In this work, available Finite Element Models for a wide range of components will be used to estimate the life time
of the solder connections. The student will perform parametric studies with as final goal to define a spreadsheet
based design tool. This tool should be able to predict life time for a component as function of several parameters
such as chip size, component size, solder joint height, board stiffness, temperature cycling conditions etc. This
study also allows investigating the mechanical impact zone of every component, in particular valid for large
components which could damage neighbouring smaller components. Verification of the tool is done through
available internal testing and from well-reported data in literature.
Project: Internship or thesis project of minimum 6 months
Degree: Master in Industrial Sciences or Master in Science or Master in Engineering majoring in mechanics, material
science, physics. Knowledge in FEM and elasticity theory are a benefit, but not required to perform the thesis
study.
Responsible scientist:
For further information or for application, please contact Bart Vandevelde (Bart.Vandevelde@imec.be).
Master Thesis/Internship Topics 2013-2014
76
X.
NERF
Introduction
Imec, VIB (Flanders’ leading life science institute), and the Leuven University have set up a joint basic research
initiative to unravel the neuronal circuitry of the human brain: Neuroelectronics Research Flanders (NERF).
Supported by the Flemish Government, NERF looks into fundamental neuroscientific questions through
collaborative, interdisciplinary research combining nanoelectronics with neurobiology. It intends to push the
boundaries of science, by zooming in on the working of neurons at an unprecedented level of detail. In the long
run, NERF will generate new insights in the functional mapping of the brain, as well as research methodologies and
technologies for medical applications, i.e. diagnostics and treatment of disorders of the central and peripheral
nervous system. The NERF labs are located at the imec premises. Read more: http://www.nerf.be/.
Design and construction of automated environments to study spatial memory
function in rodents
The Kloosterman laboratory at the NeuroElectronics Research Flanders (NERF) in Imec studies how neural
circuits and systems in the brain process and store information. For this, we monitor the activity of tens to
hundreds of neurons simultaneously as rodents (rats or mice) perform a variety of spatial memory tasks. In one
example, rats learn to associate a specific odour cue with a goal location where a small reward can be retrieved.
The behavioural testing environment in this case features odour delivery devices and automated doors that are
embedded in a multi-arm maze. The aim of this project is to design and build modular and re-usable devices to
support complex behavioural experiments for the study of spatial memory function. The project involves
embedded system design, 3D computer-aided design (CAD), rapid prototyping and printed circuit board (PCB)
design. We are looking for a candidate with a strong background in robotics, electrical engineering or mechanical
engineering and an interest in neuroscience. The ideal candidate is able to work independently and does not shy
away from challenges.
Type of project: Thesis or internship project of 6 up to 12 months
Degree: Master in Science or Master in Engineering majoring in robotics, mechanical engineering, electrical
engineering, biomedical engineering or similar field.
Responsible scientist:
For further information or for application, please contact Fabian Kloosterman (Fabian.Kloosterman@nerf.be).
Closed-loop real-time read out and control of memory processing in behaving rats
Understanding how new memories are formed and used to guide actions by our brain is a major challenge in
neuroscience. Spatial memory processing in rodents can be used as a model to investigate memory processing
dynamics. In this project we use large-scale in vivo electrophysiological recordings combined with behaviour assays
to study memory processing. In particular, we aim to decode memory-related replay of experience-dependent
neural activity patterns at a millisecond timescale. By combining decoding the activity in a real-time fashion with
online electrical or optical feedback stimulation of the brain, we can selectively interfere with ongoing memory
processing. The rationale of this closed-loop system is to provide experimental evidence for the role of replayed
activity patterns in memory consolidation and retrieval.
Master Thesis/Internship Topics 2013-2014
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Our ideal candidate will have a strong background in computer science or electrical/biomedical engineering and a
vivid interest in neuroscience. The candidate will be involved in the implementation of signal processing tools and
real-time encoding/decoding algorithms for data streams coming from an array of electrodes implanted in a rat
brain. Other activities include fabrication of brain implants for small animals and electrophysiological recordings.
Experience with Python (NumPy/SciPy), C/C++ or scientific computing in general is an advantage.
Type of project: Thesis or internship project of 6 up to 12 months
Degree: Master in Science or Master in Engineering majoring in computer science, electrical engineering,
biomedical engineering or similar field.
Responsible scientists:
For further information or for application, please contact Fabian Kloosterman (Fabian.Kloosterman@nerf.be) and
Davide Ciliberti (Davide.Ciliberti@nerf.be).
Scale-space based segmentation and identification of cells in microscopic images
In order to better measure cell’s response to different chemical or mechanical stimuli robust quantification of the
cell spatiotemporal organization is required. Accurate identification of individual cellular phenotypes can be
obtained by combining automated microscopic acquisition with extensive morphological feature extraction and
data mining strategies. The topic will include research into innovative high-performance algorithms for
segmentation of large 2D and 3D microscopic images. The work will be directed towards implementation of
automated protocols requiring minimal user interaction and allowing parallel processing of the acquired data. Two
concrete applications will be addressed: (i) measurement of glial cell activity in functional in vivo confocal or twophoton microscopic images and (ii) classification of white blood cells from live microscopic images. Specifically the
student will explore utility of scale space approaches based on successive spatial smoothing and convolution (for
example SIFT or SURF) for cell type identification. We are looking for a candidate with strong background in signal
processing or skills in programming. Experience in Java or C# will be preferred.
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Type of project: Thesis or internship project of 3 up to 6 months
Degree: Master in Science or Master in Engineering majoring in computer science
Responsible scientist:
For further information or for application, please contact Dimiter Prodanov (Dimiter.Prodanov@imec.be).
Optogenetic dissection of dopamine function for learning from reward and
punishment
One form of learning, commonly observed in humans and animals, relies on the reinforcing effect of rewarding or
aversive experience. As a result of such learning, sensory cues, behavioral responses or specific actions become
associated with positive or negative values, which is critical for seeking resources and avoiding danger. Previous
research in animals and humans has well established that neurons which use dopamine as their neurotransmitter
are key players in reward processing. These dopamine neurons mainly reside in the midbrain ventral tegmental
area (VTA) and substantia nigra pars compacta (SNc). They are activated by unexpected rewards and sensory cues
predicting future rewards. When predicted rewards are omitted they are suppressed. Thus, dopamine neurons
seem to encode the discrepancy between predicted and actual reward, also called reward prediction errors. Based
on formal theories of reinforcement learning, it has been proposed that dopamine acts as a teaching signal to
mediate learning from reward.
While the function of prediction errors has been intensively studied, the function of cue-evoked dopamine
responses has received much less attention. The goal of this project is to evaluate the behavioral relevance of cueevoked dopamine activity in awake, behaving mice, using optogenetic activation and inhibition techniques. Mice will
be trained on an olfactory conditioning task, in which different odorants are associated with reward. For selective
manipulation of dopamine neurons in vivo, optical fibers will be implanted into the brain. The master student is
expected to perform and analyze behavioral/optogenetic experiments and, depending on interest, may also acquire
mouse surgery skills. If you are interested in the project and have any questions, please do not hesitate to contact
the responsible scientist, Dr. Sebastian Haesler.
Type of project: Thesis project with internship of up to 6 months
Degree: Master in Science majoring in biology, neuroscience, psychology
Responsible scientist:
For further information or for application, please contact Sebastian Haesler (Sebastian.Haesler@nerf.be).
Using superparamagnetic nanoparticles as force actuators in cells and tissues
Nanoparticles offer exciting opportunities for the development of new technologies at the interfaces between
chemistry, physics and biology. Magnetic nanoparticles are a special class of nanoparticles which can be manipulated
using magnetic fields. Magnetic nanoparticles have provided much promise for a number of applications ranging
from targeted cell delivery, magnetic resonance imaging contrast enhancement, and targeted cancer therapy in the
form of local hyperthermia. The goal of this project is to evaluate the use of superparamagentic nanoparticles as
force actuators in cells and tissue. The techniques involved are standard molecular biology (cloning and preparation
of plasmid DNA), cell culture (human cell lines and transfection) and conventional (confocal) and advanced
microscopy such as transmission electron microscopy (in collaboration). If you are interested in the project and
have any questions, please do not hesitate to contact the responsible scientist, Dr. Sebastian Haesler.
Type of project: Thesis project with internship of up to 6 months
Master Thesis/Internship Topics 2013-2014
79
Degree: Master in Science majoring in (bio)physics, biomedical engineering, biology
Responsible scientist:
For further information or for application, please contact Sebastian Haesler (Sebastian.Haesler@nerf.be).
Design, prototyping and testing of miniaturized brain implants
The Kloosterman laboratory at the Neuro-Electronics Research Flanders (NERF) studies how neural circuits and
systems in the brain process and store information. For this, we monitor the activity of tens to hundreds of
neurons simultaneously as rodents (rats or mice) behave freely. Previously, we have used custom designed brain
implants that carry an array of wire electrodes. In collaboration with the Bioelectronic Systems group at Imec, new
silicon-based neural probes have been developed that will allow us to record from a larger number of neurons in a
wide network of brain regions. These probes will be used in combination with optical stimulation techniques in
order to perturb activity of certain types of cells to better understand their role in memory processing. The aim of
this project is to design and build prototypes of novel brain implants for rats that combine multiple wire electrodes
(tetrodes) and silicon neural probes for recording of neural activity and optical fibers for stimulation. The project
will be conducted as a joint effort of two research groups at NERF and Imec and involves 3D computer-aided
design (CAD) and rapid prototyping. Experience in printed circuit board (PCB) or embedded system design is an
asset. Prototypes will be characterized mechanically and eventually tested in experiments in vivo. We are looking
for a candidate with strong background and skills in biomedical, mechanical or electrical engineering and with
interest in neuroscience.
Master Thesis/Internship Topics 2013-2014
80
Type of project: Thesis or internship project of 6 months
Degree: Master in Science or Master in Mechanic Engineering, Electric Engineering, Biomedical Engineering
Responsible scientists:
For further information or for application, please contact Fabian Kloosterman (Fabian.Kloosterman@nerf.be) and
Dimiter Prodanov (Dimiter.Prodanov@imec.be).
Inferring population network dynamics from cellular imaging data in behaving
animals
One of the major challenges in systems neuroscience is the development of robust algorithms for understanding
the complex dynamics of neural activity during behavior. Our lab uses the mouse and various imaging and genetic
tools to study visual processing by large cortical networks in awake behaving animals. In the course of our imaging
experiments, we generate terabytes of high-speed cellular-level calcium imaging data that capture the activity of
large neuronal populations in visual cortex in the context of a virtual-reality based spatial navigation assay. To
unleash the true potential of these experimental assays, we need to develop robust probabilistic models to infer
neural spiking activity from calcium fluorescence signals, as well models of the underlying network dynamics. To
help us achieve this aim, we seek highly motivated Master’s students with strong quantitative skills, expertise the
analysis of biological signals or imaging data, and a genuine interest in making a significant contribution to
neuroscience. Our team at NERF offers a highly interdisciplinary research environment and state-of-the-art labs
and computing infrastructure. This is an ideal position for prospective students from the physical sciences seeking
to make the jump to brain research. Fluency in MATLAB, Python or/and other data-driven programming languages
is required.
Type of project: Thesis or internship project of 6 months
Degree: Master in Science or Master in (Electrical) Engineering majoring in physics, applied mathematics, computer
science, signal and imaging processing
Responsible scientist:
For further information or for application, please contact Vincent Bonin (Vincent.Bonin@nerf.be).
Master Thesis/Internship Topics 2013-2014
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Master Thesis/Internship Topics 2013-2014
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