ARTICLE IN PRESS
INTEGRATION, the VLSI journal 36 (2003) 191–209
a,
b
b a
Dipartimento di Ingegneria dell’Informazione (DII), Universit
" b
Dipartimento Elettrico Elettronico e Sistemistico (DEES), Universit
"
I-95125 Catania, Italy
Received 7 March 2003; received in revised form 2 September 2003; accepted 2 September 2003
Abstract
In this paper, the low-voltage CML D-latch topology is analyzed and compared to the traditional implementation to evaluate its speed potential and power efficiency, which are crucial aspects in current applications. To this end, an analytical delay model is first derived and then used to optimize its speed performance and understand its power-delay interdependence. The delay model, based on the approach proposed by Alioto and Palumbo (IEEE Trans. Circuits Systems I 46(11) (1999) 1330; IEEE Trans. Circuits and Systems II 47(5) (2000) 452), leads to simple expressions that are suitable for pencil-and-paper evaluations. The accuracy of the expressions obtained is tested by comparison to SPICE simulations, by using a bipolar process whose npn transistor has a transition frequency of 20 GHz. The delay expressions derived are used to design and compare the low-voltage and the traditional D-latch both in terms of delay and power-delay tradeoff, by considering a high-performance and a low-power consumption design target.
The analytical comparison carried out is general, since it does not depend on the specific bipolar process considered. Analysis shows that the low-voltage D-latch topology does not necessarily allow for a power saving or a better power efficiency, and applications where this topology exhibits some advantage over the traditional implementation are identified.
r 2003 Elsevier B.V. All rights reserved.
Keywords: Bipolar; High speed; Latch; Current mode logic; Low voltage
*Corresponding author. Tel.: +39-0577-234632; fax: +39-0577-233602.
E-mail addresses: malioto@dii.unisi.it (M. Alioto), rmita@dees.unict.it (R. Mita), gpalumbo@dees.unict.it
(G. Palumbo).
0167-9260/$ - see front matter r 2003 Elsevier B.V. All rights reserved.
doi:10.1016/j.vlsi.2003.09.001

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192 M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209
1. Introduction
The continued growth of market of mobile and satellite communication systems, as well as multiple-Gb/s optic fiber systems, demands for the implementation of high-performance CML/
ECL circuits in bipolar technology
[1–20] . In such applications, the D-latch gate is the basic circuit
used to implement a number of fundamental blocks such as prescalers, frequency dividers and sequential logic circuits
[3–6,8,13,14,17] , whose performance strongly depends on D-latch gate
performance.
The traditional implementation of CML/ECL D-latch is based on stacked emitter-coupled pairs of bipolar transistors, as shown in
Fig. 1 . To keep its speed performance as high as possible,
transistor operation in the linear region has to be ensured by using a high enough supply voltage, according to the number of stacked base-emitter junctions. In addition, a high bias current must be used to improve the speed performance, thereby determining a high static power dissipation that reduces the battery lifetime in portable devices and limits the feasibility of complex circuits.
To reduce the static power consumption, various attempts have been carried out to reduce the supply voltage by decreasing the number of base-emitter junctions between each input and ground
[21–23]
. Of these D-latch topologies, that reported in
[21]
seems to be the most promising since it allows the lowest supply voltage, and in the following it will be accordingly referred as the lowvoltage topology.
V out
C
L
R
C
D Q3 Q4 D Q5 Q6
CK Q1 Q2 CK
I
B
-V
EE
Fig. 1. Traditional D-latch topology.
R
C
C
L
V out

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M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 193
Recently, the low-voltage D-latch topology was experimentally tested to prove its suitability for high-performance applications
[24] . However, no analysis was carried out either in terms of its
speed potential or of power efficiency, therefore it is not understood whether the low-voltage feature actually allows an improvement in power dissipation, delay or their tradeoff. In this paper, these aspects are investigated by comparing performance of low-voltage topology to that of the traditional implementation. The outcome of the comparison cannot easily be predicted relying on intuition, since power consumption and delay also depend on bias current and transistor parasitic capacitances, other than supply voltage.
In this paper, an analytical delay model is first introduced and then applied to design lowvoltage D-latch and consciously manage the power-delay tradeoff, according to the methodology proposed in
[25,26] . The model is validated by means of SPICE simulations on a bipolar process
whose npn transistor has a transition frequency of 20 GHz. By using the model developed, the low-voltage D-latch is then compared to the traditional topology in terms of delay, power dissipation and power-delay product, assuming a high-performance or low-power consumption design target. Being based on an analytical approach, the comparison is independent of the technology used and hence allows one to understand in a general way which cases the low-voltage
D-latch exhibits some advantage in. The results show that the supply voltage reduction allowed by the low-voltage circuit does not always lead to a power reduction or a more efficient tradeoff with speed, and cases where an advantage is achieved are dealt with.
In Section 2, a brief discussion on the behavior of the traditional and low-voltage D-latch is provided. The delay model of both topologies is dealt with in Section 3, where the comparison to SPICE simulations is discussed to validate the model. Criteria to optimally design the topologies considered are the subject of Section 4, where a comparison in terms of speed and power-speed tradeoff is carried out by considering both a high-speed and a low-power design.
Conclusions are included in Section 5 and, finally, two Appendices are introduced to improve the readability.
2. Traditional and low-voltage D-latch topologies
2.1. Traditional D-latch topology
The traditional D-latch circuit, shown in
Fig. 1
, consists of an emitter-coupled pair Q1–Q2 driven by the input CK ; that alternatively activates the transistor pair Q3–Q4 or Q5–Q6. When
CK is high, Q2 is OFF, hence the bias current I
B flows through Q1 and is then steered by transistors Q3–Q4 according to the value of input D : Being the output set by input D ; the latch is said to be in the transparent state. When CK is low, the bias current I
B flows through transistor
Q2 and cross-coupled transistors Q5–Q6, that store the previous output value by virtue of their positive-feedback connection, and the latch is in the hold mode. Load resistances R
C convert the bias current steered by transistors to the differential output voltage V out
V out
; and the loading effects of subsequent gates and wire capacitance are accounted for by a load capacitance, C
L
:
Since the differential output voltage, V out high level V
OH
¼ R
C
I
B when I
B
V out
; has a low level equal to V
OL
¼ R
C
I
B and a is steered to left- or right-side resistance, respectively, the logic

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194 M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 swing is equal to
[27]
V
SWING
¼ V
OH
V
OL
¼ 2 R
C
I
B
: ð 1 Þ
As discussed in
[22]
, the minimum supply voltage is limited by the drop voltage across the current mirror implementing the current source I
B
; and two V
BE drops. The resulting minimum supply voltage of the traditional D-latch topology, V
DD ; min ; TR
; is about 2 V.
2.2. Low-voltage D-Latch topology
The low-voltage D-latch topology, shown in
Fig. 2
, is made up of the two emitter-coupled pairs
Q1–Q2 and Q3–Q4, biased with two current sources I
B
= 2 that are implemented by current mirrors. The transistor pair Q1–Q2 is driven by the differential input D ; while the cross-coupled pair Q3–Q4 implements the memory element.
Depending on the value of the differential input CK ; one of the two transistor pairs is alternatively deactivated by transistors Q5 and Q6, that are assumed to have an emitter area A
E5 ; 6 greater than area A
E1 ; 2 ; 3 ; 4 of the other transistors by a factor N (i.e., N ¼ A
E5 ; 6
= A
E1 ; 2 ; 3 ; 4
). When
CK is low, transistor Q6 is OFF and the cross-coupled pair Q3–Q4 holds the previous logic value thanks to the positive feedback, and the latch is in the hold state. When CK is high, transistor Q5 is OFF and Q6 is ON, thus deactivating the cross-coupled pair Q3–Q4; hence, the output is set equal to input D by the transistor pair Q1–Q2, and the latch is in the transparent state.
As demonstrated in Appendix A, the logic swing of the low-voltage D-latch is given by
V
SWING
¼ R
C
I
B
N
1 þ N
; ð 2 Þ which is lower than that of the traditional D-latch in (1) by a factor greater than two for an assigned value of R
C
I
B
: Hence, the low-voltage topology has a lower noise margin than that
C
L R
C
R
C
C
L
CK
CK
D Q1
Q5
Q2 D
Q6
Q3 Q4
I
B
2
I
B
2
-V
EE -V
EE
Fig. 2. Low-voltage D-latch topology.
V out

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M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 195 of the traditional circuit for a given value of R
C
I
B
; and to avoid an excessive noise margin degradation from (2) parameter N has to be chosen as high as possible
[24] . However, a high value
of N leads to a high emitter area of transistors Q5–Q6, thus increasing the input capacitance seen from the input CK : As suggested in
[21]
, a good compromise between the opposite requirements is to set N ¼ 2 : Since logic swing and parameter N are assigned before design (with the former set from system considerations), from (2) the product R
C
I
B is also a constant in the design.
Since the supply voltage must guarantee a drop voltage across the current mirror and only one
V
BE drop, the minimum supply voltage allowed V
DD ; min ; LV is equal to 1.1 V
[24] . Therefore, the
low-voltage topology allows for a 45% reduction of supply voltage compared to the traditional
D-latch.
3. D-Latch delay model
In this section, an analytical model of the low-voltage CML D-latch delay is developed according to the methodology proposed in
[26] , that is based on a circuit linearization and single-
pole approximation. Moreover, a brief review of the traditional D-latch delay model is included.
In general, the D-latch delay is described by two parameters, the CK 2 Q and the D 2 Q delay, that are evaluated when CK switches with D being kept constant, and when D switches with CK being kept constant, respectively
[28]
. However, in practical cases, such as in frequency dividers or dual-modulus prescalers, the speed performance is limited by the delay associated with input CK :
As a consequence, in the following we focus on the CK 2 Q delay to describe the D-latch speed performance, while the D 2 Q delay is briefly dealt with in Appendix B for the sake of completeness.
3.1. Low-voltage D-Latch CK–Q delay
Let us consider the output transition that occurs when the D-latch goes from the hold mode to the transparent mode due to a low-to-high transition of the input CK (obviously D is assumed opposite to the previously stored value, otherwise no transition takes place). From a circuit point of view, the clock signal goes high and abruptly activates the transistor pair Q1–Q2, that can be thought of as a simple CML inverter. At the same time, transistors Q3–Q4 are deactivated, and hence they affect the transient response only by their parasitic capacitances. As a consequence, the circuit can be schematized as the CML inverter Q1–Q2 loaded by an equivalent capacitance C eq at the output nodes equal to capacitive contributions associated with transistors Q3–Q4 in parallel to the load capacitance C
L
:
To evaluate the propagation delay of the equivalent inverter loaded by the capacitance C eq
; we apply the model developed in
[29]
, that represents transistors Q1–Q2 by the linearized circuit which is topologically equal to the bipolar transistor small-signal model. Moreover, the circuit is symmetrical and differential operation is assumed, thus we can limit analysis to the half-circuit model shown in
Fig. 3 .
In the equivalent circuit in
Fig. 3
, the transistor transconductance g m and input resistance r p are those of the small-signal model I
B
= 4 V
T and 2 b
F
V
T
= I
B
; respectively, while resistances r are resistive parasitics. The base-emitter capacitance C be b
; r e
; and r c is due to the diffusion capacitance
;

196 r b
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M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209
C bcx
C bci r c
+
-
V in r π C be g m
V be
C cs
C eq
R
C
V out r e
Fig. 3. Equivalent linearized circuit of the D-latch when the clock signal CK switches.
C
D
¼ 2 t
(i.e., C be
F
= R
C
¼ C
D
(where t
F
þ C je is the transistor transit time
[30]
) and to the junction capacitance
). Moreover, the base-collector capacitance, C bc
C je
; is split into an intrinsic
C bci
¼ X cjc
C bc
; and extrinsic C bcx
¼ ð 1 X cjc
Þ C bc
Finally, the collector-substrate capacitance C cs capacitances C j part, where X cjc is a parameter in the range [0, 1].
is only a junction capacitance. The junction considered are linearized by multiplying the zero-bias value, C j0
; by a coefficient
K j
; that depends on the built-in potential and the grading coefficient of the junction, as well as the maximum and minimum voltages across the junction, as shown in
[29] .
Assuming a dominant pole behavior with a time constant t that can be evaluated by using the open-circuit time constant method
[31–33]
, the CK 2 Q propagation delay of the low-voltage
D-latch t
PD ; LV CK results in t
PD ; LV CK
E 0 : 69 fð r e
þ r b
Þ C be
þ r b
C bci
½ 1 þ g m
ð r c
þ R
C
Þ
þ ð r c
þ R
C
Þð C bci
þ C bcx
þ C cs
Þ þ R
C
C eq g ð 3 Þ that was obtained by assuming term r p much higher than r b relationship (3), the equivalent capacitance C eq
þ r e
; N
X
2 and r e is the sum of load capacitance C
L
5 1 = g m
: In and the parasitic capacitance of Q3–Q4 that accounts for the collector-substrate contribution their bases (equal to C bcx
ð 1 þ g m
R
C
Þ ; as demonstrated in
[25]
).
C cs and that seen by
C eq
¼ ½ C bcx
ð 1 þ g m
R
C
Þ þ C cs
þ C
L
: ð 4 Þ
By substituting (4) into (3), and highlighting its dependence on bias current I
B of V
SWING and N ; the low-voltage D-Latch CK 2 Q delay becomes for assigned values t
PD ; LV CK
¼ a
LV CK
I
B
þ b
LV CK
I
B
þ c
LV CK
; ð 5 Þ where coefficients a
LV CK
; b
LV CK and c
LV CK process parameters and the supply voltage V
DD
; reported in
Table 1
, depend on parameter V
SWING
(that only affects the collector-substrate capacitance).
;

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M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 197
Table 1
Coefficients of the CK 2 Q delay expression
CK 2 Q delay coefficients (low-voltage D-latch) a
LV CK
0 : 69 2 r e
þ r b
V
SWING t
F
þ r b
C bci3 ; 4
4 V
T r c b
LV CK
0 : 69 V
SWING
C
L
þ C cs3 ; 4
þ C cs1 ; 2
þ C bc1 ; 2
þ 1 þ
V
SWING
4 V
T c
LV CK
0 : 69 ð r e
þ r b
Þ C je
þ r b
C bci3 ; 4
1 þ
V
SWING
4 V
T
þ r c
ð C bc3 ; 4
þ C
C bc3 ; 4 cs3 ; 4
Þ
CK 2 Q delay coefficients (traditional D-latch) a
TR CK b c
TR CK
TR CK
0
0
0 :
:
: 69 4
34
69 ½
V
2 r e
þ
V
SWING
SWING r b
C bci1 r b
C t
F
L
þ r c
ð
þ
þ C
C r b bc1
2
C bci1
V cs3 ; 4
T
þ C
þ C cs1 r c
þ cs5 ; 6
Þ þ ð r þ r b b þ 1
þ 4 C bc3 ; 4 ; 5 ; 6 r e e
þ r b
Þ C je1
E
þ C
þ t
1
F
: 38 2 je3 ; 4
ð r e
þ r b
Þ t
F
V
SWING
þ
V
SWING
4 V
T
þ ð r c
C
þ r b
Þð C bc3 bcx5 ; 6
þ C
þ bc5 r b
C bci1 r c
4 V
Þ þ r e
T
ð C cs3
þ C cs5
Þ þ ð r b
þ 2 r c
Þ C je2
Table 2
Fundamental process parameters r c r e t
F r b
C je0
C jc0
C jso
X
CJC
I
S
6 ps
56 O
81 O
5 O
37.1 fF
26 fF
22 fF
0.23
7.4 aA
Table 3
Transistor capacitances evaluation (low-voltage latch)
C je
C cs
C bcx
C bci
44.9 fF
17.4 fF
22.1 fF
6.6 fF
The low-voltage latch model was validated by SPICE simulations on a bipolar process whose npn transistor has an f
T current I
B of 20 GHz (some process parameters are reported in
Table 2 ). The bias
ranged from 100 m A to 3 mA, the load capacitance was varied from 0 to 1 pF (i.e., approximately a fan-out of 10), assuming R
C
V
DD
I
B
¼ 500 mV and a minimum supply voltage
¼ 1 : 1 V. The capacitances obtained are evaluated in
Table 3 . As an example, the error of
predicted delay (5) with respect to simulation results is plotted versus bias current in
Fig. 4 , by

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M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 error vs bias current IB
15
10
5
0
-5
-10
-15
-20
-25
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
CL=0
IB (mA)
CL=100 fF CL=1 pF
Fig. 4. Error of the predicted CK 2 Q delay (5) with respect to simulation results versus I
B
:
Table 4
Transistor capacitances evaluation (traditional latch)
C je1 ; 2
C bcx1 ; 2
C
C
C bci1 ; 2 a cs1 a je3
C bc3 ; 4 ; 5 ; 6
C
C cs3 a je4
C bcx5 ; 6
C bci5 ; 6
C cs5 ; 6
45 fF
18.9 fF
5.7 fF
16.6 fF
48.2 fF
27.5 fF
15 fF
42.4 fF
20.1 fF
6 fF
15 fF a
These capacitances were evaluated by their small-signal expressions
[26]
.
assuming C
L
¼ 0 fF, 100 fF and 1 pF. The error found is always lower than 22%. As a consequence, the delay model is accurate enough for practical purposes.
3.2. Traditional D-latch CK–Q delay
As demonstrated in
[26]
, the CK 2 Q delay of a traditional D-latch is evaluated by linearizing the circuit and assuming a single-pole circuit behavior. The resulting delay is given by t
PD ; TR CK
¼ a
TR CK
I
B
þ b
TR CK
I
B
þ c
TR CK
; ð 6 Þ where coefficients a
TR CK
; b dependencies of parameters
TR CK a and c
TR CK
LV CK
; b
LV CK are reported in
Table 1
and have the same and c
LV CK
: The resulting capacitance values are reported in
Table 4 . As discussed in
[26] , the model error with respect to simulation results is

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M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 199 always within 20%, and typically lower, by using the same bipolar process and assuming
V
DD
¼ 2 V and R
C
I
B
¼ 250 mV.
4. Optimized design and comparison
As shown by relationships (5) and (6), the delay of both traditional and low-voltage D-latches can be expressed in the form t
PD
¼ aI
B
þ b
I
B
þ c ð 7 Þ whose minimum value t
PDop r ffiffiffi b
I
Bop
¼ a is obtained by setting the bias current to
[25–26]
ð 8 Þ and results equal to t
PDop
¼ 2 p ffiffiffiffiffi ab þ c E
2 p ffiffiffiffiffi ab ; ð 9 where coefficient c is much lower than the other terms.
1
T
By defining T
PD
PD as the ratio between the propagation delay and its optimum value t
PDop
¼ t
PD
T
PD
= t
¼
PDop p ffiffiffiffiffi ab
), it is obtained
I
2
N
þ ð 1 = I p ffiffiffiffiffi ab þ
N c
Þ þ c
E
1
2
I
N
þ
I
1
N
;
(i.e.,
ð 10 Þ
Þ where the parameter I
N is the bias current normalized to I
Bop
ð I
N
¼ I
B
= I
Bop
Þ : The expression of
T
PD is independent of the circuit and process parameters, and simply expresses the power-delay tradeoff, since normalized bias current univocally determines the static power consumption
V
DD
I
B
: Its trend is reported in
Fig. 5 , which shows that the delay can be efficiently traded for a
power reduction by reducing I
N
; since the power reduction is greater than the delay increase. For example, by setting I
N
¼ 0 : 6 (i.e., a bias current equal to 60% of the optimum value), the propagation delay is only 10% worse than the optimum value. By using
Fig. 5 , other tradeoffs
could be chosen.
In the following, these considerations are used to design the D-latch topologies considered, and then to compare their performance. More specifically, a high-performance and a low-power design target is considered.
4.1. High-performance design
Let us consider the CK 2 Q delay of the low-voltage and traditional D-latch, that is minimized by setting I
B
¼ I
Bop for both topologies. Moreover, to carry out a fair comparison, comparable logic swing values have to be considered for the topologies considered. Therefore, from (1) and
1
An error of 15% and 7% is found for unity fan-out for the low-voltage and traditional latch, respectively, by assuming the typical value currents lower than I
Bop
:
V
SWING
¼ 500 mV. In addition, this error rapidly decreases for higher fan-out and bias

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1.5
1.4
1.3
1.2
1.1
1
0.4
0.5
0.6
0.7
In=Iss/Issop
0.8
0.9
1
Fig. 5. Normalized propagation delay T
PD versus normalized bias current I
N
:
(2), in the following the factor R
C
I
B as that of the traditional circuit.
of the low-voltage latch will be assumed to be twice as much
From Eq. (9), the resulting ratio t
PDop ; LV CK
= t
PDop ; TR CK circuit minimum delay is s ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi t
PDop ; LV CK
¼ t
PDop ; TR CK a
LV CK a
TR CK b
LV CK b
TR CK
: of the low-voltage and traditional
ð 11 Þ
From
Table 1 , the ratio
a
LV CK
= a
TR CK in relationship (11) is approximately equal to process considered, it is equal to 0.51), while ratio b b
LV CK
TR CK
¼ 2
C
L
C
þ
L
þ
C
C cs3 ; 4 cs3 ; 4
þ
þ
C
C cs5 ; 6 cs1 ; 2
þ 4
þ
C
C bc1 ; 2 bc3 ; 4 ; 5 ; 6 b
LV CK
þ 1 þ ð V
þ C je3 ; 4
= b
SWING
þ ð V
TR CK
= 4 V
SWING is
=
T
4
Þ C bc3 ; 4
V
T
Þ C bcx5 ; 6
;
1
2
(for the
ð 12 Þ which results in being slightly lower than two, since the denominator has essentially the same capacitive contributions as the numerator, but a slightly higher number of addends. To be more specific, the denominator has an additional term C je3 ; 4
; as well as a greater number of basecollector capacitances C bc
: As an example, for the used bipolar technology, ratio in (12) ranges from 1.59 to 1.91 for C
L ranging from 0 to 1 pF, as is shown in
Fig. 6
which plots Eq. (12) versus
C
L
: As a result, from (11) the minimum CK 2 Q delay achievable of the low-voltage latch is slightly lower than that of the traditional, and tends to be equal to it for very high load capacitances compared to transistor parasitic capacitance at the output node in the denominator of (12). Hence, the low-voltage D-latch affords a moderate speed improvement when optimum bias currents are used (up to 20% for the bipolar process considered).
Another important design aspect is represented by the power efficiency, that is measured by the power-delay product PDP : The power dissipation of the bipolar gates considered is essentially static
[27]
and equal to the product of the power supply voltage V
DD and the bias current I
B
:

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M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 201
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
0 0.1
0.2
0.3
0.4
0.5
C
L
(pF)
0.6
0.7
0.8
0.9
1
Fig. 6. Ratio b
LV CK
= b
TR CK in relationship (12) versus load capacitance C
L
(pF) for the bipolar process adopted.
Therefore, by assuming a minimum-delay design (i.e., by setting the bias current according to relationship (8)) and the supply voltage to be set to its minimum value for each latch topology, the power-delay product ratio of the low-voltage circuit, PDP
LV CK
; and the traditional circuit,
PDP
TR CK
; results in
PDP
LV CK
PDP
TR CK
E
V
V
DD ; min ; LV
DD ; min ; TR
I
Bop ; LV CK
I
Bop ; TR CK t
PDop ; LV CK t
PDop ; TR CK
¼
V
DD ; min ; LV
V
DD ; min ; TR b
LV CK b
TR CK
; ð 13a Þ where (8) and (9) were substituted to evaluate the optimum bias current and delay. Moreover, considering values V
DD ; min ; LV
¼ 1 : 1 V and V
DD ; min ; TR
¼ 2 V, it follows that
PDP
LV CK
PDP
TR CK
E
0 : 55 b
LV CK
: b
TR CK
ð 13b Þ
As previously discussed, the ratio b
LV CK
= b
TR CK in (13b) is slightly lower than two, and approaches this value for high load capacitance values, compared to transistor parasitic capacitances at the output node. Therefore, the power-delay product ratio (13b) tends to be lower than unity for low values of C
L
; which means that the low-voltage latch has a slightly better power efficiency than the traditional. The opposite considerations hold when high values of load capacitance are considered, where the traditional topology exhibits an advantage as high as 10% compared to the low-voltage circuit.
In actual design cases, the optimum bias current (8) is too high and has to be lowered by a factor I
N
¼ I
B
= I
Bop that must be set according to power-delay tradeoff considerations expressed by relationship (10), as explained before. In particular, to carry out a consistent comparison, let us consider an equal factor I
N for the two latch topologies, that determines an equal delay increase
(10) with respect to the optimum case. Therefore, the delay and power-delay ratios are still equal to Eqs. (11) and (13), respectively, and the considerations above reported are still valid.
As an example, for the bipolar process considered, a load capacitance of 100 fF (about a unity fan-out) and the conditions previously discussed, the coefficients of the delay expressions (5) and

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202 M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209
Table 5
Numerical values of CK 2 Q delay coefficients
CK 2 Q delay coefficients (low-voltage D-latch) a
LV CK b
LV CK c
LV CK
CK 2 Q delay coefficients (traditional D-latch) a
TR CK b
TR CK c
TR CK
1.11E
1.14E
13
4.8E
12
2.2E
9
9
6.69E
14
1.4E
12
(6) have the numerical values reported in
Table 5 . The resulting optimum bias current of the low-
voltage and the traditional D-latch is equal to 10.1 and 5.5 mA, that are too high in typical applications, as expected, and a reduction by a factor I
N is necessary. For these optimum bias current values, delay ratio predicted by relationship (11) is 0.93, while the simulated value is 0.8.
The PDP ratio (13) and that simulated are 0.94 and 0.81.
To keep the bias current to a lower level while paying for a small speed penalty, let us consider a bias current reduction by a factor I
N
¼ 0 : 6 as suggested in
[25–26] . The bias current of the low-
voltage and the traditional D-latch becomes 6 and 3.3 mA, respectively. The simulated delay ratio is equal to 0.79 (obviously, relationship (11) again results 0.93), and the simulated PDP ratio becomes 0.8 (relationship (13) again results 0.94). As predicted by relationship (13b), the lowvoltage D-latch has a slightly better power efficiency (i.e., a lower power-delay product) and speed performance than the traditional one.
4.2. Low-power design
For gates that are not in the critical path of the circuit under design, the speed performance is not of concern; thus, they can be designed with a bias current much lower than the optimum value
I
Bop
: In this case, the delay expression (7) can be approximated as t
PD
E
I b
B
ð 14 Þ which shows that delay is inversely proportional to the bias current in a low-power design.
To carry out a consistent comparison, let us consider the low-voltage and traditional D-latch with the same bias current I
B
: As a consequence, the delay ratio between the former and the latter circuit becomes t
PD ; LV CK t
PD ; TR CK
E b
LV CK b
TR CK
ð 15 Þ that, as discussed in the previous subsection, is slightly lower than two. This means that, in a lowpower design, the traditional latch outperforms the low-voltage gate by a factor slightly lower

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M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 203 than two in terms of speed for an assigned gate bias current (or equivalently a specified power consumption per gate).
To evaluate the power efficiency, we again consider the power-delay product ratio for the two topologies, that from (14) results in
PDP
LV CK
PDP
TR CK
E
V
V
DD ; min ; LV
DD ; min ; TR t t
PD ; LV CK E
0 : 55
PD ; TR CK b
LV CK b
TR CK
ð 16 Þ and is equal to that obtained in the high-performance design, as can be found by comparison to relationship (13). Again, for very high load capacitances compared to transistor parasitic capacitances, the low-voltage circuit PDP is 10% worse than that of the traditional one. On the contrary, for low values of C
L the power-delay product ratio (16) tends to be slightly lower than unity, thus the low-voltage latch has a small advantage in regard to power efficiency.
As an example, for the bipolar process considered, a load capacitance of 100 fF and a bias current of 100 m A, the delay ratio predicted by relationship (15) and the simulated value are 1.7
and 1.56, respectively, while the power-delay product ratio (16) and that simulated are 0.94 and
0.86, respectively.
5. Remarks and conclusions
In this paper, the low-voltage CML D-latch topology proposed in
[21]
has been analyzed and compared to the traditional implementation to understand its performance in terms of speed, power and their tradeoff. The recent interest in the low-voltage D-latch is explained by considering that it allows for a supply voltage reduction by a factor of about 0.55 with respect to the traditional topology, that could be exploited to achieve a power saving. However, the bias current should also be considered to carry out a significant comparison of the two D-latch topologies based on the speed performance achievable and the power-delay tradeoff.
To compare the performance of the traditional and low-voltage topologies, an analytical delay model was introduced and then used to optimize performance and understand the power-delay tradeoffs. The accuracy of the model was tested by means of SPICE simulations on a bipolar process whose npn transistor has a transition frequency of 20 GHz, and the predicted results agree well with the simulated one. The resulting delay expression as a function of the bias current is simple, has the same form in both topologies and does not depend on the specific bipolar process used.
By using the model developed, the low-voltage D-latch was compared to the traditional topology for a high-performance or low-power consumption design target. The results show that the low-voltage D-latch topology is advantageous in typical cases where a low CK 2 Q latch delay is required and a low fan-out is expected, since this topology exhibits a moderate speed improvement (in the order of 10–20%) compared to the traditional implementation, while this advantage vanishes for high values of fan-out. However, a comparable power increase must be paid for this speed improvement, since the low-voltage and traditional topologies have roughly the same power-delay product. For the low-power design case, the traditional topology has a significant speed advantage over the low-voltage (roughly a factor of two), while the same considerations on the power-delay product as in the high-performance case hold. Moreover, when

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204 M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 considering the D 2 Q delay, as shown in Appendix B, the traditional topology exhibits a 30% advantage both in terms of speed and power efficiency for a high-performance design, and a speed and power efficiency advantage greater than 100% and 30%, respectively, for a low-power design.
In conclusion, the low-voltage topology does never exhibit a strong advantage neither in terms of delay nor of power efficiency, but should be considered only an alternative choice in the powerdelay design space, when a reduced supply voltage can be adopted. In particular, it makes sense to choose the low-voltage circuit only in applications requiring a low CK 2 Q delay and when
D-latches have a low fan-out, as occurs in dual-modulus prescalers or asynchronous counters. In these cases, a moderate speed improvement is allowed with respect to the traditional topology.
However, this comes at the cost of a comparable increase in power consumption.
Finally, while comparing the two D-latch topologies, it should also be considered that the low supply voltage allowed by the low-voltage circuit imposes serious restrictions on the logic gates that can be implemented, since the correct operation of traditional series gates is not allowed.
Appendix A
Consider a low-voltage D-latch working in the hold state, i.e. with Q5 in the ON state and Q6 in the OFF state, where Q3–Q4 store the previous output. Ideally, in this condition the output should not be affected by the input D ; i.e., transistors Q1–Q2 should be both in the cut-off region.
Actually, transistors Q1–Q2 are only partially deactivated by transistor Q5 working in the linear region, since one of them conducts a fraction of bias current I
B
= 2 ; that influences the output voltage in a manner that depends on whether input D is equal or opposite to the stored value. To better understand this aspect, assume the input D to be low without loss of generality.
When the stored value is equal to D (i.e., at the low level, under the assumption made before)
Q3 is ON and Q4 is OFF, hence collector current of Q3 and Q4 are i
C3
¼ I
B
= 2 and i
C4
¼ 0 respectively. Moreover, transistor Q2 is OFF and Q1 in ON, hence the bias current I
B
= 2 divides between Q1 and Q5 according to their emitter area factor N : To be more specific, observe that Q1
; and Q5 have the same base-emitter voltage since they have the emitter in common and are both driven by signals at the high level, and hence i
C5
¼ Ni
C2
: As a consequence, by approximating the transistor common-base current gain to unity, the fraction of I
B
= 2 that flows in transistor Q1 is i
C1
¼
I
B
2
1
1 þ N
: ð A : 1 Þ
Therefore, the differential output voltage
V
OL ; hold j
D ¼ OUT
¼ ½ R
C
ð i
C1
V out
þ i
C3
Þ ½ R
C
V out is equal to the low level given by
ð i
C2
þ i
C4
Þ ¼ R
C
I
2
B
N
1 þ
1 þ N
: ð A : 2 Þ
By reiterating the same arguments and assuming input to be D high, it is demonstrated that the high output voltage V
OH ; hold j
D ¼ OUT when the stored value is equal to D is given again by (A.2) with an opposite sign. The logic swing for D ¼ OUT in the hold mode, that is equal to the difference of high and low output voltage, is therefore equal to
V
SWING ; hold j
D ¼ OUT
¼ R
C
I
B
N
1 þ
1 þ N
: ð A : 3 Þ

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M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 205
In cases where the stored value is opposite to input D (i.e., D ¼ OUT ), by repeating the same reasoning, the logic swing becomes
V
SWING ; hold j
D ¼ OUT
¼ R
C
I
B
N
1 þ N
: ð A : 4 Þ
The analysis presented is based on the assumption that the latch operates in the hold mode. When the latch is in the transparent mode (i.e., when CLK is high and thus transistor Q5 is OFF and Q6 is ON, thus deactivating pair Q3–Q4 and activating pair Q1–Q2, which sets the output equal to
D ), the logic swing found is given by relationship (A.3), by applying the same procedure.
By comparing (A.3) and (A.4), the worst-case logic swing (and noise margin) is achieved in the hold mode when D is opposite to the stored value OUT ; and is equal to
V
SWING
¼ R
C
I
B
N
1 þ N
: ð A : 5 Þ
Appendix B
Let us consider the low-voltage D-latch topology in the transparent state. When CLK is high, transistor Q5 is OFF and Q6 is in the linear region, deactivating the emitter-coupled pair Q3–Q4.
Therefore, when D switches, the circuit can be simplified into an inverter made up of transistors
Q1–Q2, that can be represented with the linearized half-circuit model, since differential operation is assumed. The loading effect of Q3 and Q4 can be taken into account with a linear capacitance.
As well as already done in Section 3, the D 2 Q delay can be written by explicating the dependence on the bias current, as follows: t
PD ; LV D
¼ a
LV D
I
B
þ b
LV D
I
B
þ c
LV D
ð B : 1 Þ whose coefficients a
LV D
; b
LV D and c
LV D are reported in
Table 6 , and their numerical values are
shown in
Table 7 . By comparing relationship (B.1) to SPICE simulations in the conditions
discussed in Section 3.1, the model error with respect to simulation results, plotted in
Fig. 7 , is
always within 22%, as previously obtained for the CK 2 Q delay model. The D 2 Q delay model of the traditional D-latch has the same form as in relationship (B.1) where coefficients a
TR D
; b
TR D and c
TR D are reported in
Table 6
, and the error found is always within 20%.
By applying the same design procedure in Section 4, the ratio t
PD ; LV D
= t
PD ; TR D of the lowvoltage and traditional circuit minimum D 2 Q delay were compared. From
Table 6
, the ratio a a
LV D
= a
TR CK
TR D and a is slightly higher than that evaluated in Section 4 (that was equal to
LV D has one addend more than a
LV CK
1
2
), since a
TR D
¼
: For the process used and under the same conditions as in Section 4, the ratio a
LV D
= a
TR D results in 0.71. Moreover, the ratio b
LV D
= b
TR D is slightly greater than 2, due to the additional base-emitter capacitance C je
; and tends to 2 for high values of the load capacitance (for the process used, the ratio b
LV D
= b
TR D to 2.48 when C
L ranges from 2.11
varies from 0 F to 1 pF). As a consequence, differently from results obtained for the CK 2 Q delay, the minimum D 2 Q delay ratio is always greater than unity (this is also true for scaled bias currents, as discussed in Section 4). This means that, for a high-performance design, the traditional D-latch is faster than the low-voltage, regardless of the load capacitance.

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206 M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209
Table 6
Coefficients of the D 2 Q delay expression
D 2 Q delay coefficients (low-voltage D-latch) a b c
LV D
LV D
LV D
0 : 69 2
1 : 38 V r
V e
þ r
SWING b
SWING
C
L t
F
þ r b
C bci3 ; 4 r c
þ C cs3 ; 4
4 V
T
þ C
þ 2 cs1 ; 2 r c t
F
þ
V
SWING
C bc1 ; 2
1 þ N
þ 1 þ
V
SWING
2 V
T
0 : 69 ð r e
þ r b
Þ C je
þ r b
C bci
1 þ
V
SWING
2 V
T
þ r c
ð C bci
þ C bcx
D 2 Q delay coefficients (traditional D-latch) a
TR D
0 : 69 4 r e
þ r b
V
SWING t
F
þ r b
C bci1
2 V
T r c b
TR D
0 : 69 V
SWING
C
L
þ C cs3 ; 4
þ C cs5 ; 6
þ C bc3 ; 4 ; 5 ; 6
C bc34
þ C je
2
þ C cs
Þ þ
1 þ N
þ 1 þ
V
SWING
2 V
T
C bcx5 ; 6 c
TR D
0 : 69 ð r e
þ r b
Þ C je
þ r b
C bci
1 þ
V
SWING
2 V
T
þ r c
ð C bc
þ C cs5
Þ t
F
Table 7
Numerical values of D 2 Q delay coefficients
CK 2 Q delay coefficients (low-voltage D-latch) a
LV D b
LV D c
LV D
CK 2 Q delay coefficients (traditional D-latch) a
TR D b
TR D c
TR D
1.61E
9
1.24E
13
8.78E
12
2.25E
9
5.32E
14
4.53E
12
In regard to the power-delay product ratio of the low-voltage circuit, PDP
LV D
; and the traditional circuit, PDP
TR D
; it is always greater than unity since b
LV D
= b
TR D was demonstrated to be greater than two. This means that the traditional D-latch always exhibits a better power efficiency. Moreover, since b
LV D
= b
TR D decreases as increasing the load capacitance, the advantage of the traditional circuit is more evident for low fan-out gates, and reduces to 10% for very high values of C
L
: These considerations on delay and power-delay product are immediately extended to different power-delay tradeoffs (i.e., by decreasing the bias current by a factor I
N
), as previously discussed in Section 4.1.
Finally, it is interesting to consider the case of low-power design, as previously done in Section
4.2. From relationship (15), the delay ratio for a bias current much lower than the optimum value is greater than two, which means that for low-power design the traditional latch outperforms the low-voltage by a factor greater than two. From (16), the power-delay product ratio results always

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M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 error vs bias current IB
0
-5
-10
-15
-20
-25
0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9
IB (mA)
CL=0 CL=100 fF CL=1 pF
Fig. 7. Error of the predicted D 2 Q delay (B.1) with respect to simulation results versus I
B
:
207 greater than unity, especially for low values of the load capacitance. Again, the traditional D-latch has a better power efficiency than the low-voltage circuit.
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Massimo Alioto (M’01) was born in Brescia, Italy, in 1972. He received the laurea degree in electronics engineering and the Ph.D. degree from the University of Catania, Italy, in 1997 and
2001, respectively. In 2002, he joined the Dipartimento di Ingegneria dell’Informazione (DII) of the University of Siena as a researcher. His primary research interests are the modeling and optimized design of bipolar and CMOS high-performance digital circuits in terms of high-speed or low-power dissipation, as well as arithmetic circuits.

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M. Alioto et al. / INTEGRATION, the VLSI journal 36 (2003) 191–209 209
Rosario Mita received the Laurea degree in electronic engineering and the Ph.D. degree in
Electrical Engineering from University of Catania, in 1998 and 2002, respectively. In 2003 he was professor with the Dipartimento di Ingegneria Elettrica Elettronica e dei Sistemi, University of Catania, Italy, where he held the courses of Electronic I and Digital Electronic in Electronic
Engineering. He is currently engaged is a post-Ph.D. research where he is involved in the development of new high-performance digital circuits and systems for the pseudo-random bit generation. His research interests are also in low-voltage CMOS circuits and frequency compensation techniques of multistage amplifiers.
Gaetano Palumbo was born in Catania, Italy, in 1964. He received the laurea degree in Electrical
Engineering in 1988 and a Ph.D. degree from the University of Catania in 1993. Since 1993 he conducts courses on Electronic Devices, Electronics for Digital Systems and basic Electronics.
In 1994 he joined the DEES (Dipartimento Elettrico Elettronico e Sistemistico) at the
University of Catania as a researcher, subsequently becoming associate professor in 1998. Since
2000 he is a full professor in the same department. His primary research interest has been analog circuits with particular emphasis on feedback circuits, compensation techniques, current-mode approach, low-voltage circuits. In recent years, his research has also embraced digital circuits with emphasis on bipolar and MOS current-mode digital circuits, adiabatic circuits, and high-performance building blocks focused on achieving optimum speed within the constraint of low power operation. In all these fields he is developing some the research activities in collaboration with STMicroelectronics of Catania. He was the co-author of the books ‘‘CMOS Current
Amplifiers’’ and ‘‘Feedback Amplifiers: theory and design’’, both by Kluwer Academic Publishers, in 1999 and 2002, respectively. He is a contributor to the Wiley Encyclopedia of Electrical and Electronics Engineering . In addition, he is the author or co-author of more than 200 scientific papers on international journals (over 80) and in conferences. From
June 1999 to the end of 2001 he served as an Associated Editor of the IEEE Transactions on Circuits and Systems part I for the topic ‘‘Analog Circuits and Filters’’. In 2003 he received the Darlington Award. Prof. Palumbo is an IEEE
Senior Member .