MAY/JUNE 2012
Vol. 39 No. 3
Military
Aerospace
and
Think Thin
New Federal Anti-Counterfeiting...
Transforming Mobile Electronics...
Wedge Bonding...
WWW.IMAPS.ORG
Fa
re
w
el
Pa l to
ge a
30 Fr
ie
nd
Hermetic Packaging...
F E AT U R E A R T I C L E
T
ransforming Mobile Electronics
with Copper Pillar Interconnect
Deborah S. Patterson, Director, Product and Technology Marketing, Amkor Technology, 1900 South Price Road, Chandler, AZ USA
Phone: 480-786-7891 Contact Email: deborah.patterson@amkor.com, www.amkor.com
The crux of today’s packaging innovations continues
to be driven by silicon node reduction - and its corresponding die shrinks - coupled with increased functionality and higher bandwidth requirements. Applications
processors and other logic devices are highly functioning
SoCs with considerable signal I/O density. Along with the
corresponding need for added memory and distinct operational features (such as sensors, cameras, etc.), new device integration schemes are forcing significant advances
in IC packaging.
Smartphones and tablets comprise two of the fastest
moving, highest volume, and most competitive markets in
the world - with form, fit and function evolving at an unprecedented rate. Consequently, the necessity of managing costs, design complexity, and manufacturability results
in continual innovation to meet the dynamic demands of
the market. The OSAT community must respond to this
challenge with similar innovation in the development of
new packaging methods and with the speedy assembly of
these products.
A Healthy Market for Innovation
After the iPhone was introduced in June 2007 with its
subsequent onslaught of device-specific applications, the
idea of handheld “computing platforms” took a major step
forward. Users reconsidered the types of functions that
were necessary in a cell phone. The introduction of the
iPad in January 2010 firmly established the tablet as a viable and exciting product. These types of mobile platforms
now feed widespread use of media - and have facilitated
an explosion in software development that has accelerated
further demands on the device hardware (e.g., increased
processing and functionality, decreased power and size).
The creative loop feeding both software development and
hardware innovation sees no sign of easing – it is, in fact,
accelerating at a rapid pace. Who would have predicted
that, within the past decade, so many capabilities would
be tied to our fingertips (phone, camera/video/media
player, internet/email, streaming TV/film, games, navigation, etc.) with intuitive, user-friendly interfaces built
around multi-touch screens (virtual or otherwise) which,
in turn, drive countless other applications.
Figures 1 and 2 show continued healthy forecasts for
the mobile phone and tablet sectors, respectively. Worldwide sales of mobile phones grew 6.1% year-over-year
ending 4Q2011 with smartphone sales reflecting the
strongest segment increase. The basic and enhanced
cell phone sectors (which together, comprise the majority of mobile phone shipments) will continue driving
healthy volume sales while incorporating more smartphone functions, such as mobile Internet and third-party
applications.
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Worldwide media tablet shipments rose by 155% yearover-year ending 4Q2011. The tablet market experienced
much stronger-than-expected growth across many regions
and at many price points. Tablet shipments grew 56% between 3-4Q2011. Apple retained its market share lead at
54.7% followed by Amazon, Samsung, Barnes & Noble,
and Pandigital’s entry-level tablet. In addition, eReaders also emerged with a year-over-year growth of 64.3%.
As the major players such as Amazon, Barnes & Noble,
and Kobo expand into international markets, continued
growth in this segment is expected as well.1
Trend Toward Finer Pitch Flip Chip (FPFC)
The mobile device market seeks a robust operating
system, rich user interface, high processing performance,
and resilient security. Equally desired is the ability to respond quickly to changing market conditions, to retain
tight inventory control and rapid throughput, and to
achieve high product yields. Each element must also be
achieved without compromising the reliability or quality
of the end product.
To address these requirements, fine pitch flip chip is
replacing wire bonding in many higher end devices that
require low profile and small area packaging. Within this
category of devices, copper pillar bump technology offers
several compelling advantages.
In 2005, wireless device suppliers adopted copper
pillar interconnect in RF power amplifiers and front-end
modules to obtain both performance and cost improvements. Improved stability and thermal performance was
achieved as well as the elimination of through-GaAs vias,
wafer thinning, and backside metallization.2
In 2006, it was revealed that Intel had replaced its traditional SnPb flip chip solder bumps with a combination
copper pillar/SnPb joint for its 65nm Yonah and Pressler
processors.3 The smaller bump form factor facilitated
higher I/O densities. Prismark reported that Intel eventually migrated all of its products to Pb-free copper pillar
interconnect technology.4,5
Thinner Is Indeed Better – and Modularity
Helps
Package-on-package (PoP) is a platform of choice for
handheld electronics. PoP stacks are comprised of very
low profile packages that combine independent logic and
memory BGA packages stacked one on top of the other
and leveraging a standard interface to route signals between them.
As fully assembled and tested stand-alone packages,
PoP platforms provide modularization and form the
building blocks of end-product differentiation. The PoP
structures shown in Figure 3 illustrate the flexibility of the
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Figure 1. From basic feature phones to smartphones, total mobile phone growth will continue its upward trend with lower end units slowly
integrating additional features.
individual packages that are integrated into a single BGA
platform, ready to be assembled onto a circuit board.
In the handheld market, where component height and
area are severely constrained, a typical PoP configuration
will stack mixed logic and memory. The logic die (such
as applications, image or baseband processors) are placed
in the bottom package since they require more BGA connections to the motherboard. The top package typically
contains memory, such as one or more Flash or SDRAM
stacked die. System designers can mix and match varying
logic and memory options to offer a wide range of product configurations, addressing each price/ performance
segment within multiple markets. The ability to change
memory capacity or to use multiple suppliers is also facilitated. Since the individual packages are fully tested, yield
concerns due to a faulty die impacting the entire stack are
eliminated.
In July 2010, Texas Instruments and Amkor announced the introduction of copper pillar flip chip packages in a PoP platform. The 45nm node applications processor required a 40/80 µm staggered bump pitch. Figure
(a)
Figure 2. Tablet shipments grew from 19.4M in 2010 to 68.7M in 2011 and are expected to keep
similar pace through 2012.
Source: International Data Corporation, March 13, 2012.
(b)
Figure 3. (a) The package-on-package (PoP) components are illustrated on the top left with a photo of the assembled structure below. (b) The
two cross-sections illustrate a PSvfBGA or Package Stackable very thin fine pitch BGA (top), and a PSfcCSP or Package Stackable Flip Chip CSP
(bottom).
continued on page 20
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A DVA N C I N G
MICROELECTRONICS
continued from page 19
Figure 4. (a) Cross-section of the TI XAM3715, a 45nm applications processor mounted on a BGA substrate, and (b) a close-up of the dual row
staggered copper pillar bumps. (Source: Chipworks)
4 shows a cross-section of the bottom package.6 The copper pillar bumps have a SnAg solder cap that joins to the
copper trace on the BGA substrate.
Figure 5(a) shows a SEM of 50µm in-line copper pillar
bumps with SnAg solder caps. Fifty micron pitch copper pillar bumps are in high volume production today.
When using copper pillar flip chip, 1-3 rows of staggered
perimeter pitch bumps are typical. A SEM of 40µm area
array bumps is shown in Figure 5(b) to illustrate bumping
proficiency. These dense area array footprints are more
complex than those found in handheld devices.
Fine Pitch Flip Chip (Copper Pillar) Package
Options
The continued development from early flip chip in
CSP, BGA and PoP platforms has spawned a broad selection of package types, all with the ability to integrate copper pillar interconnect. Figure 6 illustrates a selection of
package configurations, from bare die on board to complex 2.5/3D through silicon via (TSV) designs, to provide
a sense of the diversification of packaging options going
forward.
Cost of Ownership Reduction and Performance
Improvements
For mobile device manufacturers to differentiate themselves, design and manufacturing efficiencies must be delivered. These efficiencies may show up as a lower priced
cell phone, or as a higher-end smartphone boasting more
capability, longer battery life, and increased speed. And,
although the end products may be very different, one
commonality they share is the goal of reducing total cost
of ownership (CoO) and increasing profitability for the
both the OEM and IDM.
The drivers for placing fine pitch non-collapsible
bumps directly on the final metal bond pads are numerous and include both performance improvements and
cost of ownership reduction.
Traditional solder bumps used in the assembly of flip
chip die are designed to collapse upon assembly, thereby
providing self-alignment on the circuit board pad, accommodation of less than planar substrates, good wetability,
and predictable failure modes as characterized by the chosen solder material. The limitation of solder-based flip
chip joints has been one of pitch where the tightest pitches in mass production are on the order of 150µm, placing
constraints on the overall I/O layout and the density of
interconnections that can be achieved.
Although gold stud bumping has been in use for decades to provide bumps directly on the bond pad, it is
not a batch process and the lower throughput can offset
the cost savings of using a ball bonding process. Other
concerns include the high cost of gold, and the reliability
of the stud bump over subsequent reflow operations due
to the formation of brittle Au-Sn intermetallics.
Given the factors identified in Table I and their widespread impact on profitability, ease of doing business,
Figure 5. (a) SEM of 50µm in-line copper pillar bumps, and (b) 40µm copper pillar area array (Source: Amkor Technology).
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Figure 6. Examples of package structures that can support fine pitch copper pillar flip chip.
product performance and time-to-market, a concerted
development program focusing on the manufacture and
assembly of fine pitch copper pillar bumps was defined
with materials development, equipment customization,
and assembly processes investigated.
Developing the Assembly Process to Facilitate a
Mobile Revolution
The identification, development and implementation
of new materials and processes to address the structural
considerations listed in Table I was a challenging and time
consuming undertaking. Material qualification, equipment modification, and new process flows were created
and compared to conventional flip chip assembly techniques with respect to cost, performance, reliability,
throughput, etc.
The primary issues centered on developing processes
(heating profile, bond force, etc.) that preserved the structural integrity of the very thin (≤100µm), fragile (low-K/
ELK dielectric) die, the small copper pillar bump, and
the SnAg solder joint. Each step in the die prep and assembly process had to yield a planar, rugged, and reliable
structure that would pass JEDEC package and board level
requirements. “Due to their extremely small size, these
fine pitch interconnects are very fragile at the bump joint
area [and] vulnerable to joint failure due to the stresses
encountered during package and PWB assembly, created
by the thermal mismatch between the die and the organic
substrate.7
After an extensive investigation into the assembly processes to handle very thin, low-K die, the combination of
thermo-compression bonding with non-conductive paste
proved to be the optimal choice. It produced a viable,
high volume assembly solution that preserved the integrity of the die, copper pillar interconnect, and substrate.
The process is illustrated in Figure 7. The non-conductive paste is applied to the substrate; the bumped device is aligned to within ≤5µm, and the underfill is snap
cured. The most pressing challenge is the warpage that
occurs between the thin die and the substrate. The snap
cure process (a) reduces stress on the copper pillars, (b)
reduces stress on the die, and (c) allows the substrate to
maintain its planarity.
Silicon devices at the 45nm node have been qualified
at 60µm thickness and 8.2mm x 8.2mm die size. The
TC+NCP process has not yet been qualified on die sizes
over 10mm x 10mm although several large area die have
active development programs in place.
This process also delivers a very small filet (0.5mm)
compared to capillary underfill. It preserves good shape
control and offers excellent encapsulation.
The TC+NCP process has been demonstrated to a
25µm bump pitch. At the present time, 25µm pitch production is not on the roadmap.
Next Generation Approaches
The introduction of through mold via (TMV™) technology and molded underfills are further transforming the
package choices available for advanced structures. TMV™
is an ablation method that provides solderable connections through a mold cap. The technology can be used
with flip chip die or die that are wire bonded, stacked, or
that include passive components. TMV™ technology can
further extend copper pillar fine pitch bumping by driving higher density BGA footprints.
continued on page 22
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continued from page 21
Table I. Benefits of Copper Pillar Bump-on-Pad and PoP Enabled Packaging
Cost of Ownership Reduction: Copper Pillar
Why?
Use of existing I/O cell libraries
Retain current die designs and manufacturing processes
Elimination of flip chip manufacturing steps
No post-fab redistribution process, simplified under-bump
metallurgy (UBM)
Single final metal layer footprint
Eliminates need for dual wire bond and flip chip inventories
Supports die shrinks
Area savings continue to scale with die shrinks, increasing
total wafer revenue
Replacement of gold stud bumps
A batch process versus serial process; eliminates a volatile
and expensive material; increases reliability
Reduction in substrate layer count
Seen for small die with high I/O density - savings dependent
on design flexibility, die size, I/O density & body size
Routing is minimized, TSV designs are better
Bump-on-pad eliminates fan-in; routing for chip-to-chip
stacking is minimized
Turn-key process after probe
Same logistics as wire bond production and final test
Additional Performance Improvements: Copper Pillar
Why?
Lower inductance and improved device speed
No fan-in and simplified chip-to-chip routing generate
faster signal propagation, reduced noise and cross talk
Increased electromigration resistance
Increased thermal conductivity
Pb-free and low alpha particle compliancy
Additional Structural Improvements: Thermo-compression
Bonding + Non-Conductive Paste
Why?
Thin die (<100µm) increases “vertical functionality”
Elimination of ILD and bump cracking
A yield concern with Low-K and Extra Low-K (ELK) dielectrics
Reduces substrate warpage
Extends package level solder joint life
Package Example Illustrating Additional Cost of Ownership
Reduction: Package-on-Package (PoP)
Why?
Known good die (KGD) confirm higher yields
Each package is fully tested before stacking
Decoupled die differentiate product offering
Pre-packaged memory and ASICs
Better inventory and WIP management
Later stage sourcing
Rapid response to changing market conditions
Deployment decisions occur later in the product flow
Logistics are controlled upstream
Multiple sourcing for memory or logic
Standardized footprints simplify circuit board
routing
Figure 8 illustrates the excellent improvement in substrate warpage compared with the conventional flip chip
PoP.8 The Thermal Shadow Moiré plot shows four package configurations, each measuring 14mm x 14mm and
containing 7 x 7 x 0.13mm die and a 0.4mm mold cap.
Two substrate thicknesses, 0.21mm and 0.3mm, were run
for each of the PoP and TMV™ packages. The warpage
profile for the PoP packages was too severe to be considered for stacking. Conversely, note that the substrate
thickness had little effect on the TMV™ test vehicle, demonstrating essentially the same response to warpage. The
warpage profile for these packages were within typical
customer requirements of better than -60µm.
Figure 9 shows a photo and cross section of a FCMBGA
(Flip Chip Molded BGA) test vehicle that employs a molded underfill in single unit format. This technique helps
22
control warpage for thin core substrates and improves
solder joint and overall board level reliability. It provides
cost reduction compared to lidded flip chip BGAs, multidie modules or die plus memory modules. It also provides more room for passive component integration and
closer spacing between the passives and the IC.
Summary
Technology trends and consumer demand continue to
dictate downstream packaging challenges. The considerable increase in I/O densities on today’s processors and
ASICS (as a direct result of die shrinks and higher functionality) is primarily responsible for driving advanced
interconnect and packaging development. The corresponding increase in signal I/Os has accelerated packaging
complexity. The primary drivers are:9
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Thermo-compression (TC) Bonding with Non-Conductive Paste (NCP)
Figure 7. Process flow for thermo-compression bonding with non-conductive paste (TC+NCP) and resultant copper pillar bond.
Figure 8. Thermal Shadow Moiré measurement of the warpage characteristics of standard versus TMV™ PoP packages at two substrate
thickness. Note the response of the TMV™ test vehicles and how the change in substrate thickness shows little effect on the warpage response.
Figure 9. (a) An example of a FCMBGA where the center die and four memory packages are over-molded in a single step. (b) The cross-section
illustrates the option of incorporating integrated passives.
continued on page 24
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continued from page 23
• form factor reduction for handheld devices; coupled
with
• silicon node progression, both driving downstream
assembly constraints;
• higher power dissipation (where higher operating
temperatures and increased current per bump generate more severe thermal management challenges);
• higher operating frequencies and reduced noise margins;
• increased use of application specific packages (e.g.,
sensors, MEMS, camera modules);
• full conversion to green materials; and
• relentless pricing pressure.
Copper pillar interconnect, along with innovative
substrate, underfill, molding and assembly refinements
provide for high I/O density, potential substrate cost reduction versus standard flip chip, improved electrical
performance due to routing efficiencies, increased thermal
conductivity and electromigration resistance. Copper pillar stacked packages enable a higher die to package area
ratio ensuring minimum board real estate consumption
along with the ability to take full advantage of the vertical
space between the PCB and device enclosure.
Amkor has invested heavily in the development and
expansion of high volume copper pillar bumping and
TC+NCP assembly lines. The ability to respond ahead
of the curve throughout the next decade underscores the
importance of continuous improvement and innovation
to the assembly process and within the supply chain.
With movement of so many IDMs to fabless and fab-lite models, the reliance on package development, final test
and assembly are falling to OSATs to an unprecedented
degree. It is a great time to be on this side of the industry.
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Endnotes
1
2
3
4
5
6
7
8
9
IDC, “Media Tablet Shipments Outpace Fourth Quarter Targets;
Strong Demand for New iPad and Other Forthcoming Products
Leads to Increase in 2012 Forecast,” March 13, 1012.
Lee Smith, “Copper Pillar Flip Chip Momentum is Accelerating,”
Chip Scale Review Tech Monthly, March 2012.
Chipworks, “Intel D920 Presler and T2300 Yonah Copper Pillar
Bump Technology Package Analyses,” April 3, 2006.
Prismark Partners, Semiconductor Packaging Report, Third Quarter
Dec 2008.
Prismark Partners, Semiconductor Packaging Report, First Quarter
May 2010.
Chipworks, “TI Ships 40-µm Fine Pitch Copper Pillar Flip Chip
Packages,” October 4, 2010.
Lee, et al., “Study of Interconnection Process for Fine Pitch Flip
Chip,” ECTC 2009.
Curtis Zwenger, Lee Smith, Jeff Newbrough, “Surface Mount Assembly and Board Level Reliability for High Density PoP (Packageon-Package) Utilizing Through Mold Via Interconnect Technology,”
Proceedings of the SMTA International Conference, Orlando, FL,
August 17-21, 2008.
Robert Darveaux, “Challenges & Solutions in Development of New
Package & Interconnect Technologies,” SEMI Breakfast Forum,
Tempe, AZ, October 2011.
About the Author
Deborah Patterson is Director, Product and Technology Marketing at Amkor Technology. She has worked in
the packaging assembly and test sectors over 25 years.
Prior to joining Amkor, Ms. Patterson held positions in
business development, marketing and sales, and product management at Advantest, Kulicke and Soffa, Flip
Chip Technologies, and StratEdge Corporation. She has
also consulted through her own company, the Patterson
Group, LLC.
System Level Approach
•Lower cost system packaging
•Ultra-fine pitch, ultra-thin die
•Controlled stress for ULK
•2.5D/3D Through Silicon Via
(TSV) enablement
•Enhanced electromigration
resistance
•Superior thermal performance
•Pb-free / Low alpha solution
Cu pillar
µbumps
With proven reliability in
volume manufacturing!
PB-free
fc bumps
Si Interposer
& TSVs
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