Massachusetts Institute of Technology
Department of Electrical Engineering and Computer Science
6.002 - Electronic Circuits
Spring 2000
Homework #6
Issued 3/8/2000 - Due 3/15/2000
Exercise 6.1:
Use the results of Homework #5 to determine the Thevenin equivalent networks
of the amplifiers studied in Problems 5.1 and 5.2 when they are viewed from their output ports.
Assume that the inputs to the amplifiers are such that all MOSFETs operate in their saturation
regions. (In studying the amplifier of Problem 5.1, do not assume VT = 0; see solutions to
Homework #5.)
Problem 6.1:
This problem continues to study the two-stage amplifier studied first in
Problem 5.1. (Do not assume that VT = 0; see solutions to Homework #5.) In this problem, let vIN =
VIN + vin and vOUT = VOUT + vout, where VIN and VOUT are the large-signal components of vIN and
vOUT, respectively, and vin and vout are the small-signal components of vIN and vOUT, respectively.
(A)
Assume that both MOSFETs are biased so that they operate in their saturation regions.
Develop a small-signal circuit model for the amplifier that can be used to determine vout as a
function of vin. In doing so, assume that VIN defines the operating point around which the
small-signal model is constructed, and evaluate all small-signal model parameters in terms of
VIN as necessary.
(B)
Use the small-signal model to determine vout as a function of vin.
(C)
Compare the small-signal gain found in Part (B), defined as vout/vin, to that found in Part (E) of
Problem 5.1. Explain any differences.
Problem 6.2:
The circuit shown below delivers a nearly constant current to its load despite the
fact that the power supply is noisy. The noise is modeled by the small signal vs superimposed on the
constant supply voltage VS. Thus, VS and vs are the large-signal and small-signal components of the
total power supply voltage vS, respectively. IL and il are the large-signal and small-signal
components of the load current iL, respectively. The noise vs in the power supply voltage satisfies
vs « VS, and is responsible for the presence of il in iL.
The current source contains a MOSFET which operates in its saturation region such that
iDS = 0.5K(vGS - VT)2. The current source also contains a nonlinear resistor whose terminal
characteristics are described graphically below. Assume that VS > VN > VT.
(A)
Assume vs = 0. Determine VGS, the large-signal component of vGS, in terms of RB, RN, VN
and VS.
(B)
Following the result of Part (A), determine IL in terms of RB, RN, VN, VS, K and VT.
(C)
Now assume that vs ≠ 0. Draw a small-signal circuit model for the combined circuit comprising
the power supply, current source and load, with which il can be found from vs. Clearly label
the value of each component in the circuit model.
(D)
Using the small-signal model from Part (C), determine the ratio il/vs.
Load
RB
D
+
 vs
vS 

 VS
+
Current Source
& Load
G
iL = IL + il
S
Nonlinear
Resistor
i
i
+
Nonlinear
Resistor
1
Slope = ------RN
v
VN
v
Problem 6.3:
This problem studies the propagation delay of digital signals through the inverter
shown below. Assume that the MOSFET in the inverter acts as a switch with on-state resistance RON.
The inverter is loaded with a capacitor, having capacitance CGS, which models the combined input
capacitance of all logic gates connected to its output. Assume that the gates obey the static discipline
defined by VL and VH.
(A)
Assume that the MOSFET has been off for a very long time. At t = 0, vIN turns the MOSFET on.
Determine vGS(t) for t ≥ 0.
(B)
How long does it take vGS(t) to pass by VL? This delay is the fall time of the inverter.
(C)
Assume that the MOSFET has been on for a very long time. At t = 0, vIN turns the MOSFET off.
Determine vGS(t) for t ≥ 0.
(D)
How long does it take vGS(t) to pass by VH? This delay is the rise time of the inverter.
(E)
How can the fall and rise times be shortened via the design of RPU? What limits the extent to
which this design path may be followed?
VS
RPU
CGS
vIN +-
+
vGS
-
Problem 6.4:
The network shown below has two ports, two resistors and one capacitor. The
resistor values R1 and R2, and the capacitor value C, are unknown. Also shown below is the result of
an experiment performed on the network in which one port is driven with the voltage step vIN at
t = 0, and the other port is loaded with a 1 kΩ resistor. Using the experimental result, which consists
of the measured current iIN, find the values R1, R2 and C. Also, find the voltage vOUT across the load
resistor for t ≥ 0. In doing so, assume that the network capacitor is uncharged prior to t ≥ 0.
Network
iIN
R2
R1
vIN
+
-
1kΩ
C
Applied
vIN(t)
Measured
iIN(t)
3 mA
3V
iIN(t) = (1 mA) + (2 mA) e-t/1 ms
1 mA
0
t
0
t