EE616 Electronic System Design Course Project Report, EE Dept, IIT Bombay, Dec. 2013
Reset Stabilized Difference Amplifier
Navnidhi Upadhyay (133070078)<navnidhi.01@gmail.com>
Pramod kumar (133070078)<pramodku.026@gmail.com>
Instructor: Prof. P.C. Pandey
ABSTRACT
This report projects a circuit which reduces the offset error voltage and hence using this
to implement a offset free difference amplifier. The effects of offset voltages are more
pronounced especially while amplifying low level signals. Offset error is one of the major
problems in the amplifiers, as it gets amplified with the base signal. Amplifier with automatic
offset compensation can be very useful, as it can be implemented with any circuit and hence can
be used globally. One way of achieving automatic offset compensation is to use Reset Stabilized
Amplifiers. Reset stabilization is the technique in which the input signal is taken off periodically
for determining the error signal present in the circuit. This error is then again fed back to the
amplifier such that it will negate the effect of error signal in the output. The performance of such
amplifiers can be further improved by removing the glitch in the output signal, by connecting a
low pass filter circuit in the output. For a considerably low frequency signals, the glitch free
output will be almost equivalent to the desired output.
1. INTRODUCTION
Reset stabilized amplifier can be implemented using the analog switches and sample and hold
circuits. The analog input is periodically disconnected from the amplifier input using the analog
switches. During sampling time, the output of the difference amplifier is due to the offset voltage
of itself, output op-amp and sample and hold circuit. In the hold mode, the sampled output from
the sample and hold circuit is again fed back to the difference amplifier via output op-amp which
nullifies the offset error ultimately. This output contains glitches at the time duration when the
input gets disconnected. This can be reduced by using a low pass filter at the output of difference
amplifier.
2. DESIGN APPROACH
2.1 BLOCK DIAGRAM
Fig 1. Block Diagram of Reset Stabilized Amplifier for Difference Amplifier
2.2 CIRCUIT DIAGRAM
Fig 2. Reset Stabilized Amplifier for Difference Amplifier
The design consists of the following main blocks




Clock Generation by microcontroller
Difference Amplifier
Sample and Hold Circuit
Switches
2.2.1. GENERATING NON-OVERLAPPING COMPLEMENTARY CLOCKS
Microcontroller: AT89c5131 microcontroller
The microcontroller is programmed to produce two non – overlapping complementary clocks.
Code:
#include <at89c5131.h>
sbit c0 = P0^0;
sbit c1 = P0^1;
int i=1,j,k;
main()
{
TMOD = 0x11;
TH0 = 0xFC;
TL0 = 0x18;
TR0=1;
c0=1;
c1=0;
IEN0=0x86
if(i==1)
{
c0=~c0;
for(j=0;j<5;j++);
c1=~c1;
i=0;
}
else
{
c1=~c1;
for(j=0;j<5;j++);
c0=~c0;
i=1;
}
TF0=0;
TR0=0;
TH0 = 0xFC;
TL0 = 0x18;
TR0=1;
IEN0=0x86;
}
Fig 3. Output of microcontroller (Non-Overlapping clocks)
2.2.2 DIFFERENCE AMPLIFIER
IC 741 is used for a difference amplifier. The gain of difference amplifier is kept
100 to amplify small voltage signal.
2.2.3 SAMPLE AND HOLD CIRCUIT
Sample and Hold circuit is used to sample and hold the output voltage of the difference
amplifier, due to offset error. During sampling time; input is not applied to the reset
stabilized amplifier and output present is only due to the offset voltage of op-amp in the
difference amplifier. During hold time; differential input is applied to the amplifier so the
output is because of the input and error voltage which is due to the offset voltage of Op-amp.
.
Fig 4. Sample and Hold Circuit
2.2.4 SWITCHES
IC CD4066BE is used for switches. Control voltages used for switches are derived from
clocking circuit with 5v voltage. Hence the clock frequency ultimately decides the switching
frequency of the input signal.
3. EXPERIMENTAL EVALUATION
Following figures are obtained as a result of the experiment.
Fig. 5 Input to the voltage divider circuit
Giving the input as shown in fig. 5 to a voltage divider circuit we have taken a
low amplitude sine wave of 10m v p-p, which is then fed as an input to difference
amplifier.
Now we have grounded one terminal of difference amplifier and given the given
the above input to other terminal, that gives us the following output.
Fig 6: Output-1 of Reset Stabilized Amplifier
And then we shorted second terminal to ground and first terminal to input, and we
get following output.
Fig 7: Output-2 of Reset Stabilized Amplifier
From the figure given above we can easily see that the output is nearly error free with a
reasonable gain of nearly 100.
4. CONCLUSION
The error free output is successfully obtained using the reset stabilization. In some electronics
circuits, sensors are used and there output ranges in few millivolts comparable to offset voltage
of op-amp. So these small signals need to be amplified for further processing. Due to offset
voltage present at the input of op-amp, output of amplifier is erroneous and inaccurate. Hence
reset stabilized amplifier can be used to negate the effect of offset of op-amp and to get more
accurate output.
5. References
[1] Lecture Notes of EE616 Electronic System Design, EE Dept, IIT Bombay, Dec. 2012.
[2] http://pdf1.alldatasheet.com/datasheet-pdf/view/26884/TI/CD4066BE.html
[3] http://www.ti.com/lit/ds/symlink/lm741.pdf
[4] http://www.datasheetcatalog.org/datasheet/philips/LF398_2.pdf
[5] http://www.keil.com/dd/docs/datashts/atmel/at89c51_ds.pdf