Vol. 36, No. 10
Journal of Semiconductors
October 2015
A broadband 47–67 GHz LNA with 17.3 dB gain in 65-nm CMOS
Wang Chong(王冲), Li Zhiqun(李智群)Ž , Li Qin(李芹), Liu Yang(刘扬),
and Wang Zhigong(王志功)
Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China
Abstract: A broadband 47–67 GHz low noise amplifier (LNA) with 17.3 dB gain in 65-nm CMOS technology is
proposed. The features of millimeter wave circuits are illustrated first and design methodologies are discussed. The
wideband input matching of the LNA was achieved by source inductive degeneration, which is narrowband in the
low-GHz range but wideband at millimeter-wave frequencies due to the existence of gate–drain capacitance, Cgd .
In order to minimize the noise figure (NF), the LNA used a common-source (CS) structure rather than cascode in
the first stage, and the noise matching principle is explored. The last two stages of the LNA used a cascode structure
to increase the power gain. Analysis of the gain boost effect of the gate inductor at the common-gate (CG) transistor
is also performed. T-shape matching networks between stages are intended to enlarge the bandwidth. All on-chip
inductors and transmission lines are modeled and simulated with a 3-dimensional electromagnetic (EM) simulation
tool to guarantee the success of the design. Measurement results show that the LNA achieves a maximum gain of
17.3 dB at 60 GHz, while the 3-dB bandwidth is 20 GHz (47–67 GHz), including the interested band of 59–64 GHz,
and the minimum noise figure is 4.9 dB at 62 GHz. The LNA absorbs a current of 19 mA from a 1.2 V supply and
the chip occupies an area of 900 550 m2 including pads.
Key words: CMOS; 60 GHz; low noise amplifier; wideband; electromagnetic simulation
DOI: 10.1088/1674-4926/36/10/105010
EEACC: 2570
for a 60 GHz band LNA can be attained, which may lead to
significant progress in 60 GHz communication applications.
1. Introduction
Society’s increasing demand for higher data rates is driving an increase in the operating band of wireless communication to millimeter-wave (MMW) frequencies. In the past few
years, many countries have released the band around 60-GHz,
e.g., 59–64 GHz is an unlicensed band in China, for applications such as wireless personal area networks (WPAN). In order to enter the high data-rate era, much effort has been put into
researching 60 GHz transceiversŒ1 3 . In the past, III–V compound semiconductor technologies such as GaAs were adopted
in most MMW applications because of their high performance.
Fortunately, as CMOS technology is scaled in the nanometer
range, it is possible to realize 60 GHz transceivers with CMOS,
which is more attractive due to its low cost and high integration.
The low noise amplifier (LNA) is the first active block in
the receiver and plays an important role since the noise performance of the whole system is greatly determined by it. According to the Friis equation, it is significant to minimize the
noise figure and raise the gain of the LNA for better noise performance of the receiver. In addition to this, excellent input
matching and sufficient bandwidth with low power dissipation
are also key specifications. Therefore, it is a challenge to satisfy so many demands simultaneously in the design.
In this paper, a three-stage 60 GHz LNA in 65 nm CMOS
technology is proposed, which demonstrates the approach to
achieving wideband input matching, a low noise figure, high
gain and wide bandwidth. From this design, the methodology
2. Circuit design and considerations
The basic specifications for 60 GHz LNAs are the same as
those of low frequency LNAs, but there are at least three differences between themŒ4 which distinguish their design methodologies. First, 60 GHz LNAs suffer from low gain and high
noise due to the transistors operating closer to their cutoff frequencies, i.e., fT . Despite the relatively high fT technologies
are usually used to design MMW LNAs, the ratio of the operation frequency to fT actually falls. For instance, it is harder
to design a 60 GHz LNA with 200 GHz fT technology than a
5 GHz LNA with 50 GHz fT technology. Multi-stage topologies are required to provide enough gain, which consume more
power and area, and lead to poorer linearity and higher noise.
This is one of the reasons that 60 GHz LNAs have poorer performance relative to low frequency LNAs.
Second, the wavelength of the signals shrinks significantly
at 60 GHz, which means that the distributed effect cannot be
neglected even for integrated circuits. At 60 GHz, a transmission line of only 100 m may alter the performance of the
LNAs. Therefore, it should be modeled through electromagnetic (EM) tools to take full consideration in the design.
Lastly, parasitic effects have an enormous influence on the
circuits at 60 GHz, since the required component values are
relatively small in the MMW band. A parasitic capacitance of
10 fF may compare with the capacitance of the LC tank at
60 GHz and move down the resonant frequency. Since these
* Project supported by the National High Technology Research and Development Program of China (No. 2011AA010202).
† Corresponding author. Email: zhiqunli@seu.edu.cn
Received 7 June 2015, revised manuscript received 23 July 2015
© 2015 Chinese Institute of Electronics
105010-1
J. Semicond. 2015, 36(10)
Wang Chong et al.
Figure 2. MOS transistors model with Ls and Zd .
Figure 1. Schematic of the proposed LNA.
parasitic effects are difficult to accurately model, the operating
frequency of the LNAs tends to shift uncontrollably. In order
to cover the desired band in the case of frequency shifting, a
LNA with broad bandwidth is proposed in the design.
With all of the above features, a 60 GHz LNA topology
is proposed as shown in Figure 1, which makes a good tradeoff in terms of input matching, noise figure, power gain and
bandwidth. In Figure 1, C1 to C4 are DC-blocking capacitors
whose self-resonant frequency is located in the desired band, so
they can be neglected for AC analysis. The resistors R1 to R3
are connected with the bias point to restrain AC current from
passing through. Design considerations will be described in the
following.
2.1. Wideband input matching
Generally, before entering the LNAs, the received signals
from the antenna pass a bandpass filter, which demands standard load impedance, generally 50 , to minimize the ripple
of the filter in the band. For this purpose, input matching is an
important factor which should be considered in the design.
In Figure 1, since the parasitic capacitance of the pad Cp
introduces non-negligible impedance in the MMW band, it is
tuned out by an inductance Lp , which connects a bypass capacitance Cb to ground and feeds through bias voltage of the first
stage. The paralleled Lp Cp networks will not be considered in
the following analysis since they resonate at the desired band.
In conventional low-GHz LNAs, source inductance degeneration is widely used due to its excellent performanceŒ5 .
In this topology, two inductance Lg and Ls are connected to
the gate and the source of the input transistor, respectively, as
shown in Figure 1. When the frequency moves up to the MMW
band, this structure also holds its advantages. Furthermore, the
input matching develops from narrowband to wideband, making it more insensitive to simulation errors or process variationŒ6 . The wideband matching is achieved by the feedback effect of Cgd , which is intrinsic in the transistor’s model. According to the analysis below, the load impedance Zd at the drain
can reflect a resistance at the input of the gate through Cgd .
Therefore, besides the source inductance degeneration mechanism, the real part of the input impedance can close to 50 
at other frequencies by adjusting Zd , and together they form a
wideband input matching.
The simplest model of the MOS transistors with source degeneration inductor Ls and drain impedance Zd is shown in
Figure 2. The input admittance Yin at the gate of the transistors
can be written asŒ7 :
Figure 3. Equivalent input admittance of the gate.
1 gm Ls
1
1
Yin D
C sLs C
C Zd C
Cgs
sCgs
sCgd
s 2 Cgs Ls
1
Ls
C sLs C
C
C
gm
gm
Cgd Zd
C
sCgs Ls
1
C
Cgd gm Zd
sCgd gm Zd
1
1
:
(1)
From Equation (1), it can be seen that the input admittance
is equal to three impedance in parallel, as shown in Figure 3,
and they are expressed as Z1 , Z2 and Z3 respectively, where:
Z1 D
gm L s
1
C sLs C
;
Cgs
sCgs
Z2 D Zd C
1
;
sCgd
(2)
(3)
s 2 Cgs Ls 1
sCgs Ls
Ls
1
C C
C
C
:
gm
gm Cgd Zd Cgd gm Zd sCgd gm Zd
(4)
It can be observed that, if Cgd is equal to zero, Z2 and Z3
become infinite or can be neglected. The input impedance is
equal to Z1 and degenerates to a conventional expression form,
where an inductor Ls at the source as well as another inductor Lg at the gate produces an input matching point which is
narrowband. However, in the MMW band, Cgd cannot be neglected, who reflects Zd to the input impedance, providing a
new possibility for input matching. As the reactance of Zd is
usually tuned out at the operational band, it is valid to assume
Zd D Rd in the analysis. From Equations (2)–(4) and with the
existence of Lg , three resonant angle frequencies can be decided if they are far away from each other:
Z3 D sLs C
105010-2
1
;
!I D p
.Lg C Ls /Cgs
(5)
J. Semicond. 2015, 36(10)
Wang Chong et al.
!II D p
!II D s
1
;
Lg Cgd
(6)
1
Cgs
Lg C 1 C
Cgd gm Rd
:
(7)
Ls Cgd gm Rd
In Equation (5), the conventional matching point due to
source inductance degeneration emerges. The !II in Equation
(6) is much higher than the operational band and Z2 can be
omitted. At !III , the real part of Z3 can be calculated:
R3 D
Ls
1
C
:
gm
Cgd Rd
(8)
Figure 4. NFmin of the CS and cascode topology.
In general, 1/gm approaches 50  such as in the commongate input matching situations. Therefore, the second term in
the above formula should be as small as possible. Given that
the first term in Equation (2) is equal to 50 , it should satisfy:
gm Rd Cgs
:
Cgd
(9)
This illustrates that if the Rd is sufficiently high, a second
input matching point will be created at !III , which is far below !I according to Equations (7) and (9), forming a wideband
input matching character. In fact, the Miller effect works due
to Cgd , and the higher the voltage gain, the larger the impact
of Cgd . Therefore, a large Rd is needed to provide a high voltage gain from the drain to the gate. For cascode topology, the
common gate (CG) transistor usually offers low resistance at
the drain of the common-source (CS) transistor, enhancing the
reverse isolation, but it is not beneficial for input matching. In
order to achieve a large Rd , CS with passive loads such as LC
networks or T-shape networks can be used as the first stage
topology as shown in Figure 1.
2.2. Optimization of noise figure
Noise figure is the most important factor in the performance of the LNA, since it is added to the whole system counterpart directly. Generally, there are several stages for MMW
LNAs in order to provide sufficient power gain, and the first
stage is the dominant noise contributor to the LNA as well as
the whole receiver. Thus, the structure of the first stage needs
to be chosen carefully.
In Figure 1, CS topology in the first stage is selected not
only for wideband input matching, but also for minimum noise
figure purposes. Traditionally, CS, CG and cascode are usually used as the first stage in LNA design. Among them, CS
exhibits the lowest noise, CG is easy to match while cascode
provides the highest power gain and reverse isolation. In the
MMW band, CS and cascode offer more advantages than CG.
In order to illustrate the difference in noise performance between CS and cascode, we show their minimum noise figure,
NFmin , in Figure 4, where we can observe the gap between them
increasing rapidly as frequency is enhanced.
Actually, the contribution of the CG transistor in the cascode to the whole noise figure can be expressed asŒ8 :
NFcg D 4Rs gdo
!o2
!T2
Cx2 2
! ;
2 o
gm
(10)
where Rs is the source resistance, is a bias-dependent factor,
gdo is the zero-bias drain conductance of the device, Cx is the
parasitic capacitance at the source of the common-gate transistor, !o is the operating angular frequency and !T is the cut-off
angular frequency of the transistors. From Equation (10), we
can draw the conclusion that the noise of the cascode topology rises rapidly as frequency is enhanced due to the relatively
large value of !o versus !T and the existence of Cx . Although
an inductor Lm can be inserted to resonate out Cx at the desired
frequency, the finite Q factor of the inductor also degrades the
noise performance. Therefore, CS is the better choice for the
first stage for noise considerations. The noise figure is also
affected by the current density of the transistor. There is an
optimum density for the noise figure, and the value is about
0.15 mA/m, independent of the CMOS technology node or
foundryŒ9 .
The minimum noise figure occurs when the source
impedance Zs equals the optimal noise source impedance Zopt ,
i.e., achieving noise matching. For the topology shown in Figure 1, the real part of Zopt , Ropt , is inversely proportional to the
width of the input transistor. For a fixed finger width, by easily varying the number of the fingers, Ropt can be equal to the
source resistance, 50 . Then a source inductor Ls is used for
input impedance matching, whose value does not affect Ropt .
Finally, an inductor Lg is added at the gate and the sum inductance of Lg and Ls resonates with Cgs at !o . The value of
Lg for noise matching is close to the counterpart of impedance
matching. Therefore, it is able to achieve noise matching and
impedance matching simultaneously by using source inductance degeneration topology, which is a very attractive factor
in LNA design. Following the above procedure, it is possible
to achieve the minimum noise figure for a given technology.
2.3. Gain boosting techniques
According to the above analysis, CS possesses better performance than cascode in both impedance matching and the
noise figure for the first stage, at the price of loss in gain. In
order to provide sufficient gain to suppress the noise contri-
105010-3
J. Semicond. 2015, 36(10)
Wang Chong et al.
Figure 7. Amplifier with an LC inter-stage network.
Figure 5. Cascode topology with gain boosting techniques.
.gm2 C j!Cgs2 /Rd1
gm1 :
! 2 Lf Cgs2 C .gm2 C j!Cgs2 /Rd1
(13)
It can be seen in Equation (13) that the existence of Lf
leads to the transconductance of the cascode approach to gm1 at
higher frequencies. Considering the much larger output resistance of the cascode relative to CS, higher gain can be achieved
with cascode as shown in Figure 5.
Equation (12) reveals the potential instability of this topology since negative resistance will emerge if ! exceeds !r ,
where !r is defined by:
gcas D
Figure 6. CG transistor with gate feedback inductor.
bution of the following modules such as mixers, a multi-stage
structure must be used for the LNA.
In Figure 1, there are three stages. Apart from the first CS
stage, the last two stages are cascode, as shown in Figure 5,
where ZL represents the T-shape load in Figure 1. Compared
with conventional cascode topology, two inductors Lm and Lf
are added to the middle-node and the gate of M2 respectively.
They represent two gain boosting techniques with different effects in the circuit.
The parasitic capacitance at the drain of M1 and the source
of M2 exhibit small impedance in the MMW band, bypassing
most of the RF current from the drain of M1 to the ground. An
inductor Lm can be inserted in the cascode, forming an artificial
transmission line, to neutralize the effect of the capacitance.
The inductance Lf at the gate of M2 introduces a positive
feedback to the gate–source capacitor Cgs2 , raising the voltage
across Cgs2 Œ10 , as shown in Figure 6. The voltage across Lf has
a contrary sign with ugs and the relationship between ugs and
us is:
1
ugs D
us :
(11)
1 ! 2 Lf Cgs2
Then, the input impedance Zs at the source of M2 can be
obtained as:
1 ! 2 Lf Cgs2
:
(12)
Zs D
gm2 C j!Cgs2
It is shown that Lf can lower Zs as frequency increases.
Therefore, more RF current at the drain of M1 in Figure 5 will
flow into the source of M2, enhancing the transconductance of
the cascode. The output resistance at the drain of M1, which is
represented by Rd1 , also conducts a part of the RF current to
ground. If Cd1 and Cs2 are tuned out by Lm , the transconductance of the cascode in Figure 5 can be expressed as:
Iout
D
Vin
1
!r D p
1
:
Lf Cgs2
(14)
It is suggested that Lf should not be very large in the design
and attention must be paid to the stability in simulation.
2.4. Bandwidth extension with T-shape networks
As mentioned before, broad bandwidth is beneficial to the
design, since the circuits with broad bandwidth are insusceptible to parasitic effects, process corners or even simulation errors. In a robust design, the gain in the desired band should
be flat, which can be guaranteed by a broad bandwidth. Frequently, LC networks are the selected topology between the
stages as shown in Figure 7, where the input capacitance Cgs of
the next stage is used as the capacitor of the resonant LC tank.
The LC network transfers the maximum voltage gain at the resonant frequency, but the gain drops rapidly as frequency deviates from the resonance point. Thus, the LC network is only
suitable for narrowband amplifiers, restricting its application
in 60 GHz broadband systems.
T-shape networks between stages are used in Figure 1 to
extend bandwidth. Compared with LC networks, T-shape networks promise broader bandwidthŒ11 . In order to understand
the principle, the T-shape network in Figure 1 is redrawn in
Figure 8, where Iin is the current source of the former stage,
whose parasitic capacitance is represented by C1 . La , Lb and
Lc denote T-shape networks L1 L2 L3 , L4 L5 L6 or L7 L8 L9 in
Figure 1. C2 is the input capacitance of the following stage. In
particular, Lc only provides one freedom in the design and it
can be merged with C2 . We can write the transfer function from
Iin to Vout :
105010-4
J. Semicond. 2015, 36(10)
Wang Chong et al.
Figure 8. T-shape inter-stage network.
Figure 10. S21 and noise figure.
Figure 9. Die photograph of the designed LNA.
1
1
sLa C sLb ==
sLc ==
sC2
sC2
:
1
1
s 2 La C1 C sC1 sLb ==
C 1 sLa C sLb ==
sC2
sC2
(15)
Simplifying the above formula, we can obtain:
Vout
D
Iin
Vout
sLb
D 4
:
2
Iin
s La C1 Lb C2 C s .La C1 C Lb C1 C Lb C2 / C 1
(16)
There are two real poles in the denominator of the above
formula, so maximum gain is achieved at two different frequencies. Therefore, bandwidth can be extended by properly
choosing the values of La , Lb and C2 .
The main drawback of the circuit in Figure 1 is that there
are many inductors which may occupy a large area in the layout. Fortunately, the required inductance may decrease significantly as frequency is enhanced to the MMW band. Furthermore, at MMW frequencies, transmission lines can act as both
inductors and connections between devices. With the use of an
EM simulation tool, the spiral inductors and transmission lines
can be designed with flexibility. Finally, the compact layout
shown in Figure 9 is obtained.
3. Measurement and discussion
Manufactured by CMOS 65 nm LP technology, the chip
occupies an area of 900 550 m2 . In Figure 9, the RF signal
inputs and outputs from the left and right GSG pads, respectively, while the five DC pads on the top of the chip provide
the power supply as well as bias voltage needed in the circuit.
The S parameters are measured by Agilent PNA-X N5247A
up to 67 GHz. The measured and simulated S21 are shown in
Figure 11. Measured and simulated S11 /S22 .
Figure 10, where it can be seen that the operational frequency
moves down about 4 GHz. Thanks to the broadband character
of the LNA, the 3-dB bandwidth exceeds 20 GHz (47–67 GHz)
and covers the desired band (59–64 GHz) even though there is
a drop in the frequency. The maximum gain of 17.3 dB occurs at 60 GHz. The simulated/measured noise figures are also
shown in Figure 10. The measured minimum value is 4.9 dB
at 61 GHz, which is 0.2 dB lower than the simulated one.
The measured and simulated S11 and S22 are shown in Figure 11. The S11 is lower than –8 dB from 46 to 65 GHz and S22
is lower than –10 dB from 45 to 65 GHz. The loss in S11 may
originate from the inaccurate modeling of the pad. The reducing tendency of the power gain as input power rises is shown
in Figure 12, where it can be observed that the input 1 dB compression point is –17 dBm.
Consuming 19 mA from a 1.2 V supply, the LNA performs excellently in terms of power gain, bandwidth, noise and
impedance matching. In order to illustrate the advantages of the
designed LNA, it is compared with some other works in Table 1
and their FOMsŒ12 are calculated using Equation (17), which
show that the LNA in this work exhibits the highest FOM of
15.2 and the widest bandwidth of 20 GHz.
105010-5
FOM ŒGHz=mW D
S21 Œ1 BW ŒGHz
:
.NF 1/ Œ1 PD ŒmW
(17)
J. Semicond. 2015, 36(10)
Parameter
CMOS technology
Gain (dB)
3 dB BW (GHz)
NF (dB)
PD (mW)
FOM (GHz/mW)
Wang Chong et al.
Table 1. Performance summary and comparison.
Reference [9]
Reference [10]
Reference [12]
Reference [13]
90 nm
65 nm
90 nm
90 nm
14.6
18
11.4
15.5
5
12.2
12.5
8
4.5*
4
3.9
6.5
24
28.8
14.1
86
2.1
10.7
4.9
0.73
This work
65 nm
17.3
20
4.9
22.8
15.2
* Stands for simulated
References
Figure 12. Power gain versus input power.
Compared with the circuit in Reference [10] for example,
which is fabricated with the same technology, the circuit in this
work exhibits lower power consumption but lost gain and noise
figure, due to its smaller transconductance in the first stage.
But the main reason their FOMs differ is because the circuit in
Reference [10] excludes T-shape networks between the stages,
constraining its bandwidth to only 12.2 GHz, about 60% of the
value in this work.
4. Conclusions
This paper presented a wideband LNA suitable for unlicensed 60 GHz band applications. Optimization methods for
design specifications such as input matching, noise figure,
power gain and bandwidth are introduced. From the measurement results, the LNA possesses a 17.3 dB gain with 20 GHz
bandwidth (47–67 GHz) and a 4.9 dB noise figure while consuming 19 mA from a 1.2 supply. Design methodologies for
the MMW LNA can be attained from this successful design,
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