Introduction to
CMOS VLSI
Design
Lecture 20:
Package, Power, and I/O
David Harris
Harvey Mudd College
Spring 2004
Outline
q
q
q
q
Packaging
Power Distribution
I/O
Synchronization
20: Package, Power, and I/O
CMOS VLSI Design
Slide 2
Packages
q Package functions
– Electrical connection of signals and power from
chip to board
– Little delay or distortion
– Mechanical connection of chip to board
– Removes heat produced on chip
– Protects chip from mechanical damage
– Compatible with thermal expansion
– Inexpensive to manufacture and test
20: Package, Power, and I/O
CMOS VLSI Design
Slide 3
Package Types
q Through-hole vs. surface mount
20: Package, Power, and I/O
CMOS VLSI Design
Slide 4
Multichip Modules
q Pentium Pro MCM
– Fast connection of CPU to cache
– Expensive, requires known good dice
20: Package, Power, and I/O
CMOS VLSI Design
Slide 5
Chip-to-Package Bonding
q Traditionally, chip is surrounded by pad frame
– Metal pads on 100 – 200 µm pitch
– Gold bond wires attach pads to package
– Lead frame distributes signals in package
– Metal heat spreader helps with cooling
20: Package, Power, and I/O
CMOS VLSI Design
Slide 6
Advanced Packages
q Bond wires contribute parasitic inductance
q Fancy packages have many signal, power layers
– Like tiny printed circuit boards
q Flip-chip places connections across surface of die
rather than around periphery
– Top level metal pads covered with solder balls
– Chip flips upside down
– Carefully aligned to package (done blind!)
– Heated to melt balls
– Also called C4 (Controlled Collapse Chip Connection)
20: Package, Power, and I/O
CMOS VLSI Design
Slide 7
Package Parasitics
q Use many VDD, GND in parallel
– Inductance, IDD
Package
Signal Pads
Signal Pins
20: Package, Power, and I/O
Chip
VDD
Bond Wire
Lead Frame
Board
V DD
Package
Capacitor
Chip
Chip
GND
CMOS VLSI Design
Board
GND
Slide 8
Heat Dissipation
q 60 W light bulb has surface area of 120 cm2
q Itanium 2 die dissipates 130 W over 4 cm2
– Chips have enormous power densities
– Cooling is a serious challenge
q Package spreads heat to larger surface area
– Heat sinks may increase surface area further
– Fans increase airflow rate over surface area
– Liquid cooling used in extreme cases ($$$)
20: Package, Power, and I/O
CMOS VLSI Design
Slide 9
Thermal Resistance
q ∆T = θjaP
– ∆T: temperature rise on chip
– θja: thermal resistance of chip junction to ambient
– P: power dissipation on chip
q Thermal resistances combine like resistors
– Series and parallel
q θja = θjp + θpa
– Series combination
20: Package, Power, and I/O
CMOS VLSI Design
Slide 10
Example
q Your chip has a heat sink with a thermal resistance
to the package of 4.0° C/W.
q The resistance from chip to package is 1° C/W.
q The system box ambient temperature may reach
55° C.
q The chip temperature must not exceed 100° C.
q What is the maximum chip power dissipation?
20: Package, Power, and I/O
CMOS VLSI Design
Slide 11
Example
q Your chip has a heat sink with a thermal resistance
to the package of 4.0° C/W.
q The resistance from chip to package is 1° C/W.
q The system box ambient temperature may reach
55° C.
q The chip temperature must not exceed 100° C.
q What is the maximum chip power dissipation?
q (100-55 C) / (4 + 1 C/W) = 9 W
20: Package, Power, and I/O
CMOS VLSI Design
Slide 12
Power Distribution
q Power Distribution Network functions
– Carry current from pads to transistors on chip
– Maintain stable voltage with low noise
– Provide average and peak power demands
– Provide current return paths for signals
– Avoid electromigration & self-heating wearout
– Consume little chip area and wire
– Easy to lay out
20: Package, Power, and I/O
CMOS VLSI Design
Slide 13
Power Requirements
q VDD = VDDnominal – Vdroop
q Want Vdroop < +/- 10% of VDD
q Sources of Vdroop
– IR drops
– L di/dt noise
q IDD changes on many time scales
Power
Max
clock gating
Average
Min
Time
20: Package, Power, and I/O
CMOS VLSI Design
Slide 14
Power System Model
q Power comes from regulator on system board
– Board and package add parasitic R and L
– Bypass capacitors help stabilize supply voltage
– But capacitors also have parasitic R and L
q Simulate system for time and frequency responses
Voltage
Regulator
VDD
Bulk
Capacitor
Printed Circuit
Board Planes
Ceramic
Capacitor
Board
20: Package, Power, and I/O
Package
and Pins
Solder
Bumps
Package
Capacitor
On-Chip
Capacitor
Chip
On-Chip
Current Demand
Package
CMOS VLSI Design
Slide 15
Bypass Capacitors
q Need low supply impedance at all frequencies
q Ideal capacitors have impedance decreasing with ω
q Real capacitors have parasitic R and L
– Leads to resonant frequency of capacitor
10
2
1
10
1 µF
0.25 nH
impedance
0.03 Ω
10
10
10
0
-1
-2
10
4
10
5
10
6
10
7
10
8
10
9
10
10
frequency (Hz)
20: Package, Power, and I/O
CMOS VLSI Design
Slide 16
Frequency Response
q Use multiple capacitors in parallel
– Large capacitor near regulator has low impedance
at low frequencies
– But also has a low self-resonant frequency
– Small capacitors near chip and on chip have low
impedance at high frequencies
q Choose caps to get low impedance at all frequencies
impedance
frequency (Hz)
20: Package, Power, and I/O
CMOS VLSI Design
Slide 17
Input / Output
q Input/Output System functions
– Communicate between chip and external world
– Drive large capacitance off chip
– Operate at compatible voltage levels
– Provide adequate bandwidth
– Limit slew rates to control di/dt noise
– Protect chip against electrostatic discharge
– Use small number of pins (low cost)
20: Package, Power, and I/O
CMOS VLSI Design
Slide 18
I/O Pad Design
q Pad types
– VDD / GND
– Output
– Input
– Bidirectional
– Analog
20: Package, Power, and I/O
CMOS VLSI Design
Slide 19
Output Pads
q Drive large off-chip loads (2 – 50 pF)
– With suitable rise/fall times
– Requires chain of successively larger buffers
q Guard rings to protect against latchup
– Noise below GND injects charge into substrate
– Large nMOS output transistor
– p+ inner guard ring
– n+ outer guard ring
• In n-well
20: Package, Power, and I/O
CMOS VLSI Design
Slide 20
Input Pads
q Level conversion
– Higher or lower off-chip V
– May need thick oxide gates
q Noise filtering
A
– Schmitt trigger
– Hysteresis changes VIH, VIL
VDDH
A
VDDL
Y
VDDL
A
Y
weak
Y
Y
weak
A
q Protection against electrostatic discharge
20: Package, Power, and I/O
CMOS VLSI Design
Slide 21
ESD Protection
q Static electricity builds up on your body
– Shock delivered to a chip can fry thin gates
– Must dissipate this energy in protection circuits
before it reaches the gates
Diode
clamps
q ESD protection circuits
R
PAD
– Current limiting resistor
Thin
Current
gate
limiting
oxides
– Diode clamps
resistor
q ESD testing
1500 Ω
– Human body model
100 pF
– Views human as charged capacitor
20: Package, Power, and I/O
CMOS VLSI Design
Device
Under
Test
Slide 22
Bidirectional Pads
q Combine input and output pad
q Need tristate driver on output
– Use enable signal to set direction
– Optimized tristate avoids huge series transistors
PAD
En
Din
Dout
NAND
Dout
En
Y
Dout
NOR
20: Package, Power, and I/O
CMOS VLSI Design
Slide 23
Analog Pads
q Pass analog voltages directly in or out of chip
– No buffering
– Protection circuits must not distort voltages
20: Package, Power, and I/O
CMOS VLSI Design
Slide 24
MOSIS I/O Pad
q 1.6 µm two-metal process
– Protection resistors
– Protection diodes
– Guard rings
– Field oxide clamps
PAD
600/3
264 Ω
185 Ω
Out
240
48
90
160
20
40
En
In
Out
In_unbuffered
20: Package, Power, and I/O
In_b
CMOS VLSI Design
Slide 25