Vol. 37, No. 2
Journal of Semiconductors
February 2016
An ultra-low-voltage rectifier for PE energy harvesting applications
Wang Jingmin(王静敏), Yang Zheng(杨正), Zhu Zhangming(朱樟明)Ž ,
and Yang Yintang(杨银堂)
School of Microelectronics, Xidian University, Xi’an 710071, China
Abstract: An ultra low voltage rectifier with high power conversion efficiency (PCE) for PE energy harvesting applications is presented in this paper. This is achieved by utilizing the DTMOS which the body terminal is connected
to the gate terminal in a diode connected transistor. This implementation facilitates the rectifier with dynamic control over the threshold voltage. Moreover, we use input powered to take the place of output powered to reduce the
power loss and thereby increasing the power conversion efficiency. Based on standard SMIC 0.18 m CMOS technology, the simulation results show that the voltage conversion efficiency and the power conversion efficiency can
reach up to 90.5% and 95.5% respectively, when the input voltage equals to 0.2 V @ 100 Hz with load resistance
50 k. Input voltages with frequencies in the range of 10 Hz–1 kHz can be rectified.
Key words: PE energy harvesting; DTMOS; input powered; active rectifier
DOI: 10.1088/1674-4926/37/2/025004
PACS: 85.40.-e
EEACC: 2570
1. Introduction
With the increasing demand for portable electronic devices, replacement or recharging of batteries plays a significant
role in the development of microelectronics. In this case, energy harvesting systems have been researched and developed
in recent yearsŒ1 . Energy can be harvested from ambient environments such as mechanical, thermal, light, electromagnetic,
the human body, and so on to replace traditional sources. One
of the most popular and prominent methods of energy harvesting is by using piezoelectric material. Representative piezoelectric materials can be categorized into piezoceramics and
piezopolymers. Piezoelectric vibration harvesting is attractive
mainly due to the simplicity of piezoelectric transduction and
the piezoelectric systems can be easily implemented into a wide
variety of applications, especially in wearable healthcare applicationsŒ2 . Since the energy harvesting can generate mW or W
level power, the output of the piezoelectric materials is usually
an AC signal below 1 V. Therefore, a rectifier is needed to produce a dc supply source.
The most common rectifiers for the PE energy harvesting
systems are active rectifiersŒ3; 4 . The structure of an active rectifier is shown in Figure 1. The circuit consists of two stages:
the MOS full wave rectifier and the active diode. The full wave
rectifier converts the negative half waves of the input signal
into positive ones. The active diode as a second stage is to control the current direction, which could be either a conventional
diode connected PMOS or an active diode. For the low voltage
and small reverse leakage current, the active diode is more appropriate. In Figure 1(a), an active diode is composed of one
PMOS switch and one comparator. One problem for the PMOS
switch is the high threshold voltage in the conducting mode,
which is not available for the low voltage PE energy harvesting.
To obtain high voltage gain and high power conversion
with low leakage losses and fast switching, in our work, we use
the DTMOS in the PMOS switch which can dynamically alter
the threshold voltage. In this way the minimum input voltage
could be as low as 0.18 V. Moreover, we use input powered
to take the place of output powered to reduce the power loss
and thereby increasing the power conversion efficiency. The
structure of the proposed rectifier is shown in Figure 1(b).
The paper is organized as follows: Section 2 investigates
the principle of DTMOS architecture, Section 3 describes the
analysis and design of the proposed rectifier, Section 4 shows
the simulation results and discussion, and finally the conclusion is presented in Section 5.
2. The principle of DTMOS architecture
In a standard CMOS process, a diode is commonly replaced with a diode-connected MOS transistor, which is easier
to implement. The conventional way to implement the diode
connected MOS (BTMOS) with parasitic diodes is shown in
Figure 2(a), in which the gate terminal is connected to the drain
terminal and the body terminal is tied to the source terminal.
The drain current through the transistor is composed of a channel current plus the current through the parasitic diode D2 since
diode D1 is shorted due to the body-source tie. This usual connection imposes a disadvantage during the OFF-state, since it
allows the high reverse current, due to the direct current in the
parasitic diode, which rises exponentially with the increase in
reverse bias voltage.
To overcome the limitation, one possible solution is to implement CMOS transistors with dynamic VTH . In DTMOS architectureŒ5 as shown in Figure 2(b), the gate and body of
the device are connected together to dynamically change the
threshold voltage of the transistor, by utilizing the relation in
Equation (1).
* Project supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033) and the National
High-Tech Program of China (No. 2013AA014103).
† Corresponding author. Email: zmyh@263.net
Received 9 June 2015, revised manuscript received 2 August 2015
© 2016 Chinese Institute of Electronics
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Wang Jingmin et al.
Figure 1. The structure of an active rectifier. (a) Conventional active rectifier. (b) Proposed active rectifier.
Figure 3. Schematic of the negative voltage converter (NVC) using
DTMOS architecture.
half waves of the input signal into positive ones. The active
diode as a second stage is to control the current direction.
3.1. Negative voltage converter
Figure 2. (a) BTMOS architecture. (b) DTMOS architecture. (c)
PMOS threshold voltage variation with body-source voltage in SMIC
0.18 m CMOS process.
p
VTH D VTH0 C . j2F
VBS j
p
j2F j/:
(1)
In DTMOS biasing parasitic diode D2 is short circuited
due to the gate-body tie up. This not only improves the forward
conduction current but also minimizes the reverse conduction
leakage current. Figure 2(c) clearly shows that in the DTMOS
biased transistor, the VTH varies more than 35% compared with
the BTMOS biased transistor.
3. The proposed ultra low voltage rectifier circuit
As shown in Figure 1(b), the structure of the proposed
rectifier consists of two stages: the negative voltage converter
(NVC) and the active diode. The NVC converts the negative
The first stage is used to convert the negative half waves of
the input wave into positive ones, which is achieved with only
four standard CMOS transistors. Figure 3 shows the schematic
of the negative voltage converter (NVC). During the positive
half period of the input (VIN1 > VIN2 /, the transistors P1 and N2
will conduct when the input voltage increases and gets larger
than jVTHP j and VTHN . Thus, current can flow from Vin1 over P1
and the A node to the output node and then back to Vin2 over
the B node and N2. Similarly, for the negative half period of the
input, P2 and N1 are conducted and terminal A is connected to
Vin2 . Therefore, the high potential of VIN is always at node A,
while the low potential of VIN is always at node B.
In a standard CMOS process, the body terminal of the
NMOS (N1 and N2) is connected to the ground and the body
terminal of the PMOS (P1 and P2) uses DTMOS architecture.
Compared with the NVCs in References [5, 6] which adopt a
body bias technique, our negative voltage converter circuit is
simple, and does not require other devices, which results in less
chip area.
3.2. Active diode
Once the input voltage exceeds the threshold voltage, current backflow occurs, and the storage capacitor directly connected to the rectifier will discharge. Therefore it is necessary
to add a second stage to control the direction of the current.
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Wang Jingmin et al.
Figure 4. Schematic of the active diode. (a) PMOS switch. (b) Input-powered comparator.
Since the threshold voltage in a conventional diode connected
MOS transistor will result in a low efficiency, so an active
diode is adopted here. The conduction voltage drop of the DTMOS is smaller than the BTMOS diode, so the active diode
uses DTMOS as an ideal switch.
As shown in Figure 1(b), the active diode is composed of
a comparator and a PMOS switch. The PMOS switch (PMS)
is controlled by the comparator. Its drain and source terminals
are equivalent to the anode and cathode terminals of a diode
respectively. The comparator detects the voltage between these
two terminals: when VOUT is higher than VNVC , the comparator
outputs a high voltage to the gate terminal, which turns off the
PMS to prevent the reverse current. Otherwise if VOUT is lower
than VNVC , the comparator outputs a low voltage to turn on the
PMS. To reduce the on resistance, a large size of PMS should be
chosen, but it could increase the area and the gate capacitance
accordingly. Therefore, the comparator should be sufficient to
drive a large size PMOS transistor. In addition, a bypass PMOS
diode, PMBD, in parallel with the PMS is added in the circuit
to ensure that the active diode can be safe to open in all process
corners, as Figure 4(b) shows. It enhances the reliability of the
active diode under worst case conditions, although there will
be some area overhead. After the active diode opens, PMBD
will stop working and keep into a high impedance state.
Compared with the PMOS switch in References [5, 6],
which adopt the body bias technique, our PMOS switch is simple, and also does not require other devices, which results in
less chip area.
The comparator is the critical part for an active diode.
In our rectifier, a bulk-driven comparator is used. Due to the
fact that the power consumption of the comparator should be
very low, the transistors of the comparator are working in the
sub-threshold region. Moreover, compared with the common
comparators, the differential pair is powered by the VNVC directly. When the input voltage of the comparator is not high
enough, the comparator automatically stops working to save
energy consumption and improve the system efficiencyŒ6 . The
architecture of the comparator is shown in Figure 4(b).
Figure 5. The simulation waveforms of the proposed rectifier at VIN
D 200 mV.
100 Hz, the load resistance RL is 50 k, and capacitance CL is
10 F.
For PE energy applications, the minimum input voltage
with available voltage conversion efficiency and power conversion efficiency is very important. Figure 5 shows the overall simulation waveforms of the rectifier at VIN D 200 mV. As
can be seen from Figure 5, the output voltage of the rectifier
is 181 mV and the voltage drop of the rectifier is only 19 mV,
thus the voltage conversion efficiency is as high as 90.5%.
The voltage efficiency is expressed as
v D
(2)
The voltage efficiency at different process corners is
shown in Figure 6. As can be observed in Figure 6, the voltage
efficiency can achieve 85.5% when the input voltage equals to
0.18 V under the TT corner, and changes little with different
process corners.
The power efficiency is expressed as
1 R t CT
Vout .t / Iout .t/ dt
t
T
100%;
P D
1 R tCT
Vin .t / Iin .t/ dt
T t
4. Simulation results
Based on SMIC 0.18 m standard CMOS technology, the
proposed rectifier is simulated and verified. Suppose the default input voltage amplitude is 200 mV and the frequency is
vout
100%:
vin
(3)
where VIN and IIN are the input voltage and current, VOUT is
the output voltage and IOUT is the output current delivered to
the load.
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Wang Jingmin et al.
Figure 6. The voltage efficiency of the proposed rectifier at different
process corners.
Table 1. Performance summary and comparisons.
Parameter
Reference
Reference
This work*
[3]*
[4]*
Technique (m) 0.35
0.18
0.18
Minimum input 0.3
0.25
0.2
voltage (V)
Voltage
effi- 90
90
90.5
ciency (%)
Power
effi- 90
80
95.5
ciency (%)
RL D 50 k RL D 40 k RL D 50 k
*The results are obtained through the simulation.
Figure 7. (a) The power efficiency versus difference load resistance.
(b) The power efficiency versus input voltage.
5. Conclusion
The rectifiers should be able to extract the maximum
power available from the PE harvester. According to the maximum power theory, maximum power transfer is realized when
the load impedance is equal to the Thevenin impedance. Figure 7(a) reports the power efficiency with difference load resistance at different frequency. When the frequency is 100 Hz, the
power efficiency can achieve the maximum power efficiency
of 95.5% at the load resistance of 50 k. All the efficiency
can reach up to 80% in a wide load range 10–300 k under
10 and 100 Hz. As can be observed in Figure 7(a), the voltage
efficiencies at 10 and 100 Hz are nearly the same, which are
higher than at 1 kHz. Since the higher frequency will result in
more power loss in the large size transistors of NVC and the
PMOS switch, the maximum frequency of our rectifier with a
high efficiency is around 1 kHz and it is enough for most PE
energy applications.
Figure 7(b) shows the power conversion efficiency of the
DTMOS and the BTMOS circuits. It can be seen from the figure that the DTMOS rectifier obtains higher power conversion
efficiency than the BTMOS circuit. For the DTMOS circuit, it
can be seen that the power efficiency reaches 85% when the
input voltage equals to 0.16 V, and the maximum efficiency
can be up to 95.5% when the input voltage equals to 0.2 V.
In Table 1, the proposed rectifier is compared with the
other reported rectifiers. It is difficult to make a fair comparison due to the differences in the PE transducer, design environments and processing technology; however, the overall performance of our rectifier is better, which can be seen from the
Table 1.
Based on SMIC 0.18 m standard CMOS technology, a
low voltage rectifier with high power conversion efficiency
(PCE) for PE energy harvesting applications is proposed in
this paper. This is achieved by utilizing the DTMOS, which
the body terminal is connected to the gate terminal in the diode
connected transistor. This implementation facilitates the rectifier with dynamic control over the threshold voltage. Furthermore, the active diodes are used to reduce the voltage drop and
thereby increase the power extraction and conversion capability. The simulation results show the voltage conversion efficiency and the power conversion efficiency can reach up to
90.5% and 95.5% respectively, when the input voltage equals
to 0.2 V @ 100 Hz with load resistance 50 k. Input voltages
with frequencies in the range of 10 Hz–1 kHz can be rectified.
Although our paper only provides simulation results, we considered all the situations to compensate this weakness. So the
results obtained are persuasive. Therefore, the proposed rectifier can be well suited to piezoelectric energy harvesting systems.
References
[1] Nguyen T T, Feng T, Häfliger P. Hybrid CMOS rectifier based
on synergistic RF-piezoelectric energy scavenging. IEEE Trans
Circuits Syst I: Regular Papers, 2014, 61(12): 3330
[2] Wahbah M, Alhawari M, Mohammad B. Characterization of human body-based thermal and vibration energy harvesting for
wearable devices. IEEE J Emerging and Selected Topics in Circuits and Systems, 2014, 4(3): 354
[3] Peters C, Handwerker J, Maurath D, et al. A sub-500 mV highly
025004-4
J. Semicond. 2016, 37(2)
Wang Jingmin et al.
efficient active rectifier for energy harvesting applications. IEEE
Trans Circuits Syst I: Regular Papers, 2011, 58(7): 1542
[4] Yang Zheng, Li Yani, Wang Jingmin, et al. A highly efficient
interface circuit for ultra low voltage energy harvesting. IEICE
ELEX, 2013, 10(24): 1
[5] Chouhan S S, Halonen K. The design and implementation of DTMOS biased all PMOS rectifier for RF energy harvesting. IEEE
12th International New Circuits and Systems Conference (NEWCAS), 2014: 444
[6] Rao Y, Arnold D P. An input-powered vibrational energy harvesting interface circuit with zero standby power. IEEE Trans
Power Electron, 2011, 26(12): 3524
[7] Kim H S, Kim J H, Kim J. A review of piezoelectric energy harvesting based on vibration. International Journal of Precision Engineering and Manufacturing, 2011, 12(6): 1129
[8] Shen Jinpeng, Wang Bo, Liu Shan, et al A passive UHF RFID
tag with a dynamic-Vth -cancellation rectifier. Journal of Semiconductors, 2013, 34(9): 095005
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