LT6411
650MHz Differential ADC
Driver/Dual Selectable
Gain Amplifier
DESCRIPTION
FEATURES
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650MHz –3dB Small-Signal Bandwidth
600MHz –3dB Large-Signal Bandwidth
High Slew Rate: 3300V/µs
Easily Configured for Single-Ended to Differential
Conversion
200MHz ±0.1dB Bandwidth
User Selectable Gain of +1, +2 and –1
No External Resistors Required
46.5dBm Equivalent OIP3 at 30MHz When Driving an
ADC
IM3 with 2VP-P Composite, Differential Output:
–87dBc at 30MHz, –83dBc at 70MHz
–77dB SFDR at 30MHz, 2VP-P Differential Output
6ns 0.1% Settling Time for 2V Step
Low Supply Current: 8mA per Ampifier
Differential Gain of 0.02%, Differential Phase of 0.01°
50dB Channel Separation at 100MHz
Wide Supply Range: ±2.25V (4.5V) to ±6.3V (12.6V)
3mm × 3mm 16-Pin QFN Package
The LT®6411 is a dual amplifier with individually selectable
gains of +1, +2 and –1. The amplifiers have excellent distortion performance for driving ADCs as well as excellent
bandwidth and slew rate for video, data transmission and
other high speed applications. Single-ended to differential
conversion with a system gain of 2 is particularly straightforward by configuring one amplifier with a gain of +1
and the other amplifier with a gain of –1. The LT6411 can
be used on split supplies as large as ±6V and on a single
supply as low as 4.5V.
Each amplifier draws only 8mA of quiescent current when
enabled. When disabled, the output pins become high
impedance and each amplifier draws less than 350µA.
The LT6411 is manufactured on Linear Technology’s
proprietary, low voltage, complimentary, bipolar process
and is available in the ultra-compact, 3mm × 3mm, 16pin
QFN package.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
APPLICATIONS
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Differential ADC Driver
Single-Ended to Differential Conversion
Differential Video Line Driver
TYPICAL APPLICATION
30MHz 2-Tone 32768 Point FFT, LT6411
Driving an LTC®2249 14-Bit ADC
Differential ADC Driver
5V
VCC
LT6411
+
–
1.9VDC
30MHz
INPUT
370Ω
370Ω
370Ω
370Ω
–
+
1.9VDC
DGND
VEE
24Ω
AIN–
LTC2249
14-BIT ADC
80Msps
AIN+
24Ω
6411 TA01a
AMPLITUDE (dBFS)
■
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
32768 POINT FFT
TONE 1 AT 29.5MHz, –7dBFS
TONE 2 AT 30.5MHz, –7dBFS
IM3 = –87dBc
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
6411 TA01b
EN
6411f
1
LT6411
ABSOLUTE MAXIMUM RATINGS
PACKAGE/ORDER INFORMATION
(Note 1)
Total Supply Voltage (VCC to VEE) ..........................12.6V
Input Current (Note 2)..........................................±10mA
Output Current (Continuous) ...............................±70mA
EN to DGND Voltage (Note 2) ..................................5.5V
Output Short-Circuit Duration (Note 3) ............ Indefinite
Operating Temperature Range (Note 4) ... –40°C to 85°C
Specified Temperature Range (Note 5) .... –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
Junction Temperature ........................................... 125°C
IN2+
IN2–
IN1–
IN1+
TOP VIEW
16
15
14
13
VEE 1
12 DGND
VEE 2
11 EN
17
VEE 3
10 VCC
NC 4
6
7
8
OUT2
VCC
VEE
OUT1
9
5
VCC
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W
EXPOSED PAD (PIN 17) IS VEE, MUST BE SOLDERED TO PCB
ORDER PART NUMBER
UD PART MARKING*
LT6411CUD
LT6411IUD
LCGP
LCGP
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*Temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, AV = 2, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VDGND = 0V,
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Referred Offset Voltage
VIN = 0V, VOS = VOUT/2
IIN
Input Current
RIN
Input Resistance
VIN = ±1V
CIN
Input Capacitance
f = 100kHz
VCMR
Maximum Input Common Mode Voltage
Minimum Input Common Mode Voltage
PSRR
Power Supply Rejection Ratio
VS (Total) = 4.5V to 12V (Note 6)
●
IPSRR
Input Current Power Supply Rejection
VS (Total) = 4.5V to 12V (Note 6)
●
1
±4
AV ERR
Gain Error
VOUT = ±2V
●
–1.2
±5
AV MATCH
Gain Matching
VOUT = ±2V
VOUT
Maximum Output Voltage Swing
RL = 1k
RL = 150Ω
RL = 150Ω
IS
IEN
MIN
●
●
Supply Current, Per Amplifier
●
●
150
56
±3.70
±3.25
±3.10
●
Supply Current, Disabled, per Amplifier
VEN = 4V
VEN = Open
●
●
Enable Pin Current
VEN = 0.4V
VEN = V+
●
●
–200
TYP
MAX
UNITS
3
±10
±20
mV
mV
–17
±50
µA
500
kΩ
1
pF
VCC – 1
VEE + 1
V
V
62
dB
µA/V
%
±1
%
±3.95
±3.6
V
V
V
8
11
14
mA
mA
22
0.5
350
350
µA
µA
–95
0.5
50
µA
µA
6411f
2
LT6411
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VS = ±5V, AV = 2, RL = 150Ω, CL = 1.5pF, VEN = 0.4V, VDGND = 0V,
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
ISC
Output Short-Circuit Current
RL = 0Ω, VIN = ±1V
SR
Slew Rate
±1V on ±2V Output Step (Note 9)
●
MIN
TYP
MAX
UNITS
±50
±105
mA
1700
3300
V/µs
–3dB BW
Small-Signal –3dB Bandwidth
VOUT = 200mVP-P, Single Ended
650
MHz
0.1dB BW
Gain Flatness ±0.1dB Bandwidth
VOUT = 200mVP-P, Single Ended
200
MHz
FPBW
Full Power Bandwidth 2V Differential
VOUT = 2VP-P Differential, –3dB
600
MHz
Full Power Bandwidth 2V
VOUT = 2VP-P (Note 7)
525
MHz
Full Power Bandwidth 4V
VOUT = 4VP-P (Note 7)
263
MHz
All Hostile Crosstalk
f = 10MHz, VOUT = 2VP-P
f = 100MHz, VOUT = 2VP-P
–75
–50
dB
dB
Settling Time
0.1% to VFINAL, VSTEP = 2V
6
ns
ts
270
tr, tf
Small-Signal Rise and Fall Time
10% to 90%, VOUT = 200mVP-P
550
ps
dG
Differential Gain
(Note 8)
0.02
%
dP
Diffierential Phase
(Note 8)
0.01
Deg
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
VCC = 5V, VEE = 0V, AV = 2, No RLOAD, VEN = 0.4V, VDGND = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Noise/Harmonic Performance Input/Output Characteristics
1MHz Signal
HD
Second/Third Harmonic Distortion
2VP-P Differential
2VP-P Differential, RL = 200Ω Differential
–88
–87
dBc
dBc
IMD31M
Third-Order IMD
2VP-P Differential Composite, f1 = 0.95MHz,
f2 = 1.05MHz
–93
dBc
2VP-P Differential Composite, f1 = 0.95MHz,
f2 = 1.05MHz, RL = 200Ω Differential
–91
dBc
OIP31M
Output Third-Order Intercept
Differential, f1 = 0.95MHz, f2 = 1.05MHz (Note 10)
49.5
dBm
NF
Noise Figure
Single Ended
25.1
dB
en1M
Input Referred Noise Voltage Density
P1dB
1dB Compression Point
8
nV/√Hz
(Note 10)
19.5
dBm
10MHz Signal
HD
Second/Third Harmonic Distortion
2VP-P Differential
2VP-P Differential, RL = 200Ω Differential
–85
–76
dBc
dBc
IMD310M
Third-Order IMD
2VP-P Differential Composite, RL = 1k,
f1 = 9.5MHz, f2 = 10.5MHz
–92
dBc
2VP-P Differential Composite, f1 = 9.5MHz,
f2 = 10.5MHz, RL = 200Ω Differential
–89
dBc
49
dBm
OIP310M
Output Third-Order Intercept
Differential, f1 = 9.5MHz, f2 = 10.5MHz (Note 10)
NF
Noise Figure
Single Ended
en10M
Input Referred Noise Voltage Density
P1dB
1dB Compression Point
(Note 10)
24.7
dB
7.7
nV/√Hz
19.5
dBm
6411f
3
LT6411
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 5V, VEE = 0V, AV = 2, No RLOAD, VEN = 0.4V, VDGND = 0V,
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
30MHz Signal
HD
Second/Third Harmonic Distortion
2VP-P Differential
2VP-P Differential, RL = 200Ω Differential
–77
–64
dBc
dBc
IMD330M
Third-Order IMD
2VP-P Differential Composite, f1 = 29.5MHz,
Differential, f2 = 30.5MHz
–87
dBc
2VP-P Differential Composite, f1 = 29.5MHz,
f2 = 30.5MHz, RL = 200Ω Differential
–75
dBc
OIP330M
Output Third-Order Intercept
Differential, f1 = 29.5MHz, f2 = 30.5MHz (Note 10)
46.5
dBm
NF
Noise Figure
Single Ended
24.6
dB
en30M
Input Referred Noise Voltage Density
7.6
nV/√Hz
P1dB
1dB Compression Point
(Note 10)
19.5
dBm
70MHz Signal
HD
Second/Third Harmonic Distortion
2VP-P Differential
2VP-P Differential, RL = 200Ω Differential
–63
–52
dBc
dBc
IMD370M
Third-Order IMD
2VP-P Differential Composite, f1 = 69.5MHz,
Differential, f2 = 70.5MHz
–83
dBc
2VP-P Differential Composite, f1 = 69.5MHz,
f2 = 70.5MHz, RL = 200Ω Differential
–64
dBc
OIP370M
Output Third-Order Intercept
Differential, f1 = 69.5MHz, f2 = 70.5MHz (Note 10)
44.5
dBm
NF
Noise Figure
Single Ended
24.7
dB
en70M
Input Referred Noise Voltage Density
7.7
nV/√Hz
P1dB
1dB Compression Point
19.5
dBm
(Note 10)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: This parameter is guaranteed to meet specified performance
through design and characterization. It is not production tested.
Note 3: As long as output current and junction temperature are kept
below the Absolute Maximum Ratings, no damage to the part will occur.
Depending on the supply voltage, a heat sink may be required.
Note 4: The LT6411C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 5: The LT6411C is guaranteed to meet specified performance from
0°C to 70°C. The LT6411C is designed, characterized and expected to
meet specified performance from –40°C and 85°C but is not tested or
QA sampled at these temperatures. The LT6411I is guaranteed to meet
specified performance from –40°C to 85°C.
Note 6: The two supply voltage settings for power supply rejection
are shifted from the typical ±VS points for ease of testing. The first
measurement is taken at VCC = 3V, VEE = –1.5V to provide the required 3V
headroom for the enable circuitry to function with EN, DGND and all inputs
connected to 0V. The second measurement is taken at VCC = 8V, VEE = –4V.
Note 7: Full power bandwidth is calculated from the slew rate:
FPBW = SR/(π • VP-P)
Note 8: Differential gain and phase are measured using a Tektronix
TSG120YC/NTSC signal generator and a Tektronix 1780R video
measurement set. The resolution of this equipment is better than 0.05%
and 0.05°. Ten identical amplifier stages were cascaded giving an effective
resolution of better than 0.005% and 0.005°.
Note 9: Slew rate is 100% production tested on channel 1. Slew rate of
channel 2 is guaranteed through design and characterization.
Note 10: Since the LT6411 is a feedback amplifier with low output
impedance, a resistive load is not required when driving an ADC.
Therefore, typical output power is very small. In order to compare the
LT6411 with typical gm amplifiers that require 50Ω output loading, the
LT6411 output voltage swing driving an ADC is converted to OIP3 and
P1dB as if it were driving a 50Ω load.
6411f
4
LT6411
TYPICAL PERFORMANCE CHARACTERISTICS
All measurements are per amplifier with single-ended outputs unless otherwise noted.
Supply Current per Ampifier
vs Supply Voltage
Supply Current per Amplifier
vs Temperature
VEN = 0V
8
VEN = 0.4V
6
VCC = –VEE
VEN, VDGND, VIN+, VIN– = 0V
10 TA = 25°C
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
10
4
12
12
VS = ±5V
RL = ∞
VIN+, VIN– = 0V
2
8
6
4
0
1
2
20
5
0
–5
–10
VS = ±5V
AV = 2
3.5
0
TA = 125°C
–20
4.0
VS = ±5V
VDGND = 0V
–20
TA = 25°C
TA = –55°C
–40
–40
TA = 125°C
–60
TA = –55°C
–80
TA = 25°C
–100
–120
–15
–60
–2.5
5 25 45 65 85 105 125
TEMPERATURE (°C)
–1.5
0.5
–0.5
INPUT VOLTAGE (V)
1.5
6411 G04
5
VS = ±5V
4 RL = 1k
AV = 1
3
–1
–2 TA = –55°C
–3
OUTPUT VOLTAGE (V)
0
4
TA = –55°C
3
5
Output Voltage Swing vs ILOAD
(Output Low)
0
VS = ±5V
AV = 2
VIN = 2V
4
1
3
2
EN PIN VOLTAGE (V)
1
6411 G06
Output Voltage Swing vs ILOAD
(Output High)
5
TA = 25°C
0
6411 G05
Output Voltage vs Input Voltage
2
–140
2.5
TA = 25°C
2
TA = 125°C
1
VS = ±5V
AV = 2
VIN = –2V
–1
OUTPUT VOLTAGE (V)
–20
–55 –35 –15
OUTPUT VOLTAGE (V)
1.0 1.5 2.0 2.5 3.0
EN PIN VOLTAGE (V)
EN Pin Current vs EN Pin Voltage
0
EN PIN CURRENT (µA)
VS = ±5V
VIN = 0V
AV = 2
10
0.5
6411 G03
Positive Input Bias Current
vs Input Voltage
IN+ BIAS CURRENT (µA)
OFFSET VOLTAGE (mV)
0
6411 G02
Output Offset Voltage
vs Temperature
15
4
3 4 5 6 7 8 9 10 11 12
TOTAL SUPPLY VOLTAGE (V)
6411 G01
20
TA = 125°C
6
0
0
5 25 45 65 85 105 125
TEMPERATURE (°C)
TA = 25°C
8
2
2
0
–55 –35 –15
VS = ±5V
VDGND = 0V
VIN+, VIN– = 0V
TA = –55°C
10
SUPPLY CURRENT (mA)
12
Supply Current per Amplifier
vs EN Pin Voltage
TA = 25°C
–2
TA = 125°C
–3
TA = –55°C
–4
–4
TA = 125°C
–5
–4.5 –3.5 –2.5 –1.5 –0.5 0.5 1.5 2.5 3.5 4.5
INPUT VOLTAGE (V)
6411 G07
0
–5
0
10 20 30 40 50 60 70 80 90 100
SOURCE CURRENT (mA)
6411 G08
0
10 20 30 40 50 60 70 80 90 100
SINK CURRENT (mA)
6411 G09
6411f
5
LT6411
TYPICAL PERFORMANCE CHARACTERISTICS
All measurements are per amplifier with single-ended outputs unless otherwise noted.
Positive Input Impedance
vs Frequency
Input Noise Spectral Density
1000
VS = ±5V
AV = 2
TA = 25°C
en
in
10
70
VS = ±5V
VIN = 0V
TA = 25°C
10
1
VS = ±5V
AV = 2
TA = 25°C
±PSRR
60
REJECTION RATIO (dB)
100
PSRR vs Frequency
100
INPUT IMPEDANCE (kΩ)
INPUT NOISE (nV/√Hz OR pA/√Hz)
1000
50
–PSRR
40
+PSRR
30
20
10
1
0.01
0.1
1
FREQUENCY (kHz)
10
0.1
0.01
100
0.1
1
10
FREQUENCY (MHz)
100
6553 G10
9
6.5
6.4
AV = 2, VOUT = 2VP-P
6
NORMALIZED GAIN (dB)
6.3
GAIN (dB)
3
AV = 1, AV = –1,VOUT = 200mVP-P
0
AV = 1, VOUT = 2VP-P
VS = ±5V
RL = 150Ω
TA = 25°C
–6
0.1
1
AV = –1, VOUT = 2VP-P
6.2
6.1
CHANNEL 1
6.0
5.9
CHANNEL 2
5.8
HD3, RL = 200Ω
–50
HD3, RL = ∞
–60
–70
HD2, RL = 200Ω
1
10
100
FREQUENCY (MHz)
HD2, RL = ∞
–90
0
AV = 2, VCC = 5V
–10 VEE = 0V, VCM = 1.6V
RL = ∞
–20
TA = 25°C
–30
10
FREQUENCY (MHz)
100
6411 G16
10
100
FREQUENCY (MHz)
1000
–20
–50
–60
–70
Harmonic Distortion vs Load,
30MHz, Differential Input
0
HD3
VOUT = 2VP-P, DIFFERENTIAL
AV = 2, VCC = 5V
VEE = 0V, VCM = 1.6V
TA = 25°C
–30
–40
–50
–60
–70
HD3
–80
HD2
–90
–100
1
1
6553 G15
–10
–40
–90
–100
CL = 2.2pF
2
–6
0.1
1000
–80
–80
4
–4
DISTORTION (dBc)
DISTORTION (dBc)
DISTORTION (dBc)
–40
6
Harmonic Distortion vs Amplitude,
30MHz, Differential Input
0
–30
CL = 6.8pF
8
6411 G14
Harmonic Distortion vs Frequency,
Differential Input
–20
CL = 12pF
0
5.5
0.1
1000
VS = ±5V
16 A = 2
V
14 VOUT = 2VP-P
RL = 150Ω
12
TA = 25°C
10
–2
5.6
VOUT = 2VP-P, DIFFERENTIAL
AV = 2, VCC = 5V
VEE = 0V, VCM = 1.6V
DIFFERENTIAL RLOAD
TA = 25°C
100
18
VS = ±5V
AV = 2
VOUT = 200mVP-P
RL = 150Ω
TA = 25°C
6411 G13
–10
10
Frequency Response with
Capacitive Loads
5.7
10
100
FREQUENCY (MHz)
0.1
1
FREQUENCY (MHz)
6411 G12
Gain Flatness vs Frequency
AV = 2, VOUT = 200mVP-P
0.01
6411 G11
Frequency Response
vs Gain Configuration
–3
0
0.001
1000
AMPLITUDE (dB)
0.001
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
DIFFERENTIAL OUTPUT AMPLITUDE (VP-P)
6411 G17
–100
HD2
0 100 200 300 400 500 600 700 800 900 1000
DIFFERENTIAL RLOAD (Ω)
1011 G06
6411f
6
LT6411
TYPICAL PERFORMANCE CHARACTERISTICS
All measurements are per amplifier with single-ended outputs unless otherwise noted.
Third Order Intermodulation
Distortion vs Frequency,
Differential Input
Output Third Order Intercept
vs Frequency, Differential Input
0
–30
–40
RL = 200Ω
–70
RL = 200Ω
30
VOUT = 2VP-P, COMPOSITE, DIFFERENTIAL
1MHz TONE SPACING
AV = 2, VCC = 5V
VEE = 0V, VCM = 1.6V
DIFFERENTIAL RLOAD
TA = 25°C
20
RL = ∞
–80
10
–90
0
–100
0
40
30
20
50
FREQUENCY (MHz)
10
60
70
0
40
30
50
20
FREQUENCY (MHz)
10
6411 G19
2.0
1.5
100
0.5
VIN = 2.5VP-P
AV = 2
VS = ±5V
RL = 150Ω
TA = 25°C
3
2
OUTPUT (V)
OUTPUT (V)
1000
Large-Signal Transient Response
1.0
1
0
–1
–2
–3
2
4
6
–0.5
8 10 12 14 16 18 20
TIME (ns)
2
0
4
6
PERCENT OF UNITS (%)
35
–40
–60
DRIVE 2
LISTEN 1
–80
DRIVE 1
LISTEN 2
–100
1
10
100
FREQUENCY (MHz)
1635 G25
4
6
8 10 12 14 16 18 20
TIME (ns)
30
Gain Matching Distribution
35
VS = ±5V
VOUT = ±2V
RL = 150Ω
TA = 25°C
30
25
20
15
10
0
–3.0
VS = ±5V
VOUT = ±2V
RL = 150Ω
TA = 25°C
25
20
15
10
5
5
1000
2
6411 G24
Gain Error Distribution
40
VS = ±5V
VOUT = 2VP-P
RL = 150Ω
TA = 25°C
–20
0
6411 G23
Crosstalk vs Frequency
0
–4
8 10 12 14 16 18 20
TIME (ns)
PERCENT OF UNITS (%)
0
6411 G22
AMPLITUDE (dB)
10
1
FREQUENCY (MHz)
4
0
–0.10
–120
0.1
VS = ±5V
RL = 150Ω
TA = 25°C
6411 G21
–0.05
–0.15
ENABLED
VEN = 0.4V
1
0.1
0.01
70
VIN = 700mVP-P
AV = 2
VS = ±5V
RL = 150Ω
TA = 25°C
0.05
0
10
Video Amplitude Transient
Response
VIN = 100mVP-P
AV = 2
VS = ±5V
RL = 150Ω
TA = 25°C
0.10
60
100
6411 G20
Small-Signal Transient Response
0.15
DISABLED
VEN = 4V
40
–50
–60
RL = ∞
COMPUTED FOR 50Ω ENVIRONMENT
50
OIP3 (dBm)
THIRD ORDER IMD (dBc)
–20
1000
OUTPUT IMPEDANCE (Ω)
VOUT = 2VP-P, COMPOSITE, DIFFERENTIAL
1MHz TONE SPACING
AV = 2, VCC = 5V
VEE = 0V, VCM = 1.6V
DIFFERENTIAL RLOAD
TA = 25°C
–10
OUTPUT (V)
Output Impedance vs Frequency
60
0
3.0
–2.0 –1.0
1.0
2.0
GAIN ERROR–INDIVIDUAL CHANNEL (%)
6411 G26
0
–3.0
–2.0 –1.0
0
1.0
2.0
3.0
GAIN MATCHING–BETWEEN CHANNELS (%)
6411 G27
6411f
7
LT6411
PIN FUNCTIONS
VEE (Pins 1, 2): Negative Supply Voltage. VEE pins are not
internally connected to each other and must all be connected externally. Proper supply bypassing is necessary
for best performance. See the Applications Information
section.
VEE (Pins 3, 7): Negative Supply Voltage for Output Stage.
VEE pins are not internally connected to each other and
must all be connected externally. Proper supply bypassing
is necessary for best performance. See the Applications
Information section.
NC (Pin 4): This pin is not internally connected.
OUT2 (Pin 5): Output of Channel 2. The gain between the
input and the output of this channel is set by the connection
of the channel 2 input pins. See Table 1 in Applications
Information for details.
VCC (Pins 6, 9): Positive Supply Voltage for Output Stage.
VCC pins are not internally connected to each other and
must all be connected externally. Proper supply bypassing
is necessary for best performance. See the Applications
Information section.
OUT1 (Pin 8): Output of Channel 1. The gain between the
input and the output of this channel is set by the connection
of the channel 1 input pins. See Table 1 in Applications
Information for details.
EN (Pin 11): Enable Control Pin. An internal pull-up resistor of 46k will turn the part off if the pin is allowed to float
and defines the pin’s impedance. When the pin is pulled
low, the part is enabled.
DGND (Pin 12): Digital Ground Reference for Enable Pin.
This pin is normally connected to ground.
IN1+ (Pin 13): Channel 1 Positive Input. This pin has a
nominal impedance of 400kΩ and does not have an internal
termination resistor.
IN1– (Pin 14): This pin connects to the internal resistor
network of the channel 1 amplifier, connecting by a 370Ω
resistor to the inverting input.
IN2– (Pin 15): This pin connects to the internal resistor
network of the channel 2 amplifier, connecting by a 370Ω
resistor to the inverting input.
IN2+ (Pin 16): Channel 2 Positive Input. This pin has a
nominal impedance of 400kΩ and does not have an internal
termination resistor.
Exposed Pad (Pin 17): The pad is internally connected to
VEE (Pin 1). If split supplies are used, do not tie the pad
to ground.
VCC (Pin 10): Positive Supply Voltage. VCC pins are not
internally connected to each other and must all be connected externally. Proper supply bypassing is necessary
for best performance. See the Applications Information
section.
6411f
8
LT6411
APPLICATIONS INFORMATION
Since the EN pin is referenced to DGND, it may need to be
pulled below ground in those cases. In order to protect the
internal enable circuitry, the EN pin should not be forced
more than 0.5V below DGND.
Power Supplies
The LT6411 can be operated on as little as ±2.25V or a
single 4.5V supply and as much as ±6V or a single 12V
supply. Internally, each supply is independent to improve
channel isolation. Note that the Exposed Pad is internally
connected to VEE and must not be grounded when using
split supplies. Do not leave any supply pins disconnected
or the part may not function correctly!
In single supply applications above 5.5V, an additional
resistor may be needed from the EN pin to DGND if the
pin is ever allowed to float. For example, on a 12V single
supply, a 33k resistor would protect the pin from floating
too high while still allowing the internal pull-up resistor
to disable the part.
Enable/Shutdown
The LT6411 has a TTL compatible shutdown mode controlled by the EN pin and referenced to the DGND pin. If
the amplifier will be enabled at all times, the EN pin can
be connected directly to DGND. If the enable function is
desired, either driving the pin above 2V or allowing the
internal 46k pull-up resistor to pull the EN pin to the top
rail will disable the amplifier. When disabled, the DC output
impedance will rise to approximately 740Ω through the
internal feedback and gain resistors (assuming inputs at
ground). Supply current into the amplifier in the disabled
state will be primarily through VCC and approximately
equal to (VCC – VEN)/46k.
The DGND pin should not be pulled above the EN pin since
doing so will turn on an ESD protection diode. If the EN
pin voltage is forced a diode drop below the DGND pin,
current should be limited to 10mA or less.
The enable/disable times of the LT6411 are fast when
driven with a logic input. Turn on (from 50% EN input to
50% output) typically occurs in less than 50ns. Turn off
is slower, but is less than 300ns.
Gain Selection
The gain of the internal amplifiers of the LT6411 is configured by connecting the IN+ and IN– pins to the input signal
or ground in the combinations shown in Figure 1.
It is important that the two following constraints on the
DGND pin and the EN pin are always followed:
As shown in the Simplified Schematic, the IN– pins connect
to the internal gain resistor of each amplifier, and therefore,
each pin can be configured independently. Floating the
IN– pins is not recommended as the parasitic capacitance
causes an AC gain of 2 at high frequencies, despite a DC
gain of +1. Both inputs are connected together in the gain
of +1 configuration to avoid this limitation.
VCC – VDGND ≥ 3V
–0.5V ≤ VEN – VDGND ≤ 5.5V
Split supplies of ±3V to ±5.5V will satisfy these requirements with DGND connected to 0V.
In dual supply cases with VCC less than 3V, DGND should
be connected to a potential below ground such as VEE.
+V
IN+
+V
OUT+
LT6411
+
–
AV = +1
IN+
+V
OUT+
LT6411
+
–
AV = –1
IN+
LT6411
OUT–
+
–
AV = +2
IN–
IN–
–
+
OUT–
–
+
OUT–
IN–
–
+
OUT+
6411 F01
–V
–V
–V
Figure 1. LT6411 Configured in Noninverting Gain of 2, Noninverting Gain of 1 and Inverting Gain of 1, All Shown with Dual Supplies
6411f
9
LT6411
APPLICATIONS INFORMATION
Input Considerations
The LT6411 input voltage range is from VEE + 1V to
VCC – 1V. Therefore, on split supplies the LT6411 input
range is always as large as or larger than the output swing.
On a single positive supply with a gain of +2 and IN– connected to ground, however, the input range limit of +1V
limits the linear output low swing to 2V (1V multiplied by
the internal gain of 2).
The inputs can be driven beyond the point at which the
output clips so long as input currents are limited to
±10mA. Continuing to drive the input beyond the output
limit can result in increased current drive and slightly
increased swing, but will also increase supply current
and may result in delays in transient response at larger
levels of overdrive.
+V
OUT+
+
–
VDC
VDC
R1
VDC
LT6411
OUT+
+
–
VDC
V+
IN–
CLARGE
R1
OV
VDC
OUT–
–
+
VDC
R2
6411 F03
Figure 3. Using Resistor Dividers to Set the
Input Common Mode Voltage When AC Coupling
–50
–55
VCC = 5V, VEE = 0V
A V= 2
TA = 25°C
–60
–65
HD3
–70
–75
–80
IM3
–85
HD2
–90
1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5
VCM (V)
CLARGE
IN–
CLARGE
IN+
DISTORTION (dBc)
If the inputs are AC coupled or the LT6411 is preceded
by a highpass filter, the input common mode voltage can
be set by resistor dividers as shown in Figure 3. Adding
LT6411
+V
V+
R2
The inputs of the LT6411 must be DC biased within the
input common mode voltage range, typically VEE + 1V to
VCC – 1V. If the inputs are AC coupled or DC biased beyond the input voltage range of a driven A-to-D converter,
DC biasing or level shifting will be required. In the basic
circuit configurations shown in Figure 1, the DC input
common mode voltage and the differential input signal
are both multiplied by the amplifier gain. In the gain of
+2 configuration, the DC common mode voltage gain can
be set to unity by adding a capacitor at the IN– pins as
shown in Figure 2.
IN+
If the input signals are within the input voltage range
and output swing of the LT6411, but outside the input
range of an ADC or other circuit the LT6411 is driving,
OV
DC Biasing Differential Amplifier Applications
VDC
the blocking capacitor to the gain setting resistors sets
the input and output DC common mode voltages equal.
When using the LT6411 to drive an A-to-D converter, the
DC common mode voltage level will affect the harmonic
distortion of the combined amplifier/ADC system. Figure 4
shows the measured distortion of an LTC2249 ADC when
driven by the LT6411 at different common mode voltage
levels with the inputs configured as shown in Figure 3.
Adjusting the DC bias voltage can optimize the design for
the lowest possible distortion.
OUT–
–
+
VDC
6411 F02
Figure 2. LT6411 Configured with a Differential Gain of 2
and Unity DC Common Mode Gain
6411 F04
Figure 4. Harmonic and Intermodulation Distortion of the
LT6411 Driving an LTC2249 Versus DC Common Mode
Voltage. Harmonic Distortion Measured with a –1dBFS Signal
at 30.2MHz. Intermodulation Distortion Measured with Two
–7dBFS Tones at 30.2MHz and 29.2MHz
6411f
10
LT6411
APPLICATIONS INFORMATION
+V
the output signals can be AC coupled and DC biased in a
manner similar to what is shown at the inputs in Figure
3. A simpler alternative when using an ADC such as the
LTC2249 is to use the ADC’s VCM pin to set the optimal
common mode voltage as shown in Figure 5.
If unity common mode gain and difference mode response
to DC is desired, there is another configuration available.
Figure 6 shows the LT6411 connected to provide a differential signal gain of +3 with unity common mode gain. For
differential signal gain between unity and +3, three resistors
can be added to provide attenuation and set the differential
input impedance of the stage as illustrated in Figure 7. The
general expression for the differential gain is:
LT6411
VCM
OUT–
–
+
IN–
VCM
VCM
6411 F06
Figure 6. LT6411 Configured for a Differential Gain of +3
and Unity Common Mode Gain with Response to DC
+V
R = 13.7Ω
LT6411
OUT+
+
–
VCM
Scaling factor ‘k’ is the multiple between the two equalvalue series input resistors and the resistor connected
between the two positive inputs. The correct value of R for
the external resistors can be computed from the desired
differential input impedance, ZIN, as a function of k and
the 370Ω internal gain setting resistors, as described in
the equation:
OUT+
+
–
IN+
2•k
A V(DIFF ) = 1+
k+2
R=
IN+
VCM
VCM
k • R = 27.4Ω
OUT–
–
+
IN–
VCM
VCM
R = 13.7Ω
6411 F07
Figure 7. LT6411 Configured with a Differential Input Impedance
of 50Ω, a Differential Gain of +2 and Unity Common Mode Gain
ZIN • 370Ω
370Ω (k + 2) – ZIN (k + 1)
In Figure 7 k = 2 and R = 13.7Ω, setting the differential
gain to +2 and the differential input impedance to approximately 50Ω.
+V
IN+
LT6411
+
–
OV
CLARGE
LTC2249
10k
IN–
OV
–
+
CLARGE
VCM
10k
2.2µF
6411 F05
–V
Figure 5. Level Shifting the Output Common Mode Voltage of the LT6411 Using the VCM Pin of an LTC2249
6411f
11
LT6411
APPLICATIONS INFORMATION
Layout and Grounding
It is imperative that care is taken in PCB layout in order
to utilize the very high speed and very low crosstalk of
the LT6411. Separate power and ground planes are highly
recommended and trace lengths should be kept as short
as possible. If input or output traces must be run over a
distance of several centimeters, they should use a controlled
impedance with matching series and shunt resistances to
maintain signal fidelity.
Series termination resistors should be placed as close to
the output pins as possible to minimize output capacitance.
See the Typical Performance Characteristics section for
a plot of frequency response with various output capacitors—only 12pF of parasitic output capacitance causes
6dB of peaking in the frequency response!
Low ESL/ESR bypass capacitors should be placed as close
to the positive and negative supply pins as possible. One
4700pF ceramic capacitor is recommended for both VCC
and VEE. Additional 470pF ceramic capacitors with minimal
trace length on each supply pin will further improve AC
and transient response as well as channel isolation. For
high current drive and large-signal transient applications,
additional 1µF to 10µF tantalums should be added on each
supply. The smallest value capacitors should be placed
closest to the LT6411 package.
If the undriven input pins are not connected directly to a low
impedance ground plane, they must be carefully bypassed
to maintain minimal impedance over frequency. Although
crosstalk will be very dependent on the board layout, a
recommended starting point for bypass capacitors would
be 470pF as close as possible to each input pin with one
4700pF capacitor in parallel.
To maintain the LT6411’s channel isolation, it is beneficial
to shield parallel input and output traces using a ground
plane or power supply traces. Vias between topside
and backside metal may be required to maintain a low
inductance ground near the part where numerous traces
converge.
ESD Protection
The LT6411 has reverse-biased ESD protection diodes
on all pins. If any pins are forced a diode drop above the
positive supply or a diode drop below the negative supply, large currents may flow through these diodes. If the
current is kept below 10mA, no damage to the devices
will occur.
TYPICAL APPLICATIONS
Single-Ended to Differential Converter
Because the gains of each channel of the LT6411 can
be configured independently, the LT6411 can be used to
provide a gain of +2 when amplifying differential signals
and when converting single-ended signals to differential.
With both channels connected to a single-ended input,
one channel configured with a gain of +1 and the other
configured with a gain of –1, the output will be a differential
version of the input with twice the peak-to-peak (differential)
amplitude. Figure 8 shows the proper connections and
Figure 9 displays the resulting performance when driving an LTC2249. This configuration can preserve signal
amplitude when converting single ended video signals to
differential signals when driving double terminated cables.
The 10k resistors in Figure 8 set the common mode voltage at the output.
5V
VCC
LT6411
IN1+
+
–
1µF
INPUT
IN1–
370Ω
370Ω
IN2–
370Ω
370Ω
OUT1
OUT+
5V
10k
VCM
0.1µF
–
+
IN2+
10k
OUT2
OUT–
VEE
DGND
EN
6411 F08
Figure 8. Single-Ended to Differential Converter
with Gain of +2 and Common Mode Control
6411f
12
LT6411
AMPLITUDE (dBFS)
TYPICAL APPLICATIONS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
5V
32768 POINT FFT
TONE 1 AT 29.5MHz, –7dBFS
TONE 2 AT 30.5MHz, –7dBFS
IM3 = –90dBc
IN+
13
14
15
IN–
16
+
6,9,10
LT6411
AV = 2
–
50Ω
50Ω
100Ω
5
1,2,3,7
RECEIVER
6411 F10
11,12
–5V
Figure 10. Twisted-Pair Driver
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
6411 F09
Figure 9. 2-Tone Response of the LT6411 Configured with
Single-Ended Inputs Driving the LTC2249 at 29.5MHz, 30.5MHz
Twisted-Pair Line Driver
The LT6411 is ideal when used for driving inexpensive
unshielded twisted-pair wires as often found in telephone
or communications infrastructure. The input can be composite video, or if three parts are used, RGB or similar and
can be either single ended or differential. The LT6411 has
excellent performance with all formats.
Double termination of the video cable will enhance fidelity
and isolate the LT6411 from capacitive loads. Although
most twisted-pair cables have a characteristic impedance
of 100Ω, the cables can be terminated with a smaller
series resistance or a larger shunt resistance in order to
compensate for attenuation. A typical circuit for a twistedpair driver is shown in Figure 10.
Single Supply Differential ADC Driver
The LT6411 is well suited for driving differential analog
to digital converters. The low output impedance of the
LT6411 is capable of driving a variety of filters as well as
interfacing with the typically high impedance inputs of
ADCs. In addition, the LT6411’s excellent distortion allows
the part to perform with an SFDR below the limits of many
high speed ADCs. The DC1057 demo board, shown schematically in Figure 11 and physically in Figure 12, allows
implementation and testing of the LT6411 with a variety
of different Linear Technology high speed ADCs.
6411f
13
LT6411
TYPICAL APPLICATIONS
VCC
CD1
0.1µF
+
VEE
C1
OPT
“B” CASE
CD2
4700pF
VCC
VCC
3
R7
R37
OPT
2
4
R3
6
R5
C5
C9
R38
OPT
C8
TBD
0603
R13
L2
TBD
0603
CD4
0.1µF
C3
R6
T1
TBD ETC1-1TTR
0603 5
1
J2
AIN–
R2
OPT
C2
R10
C11
13
IN1–
15
IN2–
16
IN2+
OUT1
8
R8
10Ω
1%
5
R11
10Ω
1%
1
R9
10Ω
1%
LT6411
VEE
OUT2
2
3
7
C6
L1
TBD R12
0603 10Ω
1%
R35
12.1Ω
1%
C4
R36
12.1Ω
1%
C7
L3
TBD
0603
VEE VEE VEE VEE NC
C12
R16
0Ω
10 11 12
IN1+
14
R14
9
VCC VCC VCC EN DGND
4
AIN+
TO
ADC
INPUTS
AIN–
C10
VEE
R17
OPT
VCC
R18
CD5
470pF
CD6
CD7
4700pF 1µF
CD8
0.1µF
0603
R19
0Ω
+
R4
OPT
0603
E2
GND
JP1
R1
ENABLE
10Ω
1
0603 VCC 2
3
CD3
470pF
J1
AIN+
E1
VCC
C31
OPT
“B” CASE
6411 F11
E7
VEE
OPT
E8
GND
Figure 11. DC1057 Demo Circuit Schematic
Figure 12. Layout of DC1057 Demo Circuit
6411f
14
LT6411
SIMPLIFIED SCHEMATIC
VCC
VCC
TO OTHER
AMPLIFIER
BIAS
IN–
370Ω
VCC
46k
1k
IN+
EN
150Ω
370Ω
OUT
VEE
DGND
VEE
6411 SS
VEE
PACKAGE DESCRIPTION
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
BOTTOM VIEW—EXPOSED PAD
3.00 ± 0.10
(4 SIDES)
0.70 ±0.05
15
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
PACKAGE
OUTLINE
0.25 ±0.05
0.50 BSC
16
1
1.45 ± 0.10
(4-SIDES)
3.50 ± 0.05
1.45 ± 0.05
2.10 ± 0.05 (4 SIDES)
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ± 0.05
2
(UD16) QFN 0904
0.200 REF
0.00 – 0.05
0.25 ± 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
6411f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT6411
TYPICAL APPLICATION
80.6Ω
5V
IN+
+
–
–
+
1.9VDC
IN–
1.9VDC
55Ω
390nH
10Ω
55Ω
80.6Ω
9
6
3
0
–3
–6
AIN–
15pF
390nH
LT6411
or additional filtering. Figure 15 shows the corresponding
SFDR of –75.5dBc with a 30MHz tone. Figure 16 shows
the 2-tone response of the LT6411 with 29.5MHz and
30.5MHz inputs. Note that 0dBFS corresponds to a 2VP-P
differential signal.
GAIN (dB)
In cases where lowering the noise floor is paramount,
adding higher order lowpass or bandpass filtering can
significantly increase signal-to-noise ratio. In Figure 13,
the LT6411 is shown driving an LTC2249 with a 2nd order
lowpass filter that has been carefully chosen to ensure
optimal intermodulation distortion. The response is
shown in Figure 14. The filter improves the SNR over the
unfiltered case by 6dB to 69.5dB. With the filter, the SNR
of the ADC and the LT6411 are comparable; better SNR
can be achieved by using either a higher resolution ADC
–9
LTC2249
AIN+
10Ω
–12
10
100
FREQUENCY (MHz)
1
6411 F13
1000
6411 F14
0
–10 8192 POINT FFT
f = 30MHz, –1dBFS
–20 IN
SNR = 69.5dB
–30 SFDR = 75.5dB
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
10 15 20 25 30
5
0
FREQUENCY (MHz)
Figure 14. Frequency Response of the LT6411 and Filter
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
Figure 13. Optimized 30MHz LT6411 Differential ADC Driver
35
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
40
0
6411 F15
Figure 15. SNR and SFDR of the LT6411 and Filter
Driving the LTC2249
32768 POINT FFT
TONE 1 AT 29.5MHz, –7dBFS
TONE 2 AT 30.5MHz, –7dBFS
IM3 = –89.7dBc
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
6411 F16
Figure 16. 2-Tone Response of the LT6411 and Filter
Driving the LTC2249 at 29.5MHz, 30.5MHz
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1993-2
800MHz Low Distortion, Low Noise ADC Driver, AV = 2
3.8nV/√Hz Total Noise, Low Distortion to 100MHz
LT1993-4
900MHz Low Distortion, Low Noise ADC Driver, AV = 4
2.4nV/√Hz Total Noise, Low Distortion to 100MHz
LT1993-10
700MHz Low Distortion, Low Noise ADC Driver, AV = 10
1.9nV/√Hz Total Noise, Low Distortion to 100MHz
LT1994
Low Noise, Low Distortion Fully Differential Amplfier
70MHz Gain Bandwidth Differential In and Out
LT6402-6
300MHz Low Distortion, Low Noise ADC Driver, AV = 2
3.8nV/√Hz Input Referred Noise, Low Distortion to 30MHz
LT6553
650MHz Gain of 2 Triple Video Amplifier
Triple Amplifier with Fixed Gain
LT6554
650MHz Gain of 1 Triple Video Amplifier
Triple Amplifier with Fixed Gain
6411f
16 Linear Technology Corporation
LT 0606 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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© LINEAR TECHNOLOGY CORPORATION 2006