Die-on-wafer and Wafer-level 3D Integration for
Millimeter-Wave Smart Antenna Transceivers
M.M. Hella, S. Devarajan, J.-Q. Lu, K. Rose and R.J. Gutmann
Center for Integrated Electronics
Rensselaer Polytechnic Institute, Troy, New York 12180, hellam@ecse.rpi.edu
Abstract — A three-dimensional (3D) IC technology
platform for high-performance, heterogeneous integration of
silicon ICs for mm-wave smart antenna transceivers is
presented. The platform uses dielectric adhesive bonding of
fully-processed wafer-to-wafer aligned ICs, followed by a
three-step thinning process and copper damascene
patterning to form inter-wafer interconnects. A low noise
amplifier (LNA), power amplifier (PA), and an analog-todigital converter (ADC) are designed in RF-enhanced SiGe
BiCMOS process to operate in the 24GHz ISM band. These
critical design blocks serve as a step towards the realization
of a complete system integrated with I/O matching networks,
switches, antennas, and digital processing in a 3D
configuration.
I. INTRODUCTION
The next wave of wireless communications seeks to
improve data rates and channel capacity by employing
larger bandwidths with higher efficiencies. One promising
technology to attain this goal involves the use of smartantenna technology whereby multiple antennas are
combined intelligently at the transmitter and the receiver,
both at the subscriber and the base station. Various forms
of multiple antenna systems provide solutions for
communications and radars, such as multiple-inputmultiple-output (MIMO) diversity transceivers and
synthetic aperture radars (SARs) [1]. The industrial,
scientific, and medical (ISM) band at 24GHz is regarded
as a potential candidate for such applications.
Traditionally, communications systems working in the
microwave/mm-wave band are realized using multiple
microwave modules implemented mainly in GaAs, adding
to overall cost and complexity. It is envisioned that singlechip silicon-based technologies will replace current
solutions in a way similar to the trend that commercial
cellular and PCS systems have taken for their
implementation. System integration is the main key in the
development of any low cost/high performance wireless
networking system [2-3].
The major drive behind the 3D integration for mm-wave
applications is the impact of interconnect losses at these
frequencies (For example, the interconnect loss for a flipchip packaged circuit is near 1.2dB at 60GHz [4]),
together
with
the
continuing
demand
for
reconfigurable/smart silicon-based transceivers that
interface with CMOS memory-intensive digital processors
and possibly NMOS-based imagers.
In this paper various issues related to the 3D integration
for mm-wave transceivers will be addressed. The 3D
technology platform is presented in section II. Some basic
building blocks in the transceiver chain including a SiGebased low noise amplifier ( LNA), a power amplifier (PA)
and a high performance SiGe analog-to-digital converter
(ADC) are introduced.
II. 3D IC TECHNOLOGY PLATFORM
Die-to-die, die-to-wafer and wafer-to-wafer approaches
are in various stages of research and development [5].
Alternative wafer-to-wafer technology platforms are
under development involving oxide-to-oxide bonding,
copper-to-copper bonding, and dielectric adhesive
bonding [5]. Our dielectric adhesive bonding approach
accommodates
wafer
distortions
and
interface
contaminants; in addition, a handling wafer is not required
and wafers are thinned only after bonding to a host wafer.
A three-wafer stack depicting our IC technology
platform is shown in Figure 1(a) [6]. Fully processed
wafers are aligned to within a micron after spin coating a
micron thick benzocyclobutene (BCB) and soft baking the
BCB to remove volatile components. The wafer pair is
then bonded together in a bonder with a specified ambient,
temperature and pressure cycle. After bonding, the topWafer
Level
Bridge Via
Plug Via
Dielectric
Substrate
3rd
Dielectric
Substrate
2nd
(a)
Device
surface
Bond
Device
surface
Bond
Multi-level on-chip interconnects
Substrate
Antenna and
High Q Passives
(Face-to-back)
(Face-to-face)
1st
(b)
SiGe BiCMOS
Transceiver, A/D
CMOS Processor
and Memory
Device
surface
Fig. 1. (a) Schematic of a 3D integration platform, showing wafer
bonding interface, vertical inter-wafer vias (plug- and bridge-type), and
"face-to-face" and "face-to-back" bonding; (b) three-wafer/three-die
stack for SiGe-based mm-wave transceiver.
side donor wafer is thinned by backside grinding,
polishing and selective etching. Finally, inter-wafer
interconnects are formed by copper damascene patterning.
The upper level device wafer can be integrated in a similar
process flow.
An attractive wafer-level partitioning depicted in Figure
1(b) is to have the top wafer in a three-wafer stack as a
thermal-coefficient-of-expansion (TCE) matched glass, in
which high-Q passives can be processed (inductors, with
or without magnetic thin films, high density capacitors
with high dielectric constant thin films, and/or multiple
antennas for beam forming applications); the middle wafer
is a SiGe-based transceiver wafer, with vias connecting to
the high-Q passives in the upper wafer; the bottom layer is
the CMOS-based processor and memory. This
partitioning, is particularly attractive for mm-wave
applications, since the interconnect length between the
core of the transceiver and both the passives in the upper
layer, as well as the digital control in the bottom layer, can
be controlled. This allows extensive computing
capabilities as well as minimum interconnect losses.
The BCB-based bond has a critical adhesion energy
between 25 and 35 J/m2 depending upon bonding
conditions [6], well above the 5-10 J/m2 required for IC
processing. Moreover, inter-wafer via chains have been
fabricated that demonstrated the validity of the process
flow with micron-sized vias and 1-µm wafer-to-wafer
alignment, as described in detailed elsewhere [6].
The impact of our bonding and thinning processes on IC
interconnects (copper with oxide and copper with ultralow-k dielectric) has been investigated with SEMATECH
[7], and on 130 nm SOI CMOS devices and test circuits
having four-level copper/low-k interconnects with
Freescale [8]. While the ultra-low-k dielectric structure
shows some change due to the fragile structure, changes in
resistance and line-to-line leakage are small [7]. CMOS
device and circuit parameters (threshold voltage,
subthreshold leakage and ring oscillator delay) vary by
less than one-third of the original 10%-90% spread across
the wafer [8]. A FIB-SEM cross-section of a SOI CMOS
wafer BCB-bonded to a prime Si wafer after a doublebonding/thinning process is shown in Figure 2 [8].
While 3D die stacks with micron-size, through-wafer
vias may have comparable performance to wafer-level 3D
implementation, the manufacturing cost will be higher due
to the die handling and the die-by-die stack processing of
the vertical interconnects. Monolithic wafer-level 3D
implementations are more challenging than system-in-apackage (SiP) until a viable manufacturing base is
established. However, the performance advantages with
short inter-wafer interconnects, high integration density,
and low interconnectivity cost, make monolithic 3D
attractive for future wireless networking solutions.
CMOS
SOI Die
BCB
SiO2
Si
Fig. 2. FIB-SEM cross-section of SOI CMOS wafer BCB-bonded to
a prime Si wafer after the double-bonding/thinning process [8].
III. BASIC BUILDING BLOCKS IN SIGE BICMOS FOR
24GHZ TRANSCEIVER
Having presented our current 3D technology platform,
it is worth noting that in RF/mm-wave applications, the
techniques of SiP and Multi-Chip-Module (MCM) are
currently being pursued as more-realistic costperformance solutions. However, the long-term cost of
either 2D or 3D die-stack packaging solutions is affected
by chip-handling and assembly. Clearly wafer-to-wafer
implementations are a longer-term solution, but also have
the lowest cost for high-volume products since chip
handling is minimized and vertical interconnectivity is
maximized by a batch monolithic process.
In the following subsections, the designs of an ADC, an
LNA, and a PA are presented. These are the active circuit
blocks that will interface with both the bottom and upper
layers.
3.1. A SiGe-based Analog-to-Digital Converter
The increasingly challenging requirements on ADC
performance posed by: 1) new high-bandwidth standards,
2) the trend of low-IF single-heterodyne receivers, and 3)
advanced power amplifier linearization techniques, call
for device flexibility available only in BiCMOS
technologies [9]. The impact of including an ADC with an
RF/microwave transceiver IC on one wafer and
combining with digital processing IC in a second wafer is
significant, particularly for smart/reconfigurable wireless
terminals.
A conventional pipeline A/D converter is designed
using gain-of-2 sample/hold (S/H) amplifiers realized with
an operational transconductance amplifier (OTA) in a
negative feedback loop using precise-value capacitors.
IBM’s SiGe 6HP technology, which provides 47 GHz
SiGe HBTs and 250 nm node CMOS, was used. The ADC
chip architecture, micrograph, and summary of measured
Pipeline ADC Block Diagram
Chip Layout (3x3 mm2)
SiGe OTA
Chip Photograph
Measured Pipeline ADC Performance:
Resolution: 12-Bits
Sampling Rate: 34 MS/s
Simulated OTA Performance:
DC Gain: 88 dB
Unity Gain Frequency: 430 MHz
Settling Time (0.01%): 10 ns
Fig. 3. SiGe BiCMOS pipeline A/D converter.
results are shown in Figure 3 [10]. High DC gain, fast
settling, low noise OTAs capable of driving large
sampling capacitors without sacrificing output swing are
needed for realizing high-performance pipelined ADCs. A
folded cascode configuration using SiGe NPN HBTs as
cascodes with PMOS inputs resulted in a wide-bandwidth,
high-gain, fast-settling OTA. The 34 MS/s sampling rate
with 12 bit resolution was limited by capacitor mismatch
and the lack of self-calibration techniques [10].
More recently, an improved SiGe BiCMOS OTA was
designed that uses a triple-cascode architecture and
NMOS-NPN SiGe HBT Darlington inputs with cascode
SiGe HBTs to achieve fast settling response, with a
predicted 115 MS/s sampling rate at 12 bit resolution [11];
with digital self-calibration [12] using a 7-bit pipeline
seed, 205 MS/s is predicted. Using the A/D figure-ofmerit (FoM) from the 2003 ITRS [13], we obtain a
conservative estimate of 2.2 x 103 GHz/W without selfcalibration and 4.0 x 103 GHz/W with self-calibration,
both using the 6HP process introduced in 2000. In
comparison, the 2003 ITRS predicts CMOS A/D
converters to reach a FoM of 2.2 x 103 GHz/W in 2009
and 4.0 x 103 GHz/W in 2012 [13].
3.2. Low Noise Amplifier
The LNA designed is a typical common-emitter
amplifier with inductive degeneration and an isolation
cascode. To get sufficient gain two identical stages were
cascaded, similar to the design presented in [14]. Hence,
each stage was designed to have 50 ohm input and output
matching. While the design presented in [14] used a 120
GHz process to realize a 24 GHz SiGe LNA, we were able
to realize similar performance with a 60 GHz fT process
with careful component optimization.
Fig 4: 24 GHz SiGe LNA and simulated S-parameter / NF curves.
The designed LNA is shown in Figure 4. The input
transistor Q1 is inductively degenerated with Ls to
provide good input matching with a 50 ohm real part. The
bias current density is determined for low noise figure and
Q1 is sized for input matching along with Ls and Lg. Q2
is used to provide better isolation between the input
transistor and the output node. While in typical cascaded
systems there is no need to match the output impedance of
the first stage and the input impedance of the second stage
to 50 ohms, Guan [14] suggests that at a high-frequency
like 24 GHz, sensitivity to variations in other adjacent
blocks can be minimized by matching each to 50-Ohm.
Also, in a two-stage LNA design, the first stage can
exactly be replicated if it is designed with 50 ohm input
and output matching. C1, C2 and Ld are sized for
matching the output of the first stage to 50 ohms. Once the
first stage is optimized, it is replicated in order to obtain a
high gain (S21). The simulated plots of S11, S21 and NF
are shown in Figure 4.
It is worth noting that the 6.1dB noise figure can be
lowered to around 4dB if the on-chip spiral inductors can
be replaced with higher quality factor inductors. We
anticipate that this can be realized using the 3D
configuration by having high quality passives on TCEmatched glass in the upper layer.
3.3. 24GHz Power Amplifier
A 2-stage single-ended class AB power amplifier is
designed using 0.18um FETs available in the SiGe
BiCMOS technology used. High fT FETs are used rather
than the high breakdown HBTs since the latter have a
lower fT of 24GHz. Input, output, and inter-stage
matching are implemented on-chip using the inductor line
formed of the top metal layer over a deep trench to isolate
the inductor from the substrate. This technique generates
small value inductors with high quality factor. The
amplifier has been simulated with the effect of parasitics,
including ground inductances as shown in figure 5 (a) and
(b). Using 5 ground bonding pads with their typical
packaging parasitic inductances, the PA can deliver
11dBm of maximum output power. The output power is
estimated to increase to 14dBm with around 6dB increase
in gain by decreasing the ground inductance. The on-chip
72.83pF
REFERENCES
60pH
1K
200pF
OUT
[1]
200x2x0.18um
2pF
[2]
1K
200x2x0.18um
74.8pH
150fF
78x2x0.18um
2pF
2pF
78x2x0.18um
IN
[3]
150pH
Bias1
[4]
2pF
Bias2
(a)
(b)
Fig.5. (a) Output power and amplifier gain vs. input power using a 2.8V
supply. (b) Simulated output power and power gain of the amplifier.
inductor lines have a quality factor high enough that the
3D integration will not enhance the performance of the
amplifier.
[5]
[6]
IV. SUMMARY AND CONCLUSIONS
We have presented our 3D integration platform and its
application for mm-wave smart antenna transceivers.
Basic test blocks targeting the 24GHz ISM band are
designed to serve as a step towards the realization of the
complete system integrated with I/O matching network,
switches, and antennas. Simulation results from various
blocks indicate the possible increase in power gain, output
power, and noise figure with the increase in the quality
factor of inductors. Although the relative increase in
performance does not justify the higher cost of 3D
integration, the partitioning capability, possibility of
integrating multiple antennas and switches on the top
layer, and integrating processors with higher
computational power can prove 3D to be a worthy longterm solution. Another possible application is the concept
of digital assisted RF/analog design, where the
performance of each RF/analog block can be optimized in
real-time by monitoring its output and applying digital
techniques for performance improvement. This requires
high interconnect capacity, which if done in 2D can pose
cross-talk issues, and consume higher area. 3D on the
other hand can provide vertical interconnect from the
digital processing core in the bottom layer to each block in
the transceiver chain in the inter-mediate layer.
ACKNOWLEDGEMENT
This research is partially supported through the
Interconnect Focus Center for Hyperintegration, funded
by MARCO, DARPA and NYSTAR.
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
X. Guan, H. Hashemi, and Ali Hajimiri, “A Fully Integrated 24GHz Eight-Element Phased-Array Receiver in Silicon,” IEEE J. Of
Solid_State Circuits, vol. 39, NO. 12, pp. 2311-2320, Dec. 2004.
A. Smolders, N. Pulsford, P. Philippe, and F. Van Straten, “RF SiP:
The Next Wave for Wireless System Integration,” Proc. of IEEE
Radio Frequency Integrated Circuits Symposium, pp. 233-236,
May 2004.
R. Tummala, and J. Laskar, “Gigabit Wireless: System-on-aPackage Technology,” Proceedings of the IEEE, Vol. 92, No. 2,
Feb. 2004.
Modest Oprysko, “Building Millimeter-Wave Circuits in Silicon,”
Workshop on Advances in RF and High-Speed System Integration,
IEEE Radio and Wireless Conference, Atlanta 2004.
J.-Q. Lu, T.S. Cale and R.J. Gutmann, “Dielectric Adhesive Wafer
Bonding for Back-End Wafer-Level 3D Hyper-integration,”
Dielectrics for Nanosystems: Materials, Science, Processing,
Reliability, and Manufacturing, edited by R. Singh, H. Iwai, R.R.
Tummala, and S.C. Sun, pp. 312-323, ECS PV 2004-04, 2004.
J.-Q. Lu, A. Jindal, Y. Kwon, J.J. McMahon, K.-W. Lee, R.P.
Kraft, B. Altemus, D. Cheng, E. Eisenbraun, T.S. Cale, and R.J.
Gutmann, “3D System-on-a-Chip using Dielectric Glue Bonding
and Cu Damascene Inter-Wafer Interconnects,” Thin Film
Materials, Processes, and Reliability, Eds.: S. Mathad, T. S. Cale,
D. Collins, M. Engelhardt, F. Leverd, and H. S. Rathore, pp. 381389, ECS Proc. Vol. PV 2003-13, 2003.
J.-Q. Lu, A. Jindal, Y. Kwon, J.J. McMahon, M. Rasco, R. Augur,
T.S. Cale, and R.J. Gutmann, “Evaluation Procedures for Wafer
Bonding and Thinning of Interconnect Test Structures for 3D ICs,”
IEEE International Interconnect Technology Conference (IITC),
pp. 74-76, June 2003.
R.J. Gutmann, J.-Q. Lu, S. Pozder, Y. Kwon, A. Jindal, M. Celik,
J.J. McMahon, K. Yu and T.S. Cale, “A Wafer-Level 3D IC
Technology Platform,” Advanced Metallization Conference in 2003
(AMC 2003), Eds. G.W. Ray, T. Smy, T. Ohta and M. Tsujimura,
pp. 19-26, MRS Proceedings 2004.
A. Zanchi, F. Tsay, and I. Papantonopoulos, “Impact of Dielectric
Relaxation on a 14b Pipeline ADC in 3V SiGe BiCMOS,” ISSCC
Digest of Technical Papers, pp. 330-331, Feb. 2003.
S. Devarajan, M. Hourihan and K. Rose, “High-speed 12-bit
pipeline A/D converter for high-speed image capture,” SRC SiGe
Design Challenge – Phase 2, July 2003.
S. Deverajan, R.J. Gutmann and K. Rose, “A 87dB, 2.3GHz, SiGe
BiCMOS operational transconductance Amplifier,” IEEE
International Symposium on Circuits and Systems”, May 2004,
pp.1293-1296.
A. Karanicolas, Ph.D. Thesis, Massachusetts Institute of
Technology, 1994.
International Technology Roadmap for Semiconductors (ITRS):
2003 Edition, (Semiconductor Industry Association, 2003,
http://public.itrs.net).
Xian Guan, Hossein Hashemi and Ali Hajimiri, “A Fully Integrated
24-GHz Eight-Element Phased-Array Receiver in Silicon,” IEEE
Journal of Solid-State Circuits, Vol. 39, No. 12, pp. 2311-2320,
Dec 2004.