A Nondestructive Self-Reference Scheme for SpinTransfer Torque Random Access Memory (STT-RAM)
Yiran Chen, Hai (Helen) Li*, Xiaobin Wang, Wenzhong Zhu, Wei Xu† and Tong Zhang†
Seagate Technology,
Bloomington, MN, USA
{yiran.chen, xiaobin.wang,
wenzhong, zhu}@seagate.com
*ECE Department
PolyTech Institute of NYU
Brooklyn, NY, USA
hli@duke.poly.edu
Abstract—We proposed a novel self-reference sensing scheme for
Spin-Transfer Torque Random Access Memory (STT-RAM) to
overcome the large bit-to-bit variation of Magnetic Tunneling
Junction (MTJ) resistance. Different from all the existing
schemes, our solution is nondestructive: The stored value in the
STT-RAM cell does NOT need to be overwritten by a reference
value. And hence, long write-back operation (of the original
stored value) is eliminated. The robustness analyses of the
existing scheme and our proposed nondestructive scheme are also
presented. The measurement results from a 16kb testing chip
successfully confirmed the effectiveness of our technique.
Keywords-spin-transfer torque; STT-RAM; self-reference
I.
INTRODUCTION
The demands of high capacity nonvolatile memory
exponentially increase due to the fast growth of the pervasive
computing and handheld industry. Nevertheless, it is known
that Flash memory (NAND and NOR) faces significant scaling
challenges at 32nm technology node and beyond [1].
Magneto-resistive Random Access Memory (MRAM) is a
promising candidate for next-generation nonvolatile memory:
MRAM features non-volatility, fast read/write speed (<10ns),
virtually unlimited programming endurance (>1015 cycles) and
zero standby power [2]. In MRAM, Data storage is realized by
switching the resistance of magnetic tunneling junction (MTJ)
between high-resistance state (“1”) and low-resistance state
(“0”). However, in conventional MRAM that uses currentinduced magnetic field to flip the magnetization of MTJ [3][4],
scaling the amplitude of the switching magnetic field at the
scaled technologies is very challenging.
A new MRAM design, called Spin-Transfer Torque RAM
(STT-RAM) was recently invented [5][6][7]. STT-RAM uses
electrical current to flip the magnetization of MTJ. Because the
switching current is proportional to the area of MTJ, STTRAM has a better scaling property than conventional MRAM.
However, STT-RAM technology suffers from some yieldlimiting factors, such as the large MTJ resistance variation: For
example, MTJ resistance increases by 8% when the thickness
of oxide barrier in the MTJ changes from 14Å to 14.1 Å [8].
The MTJ resistance variation will be aggravated by the further
reduction of oxide barrier thickness and the large MTJ
geometry variation in scaled technology.
†ECSE Department
Rensselaer Polytechnic Institute
Troy, New York
{xuw, tzhang}@ecse.rpi.edu
Large MTJ resistance variation could lead to the false
detection of read operation: when the low (high) resistance
state of an MTJ is higher (lower) than the reference value, the
content of the memory cell is always detected as “1” (“0”) [9].
Hence, some self-reference schemes are proposed [7][10]: 1)
sense the state of an MTJ and store the result (i.e., as a voltage
level of a capacitor); 2) write a reference value to the MTJ; 3)
sense the corresponding reference state of the MTJ and
compare it to the stored result in step 1 to get the original MTJ
state; 4) write back the original state to the MTJ. We note that
such a self-reference scheme is destructive because the original
MTJ state destroyed when writing the reference value into the
MTJ. The original MTJ state could be lost if power is shut
down before the write back operation completes. This raises the
concerns about the chip reliability from non-volatility point of
view. Also, the long read latency and the high power
consumption of conventional self-reference scheme (mainly
due to the two write steps) are commercially impractical.
In this paper, we propose a novel nondestructive selfreference scheme for STT-RAM design. Although the original
state of an MTJ still needs to be read twice, there is no need to
write any reference value into the MTJ. Consequently, the long
write back operation is avoided. Compared to the conventional
self-reference scheme, our technique significantly improves the
memory reliability and reduces the read latency.
The organization of this paper is as follows: Section II
gives the basics of STT-RAM and conventional self-reference
scheme; Section III describes our proposed nondestructive selfreference scheme; Section IV presents the robustness analysis
B
B
Free Layer
Free Layer
MgO
MgO
Reference Layer
Reference Layer
A
A
SL
(a)
(b)
(c)
BL
WL
Figure 1. MTJ structure. (a) Anti-parallel (high resistance state). (b)
Parallel (low resistance state). (c) 1T1J STT-RAM cell structure.
978-3-9810801-6-2/DATE10 © 2010 EDAA
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MTJ Resistance (Ω)
2800
2600
2400
2200
2000
1800
1600
1400
1200
1000
-1000
Low resistance state : VBL,L = I R ⋅ ( RL + RTR ) or
40ns pulse
DC extrapolation
High resistance state : VBL,H = I R ⋅ ( RH + RTR ).
RH
RL
-500
0
IR
Sensing Current (µA)
500
1000
Here RL and RH are the low and the high MTJ resistance at
read current IR, respectively. RTR is the resistance of NMOS
transistor. VBL,L and VBL,H are the BL voltages when the MTJ is
at low resistance state and high resistance state, respectively.
By comparing BL voltage to a reference voltage VREF between
VBL,L and VBL,H, the MTJ resistance state can be readout. If a
VREF is shared by multiple STT-RAM cells, it needs to satisfy:
Max(VBL,L ) < VREF < Min(VBL,H ) .
Figure 2. The measured static R-I curve of an MgO-based MTJ.
comparison between our nondestructive self-reference scheme
and the conventional destructive one. Section V shows the
experimental results. Section VI concludes our work.
II.
PRELIMINARY
A. MTJ (Magnetic Tuneling Junction) Basics
An MTJ includes two ferromagnetic layers and one oxide
barrier layer, e.g., MgO. When the magnetization directions of
the two ferromagnetic layers are parallel (anti-parallel), MTJ is
in low (high) resistance state, as shown in Figure 1. In STTRAM design, the magnetization direction of one ferromagnetic
layer (reference layer) is fixed while the magnetization
direction of the other ferromagnetic layer (free layer) can be
changed by passing a switching current polarized by the
magnetization of reference layer [5].
Figure 2 illustrates the measured R-I sweep curve of an
MgO-based MTJ with 90nm×180nm cell size, under a voltage
pulse with 40ns pulse width. Some points missing from the
40ns pulse measurement are extrapolated based on DC (static)
measurement. When applying a positive voltage on point B in
Figure 1, MTJ enters the positive voltage region in Figure 2
and switches from high resistance state to low resistance state.
When applying a positive voltage on point A, MTJ enters the
negative voltage region and switches the other way.
Let RL and RH denote the low and the high MTJ resistances,
respectively. We define the Tunneling Magneto Resistance
Ratio as TMR = (RH-RL)/RL. In addition, RH, RL and TMR also
depend on the read current (or voltage), as shown in Figure 2.
In general, a larger TMR makes it easier to distinguish the two
resistance states of an MTJ. MgO-based MTJ’s are widely used
in present-day STT-RAM design because of the higher TMR
(>100%) than other materials, i.e., AlO (<30%).
B. STT-RAM Cell Basics
The most popular STT-RAM cell design is one-transistorone-MTJ (or 1T1J) structure [5][6] as shown in Figure 1(c),
where one MTJ is connected to one NMOS transistor in series.
The interconnects connected to MTJ, to the source (drain) of
NMOS transistor and to the gate of NMOS transistor are called
as bit-line (BL), source-line (SL) and word-line (WL),
respectively. MTJ is usually modeled as a variable resistor in
circuit schematic, as shown in Fig. 1(c) [11].
In a conventional voltage sensing scheme for a STT-RAM
cell [9]. Read current IR is applied to generate the BL voltage:
(1)
(2)
Here Max(VBL,L) and Min(VBL,H) denote the maximal VBL,L
and the minimal VBL,H generated by all involved STT-RAM
cells, respectively. Unfortunately, Max(VBL,L) < Min(VBL,H)
may not hold true when the bit-to-bit variation of MTJ
resistance is large.
C. Conventional Self-reference Scheme
1) Operation of conventional self-reference
To overcome the bit-to-bit variation of MTJ resistances, a
so called “self-reference” sensing scheme was proposed [10],
as shown in Figure 3: The drains of two switch transistors
SLT1 and SLT2 are connected to BL while the sources of them
are connected to voltage storage elements, i.e., capacitors C1
and C2, respectively. The top connect points of C1 and C2 are
also connected to a voltage sense amplifier.
The operation of conventional self-reference scheme is:
•
First read: A read current IR1 is applied to generate BL
voltage VBL1, which is stored in C1. VBL1 can be either
VBL,L1 or VBL,H1, which are the BL voltages when the
MTJ is at the low resistance state or the high resistance
state, respectively;
•
Erase: Value “0” is written into the same bit;
•
Second read: Another read current IR2 (>IR1) is applied
and generates BL voltage VBL2, which is stored in C2.
Here IR2 is carefully chosen to make sure:
VBL,L1 < VBL2 < VBL,H1 .
(3)
The original value of STT-RAM bit can be readout by
comparing VBL1 and VBL2.
•
Write back: The value readout in the previous step
needs to be written back to the STT-RAM bit.
2) Read current optimization
Eq. (3) can be rewritten as:
I R1 (RL1 + RTR1 ) < I R2 (RL2 + RTR2 ) < I R1 (RH1 + RTR1 )
(4)
Here RL1 and RL2 are the resistances of MTJ at the low
resistance state, at IR1 and IR2, respectively. RH1 is the resistance
of MTJ at high resistance state, at IR1. RTR1 and RTR2 are the
resistances of NMOS transistor, at IR1 and IR2, respectively.
We define the largest allowable read current that does not
disturb the MTJ state as IRmax. As we shall explain in Section
IV-A, we choose IR2= IRmax to maximize the sense margin.
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VDD
IR1
IR2
RD_EN2
RD_EN1
BL
VBL2
Decoder
SLT1
BL
SLT1
SLT2
C1
NMOS
Transistor
VBL2
VBL1
RD
WL
SenEn
+ -
+ -
RowDec
Data_Latch
SLT2
SLT1
SLT2
Output
Output
Figure 5. Schematic of nondestructive self-reference circuitry.
Figure 3. Conventional self-reference sensing scheme for STT-RAM.
The optimal IR1 that ensures the equal sense margins when
the MTJ is at both high- and low-resistance states (or |VBL,L1 –
VBL2| = |VBL2 – VBL,H1|) can be calculated by solving:
I R1 = I R2 ⋅
2 ⋅ (RL2 + RTR2 )


(I − I )
 RH2 + RL2 + (∆RHmax + ∆RLmax ) ⋅ R2 R1 + 2 RTR1 
I R2


. (5)
Here ∆RHmax (or ∆RLmax) denotes the resistance difference
when an MTJ at the high (or low) resistance state is read at a
close-to-zero read current and IRmax, as shown in Figure 4.
III.
NONDESTRUCTIVE SELF-REFERENCE SCHEME
A. Theory of Nondestructive Self-reference Scheme
We noticed that the current dependence of the high and the
low resistance states of an MTJ are quite different: the current
roll-off slope of the high resistance state is much steeper than
that of the low resistance state, as shown in Figure 2. This
special characteristic of MgO-based MTJ’s is the motivation of
our nondestructive self-reference scheme.
The conceptual schematic of our nondestructive selfreference scheme is shown in Figure 5. A switch transistor
∆RH
∆RL
IR1
The operation of nondestructive self-reference scheme is:
First read: A read current IR1 is applied to generate BL
voltage VBL1, which is stored in C1. VBL1 can be either VBL,L1 or
VBL,H1, which are the BL voltages when the MTJ is at the low
resistance state or the high resistance state, respectively;
Second read: Another read current IR2 (usually IRmax, as we
shall show in Section IV-A) is applied and generates BL
voltage VBL2. We define the read current ratio β =IR2/IR1.
Sensing: VBL1 and VBL2O are compared by the voltage sense
amplifier. If VBL1 is significantly larger than VBL2O, the original
value of STT-RAM bit is “1” (high resistance state). Otherwise,
the original value of STT-RAM bit is “0” (low resistance state).
The explanation is as follows: If the original value of STTRAM bit is “1”, we have:
VBL1 = VBL,H1 = I R1 ⋅ (RH1 + RTR1 )
VBL2 = VBL,H2 = I R2 ⋅ (RH2 + RTR2 )
RL2
IR2(IRmax)
Figure 4. R-I curve in self-reference schemes.
.
(6)
If we set α = 1/β, then
= I R1 ⋅ (RH2 + RTR2 )
RH2
RL1
SLT1 is connected to BL as well as the corresponding voltage
storage element C1. The other switch transistor SLT2 is
connected to a voltage divider. Two inputs of a voltage sense
amplifier are connected to the top connect point of C1 and the
output of the voltage divider (VBL2O), respectively. The voltage
ratio of the voltage divider α =VBL2O/VBL2.
VBL2O = VBL,H2O = α ⋅ VBL2 =
RH1
∆RHmax
∆RLmax
(IR2-IR1)
RU
VBL2O
SL
C2
C1
(IR1)
ColDec
NMOS
Transistor
VBL1
MTJ
MTJ
SLT2
I R1
⋅ I R2 ⋅ (RH2 + RTR2 )
I R2
. (7)
Here RH1 and RH2 are the resistances of MTJ at high
resistance state, under read current IR1 and IR2, respectively; and
VBL,H1 and VBL,H2 are the corresponding BL voltages,
respectively. VBL,H2O is the output of voltage divider when MTJ
is at high resistance state, under IR2. If we assume
RTR1=RTR2=RTR, then the sense margin for “1” is
∆VBL,H = VBL, H1 − VBL,H2O = I R1 ⋅ (RH1 − RH2 ) > 0
because RH1 is significantly larger than RH2.
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(8)
Similarly, if the original value of STT-RAM bit is “0”, we
have the sense margin for “0”
∆VBL,L = VBL, L1 − VBL,L2O = I R1 ⋅ (RL1 − RL2 ) ≈ 0 (9)
because RL1 is close to RL2 (see Figure 2). Here VBL,L1 and
VBL1,L2 are the BL voltages when the MTJ resistance equals RL1
or RL2, respectively. VBL,L2O is the output of voltage divider
when MTJ is at low resistance state, under IR2.
Compared to conventional self-reference scheme, our new
self-reference scheme is nondestructive because it eliminates
the “erase” and “write back” steps. The total read latency and
power consumption are dramatically reduced accordingly.
For simplicity, here we ignored the leakage current of the
voltage divider and the resistance variation of SLT2. Usually
we choose α = 0.5 (a symmetric structure of voltage divider) to
minimize the impact of process variation on our design.
B. Read Current Ratio Optimization
In practice, designing a circuit to detect two values, e.g.,
VBL,L1 and VBL,L2O, being “equal” is very difficult. Instead, we
carefully chose IR1 to ensure VBL,H1 > VBL,H2O > VBL,L2O > VBL,L1.
STT-RAM bit is “1” when VBL1 > VBL2O, otherwise it is “0”.
The optimal β that ensures the equal sense margins when
MTJ is at both high- and low-resistance states (or |VBL,H1 –
VBL,H2O| = |VBL,L2O – VBL,L1|) can be calculated by solving:
1
=
α ⋅β
RH2 + RL2 + 2 RTR2
. (10)
 1
RH2 + RL2 + (∆RHmax + ∆RLmax ) ⋅ 1 −  + 2 RTR1
 β
IV.
ROBUSTNESS ANALYSIS
There are three main factors significantly affect the
effectiveness of the nondestructive self-reference schemes: the
variation of read current ratio β, the shift of the NMOS
transistor resistance RTR under IR1 and IR2, and the variation of
voltage ratio α. We use the variation range of the above three
factors for a nonzero sense margin of a STT-RAM bit to
measure the robustness of STT-RAM self-sensing scheme.
Robustness Analysis of Read Current Ratio β
A.
1) Read current selection of conventional self-reference
The variation of β comes from the process variation of read
current driver circuit. Based on Eq. (4), the read current ratio of
conventional self-reference scheme needs to satisfy:
1+
(RL1 − RL2 ) + ∆RTR
(RL2 + RTR2 )
<
(R − RL2 ) + ∆RTR , (11)
I R2
< 1 + H1
(RL2 + RTR2 )
I R1
where ∆RTR=RTR1−RTR2. Since the NMOS transistor works at
linear region, approximately RTR1=RTR2=RTR. We have:
1+
(RL1 − RL2 ) < β < 1 + (RH1 − RL2 )
.
(RL2 + RTR )
(RL2 + RTR )
For multiple STT-RAM bits, a valid β exists only if:
(12)
 R − RL2
Max L1
 RL2 + RTR

 R − RL2
 < Min H1

 RL2 + RTR

 .

(13)
Eq. (13) shows that the conventional self-reference scheme
is also more or less affected by the bit-to-bit variation of MTJ
resistance, if multiple STT-RAM bits are considered.
2) Read current selection of nondestructive self-reference
The selection of read currents in our nondestructive selfreference scheme needs to ensure:
αI R2 ⋅ (RH 2 + RTR2 ) < I R1 ⋅ (RH1 + RTR1 ) ,
(14a)
I R2 ⋅ (RL2 + RTR2 ) < I R2 ⋅ (RH 2 + RTR2 ) ,
(14b)
I R1 ⋅ (RL1 + RTR1 ) < αI R2 ⋅ (RL2 + RTR2 ) .
(14c)
Eq. (14b) is always true. If we assume RTR1=RTR2=RTR, a
solution of β can be found as long as:
1+
∆RL
∆RH
< α ⋅ β < 1+
.
RL2 + RTR
RH2 + RTR
(15)

1
Here ∆RL = RL1 − RL2 = ∆RLmax ⋅ 1 −  and ∆RH=RH1−
 β
 1
RH2= ∆RHmax ⋅ 1 −  . A valid selection of β exists only if:
 β
∆RLmax
∆RHmax
.
(16)
<
RL2 + RTR RH2 + RTR
Eq. (16) is always true for a normal MgO-based MTJ. For
multiple STT-RAM bits, a valid β exists only if:
 ∆RLmax
Max
 RL2 + RTR

 ∆RHmax
 < Min

 RH2 + RTR

 .

(17)
Normally the left side of Eq. (17) is close to zero since
∆RLmax≈0. Increasing the maximum read current IR2 can
effectively increase the right side of Eq. (17) by reducing RH2
and increasing ∆RHmax simultaneously.
B. Robustness Analysis of NMOS Transistor Resistance ∆RTR
Even working at the linear region, the resistance of the
NMOS transistor in a 1T1J STT-RAM cell still shifts under
different read currents. In other word, ∆RTR > 0.
1) RTR variation in conventional self-reference
Recall Eq. (11), ∆RTR needs to satisfy:
(β − 1) ⋅ (RL2 + RTR2 ) − (RH1 − RL2 ) < ∆RTR
.
< (β − 1) ⋅ (RL2 + RTR2 ) − ∆RL
(18)
2) RTR variation in nondestructive self-reference
From Eq. (14a) and (14c), ∆RTR needs to satisfy:
(αβ − 1) ⋅ (RH 2 + RTR2 ) − ∆RH < ∆RTR
.
< (αβ − 1) ⋅ (RL2 + RTR2 ) − ∆RL
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(19)
TABLE I. ELECTRICAL PARAMETERS OF MTJ AND NMOS TRANSISTOR*
* Calculated based on the R-I curve of the typical device shown in Figure 2.
C. Robustness Analysis of voltage ratio α
Process variation also results in the deviation of the voltage
ratio α of voltage divider away from the designed value.
We assume ∆ is the deviation of voltage ratio from the
designed value. Replacing α in Eq. 14(a)−(c) by α (1+∆), we
have the range of ∆ for the correct read operation as:
 R + RTR 
1
 − 1 < ∆ <
⋅  L1
αβ
R
+
R
TR 
 L2
Here we assume RTR1=RTR2= RTR.
1
αβ
 R + RTR
⋅  H1
 RH2 + RTR

 − 1 . (20)

We note that the capacitance variation of C1 and C2 does
not affect the operation of conventional self-reference scheme.
V.
EXPERIMENTAL RESULTS
In our testing chip design, an auto-zero sense-amplifier with
a built-in data latch is used to eliminate the influence of device
mismatch in sense amplifier. The sizes of SLT1 and SLT2 are
carefully tuned to minimize the leakage current. There are 128
STT-RAM bits on each bitline. The impedance of the voltage
divider is ~ tens MΩ, which is significantly higher than that of
STT-RAM memory cell. Then the impact of the leakage
current through the voltage divider is minimized.
The measured parameters of a typical MTJ device (see Fig.
2) and the NMOS transistor are used in our simulations, as
shown in TABLE I. The maximum read current IR2 is set to
200µA, which is 40% of the switching current of MTJ
(~500µA) with 40ns write pulse width. The designed voltage
SM0-Con
300
SM1-Con
SM0-Nondes
SM1-Nondes
Valid β ratio for Con scheme
SM1-Con
160
40
0
-500
-300
Allowable ∆RTR for Nondes scheme
-40
300
-100
100
-100
-200
Valid β ratio for Nondes scheme
-300
1
1.2
1.4
1.6
1.8
2
IR2/IR1 Ratio (β )
Figure 6. Selection of read current ratio β= IR2/IR1 .
2.2
2.4
500
∆RTR(Ω)
Figure 7. Robustness for NMOS transistor resistance.
ratio α is set to 0.5, to minimize the impact of device mismatch
and process variation.
Figure 6 shows the relationship between the read current
ratios β and the corresponding sense margins of two selfreference schemes. We assume there are neither NMOS
transistor resistance shifting (∆RTR=0) nor voltage ratio
variation (∆=0). “SM0” and “SM1” denote the sense margin of
bits “0” or “1”, respectively. “-Con” and “-Nondes” denote the
conventional self-reference scheme and our nondestructive
scheme, respectively.
Figure 7 shows the allowable variation of NMOS transistor
resistance ∆RTR for two self-reference schemes and the
corresponding sense margins. Here we assume α and β are at
their designed values (see TABLE I). The designed value of RTR
is set to 917Ω. ±130Ω variation tolerance range means 14.2%
of RTR, which is far beyond the normal process variation.
Figure 8 shows the allowable variation of voltage ratio in
our nondestructive self-reference scheme and the
corresponding sense margins. Here we assume α is 0.5 and
∆RTR=0. Based on our experience, the variation control of
voltage ratio α is very difficult. In the design of our testing
chip, the current ratio β of read current driver can be adjusted
in testing stage to compensate the voltage ratio α variation.
The robustness analyses of two self-reference schemes are
summarized in TABLE II.
Figure 9 shows the timing diagram of our nondestructive
self-reference scheme. Different read currents are applied to
STT-RAM cell by turning on STL1 or STL2, respectively. The
signal sensing is triggered by signal “SenEn” and the output of
sense amplifier is latched by enabling signal “Data_latch”.
Figure 10 shows the simulation results of our nondestructive
self-reference scheme. The circuitry is implemented with
TSMC 0.13µm technology. The leakage current of other
SM0-Nondes
0
SM1-Nondes
Allowable ∆RTR for Con scheme 80
200
100
SM0-Nondes
120
Sense Margin (mV)
Sense Margin (mV)
400
SM0-Con
Sense Margin (mV)
MTJ parameters
RH2
RL2
2050Ω
1220Ω
∆RHmax
600Ω
∆RLmax
10Ω
RTR
917Ω
Ιmax(ΙR2)
200µA
Parameters for conventional self-reference scheme
RH1
RL1
2158.2Ω
1221.8Ω
∆RH
108.2Ω
∆RL
1.8Ω
1.22
β
Max. Sense Margin (mV)
76.6
Parameters for nondestructive self-reference scheme
RH1
RL1
2367.8Ω
1225.3Ω
∆RH
317.8Ω
∆RL
5.3Ω
2.13
β
Max. Sense Margin (mV)
12.1
-6%
SM1-Nondes
30
20
10
0
-5%
-4%
Allowable α variation for Nondes scheme
-10
-1%
1%
-3%
-2%
0%
2%
3%
Voltage Ratio Variation ∆
Figure 8. Robustness for voltage ratio.
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4%
5%
TABLE II. ROBUSTNESS OF TWO SELF-REFERENCE SCHEMES
Max. β
Min. β
Max. ∆RTR
Min. ∆RTR
Max. ∆
Min. ∆
Conventional
1.47
~1
+468Ω
-468Ω
N/A
N/A
Nondestructive
2.222
2
+130Ω
-130Ω
+4.13%
-5.71%
unselected memory cells has been considered in our simulation.
The whole read operation can complete in about 15ns.
Additional capacitor at the end of BL increases the RC
delay and consequently, elongates the read latency. A high
impedance voltage divider, however, does not change the
Elmore delay of BL. Therefore, our 2nd read usually is faster
than that of conventional self-reference scheme. To achieve
even faster output, a pre-charge stage may be needed.
Nondestructive self-reference scheme has relatively tighter
constraints on the device variations than that of conventional
self-reference scheme. However, our technique has much faster
read speed by eliminating two write steps (erase and writeback) and shortening the 2nd read step. The reliability of STTRAM is improved by maintaining the non-volatility. The sense
margin and the robustness of nondestructive self-reference
scheme can be improved by increasing the maximum allowable
read current Imax (IR2). The methods to increase Imax without
affecting the memory reliability are beyond the scope of this
research and will be discussed in the future work.
VI.
CONCLUSION
We proposed a novel self-reference read scheme of STTRAM to overcome the large bit-to-bit variation of MTJ
resistance. Compared to conventional “destructive” selfreference scheme, our scheme does not need to erase the
original value of STT-RAM bit and eliminates the write back
step. The non-volatility of STT-RAM is maintained and the
read latency is significantly reduced. The robustness analysis
shows that our scheme requires restrict control on the device
Figure 10. Simulation result of nondestructive self-reference scheme.
variation and mismatch, with relatively small sense margin.
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200
Sense Margin for "0" (mV)
A 16kb testing chip is fabricated with TSMC 0.13µm
technology. The measured sense margins of conventional
sensing scheme, conventional destructive self-reference sensing
scheme and nondestructive self-reference sensing scheme with
optimized test configurations are shown in Figure 11. Assuring
a sense margin about 8mV of the auto-zero sense amplifiers,
about 10% of bits failed to be readout by conventional sensing
scheme. However, both destructive and nondestructive selfreference schemes successfully sensed all measured bits.
Pass
100
0
-100
Fail
-200
Conv. Sensing
Conv. Self-reference
Nondestructive Self-reference
-300
-400
-100
Figure 9. Timing diagram of nondestructive self-reference scheme.
0
100
200
300
400
500
Sense Margin for "1" (mV)
600
700
Figure 11. Sense margins for all sensing schemes
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