A Dual-Mode VCO based Low-Power Synthesizer with
Optimized Automatic Frequency Calibration for
Software-Defined Radio
Jin Zhou , Wei Li, Deping Huang , Chen Lian , Ning Li, Junyan Ren
State Key Laboratory of ASIC & System, Fudan University
Shanghai 201203, China
Email: w-li@fudan.edu.cn
Abstract—A low power sigma-delta fractional-N frequency
synthesizer for software-defined radio (SDR) implemented in a
0.13μm CMOS process is presented, based on a dual-mode VCO
(DMVCO) reconfigurable between wideband mode and
quadrature mode, with optimized automatic frequency
calibration (AFC). The proposed optimized AFC enables a more
accurate band selection as well as a lower power for a dual-VCO
PLL. A multi-phase counter (MPC) accelerates the calibration
process without ruining the calibration accuracy. Simulated
phase noise is -123dBc/Hz at 1MHz offset from a 1.8GHz carrier.
The spectral purity is better than 45dBc from the output of
mixer. The locking time of PLL is about 40μs with an AFC time
less than 10μs. The 0.4-6GHz synthesizer consumes only 35mW
to 51mW from a 1.2V supply.
I.
INTRODUCTION
The fast growing demand of wireless communication
keeps on driving RFIC design into a trend which is
characterized by smaller size and lower power. Currently,
multi-standard radio and software-defined radio(SDR), instead
of the simply integration of many standalone radio, has gained
many interest due to its relatively low cost and low power. In
such applications, since the local oscillator (LO) should meet
the most demanding requirement, a wideband continuously
tunable frequency synthesizer is one of the most critical
buliding blocks. Reported state-of-the-art SDR frequency
synthesizers[1][2] usually use a dual-VCO structure with one
octave tuning range followed by a divide-by-N block to
generate a ultra wideband LO. In this architecture, VCOs are
operating at very high frequency and then LO is generated
simply by division. However, high frequency buffers and
dividers will disspate lots of power, especially when a
relatively bulky technology is used, i.e. 0.13µm CMOS in this
design. In another prevailing architecture[3], the tuning range
of the VCO is extended by a combination of mixer and
dividers and therefore the working frequency of the VCO is
relatively low so that the power issue mentioned before can be
addressed. But, in order to suppress the mixer’s image spur,
the usage of poly-phase filter(PPF) or QVCO is unavoidable
in a feasible design. In this paper, the architecture with the
combination of mixer and divider is still used for low power,
but a dual-mode VCO (DMVCO)[4] with a octave tuning
range is adopted here to replace the power hungry PPF or
QVCO with limited tuning range for single-sideband mixing.
In this DMVCO based frequency synthesizer, a dual-VCO
PLL is adopted like other wideband synthesizers for wireless
communication or broadcasting system [5]. Previous
automatic frequency calibration (AFC) algorithm in such
synthesizers is transplanted from the one in synthesizer with
single-VCO to select the optimal frequency control code.
However, by a careful analysis, it is not difficult to find that in
the overlap region of the dual-VCO a less accurate code might
be selected using the conventional algorithm. In this paper, an
optimized AFC algorithm is proposed for dual-VCO PLLs. By
using this optimized algorithm not only the AFC accuracy is
enhanced but also the power consumption of the synthesizer
can be reduced. Moreover, in order to accelerate the
calibration process without ruining the calibration accuracy, a
multi-phase counter (MPC) is used in the proposed AFC.
Meanwhile, the proposed digital-intensive AFC technique can
be easily transplanted to the emerging all-digital PLLs.
This paper firstly describes the implementation of the
synthesizer. Then the limitation of the previous AFC
technique is explained and the optimized AFC technique is
presented. Finally, the simulation results are given and
conclusion is drawn.
II.
A. Architecture
The proposed synthesizer is designed for direct conversion
transceiver and supports standards including DVB-T, GPS,
GSM, WCDMA, Bluetooth and 802.11a/b/g WLAN. Fig.1
shows the architecture of the synthesizer, which consists of a
fractional-N phase-locked loop (PLL), an AFC loop, and a LO
generator. Fractional-N PLL is adopted, since fractional-N
architecture allows arbitrary output frequency resolution
which is appropriate for SDR application. The LO generator,
which comprises a VCO multiplexer, a quadrature single
This work was sponsored by National Sci & Tech Major Projects of
China with grant number of 2009ZX03006-007-01 and National High Tech
R&D (863) Program of China with grant number of 2009AA01Z261.
978-1-4244-9474-3/11/$26.00 ©2011 IEEE
IMPLEMENTATION OF THE SYNTHESIZER
1145
Vctrl
on
I+
I-
LB
LLB
off
Vctrl
on
Q+
4
CKVCO
off
on
Mc
Mc
Q-
I-
Mc
Mc
5
DLB
I+
VBIAS
VBIAS
VCOL_EN
VCOH_EN
IQ_EN
RS
RS
CS
CS
IQ_EN
IQ_EN
4~6GHz
180°
(a)
Wide band Mode
Control
voltage
CS
IQ_EN
4~4.8GHz
180°
Couple
HB
frequency
(b)
Fig. 3 Code selection process of (a) previous AFC and (b) proposed AFC
0°
RS
CS
frequency
0°
90°
RS
A. Previous AFC Technique
Previous AFC technique can be classified as either a
closed-loop technique or an open-loop technique. Due to the
relatively fast calibration process, the open-loop method is
more popular than the closed-loop method. In open-loop
technique, the counter-based method [6] is widely used while
a recently reported period-based method [7] exhibits a very
fast calibration process. However, all these AFC techniques
are applied to a single-VCO PLL. Although in [5], an AFC
technique is used in a dual-VCO PLL, the misapplied
algorithm might lead to a selection of less optimum frequency
code and/or lead to unnecessary extra power dissipation. This
limitation of the previous AFC algorithm can be understood
by considering the following example in Fig.3 (a). It
demonstrates the binary search process for the target
frequency f1. Here we assume each VCO has a 3-bit frequency
control code for the sake of simplicity. For the target
frequency f1, the previous AFC code selection algorithm will
choose the code 10, since this code has the minimum
frequency error among the code 8, 12, 10 and 9. Nevertheless,
from Fig.3 (a) it is not difficult to find that code 6 actually has
the minimum frequency error. Moreover, since less capacitors
are switched into the tank, code 6 located in the upper band of
LB VCO has a higher tank quality factor. Therefore, less
power will be dissipated by the VCO for the same phase noise
if code 6 rather than code 10 is selected in this case.
0°
HB
LB
Q+
AUTOMATIC FREQUENCY CALIBRATION TECHNIQUE
3~4.8GHz
180°
Control
voltage
Q-
Switched
Capacitor
Array
on
off
Switched
Varactor
Array
VDD
DECODER
5
DHB
L HB
off
DECODER
CKVCO
Low Band
VCO
VDD
DECODER
4
DECODER
High Band
VCO
III.
frequency
Fig. 1 Diagram of fractional-N synthesizer
B. Dual-Mode VCO
Fig.2 depicts the circuit diagram and operation mode of the
DMVCO. Class-C NMOS VCO is adopted for its low phase
noise and wide tuning range. In quadrature mode, a phase shift
provided by the RS and CS is used to de-sensitize the VCO to
the mismatch in the tail currents. To further minimize the
mismatch between the two different LC-tanks for a precise
quadrature signal, switched varactor array and switched
capacitor array are both used here. Decoders translate binary
codes into thermometer codes to control the switches. The
DMVCO has 6-bit frequency control code, 5 bits for each
VCO and 1 bit for band selection. The 4-4.8GHz overlap
between HB and LB VCO guarantees continuous frequency
coverage with process, voltage, and temperature variation and
also enables the quadrature mode operation of the DMVCO.
division ratio ranging from 75 to 150. The delta-sigma
modulator is a third-order 12-bit MASH-111 type.
frequency
MUX 3
MUX2
sideband mixer (QSSBM), a divider chain and a output
multiplexer, generates in-phase/quadrature phase signal over
the frequency bands 0.4-3G, 5-6G, with the constraint that the
VCO never runs at the RF frequency, to avoid the well-known
pulling problem in direct conversion radio architectures. The
DMVCO that constituted by a 4-6GHz high band (HB) VCO
and a 3-4.8GHz low band (LB) VCO can be switched to HB
VCO or LB VCO, or reconfigured into a quadrature mode in
which HB VCO and LB VCO are coupled with each other in
their overlap region to generate quadrature signal for the mixer
to suppress image spur. The AFC block is used to find an
optimal VCO tuning curve that is closest to the target
frequency and to facilitate the dual mode operation of the
VCO.
4~4.8GHz
270°
Quadrature Mode
Fig. 2 Circuit diagram and operation mode of dual-mode VCO
C. Charge pump and Programmable Divider
The charge pump current is made programmable between
15uA and 105uA to compensate the variation of the division
ratio and the VCO tuning gain in order to achieve a relatively
constant PLL bandwidth for a better phase noise performance
and a more stable operation of PLL. The programmable
divider consists of 7 cascade divide-by-2/3 cells with a
B. Proposed Optimized AFC Technique
The proposed optimized AFC adopts a digital-intensive
counter-based architecture which is composed of a frequency
detector (FD) and a finite state machine (FSM) to select an
optimal VCO tuning curve that is closest to the target
frequency in either wideband mode or quadrature mode. The
detail block diagram of the proposed AFC is depicted in Fig.4.
As the calibration starts, PLL is open and VCO tuning voltage
is set to VDD/2. Then, VCO output will be firstly divided by 4
to lower the input frequency of AFC and subsequently fDIV
which equals fVCO/4 is counted to Ncnt during a period TGATE.
Meanwhile, the target frequency Ndec is obtained by
multiplying the division ratio N.F and p. Here, p=24 is chosen
1146
selected and less power is dissipated as well using the
proposed AFC technique compared to the previous one.
δ
÷
δ
Fig. 4 Block diagram of the proposed AFC
in this design which indicates Ndec includes the integer
modulus and 4 MSBs of fractional modulus of desired
division ratio N.F. Afterwards, the frequency error δ between
the target frequency and the current VCO frequency is
generated by a comparator. A minimum error register in FSM
is used to store the latest minimum frequency error and its
corresponding frequency control code (FC). Then, the state
machine shift the VCO sub-band according to the sign bit of
the δ using a binary search scheme.
Fig.5 shows the flowchart of the proposed AFC. The
overall calibration process of the proposed AFC technique can
be divided into two steps, which are step one minimum error
search and step two optimal code selection. In the first step,
the LB VCO and HB VCO are calibrated successively, and the
minimum frequency error code for each VCO is stored in the
register. In step two, the operation mode is firstly checked. If
it is quadrature mode, then the optimal control codes FCLB and
FCHB are fed into LB VCO and HB VCO respectively. If it is
wideband mode, then the minimum frequency error of LB
VCO and HB VCO are compared. The FCLB is fed to LB
VCO and LB VCO is enabled if the minimum errors are the
same since the LB VCO will dissipate less power in this case,
otherwise the one with smaller error will be chosen. The
whole process can be illustrated in Fig.3 (b). After the
calibration of both VCO, minimum error control code FCLB=6
and FCHB=10 are obtained. Then if it is quadrature mode, the
two codes are fed to the corresponding VCO. If it is wideband
mode, FCLB would be chosen since LB VCO has a smaller
frequency error. From the example in Fig.3, a more accurate
sub-band of VCO that is closest to the target frequency can be
Since the proposed optimized AFC process have to
calibrate both the LB VCO and HB VCO, the calibration time
of proposed AFC could be twice as long as that of the
previous one. In order to accelerate the calibration process
without ruining the overall calibration accuracy, a multi-phase
counter (MPC) is proposed. Fig.6 (a) depicts the counting
operation of the conventional single counter [8] architecture.
The output of divider fDIV is counted within a counting
window which has a time period TGATE=4p×TREF. Due to jitter
of the counting window, the counting number Ncnt can be 2m
or 2m+1, which indicates that the counter provides a finite
frequency resolution for fDIV and fVCO. Here, the frequency
resolution for fVCO is given by
f res =
f
1
4
⋅ VCO =
4p ⋅ TREF f DIV TGATE
(1)
Equation (1) shows that a faster counting process with a
smaller counting window will lead to a worse resolution
which will deteriorate the calibration accuracy. Fig.6 (b)
depicts the timing diagram of counting operation in the
proposed MPC. Here, actually two-phase (i.e. differential)
counter is adopted for simplicity. The differential phase
signals are generated from the output of divider fDIV using an
inverter and a pass gate respectively. Within the counting
window that is half as large as the one in Fig.6 (a), the
counting number is still 2m or 2m+1 which implies the same
resolution is obtained. Therefore, the calibration accuracy is
not deteriorated even though the counting process is twice as
fast as before.
TGATE = 4 p × TREF
(a)
TGATE = 2 p × TREF
| δ |min,LB=| δ |min,HB?
(b)
Fig. 5 Flowchart of the proposed AFC
Fig.6 Timing diagram of counting operation in (a) conventional counter
(b) proposed multi-phase counter
1147
IV.
SIMULATION RESULTS
dBc ⋅ Hz −1
The proposed frequency synthesizer is implemented in
TSMC 0.13μm CMOS process. All circuit blocks have been
integrated on chip. Layout and simulated phase noise of the
synthesizer is shown in Fig.7. The synthesizer fulfills the most
stringent phase noise requirement of GSM at 900MHz. Fig. 8
shows the spur performance in quadrature mode. The image
spur rejection ratio is better than 45dBc, which indicates
precise quadrature signals are generated from DMVCO and
fulfills the requirement for 802.11a WLAN. Note that in this
prototype, DMVCO are calibrated manually using switched
varactor array and programmable current bias for simplicity,
but calibration technique in such as [9] is applicable in future
design to correct the errors automatically. The simulated
PLL’s control voltage is depicted in Fig.9, which illustrates a
locking process in wideband mode where a frequency control
code with minimum frequency error is selected. Table 1
compares the proposed frequency synthesizer with the state-
Fig. 7 Layout and simulated phase noise of the synthesizer
TABLE I. Performance summary and comparison
Tech.
Area
Output
freq.
PN
(dBc/Hz)
Power
*
JSSC2010[1]
0.04µm
CMOS
0.3 mm2
0.1-12GHz
-123@1MHz
LO: 1.8GHz
35-51mW
-119@1MHz,
LO: 4.2GHz
56mW
-149@20MHz
LO: 3.6GHz
30mW
simulation results, with AFC integration
V.
CONCLUSION
A Σ-Δ fractional-N synthesizer based on a dual-mode
VCO for software-defined radio is presented and implemented
in 0.13μm CMOS process. The proposed optimized AFC
algorithm with a multi-phase counter enables a fast and highprecision calibration process for dual-VCO PLLs. Meanwhile,
power consumption of the synthesizer is greatly reduced by
using the DMVCO together with the proposed AFC technique.
Although applied in an analog architecture, our solutions are
general and can be applied to all-digital PLLs.
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Vctrl , mV
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of-the-art. Although using a relatively bulky technology, the
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[2]
Fig. 8 Spur performance of the synthesizer
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0.13µm
CMOS
2.2mm2
0.4-6GHz
[7]
[8]
[9]
Fig. 9 Locking Process of the PLL
1148
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