Microelectronic Engineering 83 (2006) 303–311
www.elsevier.com/locate/mee
Enhanced breakdown voltage and reduced self-heating effects
in thin-film lateral bipolar transistors: Design and
analysis using 2-D simulation
Sukhendu Deb Roy, M. Jagadesh Kumar
*
Department of Electrical Engineering, Indian Institute of Technology, Delhi, Hauz Khas, New Delhi 110 016, India
Received 25 May 2005; received in revised form 10 September 2005
Available online 10 October 2005
Abstract
In this work, we present our two-dimensional numerical simulation studies and analysis of the enhanced breakdown and self-heating
characteristics of a new collector-tub three-zone step doped thin-film lateral bipolar transistor (CT-SLBT) on silicon-on-insulator (SOI),
which shows enhanced breakdown voltage as high as 80% when compared with that of the conventional uniformly doped lateral bipolar
transistor (LBT) on SOI. The design issues and the reasons for the improved performance are discussed in detail.
2005 Elsevier B.V. All rights reserved.
Keywords: High-voltage; Thin-film; Lateral bipolar transistor; Step-doping; Collector-tub; Silicon-on-insulator; Self-heating
1. Introduction
High voltage thin-film (<1.0 lm) lateral bipolar transistors (LBTs) on silicon-on-insulator (SOI) are gaining
renewed attention because of their compatibility in the
BiCMOS process [1–3] or power integrated circuits (PICs)
[4–8]. In addition, due to conductivity modulation in the
drift region, thin-film LBTs on SOI are expected to show
reduced effective on-state resistance at an identical voltage
rating when compared with their MOSFET counterparts.
However, one major drawback of the conventional thinfilm LBTs on SOI is their low off-state blocking voltage
(100 V) [9–11], which restricts their usefulness in high
voltage analog applications such as switching, driver or
low power RF circuits [12–18]. The present paper first highlights the difficulties in realizing high breakdown voltage in
the conventional thin-film LBTs on SOI and then proposes
*
Corresponding author. Tel.: +91 11 2659 1085; fax: +91 11 2658 1264.
E-mail address: mamidala@ieee.org (M.J. Kumar).
0167-9317/$ - see front matter 2005 Elsevier B.V. All rights reserved.
doi:10.1016/j.mee.2005.09.003
a new high voltage LBT on SOI structure as discussed in
the following section.
Conventional thin-film LBTs on SOI show reduced
breakdown voltage because of the non-uniform lateral surface electric field distribution in the drift region [19,20].
One common method to overcome this difficulty has been
to use an optimum linearly graded drift-charge [21–25] in
combination with a thick buried-oxide (BOX) to produce
reduced surface electric field (RESURF) effect, thereby
enhancing the breakdown voltage. But obtaining a perfect
graded profile has been found to pose practical difficulty
due to the requirements of precise mask layout and photolithographic steps, exact implantation dose and drive-in
schedule. Hence, as an alternative, Sunkavalli et al. [26]
have introduced the concept of step doped drift-charge.
Using thick SOI film (3.0 lm) on thick BOX (3.0–7.0 lm)
in their simulation studies, they have demonstrated that a
three-zone step doped diode on SOI produces RESURF
effect and exhibits almost identical breakdown voltage as
that of a diode with an optimum graded doping profile. However, since an insulator thickness of 3.0 lm is
expected to introduce considerable thermal resistance and
304
S.D. Roy, M.J. Kumar / Microelectronic Engineering 83 (2006) 303–311
undesirable heating of the thin SOI film [27,28], we have
used a BOX thickness of 1.0 lm in our work. Our twodimensional numerical simulation studies show that the
three-zone step-doped collector thin-film LBTs (SLBTs)
on SOI: (a) allow: using high effective drift dose and (b)
produce more uniform lateral surface electric field profile
in the drift region than those of the conventional uniformly
doped collector LBTs, thereby enhancing the breakdown
voltage by about 50%. In addition, three-zone step doping
profile shows the advantage of using lower doping concentration near the base–collector (P+N) junction side to
reduce the junction electric field and improve the I–V characteristics. However, as observed in all high voltage thinfilm devices isolated from the substrate by a thin BOX,
further improvement in their breakdown is limited by the
high surface electric field and potential crowding effect in
the BOX at the collector high-low (NN+) junction side.
Previous work [29–31] has shown that the limitation of
high electric field build up at the collector NN+-junction
side can be solved if the applied potential is shared between
the collector drift and substrate regions using the collectortub (CT) concept. The difficulty with the CT-LBT structure, however, is the fact that it requires low drift-dose in
accordance with the RESURF principle to produce the
improved breakdown voltage. In this paper, we demonstrate that by using the combined effect of collector-tub
concept and three-zone step doped collector in the thin-film
LBT: (a) a high effective drift dose can be adopted than
that of the CT-LBT structure, (b) output characteristics
can be improved by tailoring the step doping profile and
(c) collector breakdown voltage can be enhanced by about
80% when compared with that of the conventional uniformly doped LBT with identical Si-film and BOX thick-
nesses. We also show that the proposed three-zone Step
doped collector LBT (CT-SLBT) structure helps to reduce
the steady state temperature rise in the active region
because of the lateral conduction of the dissipated heat
through the collector-tub into the substrate region.
In the following sections, we present the process steps to
realize CT-SLBT structure and analyze the reasons for its
enhanced breakdown voltage and compare its self-heating
characteristics with those of the conventional and stepdoped collector LBT on SOI structures.
2. Simulation methodology
Five sets of LBTs on SOI structures were created in the
two-dimensional process simulator ATHENA [32] using
experimental parameters from the literature [33–36], which
were then imported for simulation in the two-dimensional
device simulator ATLAS [37]. The first set of simulated
structures comprised of conventional LBTs to show that
at SOI film thicknesses less than 0.5 lm, the use of drift
charge is limited by the peak electric field at the base–collector junction (P+N) side and (b) the breakdown voltages
cannot be increased with the increase in drift length (LD).
Next, three sets of LBT structures were simulated with different SOI film thicknesses (1.0–0.2 lm): (a) conventional
LBTs and (b) two-zone step-doped collector LBTs and
(c) three-zone step-doped collector LBTs (SLBT) to demonstrate enhanced breakdown voltages of the SLBTs when
compared with those of the conventional and two-zone
step-doped collector LBTs. The fifth set of simulated structures was CT-SLBTs to show their 80% enhancement in the
breakdown voltage and improved self-heating effect over
those of the conventional and step-doped LBTs.
Fig. 1. Process flow for the collector-tub three-zone step doped lateral bipolar transistor (CT-SLBT).
S.D. Roy, M.J. Kumar / Microelectronic Engineering 83 (2006) 303–311
305
2.1. Process simulation to realize collector-tub three-zone
step doped collector LBT (CT-LBT) structure
2.2. Device simulation
The various models, which are used in the two-dimensional device simulator ATLAS are Fermi-Dirac distribution for carrier statistics, KlaassenÕs unified mobility
model for dopant-dependent low-field mobility, analytical
field dependent mobility for high electric field, Slotboom
model for bandgap narrowing, SelberherrÕs ionization rate
model for impact ionization and Shockley–Read–Hall
(SRH) and Klaassen Auger recombination models for
minority carrier recombination lifetime. The SRH recombination lifetime for silicon is chosen to be 2.0 ls for a carrier
concentration of 5.0 · 1016 cm 3 and for all other concentrations, recombination lifetimes are calculated using Roul-
Fig. 2. Schematics of: (a) conventional lateral bipolar transistor (LBT);
(b) three-zone step doped lateral bipolar transistor (SLBT) and (c)
collector-tub three-zone step doped lateral bipolar transistor (CT-SLBT).
12
-2
CT Three-zone step doped LBT, qD=0.6x10 cm
20
10
12
-2
Three-zone step doped LBT, qD=1.4x10 cm
+
N
11
-2
+
N
Conventional LBT, qD=0.8x10 cm
tSi=0.2 µm
tBOX=1.0 µm
LD ~ 43.0 µm
19
10
-3
Net doping [ cm ]
The sequence of process steps for obtaining CT-SLBT
is shown in Fig. 1. First, the N-collector tub region is
formed following the process steps as described in [29].
This involves etching the top silicon and BOX thicknesses, followed by phosphorus implantation and then
refilling the etched region with heavily doped poly or single crystal silicon (Fig. 1(a)). Next a pad oxide is grown
over the SOI film and using a mask, about 0.5 lm thick
nitride region is deposited for defining the base region,
followed by deposition of photoresist (Fig. 1(b)). Using
photoresist as the mask windows, the three-zone step
doped collector and N+-emitter regions are created using
multiple phosphorus implantations (Fig. 1(c)–(f)). The
photoresist and pad oxide from the exposed region are
etched away and about 1.0 lm of CVD oxide is deposited
to act as the field oxide. This is followed by etch back of
top oxide and planarization by CMP process until the
nitride layer is exposed. The nitride region is then etched
away using RIE method with the pad oxide as the etch
stop. Next blanket implantations of high and low energy
boron are performed for forming the P+-base region
(Fig. 1(g)). The multiple implantations are necessary to
keep the peak boron concentration almost uniform near
the silicon-field oxide or top silicon-BOX interfaces,
thereby preventing low base punchthrough voltage along
these interfaces. The base contact is then formed by wet
etching of pad oxide over the base region, followed by
deposition of about 0.3 lm in situ doped (1.0 · 1020
cm 3) P+-polysilicon (Fig. 1(h)). The field oxide is then
patterned and deposited with Al to form the emitter, base
and collector contacts (Fig. 1(i)). The Al metal is
extended over the field oxide at the P+N-junction and collector N+N-junction sides and their lengths are optimized
to act as metal field termination. Fig. 2 shows the final
conventional LBT, SLBT and CT-SLBT structures and
Fig. 3 shows their corresponding doping profile. The optimum device parameters and their dimensions are shown
in Table 1.
18
10
P
ND
17
10
16
10
15
10
0
5
10 15 20 25 30 35 40 45 50 55
Transistor length [ µm ]
Fig. 3. Doping profiles of the conventional LBT, three-zone step doped
lateral bipolar transistor (SLBT), and collector-tub three-zone step doped
lateral bipolar transistor (CT-SLBT).
stonÕs equation [38]. The simulated peak common emitter
current gain of all the structures is kept approximately at
30 for a collector–base voltage (VCB) of 10 V and the
306
S.D. Roy, M.J. Kumar / Microelectronic Engineering 83 (2006) 303–311
Table 1
Device parameters
Parameters
Conventional
LBT
Two-zone step-doped
LBT
Three-zone step-doped
LBT
Collector-tub three-zone
step-doped LBT
SOI thickness
1.0–0.2 lm
1.0–0.2 lm
1.0–0.2 lm
1.0–0.2 lm
Buried oxide (BOX) thickness
1 lm
1 lm
1 lm
1 lm
Emitter length
6.2 lm
6.2 lm
6.2 lm
6.2 lm
Base depth
1.5–1.6 lm
1.5–1.6 lm
1.5–1.6 lm
1.5–1.6 lm
Collector drift-region length
10–50 lm
Peak emitter doping level
5.0 · 1019 cm
Peak base doping level
2.0 · 1017 cm
Collector drift-dose
tSi = 1.0 lm
tSi = 0.5 lm
tSi = 0.2 lm
1.0 · 1012 cm
1.0 · 1012 cm
0.8 · 1012 cm
2
5.0 · 1017 cm
3
CT-junction depth
tSi = 1.0 lm
tSi = 0.5 lm
tSi = 0.2 lm
3
2
2
–
5.0 · 1019 cm
Field plate termination length
2–3 lm
3
5.0 · 1019 cm
3
5.0 · 1019 cm
3
2.0 · 1017 cm
3
2.0 · 1017 cm
3
2.0 · 1017 cm
3
1.1 · 1012 cm
1.3 · 1012 cm
1.1 · 1012 cm
2
1.2 · 1012 cm
1.6 · 1012 cm
1.3 · 1012 cm
2
1.6 · 1011 cm
6.0 · 1011 cm
6.0 · 1011 cm
2
5.0 · 1017 cm
3
5.0 · 1017 cm
3
1.0 · 1014 cm
4.5 · 1014 cm
1.0 · 1015 cm
3
5.0 · 1019 cm
10
-1
IB, IC [ Aµm ]
-6
-8
10
2
3
2
2
CT Three-zone step doped LBT
Three-zone step doped LBT
Conventional LBT
2
2
3
3
5.0 lm
2.6 lm
1.2 lm
5.0 · 1019 cm
2–3 lm
-2
-4
2
–
collector–emitter breakdown voltages (BVCEO) are compared at a collector current of about 1.0 lA. Figs. 4 and
5 show, respectively, the Gummel plots and common emitter current gain (b) curves for the conventional LBT, SLBT
and CT-SLBT structures. Other simulation parameters are
shown in Table 2.
10
40–45 lm
3
–
Collector N+ contact doping level
10
40–45 lm
5.0 · 1019 cm
3
5.0 · 1019 cm
2–3 lm
3
2–3 lm
30
25
Current gain, β
Substrate doping level
tSi = 1.0 lm
tSi = 0.5 lm
tSi = 0.2 lm
40–45 lm
3
20
VCB= 10 V
tSi= 0.2 µm
tBOX= 1.0 µm
LD~ 43.0 µm
15
10
CT Three-zone step doped LBT
Three-zone step doped LBT
Conventional LBT
5
IC
VCB= 10 V
tSi= 0.2 µm
tBOX= 1.0 µm
LD~ 43.0 µm
0
10
IB
-10
-12
10
-11
10
-10
-9
-8
-7
10
10
10
10
-1
Collector current, IC [ Aµm ]
-6
10
-5
-4
10
10
Fig. 5. Collector current versus current gain of the collector-tub threezone step doped lateral bipolar transistor (CT-SLBT) compared with
those of the conventional LBT and three-zone step doped lateral bipolar
transistor (SLBT).
-12
10
-14
10
-16
10
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Base-emitter voltage, VBE [ V ]
Fig. 4. Gummel plots of the collector-tub three-zone step doped lateral
bipolar transistor (CT-SLBT) compared with those of the conventional
LBT and three-zone step doped lateral bipolar transistor (SLBT).
3. Simulation results
3.1. Limitation of uniformly doped ultra-thin LBT structure
Fig. 6 shows the output characteristics of the conventional
LBTs on SOI optimized for maximum breakdown voltage,
Table 2
Simulation parameters
Parameters
Value
SRH electron and hole
lifetime coefficients (TAUN0, TAUP0)
SRH electron and hole lifetime
at the polysilicon base contact (TAUN0, TAUP0)
Surface recombination velocity
at the poly base contact (VSURFP)
Interface states at the silicon-oxide interface
Metal (Al) workfunction for the ohmic contact
2.0 · 10
6
3.4 · 10
10
s
s
2.5 · 106 cm s
1
5.0 · 1010 cm
4.17 eV
2
Breakdown voltage, BVCEO [ V ]
S.D. Roy, M.J. Kumar / Microelectronic Engineering 83 (2006) 303–311
307
tSi= 0.2 µm
tSi= 0.5 µm
tSi= 1.0 µm
140
12
q= 1.0x10 cm
tBOX= 1.0 µm
-2
130
120
110
100
12
-6
5
4
3
1
-6
IB=0
-1
IB=0.5x10 Aµm
0
0
25
50
75
100
Collector-emitter voltage, VCE [ V ]
125
Fig. 6. Output characteristics of the conventional LBT for identical driftregion length and different SOI film thicknesses.
1.5
12
undesirable kinks for the SOI film thickness of 0.2 lm. This
can be explained as due to additional impact ionization current being generated by the high electric field at the P+Njunction side (marked by arrowhead at point ‘‘A’’ in
Fig. 5) and therefore, suggests that for very thin SOI film
thicknesses, the drift-region dose that can be used is limited
by the high electric field at the P+N junction side. Fig. 8
shows the effect of increasing the drift-region length on the
breakdown voltage for various SOI film thicknesses. It shows
that for the conventional LBTs, breakdown voltages cannot
be increased with the increase in drift length when both the
horizontal and vertical components of the surface electric
field contribute to the avalanche processes [39,40].
3.2. Collector-tub three-zone step doped collector LBT (CTSLBT)
Electric field along Si- field oxide interface
tSi=1.0 µm, BVCEO= 122 V
A
tSi=0.5 µm, BVCEO= 112 V
tSi=0.2 µm, BVCEO= 98 V
2.0
-1
Fig. 9 compares the output characteristics of the collector-tub three-zone step doped collector LBT (CT-SLBT)
-2
qD= 1.0x10 cm
tBOX= 1.0 µm
LD~ 10.0 µm
1.0
0.5
0.0
-2
0
4
6
8
10
2
Drift-region distance [ µm ]
CT Three-zone step doped LBT
Three-zone step doped LBT
Two-zone step doped LBT
Conventional LBT
8
-1
5
50
6
2
Lateral electric field [ x10 Vcm ]
20
30
40
Drift region distance [ µm ]
Fig. 8. Breakdown voltage (VCEO) versus drift-region length (LD) of the
conventional LBT compared at different SOI film thicknesses.
-1
IB increment @ 0.5x10 Aµm
Collector current, IC [ µAµm ]
-6
-1
IC [ x10 A µm ]
7
10
tSi=1.0µm, BVCEO= 122 V
tSi=0.5µm, BVCEO= 112 V
tSi=0.2µm, BVCEO= 98 V
-2
q=1.0x10 cm
tBOX=1.0 µm
LD~ 10.0 µm
8
12
Fig. 7. Lateral surface electric field profile of the conventional LBT along
the Si-field oxide interface for various SOI film thicknesses.
7
6
-6
-1
IB increment @ 0.5x10 Aµm
5
4
3
2
-6
-1
IB=0.5x10 Aµm
1
IB= 0
0
0
each having identical drift charge (q 1012 cm 2) and drift
length (LD 10 lm) but with different SOI film thicknesses
(tSi = 1.0–0.2 lm) and Fig. 7 shows their corresponding lateral surface electric field profile along the Si-field oxide interface. We notice that the output characteristics have
tSi= 0.2 µm
tBOX= 1.0 µm
LD~ 43.0 µm
25
50
75 100 125 150 175
Collector-emitter voltage, VCE [ V ]
Fig. 9. Output characteristics of the collector-tub three-zone step doped
lateral bipolar transistor (CT-SLBT) compared with those conventional
LBT, two-zone step doped LBT and three-zone step doped lateral bipolar
transistor (SLBT).
308
S.D. Roy, M.J. Kumar / Microelectronic Engineering 83 (2006) 303–311
Table 3
Simulation results on breakdown voltage
Parameter
SOI thickness
tSi (lm)
Conventional LBT
Two-zone
step-doped LBT
Three-zone
step-doped LBT
Collector-tub three-zone
step-doped LBT
Breakdown
voltage (V)
1.0
0.5
0.2
136
120
98
164
157
124
195
185
152
320
300
180
Surface Electric field along Si-field oxide interface
CT Three-zone step doped LBT, BVCEO= 180 V
Three-zone step doped LBT, BVCEO= 152 V
Two-zone step doped LBT, BVCEO= 124 V
Conventional LBT, BVCEO= 98 V
2.0
5
-1
Electric field [ x10 Vcm ]
with those of the conventional LBT, two-zone doped collector LBT and three-zone step doped collector LBT
(SLBT) for the SOI film thickness (tSi) of 0.2 lm. It clearly
shows that the breakdown voltage of the CT-SLBT is
about 80% more than that of the conventional LBT. The
1.5
tSi=0.2 m
tBOX=1.0 m
LD~43.0 m
1.0
0.5
0.0
0
5
a
10 15 20 25 30 35
Drift region distance [ m ]
40
45
Fig. 10(a). Lateral surface electric field along the Si-field oxide interface of
the collector-tub three-zone step doped lateral bipolar transistor (CTSLBT) compared with those of the conventional LBT, two-zone step
doped LBT and three-zone step doped lateral bipolar transistor (SLBT).
Surface Electric field along top Si-BOX interface
CT Three-zone step doped LBT, BVCEO= 180 V
Three-zone step doped LBT, BVCEO= 152 V
Two-zone step doped LBT, BVCEO= 124 V
Conventional LBT, BVCEO= 98 V
-1
Electric field [ x10 Vcm ]
5
4
5
tSi=0.2 µm
tBOX=1.0 µm
LD~43.0 µm
3
2
1
0
0
b
5
10 15 20 25 30 35
Drift region distance [ µm ]
40
45
Fig. 10(b). Lateral surface electric field along the silicon-BOX interface of
the collector-tub three-zone step doped lateral bipolar transistor (CTSLBT) compared with those of the conventional LBT, two-zone step
doped LBT and three-zone step doped lateral bipolar transistor (SLBT).
Fig. 11. Potential contour lines at breakdown of the: (a) collector-tub
three-zone step doped lateral bipolar transistor (CT-SLBT); (b) three-zone
step doped lateral bipolar transistor (SLBT) and (c) conventional LBT.
S.D. Roy, M.J. Kumar / Microelectronic Engineering 83 (2006) 303–311
4. Self-heating effect
Figs. 12(a) and 12(b) compare, respectively, the terminal
base current (IB) and collector current (IC) of the conventional LBT with those of the SLBT and CT-SLBT for
the film thickness (tSi) of 0.2 lm and base–emitter voltage
(VBE) of 0.82 V when both the drift-diffusion and heat flow
equations are included. The heat flow equation takes the
lattice heating into account caused by the current flowing
through high electric field region. We can clearly identify
the effect of impact ionization [41,42] and self-heating
[43–45] on both IB and IC from Figs. 12(a) and 12(b). As
expected, since VBE is fixed at 0.82 V, IB is large and IC is
low for all the structures at very low VCE. The electric field
produced by VCE generates electron-hole pairs at the P+Njunction interface and a quasi-neutral space-charge region
around it. The excess holes are forced to enter into the base
terminal, thereby decreasing IB. IC, on the other hand,
increases as the collector terminal collects the: (a) injected
electrons from the emitter that have survived recombination in the base and (b) avalanche generated electrons.
With the increase in VCE, the space-charge volume expands
and the peak electric field at the P+N-junction side spreads.
The repeated collisions over the increasing space-charge
volume stabilize the impact generated electron-hole pairs
and therefore, IB is maintained at a constant value (region
1). With further increase in VCE, the electric field shifts
CT Three-zone step doped LBT
Three-zone step doped LBT
Conventional LBT
with self-heating
3
-1
Base current, IB [ A m ]
0.28
VBE=0.82V
0.24
2
0.20
1
1
0.16
3
2
3
2
without self-heating
0.12
0.08
0.04
0
a
25
50
75
100
125
Collector-emitter voltage, V CE [ V ]
150
Fig. 12(a). Base current of the collector-tub three-zone step doped lateral
bipolar transistor (CT-SLBT) compared with those conventional LBT and
three-zone step doped lateral bipolar transistor (SLBT) with and without
lattice-heating effect.
5
with self-heating
-1
Collector current, IC [ µA µm ]
breakdown voltages for all the simulated structures at various SOI film thicknesses are given in Table 3. The
enhancement in the breakdown voltage of the CT-SLBT
can be explained from Fig. 10(a) and 10(b) that compares,
respectively, the lateral surface electric field along the silicon-field oxide and silicon-BOX interfaces at breakdown
with those of the conventional LBT, two-zone step-doped
collector LBT and SLBT. It can be seen that the CT-SLBT
produces RESURF effect in the collector drift region and
in addition, reduces the peak electric field at the P+N-junction side. Also, as seen in the potential contour diagram in
Fig. 11(a), the collector-tub reduces the peak electric field
at the NN+-junction side by distributing the applied potential into the drift and substrate regions. On the other hand,
conventional LBT and three-zone step-doped collector
LBT show crowding of potential lines at the collector
NN+-junction side (Fig. 11(b) and (c)). For the step doped
collector LBTs, additional electric field peaks appear at the
junction steps, which redistribute the lateral surface electric
field and hence show 50% enhancement in the breakdown
voltage when compared with those of the conventional
LBTs. It is also seen from Fig. 9 that the CT-SLBT structure does not show any kink in their output characteristics
at low VCE. This is because of the step profile that uses low
doping at the P+N junction side, thereby producing
reduced junction electric field. Kink-free output characteristics, however, can also be obtained in the conventional
uniformly doped collector LBTs using a lower drift-charge
but at the expense of reduced breakdown voltage.
309
4
3
without self-heating
2
VBE=0.82V
CT Three-zone step doped LBT
Three-zone step doped LBT
Coventional LBT
1
0
0
b
25
50
75
100
125
Collector-emitter voltage, VCE [ V ]
150
Fig. 12(b). Collector current of the collector-tub three-zone step doped
lateral bipolar transistor (CT-SLBT) compared with those of the
conventional LBT and three-zone step doped lateral bipolar transistor
(SLBT) with and without lattice-heating effect.
from the P+N-junction to that of the field plate-drift-region
junction. The build-up of the electric field at the field plate
end generates more electron-hole pairs and hence IB starts
to decrease. Since the quasi-neutral space charge region is
resistive, it contributes to the self-heating as can be seen
by the increased IB and IC in the self-heating curve in
‘‘region 1’’. When the electric field at the field plate-driftregion end reaches its peak value, the avalanche generated
electron-hole pairs maintain a constant value. IB becomes
constant again in the ‘‘region 2’’ and the space-charge volume continues to expand. The power dissipation becomes
significant to produce heating effect, which increases both
IB and IC. For the CT-SLBT structure, however, ‘‘region
S.D. Roy, M.J. Kumar / Microelectronic Engineering 83 (2006) 303–311
0.9
VCE=180 V
0.6
0.3
1.5
306
1.0
303
0.5
0.0
0
5
10 15 20 25 30 35
Drift region distance [ µm ]
40
5
45
Fig. 13. Lateral surface electric field along the Silicon-field oxide interface
of the collector-tub three-zone step doped lateral bipolar transistor (CTSLBT) compared with that of the conventional LBT for every 25 V
increment in VCE and at breakdown.
1’’ and ‘‘region 2’’ are the same and IB remains constant
over the entire region. This is because of: (a) reduced junction and lateral surface electric fields; (b) insignificant
impact ionization produced electron-hole pairs and (c) formation of relatively large depletion volume. When the electric field at the P+N-junctions reaches its peak value and
remains below the critical field for breakdown, IB and IC
cease to increase (region 3). This can be verified by the electric field profile in Fig. 13, which shows the build up of electric field in the drift region for every 25 V increment in VCE
and at breakdown. It can be seen that the value of VCE
(50 V) at which the electric field at the P+N-junction side
reaches its maximum is almost same as that of the VCE at
which IB and IC saturate. As VCE is increased more, the
increase in electric field takes place at the NN+-junction
side (Figs. 10 and 13) until high critical electric field for
breakdown is reached. This can be seen from Fig. 12(a),
when excessive electron and hole currents generated by
impact ionization increase IC and reduce IB drastically
for the conventional and step-doped structures. We also
observe from Fig. 12(b) that for a fixed VBE, self-heating
effect does not affect the I–V characteristics of the CTSLBT appreciably when compared with those of the conventional and step doped LBTs. This can be attributed
to: (i) the RESURF effect in the drift region (Figs. 10(a)
and 10(b)) and (ii) the collector-tub effect of the CT-SLBT,
which allows heat conduction into the substrate region as
explained in the next section.
Fig. 14 shows the lateral temperature profile of the conventional LBT at breakdown compared with those of the
CT-SLBT and SLBT at VCE = 150 V for the film thickness
(tSi) = 0.2 lm and VBE = 0.82 V. Clearly, for all the transistors, a positive temperature gradient exists from the emitter
side to the base due to the presence of the high electric field
at the P+N-junction side. It can be seen that high temperature peaks appear at the junction steps because of the
2.0
309
300
0.0
-2.0
312
2.5
-1
5
1.2
315
3.0
5
tSi= 0.2 µm
tBOX= 1.0 µm
LD~ 43.0 µm
VCE increment @ 25 V
VCE= 98 V
CT Three-zone step doped LBT
electric field
lattice temperature
Three-zone step doped LBT
lattice temperature
electric field
Conventional LBT
electric field
lattice temperature
tSi=0.2µm
tBOX=1.0µm
318
Lattice temperature [ K ]
1.5
Lateral surface electric field at the Si-field oxide interface
CT Three-zone step doped LBT
Conventional LBT
-1
Electric field [ x10 Vcm ]
1.8
Electric field [ x10 Vcm ]
310
10 15 20 25 30 35 40 45 50 55
Lateral distance [ µm ]
Fig. 14. Lateral temperature profile at breakdown of conventional LBT
compared with those of the collector-tub three-zone step doped lateral
bipolar transistor (CT-SLBT) and three-zone step doped lateral bipolar
transistor (SLBT) at VCE = 150 V.
localized lattice heating by the high electric field at those
regions. For all the structures, however, the highest temperature peak occurs at the high electric field regions at
the NN+-junction side. Also, unlike conventional thin-film
LBT on SOI and SLBT structures, where temperature profiles closely follow lateral surface electric field profile, CTSLBT shows almost uniform temperature profile because
of the lateral conduction of the generated heat and its subsequent dissipation into the substrate.
5. Conclusion
Two-dimensional numerical simulation studies of high
voltage thin-film (tSi = 0.2 lm) collector-tub three-zone
step doped collector lateral bipolar transistors (CTSLBTS) on silicon-on-insulator (SOI) are presented that
show about 80% enhancement in the breakdown voltage
over those of the conventional uniformly doped collector
LBTs on SOI. The enhancement in breakdown voltage is
explained as due to: (a) RESURF effect in the collector
drift region and (b) sharing of the applied potential by
the drift and substrate regions. It is also demonstrated that
the collector-tub facilitates lateral conduction of the dissipated heat and provides with a heat conduction path into
the substrate region. These improved characteristics in
the CT-SLBT structure, therefore, will alleviate the tradeoff between the high breakdown voltage and reduced selfheating effect in thin-film LBT on SOI and is expected to
find wide applications in the future generation high voltage
analog devices and power integrated circuits.
References
[1] N. Akiyama, N. Tamba, A. Wakui, Y. Kobayashi, IEEE Transactions on Electron Devices 39 (4) (1992) 948–951.
[2] Q.C. Ouyang, Jin Cai Tak Ning, P. Oldiges and J. B. Johnson, in:
Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, 2002, pp. 28–31.
S.D. Roy, M.J. Kumar / Microelectronic Engineering 83 (2006) 303–311
[3] M. Kumar, Y. Tan, J.K.O. Sin, IEEE Transactions on Electron
Devices 49 (2002) 200–202, Jan..
[4] B.J. Baliga, IEEE Transactions on Electron Devices 38 (7) (1991)
1568–1575.
[5] A. Nakagawa, N. Yasuhara, I. Omura, Y. Yamaguchie, T. Ogura,
T. Matsudai, International Electron Devices Meeting Technical
Digest (1992) 229–232.
[6] E. Arnold, Journal of Electrochemical Society 141 (7) (1994) 1983–
1988.
[7] G. Amaratunga, F. Udrea, and R. McMahon, in: Proceedings of the
1999 Bipolar/BiCMOS Circuits and Technologies Meeting, 1999, pp.
75–79.
[8] D.M. Garner, F. Udrea, H.T. Lim, G. Ensell, A.E. Popescu, K.
Sheng, W.I. Milne, Microelectronics Journal 32 (5–6) (2001) 517–526.
[9] G.J. Cao, M.M. De Souza, E.M.S. Narayanan, Solid-State Electronics 44 (10) (2000) 1869–1873.
[10] J. Roig, M. Vellvehi, D. Flores, J. Rebollo, J. Millan, S. Krishnan,
M.M. De Souza, E.M. Sankara Narayanan, Solid-State Electronics
46 (2) (2002) 255–261.
[11] S. Adriaensen, D. Flandre, Solid-State Electronics 46 (9) (2002) 1339–
1343.
[12] R. Basir, D. Chen, F. Hebert, J. DeSantis, A. Ramde, S. Hobrecht, H.
You, P. Maghsoudnia, P. Meng, R. Razouk, in: Proceedings of the
European Solid State Device Research Conference (ESSDERC),
1994, pp. 217–220.
[13] V.M.C. Chen and J.C.S. Woo, in: Symposium on VLSI Technology,
Digest of Technical Papers, 1995, pp. 133–134.
[14] S. Kawanaka, T. Fuse, K, Inoh, T. Shino, H. Nii, T. Yamada, M.
Yoshimi and S. Watanabe, in: Proceedings of the IEEE International
SOI Conference, 1998, pp. 29–30.
[15] T. Yamada, H. Nii, K. Inoh, T. Shino, S. Kawanaka, Y. Minami, T.
Fuse, Y. Yoshimi, Y. Katsumata, S. Watanabe, J. Matsunaga and H.
Ishiuchi, in: Proceedings of the Bipolar/BiCMOS Circuits and
Technology Meeting, 1999, pp. 129–132.
[16] S. Adriaensen, V. Dessard, and D. Flandre, in: Proceedings of the
IEEE International SOI Conference, 1999, pp. 20–21.
[17] H. Nii, T. Yamada, K. Inoh, T. Shino, S. Kawanaka, M. Yoshimi,
Y. Katsumata, IEEE Transactions on Electron Devices 47 (7)
(2000) 1536–1541.
[18] T. Suligoj, M. Koricic and P. Biljanovic, in: 9th International
Conference on Electronics, Circuits and Systems, vol. 3, 2002, pp.
1191–1194.
[19] J.A. Apples and H.M.J. Vaes, in: International Electron Devices
Meeting Technical Digest, 1979, pp. 238–241.
[20] Y.S. Huang and B.J. Baliga, in: Proceedings of the 3rd International
Symposium on Power Semiconductor Devices and ICs, 1991, pp. 27–
30.
[21] S. Merchant, E. Arnold, H. Baumgart, S. Mukherjee, H. Pein, R.
Pinker, in: Proceedings of the 3rd International Symposium on Power
Semiconductor Devices and ICs, 1991, pp. 31–35.
[22] T.M.L. Lai, J.K.O. Sin, M. Wong, V.M.C. Poon and P.K. Ko, in:
Proceedings of the 7th International Symposium on Power Semiconductor Devices and ICs, 1995, pp. 315–320.
311
[23] S. Zhang, J.K.O. Sin, T.M.L. Lai, P.K. Ko, IEEE Transactions on
Electron Devices 46 (5) (1999) 1036–1041.
[24] J. He, X. Xi, M. Chan, C. Hu, Y. Li, Z. Xing, R. Huang,
Semiconductor Science and Technology 17 (2002) 721–728.
[25] L. Vestling, J. Olsson, K.H. Eklund, Solid-State Electronics 46 (2002)
1177–1184.
[26] R. Sunkavalli, A. Tamba and B.J. Baliga, in: Proceedings of the IEEE
International SOI Conference, 1995, pp. 139–140.
[27] J. Luo, G. Cao, S.N.E. Madathil, M.M. De Souza, Solid-State
Electronics 47 (11) (2003) 1937–1941.
[28] J. Roig, D. Flores, S. Hidalgo, M. Vellvehi, J. Rebollo, J. Millán,
Solid-State Electronics 46 (12) (2002) 2123–2133.
[29] Q. Lu, P. Ratnam, C.A.T. Salama, Solid-State Electronics 35 (12)
(1992) 1745–1750.
[30] M.J. Kumar and S.D. Roy, in: Proceedings of the 15th International
Conference on Microelectronics, Cairo, Egypt, December 9–11, 2003,
pp. 336–339.
[31] S.D. Roy, M.J. Kumar, Microelectronics International 22 (1) (2005)
3–9.
[32] Athena UserÕs Manual, Silvaco International, Santa Clara, CA, 2000.
[33] U. Magnusson, B. Edholm, F. Masszi, Microelectronic Engineering
15 (1–4) (1991) 341–344.
[34] B. Edholm, J. Olsson, A. Sodebarg, IEEE Transactions on Electron
Devices 40 (12) (1993) 2359–2360.
[35] S.A. Parke, C. Hu, IEEE Electron Device Letters 14 (1) (1993) 33–
35.
[36] M. Chan, S.K.H. Fung, C. Hu and P.K. Ko, in: Proceedings of the
IEEE International SOI Conference, 1995, pp. 90–91.
[37] Atlas UserÕs Manual, Silvaco International, Santa Clara, CA,
2000.
[38] D.J. Roulston, N.D. Arora, S.G. Chamberlain, IEEE Transactions
on Electron Devices 29 (1982) 284–291.
[39] S. Merchant, E. Arnold, H. Baumgart, R. Egloff, T. Letavic, S.
Mukherjee and H. Pein, in: Proceedings of the 5th International
Symposium on Power Semiconductor Devices and ICs, 1993, pp.
124–128.
[40] S.K. Chung, S.Y. Han, J.C. Shin, Y.L. Choi, IEEE Electron Device
Letters 17 (1) (1996) 22–24.
[41] P.R. Ganci, J.J. Hajjar, T. Clark, P. Humphries, J. Lapham, D. Buss,
in: International Electron Devices Meeting Technical Digest, vol. 40,
No. 3, 1992, pp. 417–420.
[42] H. Neubrand, R. Constapel. R. Boot, M. Füllmann, A. Boose, in:
International Electron Devices Meeting Technical Digest, 1994, pp.
123–127.
[43] J.S. Yuan, IEE Proceedings of the Circuits, Devices and Systems 141
(4) (1994) 299–306.
[44] L. Vendrame, E. Zabotto, A. Dal Fabbro, A. Zanini, G. Verzellesi,
E. Zanoni, A. Chantre, P. Pavan, IEEE Transactions on Electron
Devices 42 (9) (1995) 1636–1646.
[45] L.K. Nanver, N. Nenadovic, V. dÕAlessandro, H. Schellevis, H.W.
van Zeijl, R. Dekker, D.B. de Mooij, V. Zieren, J.W.
Slotboom, IEEE Transactions on Electron Devices 51 (1) (2004)
42–50.