Jitter in Phase-Locked Loops
John McNeill
Worcester Polytechnic Institute
McNEILL: JITTER IN PHASE-LOCKED LOOPS
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Course Overview
Measurement Techniques ↔ Design Tools
• Basic Theory
• Applications
• Measurement Techniques
• Test Issues
• Design
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Basic Theory
•
•
•
•
•
Original application: PLL clock recovery in SONET
Example of jitter (time domain)
Basic concepts: phase, jitter, modulation, phase noise
Time domain, frequency domain characterization
PLL refresher:
– Loop dynamics, jitter source, noise model
• Characterization options:
– Time/frequency domain figures of merit
– Open/closed loop
• Measurement techniques / relationships
• Benefit of measurement relationships
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Applications
• Time Domain
– SONET / serial data communication
– High Speed Clock Multiplication
– Clock Distribution ("Zero Delay buffer")
• Frequency Domain
– Wireless Communication
– Oversampling ADC
– Digital Audio
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Practical Measurement Techniques
• Time Domain
– Tektronix CSA803
– Other techniques (Time Interval Analyzer)
• Frequency Domain
– Spectrum Analyzer
– Other Techniques (HP 3048 Phase Noise Analyzer)
• Practical Measurement Techniques
– 50Ω interface
– Signal integrity
– Common pitfalls
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Test Issues
•
•
•
•
Observing nodes
Testing multiple PLLs
Self-test Issues
Test choice issues
– Time vs. frequency
– Open loop vs. closed loop
• "Shortcuts" using measurement relationships
– Time Domain
– Frequency Domain
• Diagnostic tests
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Design Techniques
• VCO Design using K figure-of-merit (time domain)
• Noise models for CMOS ring VCOs
• System level design issues
– Loop bandwidth
– Single-ended vs. differential
– Delay Lock Loop (DLL)
• Other VCO design techniques
– LC oscillator
– Interference reduction techniques
– Transient noise source simulation
– VCO design in Frequency domain
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Basic Theory Overview
Measurement Techniques ↔ Design Tools
•
•
•
•
•
SONET Application
Jitter / Phase Noise Fundamentals
PLL Fundamentals
PLL Noise Model
Different Characterization
Techniques
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Application and Requirements
• Serial data transmission over fiber optic link; requires:
– Low bit error rate (BER)
– Low cost, low power, simple interface
– Recover bit clock from serial data
Receive end
Clock recovery
Transmit end
TDATA
TCLK
Vin
fiber
link
RCLK
RDATA
Vin
RCLK
RDATA
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Clock Recovery with PLL
D
Vin
Vin
PHASE
DETECTOR
RCLK
"LATE"
RCLK
"EARLY"
RDATA
RETIMED
DATA
LOOP
FILTER
RCLK
Q
VOLTAGE
CONTROLLED
OSCILLATOR
RECOVERED CLOCK
RCLK
• Advantage
– Low cost: entire system can be integrated
– Requires integrated, low jitter VCO
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Dynamic Phase Error (Jitter)
• Cycle-to-cycle variations in recovered clock
– BER increases
– Degrades performance in repeater applications
•
TCLK
Vin
RCLK
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Jitter Referenced to Transmit Clock
TCLK
σX
RCLK
TCLK
TRIG
RCLK
TDATA
VERT
RDATA
DATA
SOURCE
CLOCK RECOVERY PLL
(D.U.T)
McNEILL: JITTER IN PHASE-LOCKED LOOPS
COMMUNICATIONS
SIGNAL ANALYZER
12
Measurement of Jitter Referenced to TCLK
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What is Phase?
• Phase is the argument of a trigonometric function:
Frequency
Initial phase
V(t) = V sin [ ω t + φ
]
Phase Φ(t)
• Frequency is the time derivative of phase:
ω =
d
Φ(t)
dt
• Phase is the integral of frequency:
Φ(t) =
McNEILL: JITTER IN PHASE-LOCKED LOOPS
t
∫ ω(t) dt + φ
14
Time Domain Phase Characterization: Jitter
Observed Voltage
V(t)
V(t)
t
Phase
Φ(t)
Φ(t)
4π
4π
3π
3π
2π
2π
π
π
0
Frequency
t
t
ω(t)
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0
t
ω(t)
t
t
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Frequency Domain Characterization : Phase Noise
IDEAL SINE WAVE
AMPLITUDE NOISE
PHASE NOISE
TIME
DOMAIN
FREQUENCY
DOMAIN
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Phase Noise: Modulation in Frequency Domain
Voltage / Time Error
2-Sided Magnitude Spectrum
Sv(f)
V(t)
f
t
εT
-fc
εV
φ(t)
0
fc
Sφ(f)
t
Phase Error vs. Time
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f
Phase Error
Magnitude Spectrum
17
Phase Noise: AM/PM Duality
SINE WAVE (IN
QUADRATURE WITH
CARRIER), AMPLITUDE
MODULATED BY PHASE
NOISE PROCESS
V(t)
NOISE MODULATION
ENVELOPE
t
V(t)
t
ADDED WITH
CARRIER
PRODUCES PHASE
MODULATED WAVEFORM
(UNMODULATED CARRIER
SHOWN FOR REFERENCE)
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V(t)
t
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Phase Noise: AM/PM Duality
SINE WAVE (IN PHASE
WITH CARRIER),
AMPLITUDE MODULATED
BY NOISE PROCESS
V(t)
NOISE MODULATION
ENVELOPE
t
V(t)
t
ADDED WITH
CARRIER
PRODUCES AMPLITUDE
MODULATED WAVEFORM
(UNMODULATED CARRIER
SHOWN FOR REFERENCE)
V(t)
t
Caution: AM, PM Have Same Magnitude Spectrum!
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Phase Noise: Sine Wave to Square Wave
Vin(t)
Vin(t)
t
t
Vin
Vout
Svin(f)
Svin(f)
f
0
fc
f
0
fc
3f c
5f c
Square wave from ideal sine wave: harmonics
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Phase Noise: Sine Wave to Square Wave
Vin(t)
Vin(t)
t
t
Vin
Vout
S vin(f)
S vin(f)
f
0
fc
f
0
fc
3f c
5f c
Shape of phase noise near fundamental unchanged
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Frequency Domain Measurement
• Equipment: Spectrum Analyzer
• "Direct Spectrum" Procedure
– Feed clock into RF input
– Observe spectrum near fundamental frequency
RF IN
SPECTRUM
ANALYZER
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VCO Spectrum Measurements
• Phase noise spectrum “close in” to carrier
• 155.52 MHz carrier 1MHz span
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Single-Sided (Phase Noise) Measurements
• Phase noise P.S.D. symmetric about carrier
• Just measure one side of spectrum
• Plot on log scale to show frequency structure
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PLL Noise Model / Loop Dynamics Refresher
• Simplified noise model
– Dominated by white noise at VCO input
(Or equivalent)
• Open loop phase noise
• PLL response to VCO phase noise
• Phase noise at PLL output
– Shaped by loop dynamics
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Simplified Noise Model
• Ideal VCO with white noise at input
V out(t)
Vctl
Vout
t
VCO
Φ(t)
"RANDOM
WALK"
IDEAL PHASE
(NOISELESS)
t
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Open Loop VCO Phase Noise
log SVctl(f)
Vctl INPUT
WHITE NOISE p.s.d.
log f
log SΦ (f)
OPEN LOOP PHASE NOISE p.s.d.
(INTEGRATED WHITE NOISE)
∝ 1/f 2
log f
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PLL Response to Phase Noise
PHASE
DETECTOR
LOOP
FILTER
Kd ( θi - θ o)
F(s)
θn
VCO
Ko
s
θi
θo
log H(f)
θi
θn
log f
θo
θn
Hs(f)
PHASE INPUT
H n(f) PHASE NOISE
TRANSFER FUNCTION
fL
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Phase Noise at PLL Output
log H(f)
θn
OPEN LOOP PHASE NOISE p.s.d.
(INTEGRATED WHITE NOISE)
CLOSED LOOP p.s.d.
(LOWPASS DUE TO
SHAPING BY LOOP)
LOOP PHASE NOISE
TRANSFER FUNCTION
θo
log f
θo
θn
McNEILL: JITTER IN PHASE-LOCKED LOOPS
fL
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Measurement Strategy Overview
• Relate different measurement techniques:
– Open loop / closed loop
– Time domain / frequency domain
– Self referenced / transmit clock referenced
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Jitter Referenced to Transmit Clock
TCLK
σX
RCLK
TCLK
TRIG
RCLK
TDATA
VERT
RDATA
DATA
SOURCE
CLOCK RECOVERY PLL
(D.U.T)
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COMMUNICATIONS
SIGNAL ANALYZER
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Measurement of Jitter Referenced to TCLK
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TCLK-Referenced Time Domain Measurement
• Advantages
– “Compresses” noise performance into one number
– CSA time base accuracy not critical
• Disadvantages
– Requires stable source for PLL lock
– Requires access to transmit clock
– “Compresses” noise performance into one number
• Little or no information on noise process
• Shape of histogram (maybe)
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Time Domain: Two sample standard deviation
• Equipment: Communications Signal Analyzer (CSA)
• Procedure
- "Self referenced:" clock is both trigger and input
- Observe distribution of delay times to threshold
crossings of clock
- Plot σ as a function of delay ΔT
D.U.T.
CLK
VERT
IN
CLK
TRIG
CSA803A
σ ΔT
To
ΔT
TRIGGER
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Average delay = NTo
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Open Loop VCO Time Domain Measurement
PHASE
DETECTOR
LOOP
FILTER
θi
VCO
θo
Open loop:
• Break PLL feedback loop by shorting input to VCO
• Tie to signal ground (constant voltage)
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Open Loop VCO Time Domain Measurement
Open loop:
σ proportional to square root of ΔT
ΔT
Model:
Period errors independent
random variables
•Variance (σ2) of sum is
sum of variances
•Standard deviation
increases as square root
100
rms jitter [ps]
σΔT(OL) (ΔT) ≈ κ
Measured
jitter
Fit to
κ = 6.14E-08 √s
10
100
1000
10000
Delay ΔT [ns]
κ
Time domain figure-of-merit
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PLL VCO Time Domain Measurement: Closed Loop
• Open loop:
σ proportional to square root of ΔT
σΔT(OL) (ΔT) ≈ κ
• Closed loop:
Action of loop limits σ for delays
longer than loop bandwidth τL
ΔT
LOOP BANDWIDTH
TIME CONSTANT
τL=1/2πfL
rms jitter [ps]
Measured
jitter
Fit to
κ = 6.14E-08 √s
10
100
1000
10000
Delay ΔT [ns]
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rms jitter [ps]
100
100
κ ΔT
2σ x
Measured
jitter
Predicted
10
100
1000
10000
Delay ΔT [ns]
37
Self-Referenced Time Domain Measurement
• Advantages
– Structure of σΔT vs. ΔT plot gives information on
noise process
– Does not require access to transmit clock
– Applicable to free running VCO (PLL open loop)
• Disadvantages
–
σΔT fails to converge in presence of frequency drift
(“wander”)
– Limited by accuracy of CSA time base at long ΔT
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Frequency Domain Measurement
• Equipment: Spectrum Analyzer
• "Direct Spectrum" Procedure
- Feed clock into RF input
- Observe spectrum near fundamental frequency
RF IN
SPECTRUM
ANALYZER
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PLL VCO Spectrum Measurements
Open loop:
spectrum proportional to 1/f2
(f = offset frequency from carrier)
N
SφOL ( f ) ≈ 21
f
Model: Dominated by
white noise at VCO input
• Carrier phase modulated
by noise at VCO input
• Phase is integral of
frequency
N1
Frequency domain
figure-of-merit
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PLL VCO Spectrum Measurements
Open loop:
Integration of white noise at VCO
input gives 1/f 2 spectrum
N1
SφOL ( f ) ≈ 2
Closed loop:
1/f 2 spectrum shaped by loop filter
Spectrum rolls off for f < f L
f
fL
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Frequency Domain Measurement
• Advantages
- Simple and quick
- Most work on phase noise has been done in
frequency domain
- Easy to see effect of loop filter on jitter
• Disadvantages
- This is not how the serial data communication
customer decides whether the part is working!
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Relating Different Jitter Measurements
• Reason
– Design in the domain that gives the most insight
– Always able to relate to end user's specification
• Analysis Domains
– Time
– Frequency
• PLL Operating Conditions
– Closed loop
– Open loop (stand alone)
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Summary: (i) Frequency domain, VCO open loop
RCLK
NO
DATA SOURCE
REQUIRED
RF IN
RDATA
CLOCK RECOVERY PLL
(D.U.T)
SPECTRUM
ANALYZER
SΦOL(f)
N1
f2
f
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Summary: ( ii) Frequency domain, VCO closed loop
TCLK
RCLK
TDATA
RF IN
RDATA
DATA
SOURCE
SPECTRUM
ANALYZER
CLOCK RECOVERY PLL
(D.U.T)
SΦCL(f)
fL
f
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Summary: ( iii) Time domain, closed loop, transmit clock ref
TCLK
TRIG
RCLK
VERT
TDATA
RDATA
DATA
SOURCE
CLOCK RECOVERY PLL
(D.U.T)
COMMUNICATIONS
SIGNAL ANALYZER
p(t)
σx
t
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Summary: ( iv) Time domain, closed loop, self referenced
TCLK
TRIG
RCLK
VERT
TDATA
RDATA
DATA
SOURCE
CLOCK RECOVERY PLL
(D.U.T)
COMMUNICATIONS
SIGNAL ANALYZER
σΔT(CL)(ΔT)
ΔT
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Summary: ( v) Time domain, open loop, self referenced
TRIG
RCLK
NO
DATA SOURCE
REQUIRED
VERT
RDATA
CLOCK RECOVERY PLL
(D.U.T)
COMMUNICATIONS
SIGNAL ANALYZER
σΔT(OL)(ΔT)
κ ΔT
ΔT
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Measurement technique summary
TIME DOMAIN
TRANSMIT CLOCK
SELF REFERENCED
REFERENCED
PLL CLOSED LOOP
FREQUENCY
DOMAIN
SΦCL(f)
σx
fL
f
ΔT
t
σΔT(OL)(ΔT)
SΦOL(f)
OPEN LOOP
σΔT(CL)(ΔT)
p(t)
N1
f2
f
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ΔT
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Mathematical relationships preview
TIME DOMAIN
TRANSMIT CLOCK
SELF REFERENCED
REFERENCED
FREQUENCY
DOMAIN
κ2 (f o/fL)2
PLL CLOSED
LOOP
N 1 /fL 2
1 + (f/f L )2
1 + (f/f L)2
S φ CL (f)
o
N1
4π fL
σx = κ
1
4π fL
2 σx 1 - exp(-2 π fLΔT)
σΔT(CL)(ΔT)
p(t)
σx
2 σx
fL
f
OPEN LOOP
1
σx = f
S φOL (f) =
N1
f2
N1 =
κ 2 f o2
ΔT
t
κ=
N1
fo
σ ΔT(OL) = κ
ΔT
σ ΔT(OL)(ΔT)
S φO (f)
L
f
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ΔT
50
Benefits of time/frequency technique
• Can relate either open loop figure of merit (κ or N1) to
closed loop jitter performance.
• Allows design to take place in most convenient domain
• Simplifies design and simualtion: need only consider
open loop VCO
• Allows stand-alone test of VCO contribution to jitter.
• Applies to any oscillator that fits 1/f^2 model
BUT...
•
κ and N1 describe jitter performance of the entire
oscillator: How to relate to design decisions on the
level of the ring delay stage?
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Applications Overview
• Time Domain
– SONET / serial data communication
– Hgih speed clock synthesis (multiply-by-N)
– Clock distribution (“zero delay buffer”)
• Frequency Domain
– Wireless communication
– Oversampling ADC / digital audio
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SONET Application
• Serial data transmission over fiber optic link
• Bit rates:
– OC-3
155.52MHz
– OC-12 622.08MHz
– OC-48
2.488GHz
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Clock Recovery with PLL
FREQUENCY
DETECTOR
D Q
RETIMED
DATA
Vin
PHASE
DETECTOR
RDATA
UP
UP
VCO
CHARGE
PUMP
LOOP
FILTER
VOLTAGE
CONTROLLED
OSCILLATOR
RECOVERED CLOCK
DN
DN
RCLK
LOOP FILTER
• Frequency detector
aids initial acquistion
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• Assume charge pump
PD, typical loop filter
54
SONET Standard Documents
• Available from Telcordia (formerly Bellcore)
• GR-253-CORE
– Synchronous Optical Network (SONET)
Transport Systems: Common Generic Criteria
($1,500)
• GR-1244
– Clocks for the Synchronized Network: Common
Generic Criteria ($85)
• TR-NWT-000917
– SONET Regenerator (SONET RGTR) Equipment
Generic Criteria ($110)
[Source for information in this section]
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SONET Specifications
•
•
•
•
•
•
•
•
Jitter Generation
Jitter Transfer
Jitter Peaking
Jitter Tolerance
Wander
Time Interval Error
Time Deviation / Time Variance
Holdover
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Jitter / Wander
• “Two sides of same coin”
• Jitter:
– Phase error > 10Hz modulation
– Defined in terms frequency content of modulation
– Test in time or frequency domain
• Wander:
– Phase error < 10Hz modulation
– Defined over observation time > 0.1sec
– Test with Time Interval Analyzer
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Jitter Generation
•
•
•
•
SONET Specification:
rms output jitter ≤ 0.01 unit interval (UI)
Assumes jitter-free serial data input
Test in time domain (TCLK referenced)
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Jitter Tolerance
• SONET
Specification:
• Tolerate p-p jitter
with equivalent
1dB BER penalty
• Test with BER tester
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Jitter Transfer / Peaking
0 dB
• SONET
TYPICAL
Specification:
TRANSFER
FUNCTION
• Transfer function
from input phase
to output phase
• Test with amplitude
from jitter tolerance
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SONET Regenerator
• Jitter transfer critical in regenerator
• Any peaking will accumulate
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Maximum Time Interval Error
• SONET Definition
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Time Deviation / Time Variance
• Standard deviation of Time Interval Error
– observed over a given time interval
• Time domain test
– Two sample standard deviation
• Test with
– CSA (short interval)
– Time interval analyzer (long interval)
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Holdover
• Maintain stable frequency with no
transitions at input
• Factors:
– Charge pump leakage
– VCO stability
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Recovery from Holdover
t0 enter holdover
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t1 reference available
2t1 reference valid
65
SONET Application Summary
• Jitter Generation: 0.01 UI rms
• Jitter Transfer:
– Determines PLL loop bandwidth
– Jitter peaking critical in regenerator application
• Holdover
– Maintain frequency in absence of input data
– Some wander allowed
– Limit phase transient in recovery from holdover
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High Speed Clock Synthesis / Multiplication
• High speed digital clock distribution
– Distribute low frequency clock
– Use on-chip PLL to multiply to higher frequency
– Jitter reduces timing margin
PHASE
DETECTOR
LOOP
FILTER
VCO
θi
θo
÷N
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“Zero delay buffer”
• Phase lock output clock to input
• Use on-chip PLL to generate clock
BUFFER
θi
PHASE
DETECTOR
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LOOP
FILTER
VCO
68
Typical Specifications
• Static phase
– Measure in time domain; input clock reference
• Cycle-to-cycle jitter
– Measure in time domain; self referenced
–
κ model applied to one cycle of clock
• Spread spectrum
– Intentionally add “jitter” to improve EMC
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Spread spectrum
• Intentionally add “jitter” to improve EMC
• Modulate inside loop (usually VCO input)
• Reduces spectral peak: improves EMC
LOOP FILTER
PHASE
DETECTOR
BUFFER
VCO
V tri
V tri
t
BEFORE
EMC IMP ROVEMEN T
AF TER
f
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Oversampling ADC/DAC / Digital Audio
• Digital audio / oversampled data conversion
– PLL used to generate multiple of fundamental
sampling rate required for Σ-Δ ADC/DAC
– Phase noise causes audible distortion
– “Smearing” in convolution by non-impulse
• Test in frequency domain
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Effect of Phase Noise
Ideal sampling clock (impulse):
Svin(f)
Sfs(f)
f
Svout (f)
*
0
f
0
=
fS
f
0
Real sampling clock (with phase noise):
Svin(f)
Sfs(f)
f
Svout (f)
*
0
f
0
fS
=
f
0
"Smearing" of frequency content in sampling (convolution)
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Wireless Communication
• Wireless communication
– PLL used in demodulation of RF signal
– Requires low phase noise LO
• Bluetooth
– Wireless personal device connectivity
• DECT
– Digital cordless telephone
• Test in frequency domain
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Typical Specifications
• DECT: 1.6GHz to 2.0 GHz
• Phase noise:
-99dBc/Hz @ 1.7MHz offset
-117 dBc/Hz @ 3.2 MHz offset
-131 dBc/Hz @ 4.7MHz offset
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Example of DECT Phase Noise Specification
CARRIER
P OWER
+6 d B m
P H ASE NOISE a t 1.7MHz OFFSET
(NORMALIZE D TO CARRIE R P OWE R)
-93dBm /H z - (+6dBm ) = -99d B c /Hz
("dBc" = "dB RE LATIVE TO CARRIE R")
1.7MHz
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f
P HAS E N OIS E
P OWER D EN S ITY
-93 d B m /Hz
75
Overview: Practical Measurement Techniques
• Time Domain
– Tektronix CSA803 / 11801
– Other techniques (Time Interval Analyzer)
• Frequency Domain
– Spectrum Analyzer
– Other techniques (Phase Noise Analyzer)
• Circuit-level issues
– 50Ω interface
– Signal Integrity
– Common Pitfalls
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Time domain
• Tektronix CSA803/11801
• Equivalent time sampling scope
• 1psec/div time domain resolution
TRIG
INCREASING
DELAYS
TRIG
TRIG
LEVEL
VERT
DELAY
VERT
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A/D
DISPLAY
77
Equipment Requirements
• Minimum requirements to achieve desired
accuracy
• "Jitter floor"
– Uncertainty of CSA time base depends on delay
– Assume independent: adds in rms fashion
σ TOTAL = σ CSA2 + σ SIGNAL 2
1
– Error ≈ 10% when σ CSA = σ SIGNAL
2
McNEILL: JITTER IN PHASE-LOCKED LOOPS
78
CSA “Jitter Floor”
100
10
rms
Jitter
(psec)
Measured Tektronix 11801C
"Jitter Floor"
1
10
McNEILL: JITTER IN PHASE-LOCKED LOOPS
100
1000
10000
79
Example: Show jitter floor next to all data plotted
MEASURED DATA
κ ΔT
CSA803 “JITTER FLOOR”
• Software controls CSA over HPIB
• Also show κ√ΔT plot
McNEILL: JITTER IN PHASE-LOCKED LOOPS
80
Triggering
• Separate trigger input
– Can’t trigger off “scope display”
Solutions:
Differential
output buffer
Power
splitter
TRIG
TRIG
VERT
VERT
ECL
(e.g. 10H124)
McNEILL: JITTER IN PHASE-LOCKED LOOPS
(6 dB LOSS)
81
Triggering: Duty cycle distortion / jitter
– More common with single-ended systems
– Usually not important for timing (use good edge)
– Very important for phase noise!
(spectrum analyzer “sees” both edges)
– Choose correct (same) edge for all measurements
– Increase in measured jitter if “wrong” edges used
"GOOD
EDGE"
"BAD
EDGE"
CLK
CLK
McNEILL: JITTER IN PHASE-LOCKED LOOPS
82
Problems: Minimum Delay
• Minimum delay from trigger to first sample:
~ 30nsec
• Use cable delay line
• Watch out for “mechanical jitter”
(1psec = 0.3mm change in electrical length)
TRIG
(TO CSA)
VERT
McNEILL: JITTER IN PHASE-LOCKED LOOPS
83
Other time domain methods
TIA (Time Interval Analyzer)
• Advantage
– More accurate at long delays
• Disadvantage
– Not a sampling scope:
• no picture of waveform
• no indication of reflections / signal integrity
problems
McNEILL: JITTER IN PHASE-LOCKED LOOPS
84
Frequency domain
• Spectrum Analyzer
– General purpose frequency domain instrument
– Example: HP8560E used for following plots
• Phase Noise Analyzer
– Optimized for phase noise measurements
– HP3048
• Test Options
– Phase noise plot
– Phase noise at a specified offset frequency
– (“Spot Frequency”)
McNEILL: JITTER IN PHASE-LOCKED LOOPS
85
Spectrum Analyzer (HP8560E)
Source: Hewlett-Packard Application Note AN-150
McNEILL: JITTER IN PHASE-LOCKED LOOPS
86
Phase Noise Measurement
• HP85671A Phase noise “plug-in”
– Measures noise power density at offset
frequencies near carrier peak
• Equipment requirements
– Spectrum analyzer phase noise floor depends
on frequency
– Test with HP8648D low-phase-noise signal
source
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87
HP8560E Phase Noise Floor: 155 MHz
McNEILL: JITTER IN PHASE-LOCKED LOOPS
88
HP8560E Phase Noise Floor: 622 MHz
McNEILL: JITTER IN PHASE-LOCKED LOOPS
89
HP8560E Phase Noise Floor: 2488 MHz
McNEILL: JITTER IN PHASE-LOCKED LOOPS
90
Noise measurement cautions
• Common pitfalls to watch out for
– BW filter shape
– Amplitude noise / phase noise ambiguity
– Noise units problem (older spectrum analyzers)
McNEILL: JITTER IN PHASE-LOCKED LOOPS
91
Incorrect Resolution Bandwidth
• Phase noise peak narrower than RBW filter
• Plot shows shape of RBW bandpass filter (not phase noise!)
McNEILL: JITTER IN PHASE-LOCKED LOOPS
92
Correct Resolution Bandwidth
INCORRECT
• RBW filter too wide
McNEILL: JITTER IN PHASE-LOCKED LOOPS
CORRECT
• RBW filter narrower than
phase noise
• Note loooong sweep time!
93
Amplitude noise / phase noise ambiguity
• Spectrum analyzer responds to magnitude
• AM, PM spectra indistinguishable
• Solution: use limiter:
ECL GATE
(OR COMPARATOR
IF Vin SMALL)
McNEILL: JITTER IN PHASE-LOCKED LOOPS
94
Noise units problem (some spectrum analyzers)
• Spectrum analyzer uses envelope detector to
determine magnitude of frequency component
• Sinusoid vs. Gaussian noise:
Detector response different!
• Units:
– Carrier: power (dBm) in (ideal) impulse
– Noise: power density (dBm/Hz) per unit bandwidth
– Phase noise: dBc/Hz (normalize to carrier power)
• May need “fudge factor” to account for envelope
detector on some spectrum analyzers
– HP Application Note AN-150
McNEILL: JITTER IN PHASE-LOCKED LOOPS
95
Other time domain techniques: Phase Noise Analyzer
• HP E5500 series ~ $40,000+ (replaces discontinued HP3048)
• Generally better than required for integrated VCOs
McNEILL: JITTER IN PHASE-LOCKED LOOPS
96
Interfacing to 50Ω input
• ECL/PECL coupling network:
vCC = +5V
(CERAMIC NPO)
1000pF
100Ω
ECL/PECL
INPUT
1000pF
100Ω
ECL
(e.g. 10H116)
100Ω
SMA
or
SMB
100Ω
(ALL R, C SURFACE MOUNT)
McNEILL: JITTER IN PHASE-LOCKED LOOPS
97
CMOS-ECL: Options for interfacing to 50Ω input
1) Use CMOS/TTL-to-ECL/PECL translator with
50Ω coupling network
2) Step-down RF transformer:
SELECT BASED ON
MINIMUM FREQUENCY
SELECT BASED ON
ROUT OF CMOS DRIVER
N:1
CMOS OUTPUT
DRIVER
RTERM
CCOUPLE
Current drive
requirement
easier by N2
SMA
or
SMB
RF
TRANSFORMER
Caution: transformer bandwidth
McNEILL: JITTER IN PHASE-LOCKED LOOPS
98
Signal Integrity
• For evaluation boards, usual suspects:
– Ground plane
– Transmission line approach
– Moderately well controlled impedance
• Don’t need super-expensive PCB (622MHz)
– SMA or SMB (or other RF connector)
– SM components
– Identical differential paths
McNEILL: JITTER IN PHASE-LOCKED LOOPS
99
Test Issues
•
•
•
•
Observing nodes
Testing multiple PLLs
Self-test issues
Choice of test/measurement
– Time vs. frequency
– Open loop vs. closed loop
• “Shortcuts” using measurement
relationships
– Time domain
– Frequency domain
• Evaluation (pass/fail) vs diagnostic
McNEILL: JITTER IN PHASE-LOCKED LOOPS
100
Observing nodes
• Effects of bringing out PLL signal(s) to
external pin(s)
– VCO control voltage
– VCO output
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101
VCO control input
• Advantage
– Measure VCO V-f characteristic
– Close loop, lock to different f, measure VCTL
– Could force VCTL open loop, measure f (harder)
• Indirect method
– Off-chip loop filter
capacitor
– (assumes negligible
IR drop on Rz)
• Disadvantage
CHARGE
PUMP
LOOP FILTER
VCO
VCTL
Rz
ON-CHIP
OFF-CHIP
– Noise coupling path to
(sensitive) VCTL node
McNEILL: JITTER IN PHASE-LOCKED LOOPS
102
VCO output
• At-frequency testing
• When needed, when is it not required
• Problem: driving GHz to off-chip pins
McNEILL: JITTER IN PHASE-LOCKED LOOPS
103
Divide Down VCO Output
• Possibility: bring out divided-by-M version
– Register to avoid pattern jitter
• Time domain:
– Same jitter κ
• Frequency domain:
ON-CHIP
CLK
– Phase noise power
divided by factor M2
• Don't divide by too
much:
– Might be better than
spectrum analyzer!
McNEILL: JITTER IN PHASE-LOCKED LOOPS
÷M
D
Q
OFF-CHIP
CLK/M
CK Q
CLK
CLK/M
104
Multiple PLL testing
• Multiplex to single output pin
• Watch out for crosstalk paths
• Multiplexer
– Disable other mux
inputs
• Other paths (e.g.
substrate)
– Switch off everything
else if possible
• Jitter through mux path
usually not too bad
– Doesn't accumulate
McNEILL: JITTER IN PHASE-LOCKED LOOPS
ON-CHIP
OFF-CHIP
CLK1
CLK
EN1
CLK2
EN2
CLKn
ENn
MUX
105
Self-Test Issues
•
•
•
•
•
Open loop test vs. close loop test
Frequency
Phase noise
Jitter
Choice of conditions
McNEILL: JITTER IN PHASE-LOCKED LOOPS
106
Open vs. closed
• Open better / simpler
• No need for precise source (but do need
low noise "zero" input to VCO)
• No need to wait for acquisition
• Open loop parameters can be related to
closed loop performance
McNEILL: JITTER IN PHASE-LOCKED LOOPS
107
Time, frequency
• Depends on application/specification
McNEILL: JITTER IN PHASE-LOCKED LOOPS
108
Frequency self-test
• Open loop - on-chip counter to count
cycles during externally set time window
ON-CHIP
n
VCO_CLK
OFF-CHIP
COUNT
EN
GATE
COUNTER
f = N / TG
VCO_CLK
GATE
COUNT
TG
0
McNEILL: JITTER IN PHASE-LOCKED LOOPS
1
2
3
N
109
Center Frequency self-test
• Center Frequency: short VCO input
TEST
LOOP FILTER
CHARGE
PUMP
McNEILL: JITTER IN PHASE-LOCKED LOOPS
VCO
(DIFFERENTIAL
INPUT)
110
Tuning range self-test
• Max - min range
• Min max frequency by
disabling PD or ramping
charge pump to +/- rails
• Saturate VCO input +/• Indication of ability to
cover tuning range
• Advantage: can be done
“digitally” (no need for
good quality analog
shorting switch
McNEILL: JITTER IN PHASE-LOCKED LOOPS
UP
UP
VCO
CHARGE
PUMP
DN
DN
LOOP FILTER
111
Time Domain Shortcuts
• Could compile full σ vs. delay plot
• Establishes confidence in κ model
• Or shortcut: just check at single delay
κ ΔT
σ
σ
σx
DELAY ΔT
τL
2
FULL PLOT
DELAY ΔT
“SHORTCUT” FROM t-f RELATIONSHIPS
σx
{
CLOSED
LOOP
JITTER
McNEILL: JITTER IN PHASE-LOCKED LOOPS
1
=κ
4 πf L
1
τL =
2 πf L
14243
LOOPBANDWIDTH
TIMECONSTANT
112
Frequency Domain Shortcuts
• Could compile full phase noise plot
• Establishes confidence in 1/f2 model
• Or shortcut: just check at specified offset
McNEILL: JITTER IN PHASE-LOCKED LOOPS
113
Phase noise self-test
• Could measure phase noise with VCO
input railed (VCO output at fmin or fmax )
• If VCO has unusual characteristic, may
want to short out in midscale
f
Δf
fMAX
Δf
fMIN
VCTL
ΔV
McNEILL: JITTER IN PHASE-LOCKED LOOPS
ΔV
114
Choice of Measurement
• Evaluation (pass/fail) vs. diagnostic
• Pass/fail
– Single (“shortcut”) measurements
• Diagnostic
– Full plots
– Structure shows information
McNEILL: JITTER IN PHASE-LOCKED LOOPS
115
Crosstalk/Coupling Diagnostic
• Crosstalk / interference issues
• Theory predicts what closed loop jitter /
phase noise should be based on open loop
• Close loop, run other circuitry
• Look for artifacts
– Frequency domain: spurs etc.
– Time domain: increased jitter
McNEILL: JITTER IN PHASE-LOCKED LOOPS
116
Crosstalk/Coupling Diagnostic Example
• On-chip coupling of digital noise from phase
detector
• Jitter higher at low delays when loop closed
rms jitter [ps]
Measured
jitter
Fit to
κ = 6.14E-08 √s
10
100
1000
10000
Delay ΔT [ns]
McNEILL: JITTER IN PHASE-LOCKED LOOPS
rms jitter [ps]
100
100
Measured
jitter
Predicted
10
100
1000
10000
Delay ΔT [ns]
117
Overview: Design Techniques
• VCO Design using κ figure-of-merit (time domain)
• Noise models for CMOS ring VCOs
• System level design issues
– Loop bandwidth
– Single-ended vs. differential
– Delay Lock Loop (DLL)
• Other VCO design techniques
– Transient noise source simulation
– LC oscillator
– VCO design in frequency domain
McNEILL: JITTER IN PHASE-LOCKED LOOPS
118
VCO Design Using κ Parameter
Open loop:
σ proportional to square root of ΔT
σΔT(OL) (ΔT) ≈ κ
ΔT
rms jitter [ps]
100
Measured
jitter
Fit to
κ = 6.14E-08 √s
10
100
1000
10000
Delay ΔT [ns]
McNEILL: JITTER IN PHASE-LOCKED LOOPS
119
Benefits of Designing With κ
• Can relate either open loop figure of merit (κ or N1) to
closed loop jitter performance.
• Allows design to take place in most convenient domain
• Simplifies design and simulation: need only consider
open loop VCO
• Allows stand-alone test of VCO contribution to jitter.
• Applies to any oscillator that fits 1/f^2 model
BUT...
•
κ and N1 describe jitter performance of the entire
oscillator: How to relate to design decisions on the
level of the ring delay stage?
McNEILL: JITTER IN PHASE-LOCKED LOOPS
120
Effect of Length of Ring
• Rings of lengths 3, 4, 5, 7, and 9 stages were fabricated
• All delay stages identical
N delay stages
What effect does the length of the ring have on jitter?
McNEILL: JITTER IN PHASE-LOCKED LOOPS
121
Schematic of Ring Stage for Experiments
VCC
CS1
R1
500Ω
R2
500Ω
CS2
Q4
Q3
Q1
+
Vin
-
Q2
+
Vout
-
IEE
VCC
+
VCTL
-
250Ω
300
µA
400
µA
4kΩ
3kΩ
200
µA
200
µA
6kΩ
6kΩ
VBIAS
VEE
McNEILL: JITTER IN PHASE-LOCKED LOOPS
122
Results: Ring Length Not A Factor!
κ
[E-08√s]
fo
[MHz]
td
[ps]
3
4
4.17
3.56
170.1
164.1
980
762
5
3.78
102.7
974
7
3.77
71.9
993
9
3.94
56.8
978
• Jitter depends only on
number of gates traversed,
not number of oscillator
periods:
100
rms jitter [psec]
RING
STAGES
predicted
3
4
5
7
9
Length of ring is not a factor!
• Only need to consider κ of
individual gate to know jitter
performance of ring
McNEILL: JITTER IN PHASE-LOCKED LOOPS
10
100
ΔT delay [nsec]
1000
10000
123
Ring length experiment: Handwaving explanation
• Example: two rings: 3 -stage and 5-stage
• 10nsec delay per stage (all stages identical)
• What is jitter after 150nsec delay?
A
B
C
D
E
A'
150 nsec
B
C
D
E
1
6
2
3
15
11
7
12
3
A'
B'
8
4
C'
150 nsec
10
5
A
B'
C'
1
6
4
2
9
7
5
12
10
8
15
13
11
14
13
9
McNEILL: JITTER IN PHASE-LOCKED LOOPS
14
124
Ring length experiment: Handwaving explanation
•
•
•
•
Jitter will be the same for each ring
In both cases, edge has traversed 15 gate delays
Jitter errors added in each delay are independent
Note: edge has not traversed same number of oscillator periods
– When analyzing jitter in ring oscillators, the gate delay is the
fundamental unit of time, not the oscillator period
A
B
C
D
E
A'
150 nsec
B
C
D
E
1
6
2
3
15
11
7
12
3
A'
B'
8
4
C'
150 nsec
10
5
A
B'
C'
1
6
4
2
9
7
5
12
10
8
15
13
11
14
13
9
McNEILL: JITTER IN PHASE-LOCKED LOOPS
14
125
Meaning of ring length experiment
• Can design ring from single gate
• Determine κ for one gate
• Within gate, find κ for each noise source
McNEILL: JITTER IN PHASE-LOCKED LOOPS
126
Benefits of Designing With κ
• Can predict system level closed loop jitter as a function of circuit
level parameters (resistor values, currents, etc.)
• Quick estimate of achievable jitter as a function of fundamental
parameters
– Power dissipation
– Signal amplitude
• Identifies major source(s) of jitter
•
κ independent of:
– Number of stages in ring N
– Load capacitance C
• Allows designer freedom to choose N, C to set center frequency
without affecting jitter
– Usually: few stages (3 or 4), maximize power for lowest jitter
McNEILL: JITTER IN PHASE-LOCKED LOOPS
127
Design Strategy
• System level:
– Determine PLL loop bandwidth
– Determine (system-level) κ for required
performance
• VCO level: determine
– Center frequency
– Number of stages (usually 3 or 4)
– Individual gate delay
• Gate level:
– System-level κ also applies to gate
– Design individual gate stage to meet κ
– Depends on circuit architecture
McNEILL: JITTER IN PHASE-LOCKED LOOPS
128
Gate level design
• Assumptions
• Types of ring delay stages
– Bipolar ECL (differential)
– CMOS ECL (differential)
– CMOS inverter (single-ended)
• κ expressions for noise sources
• Experimental results
McNEILL: JITTER IN PHASE-LOCKED LOOPS
129
Assumptions
• Dominated by white noise
– 1/f noise negligible
– Inside PLL bandwidth
• Noise sources independent
– Add in rss fashion
• “Dominant pole”
– Only one major delay mechanism
– Load capacitance
McNEILL: JITTER IN PHASE-LOCKED LOOPS
130
Bipolar ECL Gate Level Sources of Jitter
Differential pair delay stage
Delay stage with noise sources
VCC
VCC
enRL
CL1
enRL
CL2
RL1
RL2
CL1
CL2
RL2
RL1
Vout
- +
Vout
- +
Q1
+
Vin
-
Q2
IEE
VBIAS
en1
+
Vin
-
en2
Q1
Q2
Q3
IEE
RE
VEE
McNEILL: JITTER IN PHASE-LOCKED LOOPS
inEE
VEE
131
Handling Multiple Noise Sources
• Each source independent
• Contributions will add in rms fashion
• Find κ due to each noise source
McNEILL: JITTER IN PHASE-LOCKED LOOPS
132
Collector Resistance Noise Model
VCC
enRL
t
Vc1
enRL
Vn1(t)
CC
RC1
CC
RC2
Vc2
Vc1
Vc2
t=0
- Vout +
Vn2(t)
slope S
Td
t
t=0
δt
IEE
VEE
Vc2 - Vc1
κR
C
McNEILL: JITTER IN PHASE-LOCKED LOOPS
≈ (1.699)
δv
kT
I EE R C
133
Collector R noise result
Voltage standard deviation
(amplitude noise):
2 kT
σV =
CC
Slope at zero crossing:
dV I EE
S=
=
dt
CC
V n1(t)
V c2
t=0
V n2(t)
Time standard deviation (jitter):
2 kTCC
σ V dV
σV
=
⇒ σt =
=
σt
dt
dV dt
I EE 2
slope S
Td
t
δt
V c2 - V c1
McNEILL: JITTER IN PHASE-LOCKED LOOPS
t
V c1
δv
134
κ for collector R noise result
Gate delay:
Td = ln(2) RC CC
Time standard deviation (jitter):
σt =
2 kTCC
I EE 2
Definition of κ:
κ=
JITTER
σ
= t
DELAY Td
κ=
kT
2
ln(2) I EE 2 RC
Key: DC power dissipation in RC
McNEILL: JITTER IN PHASE-LOCKED LOOPS
135
Tail current source noise model
VCC
CC
t
Vc2
CC
RC
RC
Vc1
Vc2
Vc1
- Vout +
t=0
Vn2(t)
t=0
IEE
Vn1(t)
in
Td
VEE
t
δt
General form of κ
expression:
1
in
κ=
2 ln(2) I EE
McNEILL: JITTER IN PHASE-LOCKED LOOPS
Vc2 - Vc1
δv
136
Tail current noise result
Noise dominated by thermal noise
in degeneration resistor RE:
κ=
1
ln(2)
kT
I EE 2 RE
t
Vc2
Vc1
t=0
Vn2(t)
Similar to collector resistor result
Vn1(t)
Key: DC power dissipation in
degeneration resistor RE
Td
t
Noise dominated by shot noise of
bias current IEE:
κ=
1
2 ln(2)
δt
Vc2 - V c1
δv
qe
I EE
McNEILL: JITTER IN PHASE-LOCKED LOOPS
137
Switched input noise model
CC
Vin2
CC
RC
RC
Vin1
Vc1
Vin1
+
Vin
Vin2
t
±VT
VCC
Vc2
- Vout +
en
gm
Q1
gm(t)
Q2
Vc1
IEE
VEE
Vc2
t=0
•Bipolar differential pair
•Convenient analytical
expression for
transconductance gm
McNEILL: JITTER IN PHASE-LOCKED LOOPS
δt
δv
Vc2 - Vc1
138
Switched input noise result
t
±VT
Vin2
Vin1
κ=
gm
1
en
6 ln(2)
I EE 2 RC
Keys:
• DC power dissipation in
degeneration resistor RE
gm
gm (t)
V c1
V c2
t=0
δt
• Peak transconductance gm
δv
• Total nput referred noise
density en
McNEILL: JITTER IN PHASE-LOCKED LOOPS
Vc2 - V c1
139
Validation: κ vs. Tail Current IEE
4.0
MEASURED
PREDICTED
κ [E-08 √sec]
3.5
3.0
2.5
IEE [µA]
2.0
200
300
F ig. 4.20.
McNEILL: JITTER IN PHASE-LOCKED LOOPS
400
500
600
700
κ vs. t a il cu r r en t I EE .
140
κ due to input-referred noise in VCO control path
1 KO
κ=
en(VCO)
2 ωO
• Applies to any VCO dominated by input white noise
(or equivalent)
• Parameters:
KO
VCO control constant
ωO
VCO center frequency
en(VCO) Noise in VCOcontrol path referred to VCO input
• Use compatible units for KO , ωO !
Hz V
rad (V ⋅ sec)
OR
Hz
rad sec
McNEILL: JITTER IN PHASE-LOCKED LOOPS
141
Bipolar Differential Pair κ Expression Summary
Differential pair collector load resistance
κ=
kT
2
ln(2) I EE 2 RC
Tail current
(thermal dominated)
κ=
1
ln(2)
kT
I EE 2 RE
(shot noise dominated)
κ=
1
2 ln(2)
qe
I EE
Differential pair input referred noise
κ=
gm
1
en
6 ln(2)
I EE 2 RC
Input referred noise of VCO control path
κ=
1 KO
en(VCO)
2 ωO
Dominant contributor depends on details of VCO design
McNEILL: JITTER IN PHASE-LOCKED LOOPS
142
Intuitive meaning of K expressions
• Time domain figure of merit κ :
- has dimensions of square root (time)
- quantifies gate's ability to measures time accurately
• All equations for κ take form:
UNCERTAINTY IN QUANTITY
QUANTITY FLOW RATE
•
κ from thermal noise in collector load resistor Rc
κRC ≈ (1.699)
•
kT
I EE 2 R C
joule
joule/sec
κ from shot noise in tail current IEE
κI EE
≈ (0.849)
McNEILL: JITTER IN PHASE-LOCKED LOOPS
q
I EE
coul
coul/sec
143
Differential CMOS Noise Sources
Differential pair delay stage
Delay stage with noise sources
V DD
V DD
enR L
CL1
enR L
CL2
RL1
RL2
CL1
CL2
RL1
Vout
- +
RL2
Vout
- +
M1
+
Vin
-
M2
en1
+
Vin
-
ISS
VBIAS
en2
M1
M2
M3
ISS
VSS
McNEILL: JITTER IN PHASE-LOCKED LOOPS
i nSS
V SS
144
κ expressions: load resistance, tail current
Differential pair drain load resistance
2
kT
κ=
ln(2) I SS 2 R L
Tail current
1
κ=
2 ln(2)
in
I SS
Analogous to bipolar differential pair expressions
Switching action of differential pair similar in both cases
McNEILL: JITTER IN PHASE-LOCKED LOOPS
145
κ expression: switched input noise model
INP UT LINE AR RANGE
VDD
CL
t
Vin2
CL
RL
RL
Vin1
Vd1
Vin1
+
Vin
Vin2
- Vout +
en
gm
Vd2
M1
gm(t)
M2
Vd1
ISS
VSS
•MOS differential pair
•No nice analytical
expression for
transconductance gm
Vd2
t=0
δt
δv
Vd2 - Vd1
•Use approximation
McNEILL: JITTER IN PHASE-LOCKED LOOPS
146
κ expression: switched input noise
Approximating transconductance
gm as shown:
ΔIOUT
+ISS
κ due to input referred noise en:
ΔV IN
1
gm
κ=
en
2 ln(2)
ISS 2 RL
-I SS
Again, analogous to bipolar
differential pair expression
-V LIN
+V LIN
gm(ΔV IN )
gm
ΔV IN
McNEILL: JITTER IN PHASE-LOCKED LOOPS
147
MOS Differential Pair κ Expression Summary
Differential pair drain load resistance
κ=
2
kT
ln(2) I SS 2 R L
Tail current
κ=
1
2 ln(2)
in
I SS
Differential pair input referred noise
κ=
1
gm
en
2 ln(2)
ISS 2 RL
Input referred noise of VCO control path
κ=
1 KO
en(VCO)
2 ωO
Does not include short channel effects!
McNEILL: JITTER IN PHASE-LOCKED LOOPS
148
κ Expressions: Implications for Design
• For lower jitter, need lower κ
• Denominator of all gate-level κ expressions have
• current I
• power dissipation I2R
• voltage signal swing IR
⇒ For lower jitter, need to increase current, power, swing
• Implication:
⇒ As supply voltages, allowable power dissipation
decrease, low jitter becomes harder to achieve
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149
Single-ended CMOS Ring Oscillator
• Research underway (NSF CAREER grant)
• Test chip evaluation to be completed Dec 1999
• Preliminary results indicate similar tradeoffs
– power dissipation, voltage swing vs. jitter
• Caution: single-ended approach more prone to
supply, substrate noise coupling
– increases apparent jitter above theoretical limit
set by fundamental noise mechanisms
expressed in κ relationships
McNEILL: JITTER IN PHASE-LOCKED LOOPS
150
Example of κ design:
• 155.52MHz SONET jitter specification
• Goal: from system-level specification,
estimate required gate-level parameters
such as voltage swing, power dissipation,
bias current, etc.
• Required jitter σx = 0.01UI
• One UI = 1 / 155MHz = 6.43 nsec
• 0.01UI = 6.43nsec / 100 = 64.3 psec
• 2X safety margin: try for σx = 32 psec
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151
Example of κ design:
• System-level σx related to gate-level κ by
time-frequency relationships:
σx = κ
1
4 πf L
⇒ κ = σ x 4 πf L
• Loop bandwidth fL= 200 kHz (from SONET spec)
κ = (32 p sec) 4 π(200 kHz )
⇒ κ = 5.1E − 8 sec
• Estimate: apportion κ equally from four sources
κ= 2.5E-8 √sec
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for each source
152
Example of κ design: Load power dissipation
• κ expression for load resistance
κ=
2
kT
ln(2) I SS 2 R L
• At T=300K, estimated power dissipation
required in load element is
2.5 E − 8 =
2
( 4.0 E − 21)
ln(2)
ISS 2 RL
⇒
ISS 2 RL = 18.3µW
• If maximum allowable voltage swing is
limited (for example, to ISSRL = 0.3V),
then required bias current is
18.3 µW / 0.3 V = 61 µA
McNEILL: JITTER IN PHASE-LOCKED LOOPS
153
Example of κ design:
• Similar estimates can be calculated for
other contributors:
– tail current noise
– input referred noise of diffrrential pair
– noise in VCO control input path
• Allocations to total κ can be revised
– refine original “all contribute equally”
apportionment
• Identify dominant contributor
– where to push for maximum jitter benefit
McNEILL: JITTER IN PHASE-LOCKED LOOPS
154
Example of K design (AD806)
• Applications and performance requirements
• Development of basic ring VCO
• Shortcomings of basic VCO
- Design improvements
- Experimental results
• Summary
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155
AD80X clock recovery: design goals
SPECIFICATION
GOAL
CENTER
FREQUENCY fo
TUNING RANGE
155.52 MHz
MEASURED
RESULT
± 10 %
155.5 MHz
(trim)
± 10 %
60 ps rms
0.95 % UI
±5%
30
45 ps rms
0.7 % UI
0.5
±1%
TEMPERATURE
DRIFT OF fo
DUTY CYCLE
± 10 %
±5%
50 % ± 1 %
50 % ± 1 %
QUADRATURE
90 ° ± 10 °
TOTAL PLL
POWER
(5V supply)
140 mA
700 mW
JITTER
LINEARITY
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--25 mA
125 mW
COMMENTS
Should also be insensitive to supply noise
Affects closed loop
parameters
Stay within VCO
tuning range over T
Important for phase
detector
For frequency
detector; not critical
Low capacitance of
DI process (XFCB)
156
Basic design
• Inherent 50% duty
cycle
+
VA
-
• Quadrature to the
extent that stage
delays are
matched
• Control frequency
by controlling
stage delay
McNEILL: JITTER IN PHASE-LOCKED LOOPS
+
VB
-
d1
d2
"I"
OUTPUT
d1
d2
"Q"
OUTPUT
d1
d2
VA
VB
157
Interpolator
VCC
VFAST
RL
RL
dFS
VSLOW
Q2A
+
Q2B
+
Vout
-
VFAST
+
Q1A
Q1B
VSLOW
-
IFAST
ISLOW
+
VCTL(diff)
-
Q3A RD
Vout
(x = 0)
Vout
(x = 1/2)
Vout
(x = 1)
RD Q3B
IB
VEE
E. H. Armstrong, "A method of reducing disturbances in radio
signaling by a system of frequency modulation," Proceedings
of the IRE, vol. 25, no. 5, May, 1936.
McNEILL: JITTER IN PHASE-LOCKED LOOPS
• Interpolation fraction
x controlled by
differential VCTL(diff)
• Avoid common mode
influence
158
Basic VCO design
+
VA
-
d1
+
VB
-
d2
+
VC VSLOW
-
VOUT
+
VD
-
d1
+
VE
-
d2
+
VF VSLOW
-
d3
VFAST
VCTL(diff)
Requirements met:
√ Low duty cycle
distortion
√ Quadrature
√ Low power
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VOUT
d3
"I"
OUTPUT
VFAST
VCTL(diff)
"Q"
OUTPUT
Shortcomings:
• Control nonlinear
• Temperature drift
• Jitter from supply
159
Nonlinearity fix
• Delay interpolation: Linear in time T
• Frequency f = 1/T : inherently nonlinear V-to-f
• Simulated linearity error: ± 4 %
180
MHz
FREQUENCY
UNCOMPENSATED
WITH
COMPENSATING
NONLINEARITY
170
MHz
160
MHz
150
MHz
140
MHz
VCTL(diff)
-0.2V
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+0.0V
+0.2V
160
Nonlinearity Fix
• Translinear cell with emitter area unbalance λ:1 (CMOS-able)
• Well controlled compensating nonlinearity
VCC
I
IFAST'
ISLOW'
IB
RD
RD
Q8A
+
Q8B
VCTL(diff)
IFAST
Q9A
VCTL(diff)
J. McNeill, “Interpolating ring VCO with V-to-f
linearity compensation" Electronics Letters, vol.
30, no. 24, Nov., 1994.
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IFAST'
ISLOW'
Q10A Q10B
λ
ISLOW
Q9B
1
IB' (PTAT)
VEE
161
Measured linearity
OUTPUT FREQUENCY [MHz]
180
170
160
150
140
130
120
LINEARITY
ERROR [%]
2%
-0.6
-0.4
-0.2
-0.0
0.2
0.4
0.6
1%
0%
-1%
-2%
-0.6
-0.4
-0.2
-0.0
0.2
0.4
0.6
VCO INPUT [V]
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162
Overview: other VCO design techniques
•
•
•
•
•
Design / simulation (transient noise)
System level design issues
Other types of integrable VCOs
Different design methodologies
Stability / Loop Bandwidth Considerations
McNEILL: JITTER IN PHASE-LOCKED LOOPS
163
Transient Noise Simulation
• Transient simulation required for realistic
modeling of noise effects in nonlinear circuit
• Picosecond time step + transient simulation +
multiple gate VCO + large PLL =
Long simulation time?
NO!
• Only need to simulate one gate delay
• Find σt (sample standard deviation of delays)
• σt/√delay = κ (time domain figure-of-merit)
• Use relationships for system-level performance
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164
Transient noise source design/simulation
Vin
Td1
Vout
ONLY NEED TO
SIMULATE ONE GATE
Td2
Vin
Vout
Vout
Td100
TRANSIENT
NOISE
SOURCE
Vout
Vin
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Vout
• Monte Carlo ≈ 100 simulations
• Use mean, standard deviations of
simulated delays Td1, Td2, ...
165
Simulation: Transient Noise source
σv
V
σv2
t
T
Pulsed sample-and-hold
waveform for transient noise
simulation.
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T
Autocorrelation of pulsed
sample-and-hold waveform
166
Single-sided PSD of PSH waveform
WHITE NOISE en
2 σv 2T
0
0
1/T
Choose T ≈ 1/10 of shortest time constant
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167
Specifying Transient Noise Source
• Choose T ≈ 1/10 of shortest time constant
• Choose σv for desired noise density en
en
σv =
2T
• Or choose σi for current noise density in
in
σi =
2T
McNEILL: JITTER IN PHASE-LOCKED LOOPS
168
System level design issues
• Reducing κ improves gate-level influences on jitter
• What design options are available at the system level?
• VCO level
– Single-Ended vs. Differential
• PLL level
– Choice of Loop Bandwidth
• Architecture level
– Delay Lock Loop (DLL)
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169
VCO design issues: Differential vs. single-ended
• Differential signal in VCO
– Advantage: much better immunity to coupling of common mode
noise (supply, substrate, crosstalk from digital signal lines)
– Disadvantage: signal swing in differential pair usually limited to
be much less than supply rails
• κ expressions all indicate lower jitter with larger signal swing
• Single-ended signal in VCO
– Advantage: allows larger signal swing, potentially lower jitter.
BUT:
– Disadvantage: probably won’t realize low theoretical jitter, since
single-ended signal is much more susceptible to noise
⇒ Differential signal safer choice in “real-world” mixed signal chip
• Corollary: maintain signal swing as large as possible
(beware of VCO tuning methods that change signal amplitude)
McNEILL: JITTER IN PHASE-LOCKED LOOPS
170
System design issues: Loop Bandwidth
• Time-frequency relationships indicate that jitter
(due to VCO phase noise) can be reduced by
increasing the loop bandwidth fL:
σx
{
CLOSED
LOOP
JITTER
1
=κ
4 πf L
• Problems:
– Often, no choice! Loop bandwidth determined
by something else (e.g. SONET spec).
– Pattern jitter if loop bandwidth is too large
relative to frequency at phase detector output
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171
Pattern jitter example: synthesizer application
• Subtlety: Loop filter actually has two functions
– Sets loop bandwidth (system-level controls analysis)
– Also acts as a lowpass filter to “smooth” pulses at
output of phase detector
PHASE
DETECTOR
LOOP
FILTER
VCO
IN
OUT
P DOUT
OUT/N
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VCTL
÷N
172
Pattern jitter example: synthesizer application
• Subtlety: Loop filter actually has two functions
– Sets loop bandwidth (system-level controls analysis)
– Also acts as a lowpass filter to “smooth” pulses at
output of phase detector
REPEATING
JITTER PATTERN
OUT
OUT
OUT/N
OUT/N
PDOUT
PDOUT
VCTL
VCTL
Long loop filter τ (narrow loop
bandwidth) smooths PDOUT
pulses at VCTL input
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Loop filter τ too short
(Loop bandwidth too wide)
173
System design issues: Loop Bandwidth Result
• Loop bandwidth fL usually can be
no larger than a few percent of signal frequency
at output of phase detector
• If loop bandwidth is too high, pulses at phase
detector output are not sufficiently smoothed at
VCO control input
⇒ Result of too-high fL is pattern jitter at VCO
output
McNEILL: JITTER IN PHASE-LOCKED LOOPS
174
System-Level Design: Delay Lock Loop
• Phase Lock Loop (PLL)
– Synchronizes clock by generating a new clock with a
VCO, then using phase detector in PLL to line up clock
phases
• Delay Lock Loop (DLL)
– Synchronizes clock using an adjustable delay to “slide”
phase of existing clock in time.
– Does not use a VCO to generate a clock
PHASE
DETECTOR
LOOP
FILTER
φIN
VCTL
VOLTAGE
CONTROLLED
DELAY
φOUT
CLKIN
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175
DLL Advantages / Disadvantages
• Advantages
– No jitter accumulations as in VCO
– Loop easier to stabilize
• Disadvantages
– No output if input goes away (no "holdover")
– Can't improve jitter of noisy source
– Difficult frequency multiplication
McNEILL: JITTER IN PHASE-LOCKED LOOPS
176
System-Level Design: Delay Lock Loop
• Consider DLL for some applications
(e.g clock synchronization at known clock
frequency with low jitter )
• References:
– Lee and Bulzacchelli, “A 155-MHz Clock Recovery Delay- and Phase-Locked
Loop,” IEEE J. Solid-State Circuits, vol. 27, no. 12, Dec. 1992, pp. 1736-1746.
– Maneatis, “Low-Jitter and Process Independent DLL and PLL Based on SelfBias Techniques,” ISSCC Digest of Technical Papers, Feb. 1996, pp. 130-131.
– Johnson and Hudson, “A Variable Delay Line Phase-Locked Loop for CPUCoprocessor Synchronization,” IEEE J. Solid-State Circuits, vol. 31, no. 5, Oct.
1988, pp. 1218-1223
– Lee et. al, “A 2.5V CMOS Delay-Locked-Loop for 18Mbit, 500MB/s DRAM,”
IEEE J. Solid-State Circuits, vol. 29, no. 12, Dec. 1994, pp. 1491-1496.
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177
Jitter of Integrable VCOs
• Ring
–Empirical results show good jitter
– κ expressions allow design for requried performance
• LC resonant
–Known to have best jitter performance
–Small on-chip L restricts frequency to ≥ 1 - 10 GHz
• Multivibrator
–Example: Abidi & Meyer, “Noise in Relaxation
Oscillators,” IEEE J. Solid-State Circuits, vol. 18, no.6,
Dec. 1983, pp. 794-802.
–Known to have poor jitter performance
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178
LC integrated VCO
• Bond wire inductance
– Small L --> f ~ 10GHz
• Spiral inductor
– Moderate L --> f ~ 1 GHz
– Nguyen and Meyer, “Si IC Compatible Inductors
and LC Passive Filters,” IEEE J. Solid-State
Circuits, vol. 25, no.4 pp. 1028-1031, Aug. 1990
• Problem:
– Low Q due to substrate losses for L, C
– Improve Q → improve phase nosie
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179
Low Q solutions
• Methods of improving LC resonator Q to
improve phase noise
– Breaks in substrate
• Reduce eddy currents
– SOI
• Very high substrate resistance
– MEMS
• Etching away substrate
• Dec and Suyama, a 1.9GHz Micromachined-based Low-Phase-Noise
CMOS VCO, ISSCC Digest of Technical Papers, Feb. 1999, pp. 80-81
McNEILL: JITTER IN PHASE-LOCKED LOOPS
180
Other design methodologies
• References for frequency domain (phase
noise oriented) design methodologies:
– Hajimiri and Lee, “A General Theory of Phase Noise in
Electrical Oscillators,” IEEE Journal of Solid-State
Circuits, vol. 33, no. 12, Dec. 1998, pp. 2035-2041.
– Weigandt, Kim, and Gray, “PLL/DLL System Noise
Analysis for Low Jitter Clock Synthesizer Design,” 1994
ISCAS, vol. 4, pp. 31-34.
– Razavi, “A Study of Phase Noise in CMOS Oscillators,”
IEEE Journal of Solid-State Circuits, vol. 31, no. 3, Mar.
1996, pp. 331-343.
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181
Stability / Loop Bandwidth Considerations
• Typical synthesizer PLL application:
PHASE
DETECTOR/
CHARGE
PUMP
Loop filter transfer function
(assume C1 << C2)
1 + sRZ C2
F(s) =
sC2 (1 + sRZ C1 )
ICP
2π
LOOP
FILTER
VCO
KVCO
s
F(s)
θi
For stability analysis, break
PLL loop and find loop gain
(loop transmission) T(s)
I K
1 + sRZ C2
T ( s) = CP VCO 2
2 πN s C2 (1 + sRZ C1 )
McNEILL: JITTER IN PHASE-LOCKED LOOPS
θO
Rz
C1
C2
1
N
182
Stability / Loop Bandwidth Considerations
|T(ω)|
Loop transmission has: two poles
at the origin, a zero (lead
compensation) from RZ, and a
higher order pole from C2.
-40dB/dec
-20dB/dec
1
RZC1
For PLL to be stable (adequate
phase margin), it is necessary that
ω
1
1
<< ω t <<
RZ C2
RZ C1
1
RZC2
I K
R
T (ω ) ≈ CP VCO Z
2 πN
ω
-20dB/dec
T(ω)
where ωt will be the loop bandwidth
Given the stability condition, |T(ω)|
for ω ≈ ωt can be approximated by
ωt
ω
0°
-90°
PHASE MARGIN
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183
Stability / Loop Bandwidth Considerations
At the loop bandwidth frequency ωt , the loop
transmission is unity.
Equating |T(ωt)| =1 and solving for the loop bandwidth
ωt gives:
1
⋅ KVCO ⋅ ICP RZ
ωt ≈
2 πN
Note that ICPRZ product is a voltage that can be
• derived from a bandgap for temperature stability of ωt , or
• changed via ICP for adjustment of ωt
McNEILL: JITTER IN PHASE-LOCKED LOOPS
184
Summary: “Big Picture “ Key Concepts
• Time-frequency relationships among jitter
characterization technique enable specification,
design, measurement, simulation in most
convenient domain.
• κ expressions relate fundamental noise
mechanisms to system-level jitter / phase noise
performance
• In general, increasing power / current / voltage
swing improves jitter
• To achieve fundamental limit of jitter performance,
watch out for interference (e.g. substrate / supply
noise coupling). May drive choice of delay stage
(e.g. differential rather than single-ended).
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185