Technical R&D Report: July, 1995
Sponsored by: Advanced Research Projects Agency
Monitored by: The United States Departemnt of Justice
Under Contract #J-FBI 92-150

1.1 Wideband Digital Portable Communications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Sam Sheng, Robert W. Brodersen
1.2 Low-Power Analog-Digital Conversion for Spread-Spectrum Communications. . . 9
Lapoe Lynn, Ian O’Donnell, Robert W. Brodersen
1.3 Architecture and Design of CDMA Modem Symbol Detector/Demodulator . . . . 11
Kevin M. Stone, Ian O’Donnell, Sam Sheng, and Robert W. Brodersen
1.4 Low-Power High-S38peed Analog Techniques for Spread Spectrum Baseband
Recovery Circuits13
Keith Onodera and Paul R. Gray
1.5 Commercial Radio Implementation of InfoPad Downlink and Uplink . . . . . . . . . . 14
Craig Teuscher, Dennis Yee, Robert W. Brodersen
1.6 VGA for InfoPad Receiver Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Pramote Piriyapoksombut and Robert Meyer
2.1 Quasi-Direct Conversion Receiver Architectures for Adaptive Infopad RF
Communications20
Thomas B. Cho, Jacques C. Rudell, and Paul R. Gray
2.2 Frequency Synthesizer Design for High Integration Personal Communications
Transceivers22
Todd Weigandt, Srenik Mehta, and Paul R. Gray
2.3 CMOS RF Low-Noise Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Jia-Jiunn Ou and Paul R. Gray
2.4 Transmitters for High-Data Rate RF Communications. . . . . . . . . . . . . . . . . . . . . . . . 25
R. Sekhar Narayanaswami and Paul R. Gray
2.5 Micro-Power ADCs for Portable Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Thomas Byunghak Cho, George Chien, and Paul R. Gray
2.6 Micro-Power Baseband Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Thomas B. Cho, Francesco Brianti and, Paul R. Gray
2.7 High-Speed Low-Power Sigma-Delta Modulators for PCS Applications . . . . . . . . 30
Arnold Feldman, Paul R. Gray, and Bernhard Boser
2.8 Substrate Coupling Issues in Mixed Signal ICs.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Ranjit Gharpurey, Robert G.Meyer

3.1 50-Mb/s Wireless Infrared Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Gene W. Marsh, Joseph M. Kahn
3.2 Wireless Infrared Downlink for the InfoPad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Catherine Lee, Joseph M. Kahn

ARPA Project Summary for July 1994 - June 1995
Contract # J-FBI 92-150
Robert Brodersen
Paul R. Gray
Robert G. Meyer
Joseph M. Kahn
The goal of this research is to develop and implement new architectural and circuit approaches for highly integrated, low-power, RF and IR-based transceivers required for the Infopad and Infopad-like personal communicators. The approaches we are investigating utilize scaled CMOS VLSI technology to implement direct conversion transceivers using mostly-digital signal processing for signal detection and decoding. The architecture, circuit design, and packaging concepts which are successfully demonstrated in this program should have major impact in reducing the power dissipation, form factor and cost of the RF portions of a variety of types of personal communications devices.
The three major elements of our approach are:
• Use of the exceptionally high available bandwidth (as measured by device f t
of scaled submicron CMOS VLSI to implement the RF function in high-integration transceiver implementations, as opposed to the conventional approach of implementing these functions on separate chips using bipolar or GaAs technologies).
• Use of direct conversion and quasi-direct conversion receiver and transmitter architectures together with mostly-digital, power-optimized receiver signal

processing to reduce or eliminate the high-frequency, high-Q analog filtering functions that are not realizable in silicon integrated form.
• Use of low-voltage, highly paralleled dsp implementation in signal detection and decoding, and the coding and symbol generation portions of the transceiver to realize power dissipation that approaches the minimum achievable level.
• Exploration of high-data-rate TDMA-based IR links as an alternative to RF.
Three system applications are being used as the vehicles for demonstration purposes for these concepts:
1. The 2Mb/sec CDMA-based down link for the Infopad multimedia personal communications terminal. This modem utilizes a chip rate of 64Mchips/sec with two bits per chip, giving a spread factor of 64. This system application will demonstrate concepts of CMOS direct conversion sampling mixers as applied to
CDMA systems. Because of the large amount of high speed digital signal processing required for synchronization and de-correlation in the receiver, this vehicle will also demonstrate the application of very low-power digital design methodology to the CDMA receiver problem.
2. An adaptive, multi-standard transceiver for Infopad. This involves development of receiver architectural concepts and a family of CMOS transceiver building blocks which will enable the Infopad to inter-operate and exchange data with other types of RF-based systems such as public cellular telephone networks, cordless telephone and PBX systems, wireless LANs, and other PCS systems.
This requires CMOS VLSI implementation of receiver elements in a unique architecture with enough performance and adaptability for this wide spectrum of TDMA and CDMA applications.
3. A 50mbit/sec IR free-space data link for implementation of high-data-rate wireless LAN functionality in a picocell based system with cell sizes on the order of 20 meters. The IR link is a potential alternative to the RF CDMA link for
Infopad, where individual user data would be transmitted on a shared basis using TDMA. At these higher data rates, the problems of multipath propagation and background light noise power require new approaches to coding and to receiver design.

This portion of the project involves a comprehensive set of activities aimed at RF wireless communications modules that meet the system requirements of the Xwindows-based Infopad terminals. The basic system involves a high data-rate (2 Mb/ sec per user) downlink from a base station to users residing in the picocell serviced by the station, with the dimensions of the picocell ranging from 5 to 50 meters. Each picocell can thus contain on the order of 50 users, each receiving independent data streams that may include video information. The uplink channel, carrying pen/speech data from each mobile terminal, requires a significantly lower data rate than the downlink. As a result, the uplink can be achieved using much lower transmit power, and the utilization of a more conventional approach such as TDMA. The downlink is well-suited to CDMA, since for the downlink the complexities of power control are not needed. However, this critical problem from an RF design standpoint is that the receiver/demodulator in the InfoPad terminal must receive and decode the wideband
CDMA signal at extremely low power levels. Overall dissipation in the receiver electronics must be on the order of 100 mW or less when actively recovering a user’s 2
Mb/sec video stream from the aggregate 100 Mb/sec downlink. The focus of the research is on the circuit design techniques, packaging techniques, CAD tools, and receiver architectures needed to realize this receiver.
Three testchips - comprising the CDMA base-station transmitter, the analog RF unit in the mobile receiver, and the digital CDMA recovery block in the mobile - have been fabricated in the 1.0 micron MOSIS CMOS process. Embodying the efforts of several students, these chips implement most of the functionality required for the 100
Mb/sec Infopad downlink modem. The receiver is designed to operate at a carrier frequency of 1.088 GHz, employing a four-state QAM/PSK encoding and utilizing
CDMA as the multiple access strategy. At two bits/symbol, and employing a chipping rate of 64 Mchip/sec, this achieves an effective raw data rate of 128 Mb/sec and data rate after de-spreading of 2Mb/sec.
On the transmit side, the base-station transmit/modulator chip accepts the incoming parallel user data streams, performs the required data encoding and spectrum spreading to 64 Mchip/sec, and then pulse-shapes the spread signal at
256 MHz for transmission, bandlimiting it to approximately 85 MHz. This chip has been functionally verified at 200 MHz. On the receive side, the two chips implement the required front-end low-noise amplifier, homodyne frequency conversion via sampling of the RF signal, baseband variable-gain signal amplification (see Sheng report), an interleaved 256 Msample/sec A/D converter (see Lynn report), and a lowpower digital implementation of the CDMA baseband receiver circuitry, including both timing synchronization and data recovery (see Stone report). Preliminary testing has

shown that the CDMA baseband receiver is functionally correct, and the A/D converter is operating at the required frequencies.
A low-power CDMA correlator/demodulator has been layed out in 1.2 micron
CMOS, and will be fabricated in the July-August time frame. This prototype will demonstrate the concept of using passive-sampling analog correlators and low-datarate A/D converters as an alternative low-power implementation of CDMA receivers.
(Onodera report)
To support research in network protocols and facilitate the development of the remainder of the Infopad system, a low-datarate prototype of the overall wireless-link system has been implemented using commercially-available radio transceivers.
Employing a Plessey 700 kb/sec transceiver in the downlink, and a Proxim 242 kb/sec transceiver in the uplink, these were interfaced into an Infopad prototype via Xilinx
FPGA’s, and operationally demonstrated as part of the Infopad presentation at the
CHI’95 conference. (Teuscher report)
An auxiliary front-end low-noise amplifier with variable gain capability has been designed and an experimental prototype will be fabricated this summer. The need for variable-gain at the carrier frequency is borne out by system simulations, which indicate that the provision of gain control prior to sampling demodulation will significantly improve bit-error performance in the mobile Infopads, by ameliorating the dynamic range considerations caused by distance, fading, etc. This project is intended to explore AGC implementations at RF that maintain sufficient linearity for the Infopad application. (Piriyapoksombut report)

The focus of this project is to investigate and develop techniques for digital wireless communications capable of handling extremely high data rates, within a small portable device. In particular, the goal is the hardware design and implementation of an integrated analog RF front-end to be used in the U.C. Berkeley Infopad wireless computing project. The requirements that Infopad places on the radio are:
Picocellular network (cell size < 10 meters) to maximize spectral efficiency
User data rates from 9.6 kbps to 2 Mbps (for video)
Maximum number of 50 users/cell
Raw data bandwidth = 100 Mbps
Carrier frequencies > 1 GHz
Due to the extremely small cell size, transmit power will be limited to less than 1 mW, which also minimizes the power consumed in the transmitter and the dynamic range that the receiver must accommodate.
The link-level design is based on a scaled version of the IS-95 cellular radio standard; it uses direct-sequence code-division multiple access. The user data is modulated by differential quadrature phase-shift keying from 2 Mbps to 1 Mbaud, and then spread to a chipping rate of 64 Megachips/second with a hybrid Walsh-PN encoding strategy. The Walsh codes are used to orthogonally multiplex the users; the
PN code is used to provide good autocorrelation properties in the signal; furthermore, the PN code combined with the DC Walsh code (Walsh code 0) is used as a pilot tone for simplifying timing recovery in the receiver.
In Figure 1.1-1, the block diagram for the overall system is shown. With the exception of the two off-chip noise rejection filters, the antenna, and a clock oscillator, the entire receiver is fully integrated. For example, the low-noise front-end amplifier is designed for a gain of 12 dB over a 1.3 GHz band; it exhibits a noise figure of 5 dB, with a -1 dB gain compression point of -10 dBm. While several existing commercial LNA’s have exhibited noise figures of 2 dB or less, they do so at the expense of power: the
LNA consumes under 20 mW of power. The same design can be modified to have a NF of 2.7 dB, at the expense of doubling the power consumption. The concept that silicon
MOS can move into the analog arenas traditionally dominated by bipolar or GaAs FET devices is one that we are strongly developing, taking advantage of the sharp increases in device speed afforded by dimensional scaling. Due to current technology limitations
(MOSIS 1.0
µ
), for testing purposes the carrier frequency will be placed at 1.088 GHz, with a modulation bandwidth of approximately 75 MHz. In future revisions employing better technologies, the design can be scaled to either the 2.4 GHz or 5.8 GHz ISM bands, which are both sufficiently broadband and unregulated by the FCC.
Furthermore, traditional superheterodyne receivers have utilized multiple stages of complex analog processing and voltage-controlled oscillators to achieve the

requisite demodulation. Instead, a much more effective method to achieve demodulation is to utilize a passive passband sampling technique to perform both downconversion and sampling in a single step. Essentially, the entire mixer/oscillator section of the receiver has been reduced to a simple switch, with only a few transistors in the active path. This is attractive not only from a complexity perspective, but from a low-power one as well. Unlike an active mixer, the op-amp needs only to operate at the baseband sampling frequency, as opposed to the full carrier bandwidth. Also, since the demodulator is passive, mixer linearity is not an issue; in a prototype that we fabricated last year, distortion only became measurable after the input signal exceeded
+15 dBm (the point at which the switches began to turn off). The baseband sampling rate is required to be 128 MHz for timing recovery (twice the chipping rate), and two switches are employed, one to recover the in-phase signal and one to recover the quadrature.
At this point, the signal is now an analog sampled-data stream; it is fed into a discrete-time automatic gain control block, followed by a 4 bit flash A/D converter.
The ability to reliably recover the data using only 4 bits of quantization comes directly from the spread-spectrum nature of the signal; in essence, the signal is already buried in noise, since all users are simultaneously transmitting. As long as the quantization noise plus the channel interference does not exceed the 18 dB jamming margin in the link, the signal can be reliably recovered; from simulation, we have found that 4 bits is sufficient. This minimizes both power and complexity requirements in the A/D; in spite of the fact that it must run at 128 MHz, the A/D converter requires only 10 mW given its low resolution requirements and the fact that it only drives on-chip loads.
Within the digital baseband section, there are four distinct functional blocks.
First, timing recovery must be accomplished: a delay-locked loop is used to accomplish this. A pair of correlators are employed to track the autocorrelation peak of the pilot tone, and the difference between these two correlators is fed back to drive the sampling point of the switching demodulator. The timing loop and the data recovery are independent of one another; by doing this, we can minimize the probability of false lock. Second, the presence of the pilot tone also enables us to estimate and track the time-varying radio channel, and use this data to maximize the signal-noise ratio in the data recovery block. Three correlators are employed here, each tracking a separate peak in the channel impulse response. Third, since each cell in the system has its own pilot tone, one correlator is used to “scan” for adjacent cells, and measure the received energy from each. Thus, handoff from cell-to-cell can be accomplished digitally. Lastly, the data recovery block uses the estimated channel impulse response to recover the symbols, and then passes the stream into a DQPSK demodulator for final conversion to the output at 2 Mbps.
The benefits of spread-spectrum are apparent here: it enables the receiver to perform digitally what traditional systems have done in the analog domain. For example, user multiplexing, conventionally done by assigning each user a separate frequency, is done by a simple digital correlator as opposed to a filter, mixer, and a
VCO. Furthermore, cell-to-cell handoff does not require changing carrier frequencies or analog hardware control; again, it is estimated and controlled entirely in the digital domain. The use of differential phase-shift keying also allows the use of incoherent

demodulation: nowhere is an analog phase-locked loop needed. Carrier offsets between the transmitter and the receiver translate into a slow spin in the constellation; so long as this offset is less than the 1 MHz data rate (simple with crystal-based frequency references), it is eliminated automatically by the data recovery block.
It is apparent that the key hardware in the digital section is the correlator, and minimizing its power consumption and complexity are paramount. By employing several stages of pipelining, as well as some parallelism, the digital section can be run at a supply voltage of 1.5V, in spite of the 128 MHz processing requirement. The reduction in supply voltage radically drops the power; the baseband digital section requires a total of 9 correlators along with some ancillary circuitry (comprising mostly of control and clocks); total power consumption is under 30 mW.
Three key testchips have been designed and fabricated, representing the RF analog receiver section, digital baseband receiver section, and the base-station modulator/transmitter. Currently, both receiver sections are under test; the digital section has been functionally verified and is currently undergoing testing for speed and power. The base-station modulator/transmitter has been tested and is functional to a measured frequency of 200 MHz.
Antenna External
Components
Image Rej
Filter
Noise
Filter
Sampling Demod
(in-phase and quadrature)
I
Gain Control
Power
Detector
A/D
Converter
4
RF LNA
Tming
Recovery
Delay-locked
Loop
Demod Input
Buffer
Oscillator
256 MHz
I and Q sampling clocks
(128 MHz)
VCO
Q
Sampled-Data
AGC Amp
A/D
Converter
4
-
Correlator
Correlator
Adjacent-Cell Scan
Data Recovery
To ARM Microprocessor
Data Out
(2 Mbps)
DQPSK
Decoder
Correlator
RAKE Receiver
(3 correlators)
PN
Decoder
Channel Impulse
Response Estimation
Channel Estimators
(3 Correlators)
(Thick line indicates both I & Q)
System
Block Diagram
Figure 1.1-1: System Block Diagram

(a)
(b)
(c)
Figure 1.1-2: Infopad CDMA testchip set
(a) Base-station transmit/modulator
(b) Analog RF receiver section
(c) Digital CDMA baseband receiver section

Receivers for portable communications systems such as the Infopad require analog-digital conversion of the received signal for digital processing. High data rates on the order of 2 Mbit/sec per user along with the use of error correction and/or spreading codes necessitate an extremely high conversion rate for the ADC.
Furthermore, the direct conversion of the signal from an intermediate frequency to a socalled “digital IF” places even more strict speed requirements on the converter.
Fortunately, the choice of a spread-spectrum based communications system provides a measure of natural immunity to noise and interference -- relaxing the required SNR of the converter (and therefore the required number of bits resolved). Computer simulations (see Teuscher and Sheng) have shown that with a spreading gain of 64, less than 4 bits of resolution are sufficient for the ADC to meet the SNR requirements of the system.
The purpose of this project is to design an analog-to-digital converter capable of converting an analog signal into four bits of digital information at a rate of 128
Msamples per second (MS/sec). Two parallel paths (one for In-phase and the other for
Quadrature-phase) should provide a net throughput of 256 MS/sec. The goal of the
Infopad receiver is to fully integrate the entire receiver (LNA, Mixer, AGC, ADC, and base-band) onto a single CMOS die. In 1.0 micron CMOS, 128MS/sec is a very high conversion rate, and has led to the choice of a flash architecture over pipelined or subranging ADC architectures. However, by using hardware already implemented in the
AGC, it was possible to pipeline one bit of the A/D function, resulting in a net savings in power at no extra cost.
The design of an ultra low-power portable communications system makes a highly integrated implementation desirable. Unfortunately, the choice of making the
ADC capable of being integrated onto a mixed-signal chip limits the technology to a standard digital CMOS process. Mixed signal integration also makes multiple supply voltages necessary in order to maintain low power. Therefore, the converter must accept an analog input signal coming from circuitry operating off of an analog supply
(5 volts here) and then output digital bits at a lower supply voltage (3.3 volts in this case)
Perhaps the greatest concern of an analog design for a mixed signal chip is the presence of digital switching noise. To reduce unwanted coupling of this noise, the signal path is maintained differential. Differential comparison is accomplished without input sampling capacitors reducing the input capacitance of the converter. An added bonus is the elimination of the large area occupied by capacitors in a single polydigital process.
An analog to digital converter meeting these requirements has been designed with minimizing power consumption as a key constraint. The goal was to implement two 4-bit converters operating at 128 MS/s in 10-15 mW total power. The design has

been integrated onto a single chip with an analog front-end receiver (including sampling demodulator) and as a stand-alone block. Test boards have been designed and the design is currently being tested for speed and linearity. Preliminary results on the stand-alone A/D verify the functionality of the converter up to 128 MHz. However, loading due to test equipment causes severe digital noise coupling and supply bounce
(even with isolated analog and digital supplies) making accurate measurements of offset and linearity difficult. The load added by test probes and board-level parasitics would not be present in a fully integrated design. Testing is still in progress.

The goal of this project is to develop the required baseband DSP circuitry to support code-division multiple access for 50 users per base-station, where each user can receive raw data at a rate of up to 2Mb/sec. This is accomplished by using DQPSK modulation which encodes 2 bits/symbol, transmitting at a symbol rate of 1MHz, and spreading these user symbols to a chipping rate of 64 Mchip/sec. Ostensibly, the DSP circuitry must then be able to recover and a sampling rate in excess of 128MHz for timing recovery. Besides recovering user data, the backend section must perform the following functions: initial coarse timing recovery to align the receiver and transmitter to within 1 spreading chip, periodic fine (chip) timing recovery to keep the receiver and transmitter aligned to within 1/8 of a chip, detection of other nearby base-stations, and picocell-to-picocell handoff.
Since this chip will be used in a mobile, battery-operated receiver, minimizing power consumption is also of the utmost importance. In order to support our throughput requirements while minimizing power consumption, we found it necessary to use three different supply levels: 1.5V, 3.3V, and 5V. The 1.5 volt supply is used to power the seven correlators that constitute the core of the chip (see Figure 1.3-1 below).
Each correlator must be able to accumulate data at the chipping rate of 64 MHz.
Through several low-power architectural design modifications, power consumption in this block has been extensively minimized; the predicted consumption for each correlator while maintaining throughput is approximately 1 mW of power. Due to timing constraints, the control logic necessitates a 3.3V supply, while the clock generator, with a critical path of 4ns, requires a 5V supply. Fortuitously, the Infopad system itself requires these three supply voltages; the use of multiple supplies to optimize power is not a penalty. Our power consumption target for the entire chip is
30mW, which compares favorably against similar chips produced in industry that consume in excess of 1W of power at much lower performance levels.
The digital receiver chip implementing the above has returned from fabrication, and is currently under test. Preliminary results confirm logical functionality, and we are currently undertaking both speed and power verification. System level simulation for the chip was written in VHDL and run under the Viewlogic simulation package.
Each on-board functional block was designed using Viewlogic’s behavioral VHDL to stdcell package, Viewlogic’s schematic capture program (viewdraw) which acts as an interface to the OCT database, and magic. The test board was designed using Viewlogic

for schematic capture with a backend into Racal/Redac for layout, routing, and Gerber generation.
Figure 1.3-1: Correlator die photo

In this research a complete baseband (data recovery) receiver is being implemented which will operate with an effective sampling rate of 128Ms/s and data rate of 2Mbit/s using a 1.2u CMOS process. The chip will include full quadrature processing (I & Q) for acquisition (initial synchronization), tracking and data demodulation. It is designed for data bits of chip length 64 and PN (pseudo-random noise) code of chip length 32,768. It can be programmed to detect 1 of 64 Walsh function codes to select the recovery of the desired transmitted channel.
At the heart of this data recovery systemize the correlation block. In contrast to a digital correlation approach, this correlator is implemented in the analog domain using a sampled data system. Since there is a decimation of the sampling rate by the correlator it can be followed by a low speed- low power A/D converter operating at the 1Ms/s data rate.
The potential benefit of this approach is a better speed-power-accuracy performance than in a digital correlation approach. Comparing the two methods (for the same data rate); for a given accuracy the analog approach will have a lower power; or for a given power the analog approach will have a better BER owing to a better input resolution (accuracy).
The active area of the chip is 30 mm
2
(47K mil
2
) and the estimated power dissipation is 60mW at 5V. The layout of the chip is nearly completed and silicon is expected at the end of the summer.

The goal of this project is to implement the wireless downlink and uplink for the
InfoPad system with commercially available transceivers. This commercial implementation provides a temporary solution in lieu of a custom radio. The Plessey
DE6003 transceivers were used for the downlink, whereas the Proxim RDA 100/2 transceivers were used for the uplink. The interface between the radios and the InfoPad system was implemented using a Xilinx FPGA.
For the wireless uplink, Proxim RDA 100/2 radios were used, providing a 242
Kbps link. The Proxim radio employs direct sequence spread spectrum in the 900 MHz band to achieve Part 15 compliance. Four separate frequency channels are provided to accommodate additional users. Significant features of merit for the transceiver include an output power level of 100mW, and power requirements of 425 mW in receive mode, and 850 mW in transmit mode.
For the wireless downlink, Plessey DE6003 transceivers were used, providing a maximum data rate of 625 Kbps. The Plessey radio operates in the 2.4-2.5 GHz range, and is designed for frequency hopping operation with 100 1 MHz channels. The output power level is switchable between 20 dBm (100 mW) and 10 dBm (10 mW), and the radio consumes about 650 mW of power in receive mode, 1500 mW in transmit mode.
Proper configuration of the radios was implemented in the Xilinx FPGA. In addition, the Xilinx FPGA provided clock recovery, bit synchronization, frame synchronization, parallel-to-serial conversion for the transmitters, and serial-to-parallel conversion for the receivers.
The clock recovery algorithm was implemented using VHDL code and then mapped to Xilinx logic blocks. Digital integration using a variant of the tau-dither loop is used to determine the optimal sampling point, rather than simple edge detection. As a consequence, the initial sampling phase is far less susceptible to spurious noise spikes. In addition, the clock recovery includes a closed-loop update component that allows tracking of small frequency offsets. Finally, the actual bit decision at the sampling point utilizes redundancy to improve performance, using the integrated bit interval value rather than the instantaneous value at the sampling point.
In order to provide a good initial estimate of the sampling phase, a bit synchronization sequence of 8 alternating bits (01010101) is expected at the beginning of each packet. Data passes through the clock recovery module only when a valid synchronization sequence is detected. Immediately following the bit synchronization sequence is a user-programmable 16 bit frame synchronization sequence, followed by the packet payload. Also, in order to meet the DC balance requirements of the two radios, data is “scrambled” and “unscrambled” at the transmitter and receiver, respectively, by performing a bitwise XOR operation on each 8 bit data word with a fixed 8 bit scrambling sequence.

The commercial radio implementation was successfully demonstrated in May
1995. Future work in this area includes measuring the bit error rate for both commercial radios.

A wireless communication network such as InfoPad must be capable of operating over a wide range of received signal strengths. Due to such variable factors as fading, reflection and transmitter proximity, the receiver is required to function with low bit-error-rate over a 40 dB signal range. This requires incorporation of a widedynamic-range variable-gain front-end amplifier in the system.
Various circuit topologies were systematically examined for use in this critical application. The requirements of low noise figure, low distortion and matched terminal impedances over a wide gain control range are very stringent. The architecture employed is a two-0stage amplifier with variable local shunt feedback to achieve gain control while still maintaining good matches to 50. An output buffer stage drives the load. Operating from a single 2.7V supply, simulations show the circuit has a maximum gain of 20 dB with 2.6 dB noise figure at 1GHz. The noise figure increases to
6.7 dB as the gain is reduced to 6 dB. Input and output mathces are maintained with a return loss below -13 dB. Third-order intercept point was simulated at -15 dBm input at
20 dB gain, rising to -2 dBm input at 6 dB gain. Circuit performance is maintained over a range of supply voltage (2.7V to 5.5V), temperature (-40
°
C to 125
°
C) and 130 MHz bandwidth at a center frequency of 1 GHz. All simulations include complete package parasitics and external supply parasitic inductance. A test circuit is currently being fabricated in a 12 GHz BiCMOS process. The circuit schematic is shown in Fig. 1.6-1 and the chip layout is shown in Fig. 1.6-2.
Figure 1.6-1: Circuit Schematic

Figure 1.6-2: Chip Layout

The goals of this research are twofold. The first is to find and demonstrate techniques that allow the implementation of digital radio transceivers for PCS applications at much higher integration levels than is the case at present. The second goal is to find and demonstrate receiver architectures and transceiver block circuit implementations that allow the Infopad personal communications device to adaptively communicate with other RF communication systems, including, for example, public network cellular systems, cordless phone and wireless PABX systems, and wireless
LAN systems.
Considering North America, Japan, and Europe, such capability could involve compatibility with as many as 9 standards at the current time, and additional ones as they emerge. These standards differ in carrier frequency, bit rate, modulation technique, channel bandwidth, transmit power level, and other aspects. The different standards involve various mixtures of FDM, TDMA, CDMA, and frequency hopping.
The multi-standard objective has strong implications for the overall architecture of the modem, as well as for the implementation of the various blocks.
Antenna diversity with multiple RF interfaces and LNAs will be required to interface antennas suitable for the three basic frequency ranges (900MHz, 1.8GHz,
2.4GHz). Performing the frequency synthesis required with sufficiently fine channel spacing and sufficiently low phase noise to address the most critical applications
(cellular phone network interfaces) requires new approaches to the CMOS implementation of monolithic VCOs and synthesizers.
Implementation of the power amplifier function over the wide range of power levels required (100mW to 3W) with high efficiency at all settings is a difficult problem.
Realization of the high required power levels on voltages compatible with VLSI CMOS will require transformer coupling at the PA output. Finally, performing the baseband analog filtering, A/D conversion, and dsp-based final filtering, symbol timing recovery, carrier recovery, and decision process with low power dissipation over the range of modulation schemes, symbol rates, and frequencies will require a new approach to the overall function in which a more generic programmable communications processor architecture is used.
Design has been completed on all of the major blocks of a prototype integrated receiver in 0.6 micron CMOS. The architecture chosen was a quasi-direct conversion receiver with phase-noise-shaped synthesizers based on ring oscillators. The Digital
European Cordless Telephone (DECT) standard was used in this prototype as a

demonstration example. Fabrication of the prototype LNA, mixers, baseband filtering and ADC, transmit power amplifier, and synthesizers will be completed during the summer of 1995. Experimental evaluation of all blocks and the complete receiver will take place in the fall of 1995.
In addition, the feasibility of multistandard operation using this architecture has been studied. The key element is a power-optimized baseband processor embodying all the functions required for the various types of systems. Overall general feasibility of an integrated multistandard transceiver has been evaluated and critical RF performance requirements identified.
Specific achievements in the implementation of the different blocks are described below.

The focus of this research is to evaluate and compare overall architectures for a single chip CMOS solution for a radio frequency data communication receiver with multi-standard communications capability for Infopad. By virtue of the highest level of integration coupled with the utilization of a CMOS process, form factors and power dissipation comparable with single-standard transceivers should be realizable.
Considerable saving can be attained with regard to both power and cost.
A summary of the characteristics of many of the standards involved is given in
Table 1. To achieve compatibility with even a subset of the standards listed, a transceiver will need to accommodate carrier frequencies up to 2.6GHz. From technology perspective, initial studies on the receiver indicate that a 0.6um CMOS process may be used for the front-end RF sections up to around 2GHz, and for 2.6GHz
band, more advanced CMOS technologies, 0.5um or below, may be required.
From the system perspective, a new “quasi-direct conversion” receiver architecture has been developed. In this architecture, a signal at the carrier frequency is first amplified through the LNA and then gets translated to the baseband in two IF mixing steps without IF bandpass filtering requiring all the channel select filtering at baseband. Because little RF & IF filtering is performed in this architecture, image component located at frequencies below first local oscillator clock frequency can interfere the signal during two step mixing process. This problem can be resolved with a image reject mixer which rejects this image component by properly combining inphase and quadrature components of the signal. Although this image reject configuration requires extra mixer stages, external the usual RF bandpass filter after the
LNA can be eliminated keeping all the signal path on chip. Local oscillators(LO’s) provide two frequency components to mixers for frequency translation, where the first
LO is a fixed frequency oscillator and the second LO is a tuned oscillator for channel selection at much lower frequency than the first LO. Finally, at baseband, channel select filtering and signal amplification are performed before A/D conversion for further DSP.
Key advantages of this architecture over other conventional architectures include no need for external RF & IF bandpass filters for smaller form factor and reduced power dissipation, and relaxed phase noise requirement on the second LO which is an oscillator tuned to the desired channel frequency. Also, the two-step mixing scheme suppresses the carrier feed-through problem which is critical in direct conversion receiver.
Current status is that the system requirements and simulations have been completed and a test chip is under development. The die will include low noise amplifier, image-reject mixer, baseband filter and A/D converters, frequency synthesizers, and power amplifier. To suppress the noise coupling due to high integration, differential signal path is used for the entire system. Initial test results should be available by October of 1995.

Table 1: Summary of Cellular Phone, Cordless Phone, Wireless LAN & PCS
Parameter AMPS IS54 GSM JCP
Origin
Access
EIA/TIA EIA/TIA ETSI
FDD FDM/
FDD/TD
M
FDM/
FDD/TDM
Modulation FM pi/4QPSK GMSK, differential pi/
4DQPSK
Baseband filter
Data rate per
RF channel
NA
FM Deviation 3khz
RF Channel frequencies
824.04-
848.97(X)
869.04-
893.97(R)
833 No of RF
Channels
Channel
Spacing
30kHz
Root raised cosine
48kb/sec
(2bits/ symbol)
NA
824.04-
848.97(X)
869.04-
893.97(R)
833
30kHz
Root raised cos.
beta=0.3
270.8kb/ sec
NA
890-
915(X)
935-
960(R)
124
200khz
Root raised cosine
42kb/sec
(2bits/ symbol)
NA
1600
Synthesizer switching speed
Frequency
Accuracy slow
2.5ppm
Speech channels per RF
Channel (full/ half rate)
1
Speech coding
Analog companded slow
200hz
3
VCELP
8kb/s
8/16
RELP-LTP
13kb/sec
Frame
Length
Power Control rqmt
NA 40ms
Peak Power: 3W(6max) 3W(6max) 3W(20ma x
7 steps 7 steps
3/6
VCELP
8kb/sec
DECT
ETSI
FDM/TDM/
TDD
GFSK
Gaussian
BT=0.5
UK
CT2
FDM/TDD
GFSK
Gaussian
BT=0.5
1.152Mb/sec 72kb/sec
288kHz
0:1897.344M
hz,
9:1881.792M
hz
10
1.728Mhz
30us(BS)
450us(HS)
50kHz
12/24
32kb/s
ADPCM
14.4-25.2kHz
1:864.15Mhz
40:868.05Mh
z
40
10kHz
1ms(ch-ch)
2ms
10kHz
1/1
32kb/s
ADPCM
10ms(12Tx+1
2Rx)
2ms
(1Tx+1Rx)
250mW 10mW no no
NA
52
4/8
5ms
PHP
Japan
TDM/TDD pi/4-DQPSK
Root Nyquist alpha=0.5
384kb/sec
1895-
1911Mhz
300kHz
30us(BS)
1.5ms(HS)
3ppm
32kb/s
ADPCM
(4Tx+4Rx)
100mW
802.11F
H/part 15
IEEE
FH/FDM
(G)FSK
500khz LP
1Mb/sec/
2Mb/sec
~225kHz
2.4-2.48G
75
1Mhz
300us
75kHz
NA
NA
1 watt?
optional

A critical requirement for a multi-standard RF interface for Infopad is the implementation of a low-power local oscillator synthesizer that can realize the combination of low phase noise, rapid channel acquisition, and close channel spacing that is needed in the different standards. The goal of low power dissipation, in particular, dictates a high level of integration. Previous generations of synthesizers in the 900 MHz to 2.4 GHz range have been designed at relatively low levels of integration. Higher integration imposes some obstacles on synthesizer design, but offers some new opportunities as well. The focus of this research is on re-evaluating synthesizer design trade-offs for high integration receivers, looking at new, partlydigital architectures and the possibility of using ring-oscillators in place of conventional
LC-tank oscillators to reduce the off-chip component count.
The goal of this work is the design of a highly integrated, multi-standard frequency synthesizer architecture for the various personal communications bands from 900 MHz to 2.4 GHz. Frequency synthesizers are used in the local oscillator subcomponent for most heterodyne and super-heterodyne radio receivers. In such systems the local oscillator output (which determines which incoming channel is selected) is created by locking a tunable, high-frequency oscillator to a high-accuracy, lowfrequency reference, using a phase-locked-loop. A critical performance parameter which determines the selectivity of the radio (ability to reject neighboring channels), is the phase noise and spurious harmonic performance of the local oscillator. This performance is determined by a combination of: (1) the phase noise in the tunable, voltage-controlled oscillator (VCO), (2) the bandwidth and architecture of the frequency synthesizer PLL.
Research efforts to this point have explored the phase noise performance of
CMOS ring oscillators for possible use as VCO’s [1, 2]. Ring-oscillator are easy to integrate on chip, and do not require the off-chip tunable capacitor (varactor) required in most LC-tank type oscillators. Although phase noise performance is typically worse than in tuned oscillators, ring-oscillator phase noise improves with power consumption at a rate of 10 dB per decade. With a power budget of 60mW, for example, a differential ring oscillator can attain phase noise performance on the order of -109 dBc / Hz at 1.7
MHz away from carrier, making it usable for a DECT standard radio receiver. Ringoscillators are more promising for some of the newer generations of standards (mostly digital) with wider channel spacings, as opposed to backwards compatible channel spacings like those of the IS-54 digital Standard. The reason, is that phase noise falls at a rate of 20 dB per decade offset from carrier, while the bandwidth of channels only rises by 10 dB per decade. The net benefit in the blocking ability for interfering channels is 10 dB per decade.
Another possibility for increasing the applicability of ring-oscillators is designing synthesizers with a much wider PLL loop bandwidth so that the received

signal band lies within the bandwidth of the PLL and the ring-oscillator phase noise is attenuated by the action of the loop. One of the key trade-offs in frequency synthesizer design is between the bandwidth of the PLL, and the channel spacing of the local oscillator output. A high bandwidth PLL rejects ring-oscillator phase noise out to higher frequencies, but results in higher spurious harmonic tones, unless the channel spacing is changed. New architectures are being explored which attempt to workaround this bottle-neck.
In this project a new approach to avoiding the PLL bandwidth / channel spacing bottleneck is proposed. This technique utilizes a phase-interpolation block, which interpolates between phases in the ring oscillator to provide a fractional divideby ratio in the PLL feedback loop. The result is a higher potential PLL loop bandwidth for a given channel spacing. This approach should yield performance improvements similar to those found in other fractional synthesis techniques [3, 4]; however, spurious tones should depend on feedback phase linearity which is potentially better than the tone-generating mechanisms in conventional fractional synthesis. The spurious tone performance is expected to be better than the DDS / Mixer approach as well. The high
PLL loop-bandwidth helps reject ring-oscillator phase noise and also results in faster settling for frequency hopping applications.
[1] T. Weigandt, B. Kim, P. R. Gray “Analysis of Timing Jitter in CMOS Ring Oscillators”, ISCAS Proceedings,
Vol 4, June 1994, pp 27-30.
[2] B. Kim, T. Weigandt, P. R. Gray “PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design”,
ISCAS Proceedings, Vol 4, June 1994, pp 31-34.
[3] V. Reinhardt, K Gould, K. McNab, M. Bustamante, “A Short Survey of Frequency Synthesizer Techniques”,
Proc 40th Annual Freq. Control Symposium, May 1986, pp. 355-365.
[4] T. Riley, M. Copeland, T. Kwasniewski, “Delta-Sigma Modulation in Fractional-N Frequency Synthesis”,
IEEE Journal of Solid-State Circuits, Vol 28, No. 5, May 1993, pp. 553-559.

With the advance of submicron MOS technologies, it has become possible to build RF low-noise amplifiers (LNA) for some applications using CMOS technologies as opposed to the more traditional bipolar and GaAs technologies. The potential results are lower cost and higher levels of integration in the overall RF transceiver. Higher levels of integration improve both overall cost and, potentially, overall power dissipation since off-chip signal paths at RF frequency are eliminated.
The goal of this project is to investigate circuit configurations for RF LNAs suitable for implementation in standard CMOS technologies.
Key requirements for LNA are noise figure, input impedance matching, intermodulation distortion, and power consumption. We are investigating a singlestage differential-mode amplifier operating at 1.9GHz for DECT using on-chip spiral inductors as well as bond-wire inductors to achieve input matching through both series input lead tuning and source degeneration. The spiral inductors are also used for load tuning. The key research problem is the modeling and optimization of the relatively low-Q inductors with their high parasitic capacitance.
The simulation results showed that noise figure 2.5dB, S11 -24dB, power consumption 33mW at 3.3V power supply, and voltage gain 17dB at 1.9GHz can be achieved in standard 0.6 micron CMOS technology. A prototype is completed and will be fabricated in summer 1995.

The goal of this project is to examine the feasibility of implementing highfrequency moderate power-level Power Amplifiers in a standard CMOS process. The focus of this project is the design of a power amplifier that will generate a 250 mW signal at a carrier frequency of 1.9 GHz with reasonably high efficiency. Because this whole RF project is intended for portable applications, where the unit containing this radio is powered by a battery, the real challenge (beyond the difficult frequency and data rate requirements) is to keep the efficiency high over the range of required power output levels and to keep power consumption low.
At the present time, a test chip is being fabricated to test out some of the analysis done to this point. The design is a three stage, differential design. Each of the individual stages consists of 2 transistors in a cascode configuration. The use of spiral on-chip inductors was investigated, but it was found that the Q of a spiral on-chip inductor in a standard CMOS process was too low, and that the efficiency greatly suffered with these inductors. Therefore, it was decided that the inductance of bond wires be employed in tuning out the gate and drain capacitance of the active devices.
The first stage has a tail source current, which will be used in the future for power control. The following two stages are biased very close to the MOS threshold voltage, so as to minimize the DC current flowing in the circuit. The design therefore is a Class
B amplifier, where each half of the differential circuit is in operation for approximately half of each cycle. Simulations have shown that the PA can reach an efficiency of between thirty and forty percent.
The future goals for this project are to check the functionality and performance of the test chip, and compare them to the expected results. The next stage of the design is to add the power control functionality and finish the design of the Power Amplifier so that it conforms to the DECT standard, which is the standard the larger RF Modem project has chosen as a demonstration vehicle.

For portable communication systems based on the digital processing, analog-todigital converters (ADC’s) are needed at the receiver front ends.The key requirement for these ADC’s is the low power dissipation for portable operations due to limited power supply from the battery. Also, to be integrated with digital circuits on the same chip, the ADC must be able to operate with low voltage power supply, typically less than 5V.
The objective of this research project is to design an ADC which can achieve
10bit-resolution at 20MS/sec conversion rate with minimum power consumption with
3.3V power supply and to provide some guidelines for low voltage and low power analog circuit design.
In order to achieve low power, a pipeline architecture is used to eliminate usages of large DC power consuming circuits such as resistor strings and precision comparators, and inter-stage residue amplifiers are optimized to minimize their DC power consumption. As a key building block of this inter-stage residue amplifier, a high-gain fast settling operational amplifier that can operate with 3.3V power supply is designed. The operational amplifier is in two stage configuration with low gain preamp on the first stage for fast settling, and the gain enhancement technique[1] is used to increase the DC gain by 20-30dB. Also, since the digital error correction[2] can tolerate large offset of the comparators in sub ADC of each stage, simple dynamic comparators are used to eliminate static power consumption.
One major problem with low voltage supply is that MOS switches do not function properly due to insufficient gate voltage, and as a result, sampling and transferring the voltage signal becomes difficult. Therefore, a bootstrap technique is used to generate 5V clock waveforms from a 3.3V supply to drive the switches. With this technique, only NMOS switches are needed, and therefore parasitic capacitances from switches are reduced compared to regular CMOS transmission gates.
Cascaded pipeline stages are scaled down to lower the power consumption. This is possible due to reduced requirements on the inter-stage amplifier down the pipeline.
For instance, if each stage of the pipeline resolves 2 bits and the total resolution of the
ADC is 10 bits, the first stage needs to meet the requirement to full 10 bit accuracy, while the next stage needs to meet the requirement only to 8 bit accuracy. Therefore, scaling of the stages to the given requirements reduces considerable amount of power consumption.
An experimental prototype of ADC has been fabricated in a 1.2
µ m CMOS technology. Chip area is 3.2 x 3.3 mm
2
, not including the pad ring. At a 20MS/s conversion rate, 35 mW of power consumption was achieved. The SNDR (signal-tonoise-plus-distortion-ratio) was 59.1 dB for 100kHz sine wave input signal.
Current work is aimed at translating this design concept into 0.6 micron technology to determine the power dissipation attainable at that line width. An

integrated version of the ADC in 0.6um CMOS has been designed and layout. A few changes have been made since the 1.2um version.In particular, an on-chip digital correction algorithm has been implemented and the elimination of gain-boost amplifiers, made possible with the advanced technology, has reduced the power consumption. The active area of the ADC is measured 1.2umx1.2um and the power consumption is estimated to be less than 1mW per MS/s.
[1] K. Bult and G. Geelen, “A Fast-Settling CMOS Op Amp with 90 dB dc-gain and 116MHz Unity Gain Frequency,” Int. Solid-Stage Circuits Conf. Technical Digest, February 1990, pp.108-109.
[2] G. Jusuf and P.R. Gray, A 1-bit/Cycle Algorithmic Analog-to-Digital Converter Without High-Precision Comparators, UC Berkeley Electronics Research Laboratory, Memorandum No. UCB/ERL M90/69, August 1990.
[3] T. Cho and P. R. Gray, “A 10 bit, 20MS/sec, 35mW Pipeline ADC in 1.2 Micron CMOS”, Digest of Papers,
1994 Custom Integrated Circuits Conference, San Diego, CA June 1994

One of the challenges in a portable multi-standard CMOS radio receiver is to design baseband signal processing circuits that are adaptable to different specifications of several wireless communication standards including DECT, GSM, and AMPS.
Baseband analog signal processing here includes channel selection filtering, VGA
(variable gain amplification) with AGC (automatic gain control) before A/D conversion and symbol/timing recoveries plus other controls in DSP. These functions are required to detect a small signal in the presence of strong interferes in a typical wireless communication environment.
For instance, the desired signal after RF section may be ~0.1-1mV in the worst case situation requiring a large signal amplification before a reliable symbol recovery can be performed. However, due to a possible presence of a strong adjacent channel signal, which may be 60dB larger than the desired signal, the output of the amplifier can saturate with a large gain. Therefore, a channel selection filter must be able to suppress the adjacent channel signal during the amplification process to prevent the saturation of the signal path. For different signal amplitude, the gain must be controlled accordingly with an AGC from backend DSP. DC offset voltage correction at the input of the filter is also required to eliminate/suppress the device-mismatchinduced and 1/f-related low frequency offset voltage, especially at high gain setting, to prevent the saturation of the signal at the input of the A/D converter.
Our approach to the baseband filters is to use a switched-capacitor low pass filter for good linearity and programmable gain control. Linearity is an important performance parameter since the signal amplitude varies over 60dB range, and the switched capacitor circuit implementation provides good linearity performance due to its op-amp based closed-loop configuration. Also, the filter gain can be easily programmable by changing the sampling capacitor value with a set of parallel capacitor arrays. Another important advantage is that the filter bandwidth can be programmable by changing the sampling clock frequency, which is particularly desirable for multi-standard capability.
Switched capacitor filters require continuous time anti-aliasing filter in front to reject interfering signal at high frequencies, and designing a low noise, low-distortion filter is also a challenging task. Such a filter again needs to be in closed-loop configuration to obtain large dynamic range, and Sallen-Key configuration is therefore chosen. Offset voltage of the filter section is corrected by the 6bit current DAC which feeds small current to the resistive load of the mixer output.
At the present time, initial design and layout of the both filters and the DAC are complete, and they are under verification process. Key performance parameters include: for Sallen-Key anti-aliasing filter, 3dB frequency of ~2MHz with 5th order low pass filter response and power dissipation of 6mW/channel, and for switched capacitor filter, 4 cascaded biquads with nominal operating sampling frequency of
31MHz with analog power dissipation of 14mW/channel. The gain of the filter is

programmable from 3dB to 51dB in 7 bit binary steps. The test die will be fabricated in
0.6um CMOS technology, and its initial test result should be available by October of
1995.

Current implementations of digital portable communication system receivers use analog filters to select the desired channel followed by a Nyquist rate analog-todigital converter (ADC). To achieve greater programmability in a multi-standard receiver, it would be attractive to select the desired channel using a digital filter. To remove the analog channel-selection filtering entirely would require a wide dynamic range ADC, such as a sigma-delta modulator. The over-sampled ADC would digitize both the desired and undesired channels and remove the undesired channels using a digital decimation filter. An additional benefit of a wide dynamic range ADC is the reduction of AGC requirements in the receive path.
The goal of this work is the realization of a sigma-delta modulator to meet the requirements of such a receiver: 14 bits at 2 MS/s and minimum power dissipation using a 3.3 V supply. To make such a high-speed modulator practical, the oversampling ratio must made as low as possible [1]. We are currently investigating a cascade architecture using three second-order modulators (2-2-2 cascade) with an oversampling ratio of 16. The architecture employs single bit DACs in the first two stages and a three-level DAC in the third stage. The architecture is sensitive to component mismatches which requires calibration of the first inter-stage gain to achieve 14 bit resolution; calibration can be done digitally using the LMS algorithm.
Both system and circuit level techniques are required to reduce power dissipation. At the system level, internal signals throughout the cascade are scaled to maximize their dynamic range. Similar to a pipeline ADC, cascaded stages may be scaled down to reduce power dissipation as the noise shaping of the modulator reduces their required resolution [2]. Circuit level approaches include the use of a twostage rail-to-rail operational amplifiers optimized for minimum power dissipation.
Current work focuses on circuit design of the analog portions of the sigma-delta modulator for fabrication by the end of 1995.
[1] B. P. Brandt and B. A. Wooley, “A 50 MHz Multibit Sigma-Delta Modulator for 12-b 2-MHz A/D COnversion,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 12, December 1991, pp. 1746-1755.
[2] T. B. Cho and P. R. Gray, “A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter,” IEEE Journal of Solid-
State Circuits, Vol. 30, No. 3, March 1995, pp. 166-172.

Substrate Coupling has been identified as one of the sources of interaction amongst devices sharing a common substrate. Noise-generating circuits and circuits requiring a low-noise environment are integrated on the same substrate in mixed analog-digital and highly integrated radio-frequency designs. It is very important in these applications to identify the effects of interaction and find possible solutions at the design stage. In order to do so, it is essential to develop fast simulators, which can be used for layout optimization so as to minimize the effects of the finite-impedance of semiconductor substrates on circuit performance.
The substrate is a distributed impedance. Modeling a large problem involving several hundred to several thousand device-to-substrate contacts is a non-trivial problem. A fast and elegant simulator which uses a combination of the classical Green function techniques and the Fast Fourier Transform algorithm has been developed for this purpose[1]. The simulator generates a lumped equivalent of the distributed impedance, which can be used in traditional circuit simulators such as SPICE. The lumped equivalent can be resistive, for example in silicon up to 2GHz, capacitive or in general complex.
New features are being currently added to the simulator. The first addition is the inclusion of a junction-depth parameter in the simulator, so that individual device junction-depths can be taken into consideration during the simulation. This is done by applying the Taylor-series expansion to the monopole approximation of the exact substrate-contact current distribution. Another improvement to the simulator has been made by combining the technique with efficient partioning algorithms to solve complex substrate problems in nearly O(N) time, with suitable substrate surface partitions. This feature helps to sparsify the transadmittance matrices, which are solved by the circuit simulator and thus reduces circuit-simulation time. In addition to being fast, the technique is memory-efficient as well. Possible applications of the technique in modeling interconnects and inductors need to be investigated.
Several circuit effects of substrate-coupling have been identified. These include noise injection, amplifier noise-figure degradation, change in circuit-bandwidth and the degradation of the quality-factor in components due to substrate power-loss. Isolation techniques to alleviate these problems have been studied.
Guard-rings are a low-cost isolation technique. Extensive simulation has been carried out on guard-rings and layout guidelines for the placement and sizing of guardrings have been developed. Simulations have also been performed to determine the dependence of isolation on substrate doping profiles and on layout in different types of substrates.
DC verification of the substrate models has been carried out by using a teststructure consisting of substrate contacts distributed across the surface of the chip.

Good agreement has been found between the measured and simulated resistance matrices.
[1] "Modeling and Analysis of Substrate Coupling in Integrated Circuits" by R. Gharpurey and R. G. Meyer in the proceedings of the Custom Integrated Circuits Conference, May 2-4, 1995, Santa Clara.

As a medium for short-range, wireless indoor LANs, infrared offers significant advantages over radio [1]. The infrared region represents a vast, unregulated spectrum.
As infrared does not pass through walls, it is possible to operate at least one link in each room of a building without interference, and infrared links are easily secured against eavesdropping. When intensity modulation and direct detection are employed, the short carrier wavelength and large, square-law detector lead to efficient spatial diversity that completely eliminates multipath fading. Infrared links using nondirectional transmitters and receivers are still subject to multipath distortion, which can induce intersymbol interference (ISI) in links operating at bit rates above 10 Mb/s. This intersymbol interference can be mitigated by adaptive equalization, or by use of multiple-subcarrier modulation.
Infrared has some drawbacks as well. Although diffuse, multipath propagation obviates the need for a strict line-of-sight path between the transmitter and receiver, an infrared link is still susceptible to severe shadowing; an infrared receiver cannot be carried in a shirt pocket, for example. Also, infrared links have a limited range, because the noise from ambient light is high, and also because the square-law nature of a directdetection receiver doubles the effective path loss (in dB) when compared to a linear detector. Often, infrared links must employ relatively high transmit power levels.
While the transmitter power level can usually be increased without fear of interfering with other users, transmitter power may be limited by concerns of power consumption and eye safety, particularly in portable transmitters.
Presently, commercially available wireless infrared LANs achieve bit rates as high as 4 Mb/s, over a range of 15 m, and current system designs are extensible to bit rates as high as about 10 Mb/s. Our previous research [1] has suggested that with new link design strategies, bit rates as high as 100 Mb/s should be achievable.

This project is intended to prove the feasibility of high bit-rate infrared links. We have utilized many off-the-shelf components, and no effort has been made to reduce the size or power consumption of the transmitter or receiver. Within the context of the
InfoPad project, a 50-Mb/s infrared link would be well-suited to serve as a downlink.
With time-division-multiplexing, it could convey 25 independent, 2-Mb/s bit streams.
This project received its initial funding from IBM Corporation and the California State
MICRO program. Since June, 1994, it has been funded under the InfoPad grant.
Our experimental 50-Mb/s links uses baseband on-off keying. A block diagram is shown in Figure 3.1-1. The transmitter uses eight laser diodes, whose output is
Diffuser
Laser Diodes
Modulation
Input
Lens
n = 1.78
Interference
Filter
30 nm BW
Silicon p-i-n
Detector
1 cm
2
Area
10-k
Ω
High-
Impedance
Preamplifier
Dominant
Pole
Equalizer
25-MHz
5-pole
Bessel LPF
1.6-MHz
1-pole
HPF
Timing
Recovery
Four-Tap
T/2-Spaced
Transversal
Filter
+
+
Σ
-
Four-Tap
T-Spaced
Transversal
Filter
1.6-MHz
1-pole
LPF
Analog Decision-Feedback Equalizer with Quantized-Feedback
Baseline Restoration
Output
Bits
Figure 3.1-1: Experimental 50-Mb/s infrared communications link.
passed through a translucent Plexiglas diffuser to create an eye-safe second order
Lambertian radiation pattern having 475-mW average power at a wavelength of 806

nm. In typical operation, the transmitter emission is directed upward toward the ceiling, creating a diffuse link configuration.
Light enters the receiver through a hemispherical optical filter attached to a glass hemisphere, permitting us to simultaneously achieve a narrow bandwidth and a wide field of view. The glass hemisphere has an index of refraction of 1.78 and a 2-cm radius.
The optical filter has a center wave length of 815 nm (at normal incidence), a halfpower bandwidth of 30 nm, and a peak transmission of 68%. The filter and lens combination achieves a peak optical gain of 1.8 dB, and a FOV of 65
. The receiver employs a 1-cm
2
; silicon p-i-n detector having a capacitance of 35 pF, followed by a
10-k
high-impedance preamplifier. Even after a passive R-C circuit compensates the resulting 455-kHz pole, the receiver has a transit-time limited 3-dB bandwidth of 23.4
MHz. The preamplifier has an equivalent input noise current density (one-sided) of
5.73 pA/ Hz , averaged over the bandwidth of the 25-MHz Bessel low-pass filter used to provide noise immunity. A high-pass filter is used to combat fluorescent light noise, with quantized feedback (QF) removing the resulting baseline wander. A decisionfeedback equalizer (DFE), constructed using analog tap delay lines and manually controlled tap gains, is used to mitigate multipath-induced intersymbol interference
(ISI).
The system and its components have been extensively tested, and the results compared to theory. Figure 3.1-2 shows the performance of the system in different
10
-2
10
-3
10
-4
50-Mb/s OOK
Diffuse, unshadowed
3.05-m Horizontal Range
10
-5
10
-6
Skylight
10
-7
10
-8
10
-9
No light
Fluorescent light
10
-10
-34.5
-34 -33.5
-33 -32.5
-32 -31.5
-31 -30.5
Average Received Irradiance (dBm/cm
2
)
Figure 3.1-2: Bit-error rate performance of 50-Mb/s infrared link in presence of various types of ambient illumination

types of ambient light. With no background light, a BER of 10
-9
is achieved with a received irradiance of -32.2 dBm/cm
2
. Fluorescent lights increase this value by only
0.1 dB, i.e., their effect is negligible. Bright skylight which causes a DC photo current of
112
A cause the required optical irradiance to increase by 1.5 dB. The DFE yields a reduction of multipath power penalties that is in good agreement with theory. The system achieves a range of 2.9 m at a BER of 10
-7
in a brightly skylit room. Shadowing could be overcome by increasing the source power by approximately 3.5 dB.

As we have proved the basic feasibility of building infrared links at bit rates as high as 50 Mb/s, we are now building an infrared downlink for the InfoPad. Unlike our first-generation 50-Mb/s prototype receiver, the InfoPad portable infrared receiver will be highly integrated, so as to minimize size and power consumption. The InfoPad downlink will operate at a bit rate of 8 Mb/s, so that it will be able to accommodate four 2-Mb/s bit streams by time-division multiplexing.
The base-station transmitter will be diffuse, i.e., it will illuminate an extended area of the ceiling to alleviate the need for a direct line-of-sight transmission path. The transmitter will be implemented using an array of 100 LEDs, emitting an average power of about 2 W at a wavelength near 870 nm. Each LED will be driven by two
BJTs in a differential-pair configuration. On-off-keying (OOK) modulation using biphase pulses will be used because its power spectrum has a null at d.c. This d.c. null will allow the receiver to employ electrical high-pass filtering to remove much of the interference due to fluorescent lights.
The receiver will utilize one to three silicon p-i-n photodiodes, each
5 mm
×
5 mm in size, to convert the received optical intensity into an electrical current.
If multiple photodiodes are used, they will be tilted in different directions to provide angle diversity. To collect sufficient signal power, a hemispherical lens having a refractive index of n = 1.45 will be placed on top of each photodiode, providing an optical gain of approximately n
2
= 2.1. In order to minimize the shot noise induced by ambient light, a band-pass optical filter with a bandwidth of 60 nm will be placed atop the hemispherical lens. The photodiode output will be amplified by a low-noise, wideband transimpedance preamplifier. A transimpedance front end will be used because of its wide bandwidth and large dynamic range. The transimpedance front end design will use a CLC425 operational amplifier, providing a transimpedance gain of 2 k
Ω
and a 3-dB cutoff of 50 MHz. Following the transimpedance front end, a high-pass filter having a cut-on frequency of 8 kHz will eliminate much of the interference due to the fluorescent lights. Using the high-pass filter, the optical power penalty due to the fluorescent lights is predicted to be only 0.28 dB at 8 Mb/s. Following the high-pass filter, the signal will be conditioned by an AGC circuit. The receiver filtering will be implemented partly in analog fashion and partly in the digital domain. The signal will be filtered first by a five-pole Bessel filter having a 3-dB cutoff of 11 MHz, and then digitized using a five-bit A/D converter at a sampling rate of twice the symbol rate, i.e.,
16 MHz. The remainder of the receiver filtering, along with the decision device, will be

implemented using a delay-and-compare digital filter. We are currently working on a digital implementation of the timing recovery circuit.
[1] J.M. Kahn, J.R. Barry, M.D. Audeh, J.B. Carruthers, W.J. Krause, and G.W. Marsh, “Non-Directed Infrared
Links for High-Capacity Wireless LANs”, IEEE Pers. Commun. Mag. vol. 1, no. 2, pp. 12-25, 1994 (Invited
Paper).
[2] G.W. Marsh and J.M. Kahn, “50-Mb/s Diffuse Infrared Free-Space Link Using On-Off Keying with Decision-
Feed back Equalization”, IEEE Photonics Technology Letters, vol. 6, no. 10, October,1994.
[3] G.W. Marsh and J.M. Kahn, “Performance Evaluation of Experimental 50-Mb/s Diffuse Infrared Wireless
Link using On-Off Keying and with Decision-Feedback Equalization”, subm. to IEEE Journal on Selected
Areas in Communications, March, 1995.
[4] G.W. Marsh and J.M. Kahn, “50-Mb/s Diffuse Infrared Free-Space Link Using On-Off Keying with Decision-
Feed back Equalization”, Proceedings of the Fifth International Symposium on Personal, Indoor and Mobile
Communications (PIMRC’94), J.H. Weber, J.C. Arnbak, and R. Prasad, editors, vol. IV, pp. 1086-1089,
Amsterdam, September, 1994. IOS Press (Invited Paper).
[5] G.W. Marsh and J.M. Kahn, “50-Mb/s Diffuse Infrared Free-Space Link Using On-Off Keying with Decision-
Feed back Equalization”, Twenty-Eighth Asilomar Conference on Signals, Systems, and Computers, A. Singh, editor, vol. I, pp. 74-77, Los Alamitos, CA, October, 1994. IEEE Computer Society Press.