CY62256
256K (32K x 8) Static RAM
Functional Description[1]
Features
• High speed: 55 ns and 70 ns
• Voltage range: 4.5V–5.5V operation
• Low active power (70 ns, LL version)
— 275 mW (max.)
• Low standby power (70 ns, LL version)
— 28 µW (max.)
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Package available in a standard 450-mil-wide (300-mil
body width) 28-lead narrow SOIC, 28-lead TSOP-1,
28-lead reverse TSOP-1, and 600-mil 28-lead PDIP
packages
The CY62256 is a high-performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and three-state drivers. This device has an
automatic power-down feature, reducing the power
consumption by 99.9% when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O0 through I/O7) is written into the memory location
addressed by the address present on the address pins (A0
through A14). Reading the device is accomplished by selecting
the device and enabling the outputs, CE and OE active LOW,
while WE remains inactive or HIGH. Under these conditions,
the contents of the location addressed by the information on
address pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Logic Block Diagram
I/O0
INPUTBUFFER
I/O1
512 x 512
ARRAY
I/O2
SENSE AMPS
ROW DECODER
A10
A9
A8
A7
A6
A5
A4
A3
A2
I/O3
I/O4
I/O5
CE
WE
COLUMN
DECODER
I/O6
POWER
DOWN
I/O7
A12
A11
A1
A0
A14
A13
OE
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05248 Rev. *B
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 27, 2002
CY62256
Pin Configurations
Narrow SOIC
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11
DIP
Top View
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
I/O0
I/O1
I/O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A4
A3
A2
A1
OE
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
22
23
21
24
25
26
27
28
1
2
3
4
5
6
7
19
18
17
16
A11
A10
A9
A8
A7
A6
A5
VCC
WE
A4
A3
A2
A1
OE
20
TSOP I
Top View
(not to scale)
15
14
13
12
11
10
9
8
6
1
28
27
26
25
24
23
22
A12
A13
A14
I/O0
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A0
8
9
7
5
4
3
2
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A14
A13
A12
10
11
12
13
14
15
16
17
18
TSOP I
Reverse Pinout
Top View
(not to scale)
19
20
21
DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature .................................–65°C to +150°C
Ambient Temperature with
Power Applied................................................... 0°C to +70°C
Supply Voltage to Ground Potential
(Pin 28 to Pin 14) ........................................... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High-Z State[2] ....................................–0.5V to VCC + 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range
Ambient Temperature
VCC
0°C to +70°C
5V ± 10%
–40°C to +85°C
5V ± 10%
Commercial
Industrial
Electrical Characteristics Over the Operating Range
CY62256−55
Parameter
Description
Min. Typ.[3]
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = −1.0 mA
VOL
Output LOW Voltage
VCC = Min., IOL = 2.1 mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IIX
Input Leakage Current
IOZ
Output Leakage Current GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
Current
ISB1
CY62256−70
Max.
2.4
Min. Typ.[3]
2.4
2.2
Unit
V
0.4
GND < VI < VCC
Max.
0.4
V
VCC
+0.5V
V
VCC
+0.5V
2.2
–0.5
0.8
–0.5
0.8
V
–0.5
+0.5
–0.5
+0.5
µA
+0.5
–0.5
+0.5
µA
28
55
28
55
mA
L
25
50
25
50
mA
LL
25
50
25
50
mA
Automatic CE
Max. VCC, CE > VIH,
Power-down Current— VIN > VIH or VIN < VIL, f = fMAX L
TTL Inputs
LL
0.5
2
0.5
2
mA
0.4
0.6
0.4
0.6
mA
0.3
0.5
0.3
0.5
mA
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
–0.5
Notes:
2. VIL (min.) = −2.0V for pulse durations of less than 20 ns.
3. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions
(TA = 25°C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
Document #: 38-05248 Rev. *B
Page 2 of 11
CY62256
Electrical Characteristics Over the Operating Range (continued)
CY62256−55
Parameter
Description
Automatic CE
Max. VCC, CE > VCC − 0.3V
Power-down Current— VIN > VCC − 0.3V, or VIN <
0.3V, f = 0
CMOS Inputs
ISB2
Min. Typ.[3]
Test Conditions
Indust’l Temp Range
CY62256−70
Max.
Min. Typ.[3]
Max.
Unit
1
5
1
5
mA
L
2
50
2
50
µA
LL
0.1
5
0.1
5
µA
LL
0.1
10
0.1
10
µA
Capacitance[4]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
Max.
Unit
6
pF
8
pF
AC Test Loads and Waveforms
R1 1800 Ω
R1 1800 Ω
5V
5V
OUTPUT
ALL INPUT PULSES
OUTPUT
R2
990Ω
100 pF
INCLUDING
JIG AND
SCOPE
3.0V
R2
990Ω
5 pF
INCLUDING
JIG AND
SCOPE
(a)
90%
10%
90%
10%
GND
< 5 ns
< 5 ns
(b)
Equivalent to:
THÉVENIN EQUIVALENT
639Ω
OUTPUT
1.77V
Data Retention Characteristics
Parameter
Conditions[5]
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
Typ.[3]
Min.
2.0
L
LL
VCC = 3.0V, CE > VCC − 0.3V,
VIN > VCC − 0.3V, or VIN < 0.3V
Chip Deselect to Data Retention Time
Operation Recovery Time
Unit
V
LL Ind’l
tCDR[4]
tR[4]
Max.
2
50
µA
0.1
5
µA
0.1
10
µA
0
ns
tRC
ns
Data Retention Waveform
DATA RETENTION MODE
VCC
3.0V
VDR > 2V
tCDR
3.0V
tR
CE
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. No input may exceed VCC + 0.5V.
Document #: 38-05248 Rev. *B
Page 3 of 11
CY62256
Switching Characteristics Over the Operating Range[6]
CY62256−55
Parameter
Description
Min.
Max.
CY62256−70
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
55
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
55
70
ns
tDOE
OE LOW to Data Valid
25
35
ns
OE LOW to
tHZOE
OE HIGH to High-Z[7, 8]
CE LOW to
Low-Z[7]
tHZCE
CE HIGH to
High-Z[7, 8]
tPU
CE LOW to Power-up
tPD
CE HIGH to Power-down
tLZCE
Write
55
5
Low-Z[7]
tLZOE
70
ns
70
5
5
ns
5
20
5
ns
25
5
20
0
ns
ns
25
0
55
ns
ns
ns
70
ns
Cycle[9, 10]
tWC
Write Cycle Time
55
70
ns
tSCE
tAW
CE LOW to Write End
45
60
ns
Address Set-up to Write End
45
60
ns
tHA
Address Hold from Write End
0
0
ns
tSA
Address Set-up to Write Start
0
0
ns
tPWE
WE Pulse Width
40
50
ns
tSD
Data Set-up to Write End
25
30
ns
tHD
Data Hold from Write End
0
0
ns
tHZWE
tLZWE
WE LOW to
High-Z[7, 8]
WE HIGH to
Low-Z[7]
20
5
25
5
ns
ns
Switching Waveforms
Read Cycle No. 1 [11, 12]
tRC
ADDRESS
tOHA
DATA OUT
PREVIOUS DATA VALID
tAA
DATA VALID
Notes:
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance.
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate
a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.
10. The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
11. Device is continuously selected. OE, CE = VIL.
12. WE is HIGH for Read cycle.
Document #: 38-05248 Rev. *B
Page 4 of 11
CY62256
Switching Waveforms (continued)
Read Cycle No. 2 [12, 13]
tRC
CE
tACE
OE
tHZOE
tHZCE
tDOE
DATA OUT
tLZOE
HIGH IMPEDANCE
HIGH
IMPEDANCE
DATA VALID
tLZCE
VCC
SUPPLY
CURRENT
tPD
tPU
ICC
50%
50%
ISB
[9, 14, 15]
Write Cycle No. 1 (WE Controlled)
tWC
ADDRESS
CE
tAW
tHA
tSA
WE
tPWE
OE
tSD
DATA I/O
NOTE 16
tHD
DATAIN VALID
tHZOE
Write Cycle No. 2 (CE Controlled)
[9, 14, 15]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
WE
tSD
DATA I/O
tHD
DATAIN VALID
Notes:
13. Address valid prior to or coincident with CE transition LOW.
14. Data I/O is high impedance if OE = VIH.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05248 Rev. *B
Page 5 of 11
CY62256
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[10, 15]
tWC
ADDRESS
CE
tAW
WE
tHA
tSA
tSD
DATA I/O
NOTE 16
tHD
DATAIN VALID
tHZWE
tLZWE
Note:
16. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05248 Rev. *B
Page 6 of 11
CY62256
Typical DC and AC Characteristics
1.4
1.0
0.8
0.6
VIN =5.0V
TA =25°C
0.4
1.0
2.0
0.8
0.6
VCC =5.0V
VIN =5.0V
0.4
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
1.3
1.4
AA
1.6
NORMALIZED t
NORMALIZED t AA
25
1.2
1.1
TA =25°C
1.0
0.9
5.5
6.0
1.2
1.0
VCC =5.0V
0.6
−55
25
125
AMBIENT TEMPERATURE (°C)
OUTPUT SOURCE CURRENT (mA)
SUPPLY VOLTAGE (V)
25
105
AMBIENT TEMPERATURE (°C)
0.8
5.0
-0.5
−55
125
NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE
1.4
4.5
VCC =5.0V
VIN =5.0V
AMBIENT TEMPERATURE (°C)
NORMALIZED ACCESS TIME
vs. SUPPLY VOLTAGE
0.8
4.0
1.0
0.0
0.0
−55
6.0
ISB
1.5
0.5
0.2
ISB
0.0
4.0
1.2
2.5
OUTPUT SINK CURRENT (mA)
0.2
3.0
ICC
ISB2 µA
1.2
NORMALIZED I CC
NORMALIZED ICC, I
SB
1.4
ICC
STANDBY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. AMBIENT TEMPERATURE
NORMALIZED SUPPLY CURRENT
vs. SUPPLY VOLTAGE
OUTPUT SINK CURRENT
vs. OUTPUT VOLTAGE
140
120
100
80
60
VCC =5.0V
TA =25°C
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE
120
100
80
VCC =5.0V
TA =25°C
60
40
20
0
0.0
1.0
2.0
3.0
4.0
OUTPUT VOLTAGE (V)
Document #: 38-05248 Rev. *B
Page 7 of 11
CY62256
Typical DC and AC Characteristics (continued)
TYPICAL ACCESS TIME CHANGE
vs. OUTPUT LOADING
30.0
2.5
25.0
2.0
1.5
1.0
20.0
15.0
VCC =4.5V
TA =25°C
10.0
1.00
VCC =5.0V
TA =25°C
VIN =0.5V
0.75
5.0
0.5
0.0
0.0
NORMALIZED I CC vs.CYCLE TIME
1.25
NORMALIZED ICC
3.0
DELTA tAA (ns)
NORMALIZED I
PO
TYPICAL POWER-ON CURRENT
vs. SUPPLY VOLTAGE
1.0
2.0
3.0
4.0
5.0
0.0
0
SUPPLY VOLTAGE (V)
200
400
600
800 1000
0.50
10
CAPACITANCE (pF)
20
30
40
CYCLE FREQUENCY (MHz)
Truth Table
CE
WE
OE
Inputs/Outputs
Mode
Power
H
X
X
High-Z
Deselect/Power-down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High-Z
Deselect, Output Disabled
Active (ICC)
Ordering Information
Speed
(ns)
55
70
Ordering Code
CY62256LL−55SNI
Package
Name
SN28
CY62256LL−55ZI
Z28
CY62256−70SNC
SN28
Package Type
28-lead (300-Mil Narrow Body) Narrow SOIC
Operating
Range
Industrial
28-lead Thin Small Outline Package
28-lead (300-Mil Narrow Body) Narrow SOIC
Commercial
CY62256L−70SNC
CY62256LL−70SNC
CY62256L–70SNI
Industrial
CY62256LL−70SNI
CY62256LL−70ZC
Z28
CY62256LL−70ZI
Z28
CY62256−70PC
P15
CY62256L−70PC
P15
CY62256LL−70PC
P15
CY62256LL−70ZRI
ZR28
Document #: 38-05248 Rev. *B
28-lead Thin Small Outline Package
Commercial
28-lead (600-Mil) Molded DIP
Commercial
Industrial
28-lead Reverse Thin Small Outline Package
Industrial
Page 8 of 11
CY62256
Package Diagrams
28-lead (600-mil) Molded DIP P15
51-85017-A
28-lead (300-mil) SNC (Narrow Body) SN28
51-85092-*B
Document #: 38-05248 Rev. *B
Page 9 of 11
CY62256
Package Diagrams (continued)
28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28
51-85071-*G
28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28
51-85074-*F
All product and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05248 Rev. *B
Page 10 of 11
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62256
Document Title: CY62256 256K (32K x 8) Static RAM
Document Number: 38-05248
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
113454
03/06/02
MGN
*A
115227
05/23/02
GBI
Changed SN Package Diagram
*B
116506
09/04/02
GBI
Added footnote 1.
Corrected package description in Ordering Information table
Document #: 38-05248 Rev. *B
Description of Change
Change from Spec number: 38-00455 to 38-05248
Remove obsolete parts from ordering info, standardize format
Page 11 of 11