Study and methodology for decreasing noise
emissions of DC-DC converters through PCB
layout
Cristián Fuentes Rojas
TWEPP 2010 Aachen, September 2010
Sunday, September 26, 2010
1
Power working group
Introduction
As presented at previous session, studies have been
made to decrease the noise of dc-dc converters.
For being able to decrease the noise through PCB
layout, the sources of noise and paths must be
identified.
The sources are due to the switching nature, and their
amplitude can be identified through Fourier series of
theoretical or measured temporal signals.
Several paths are not in schematics, and must be found
in the real PCB board and2setup.
Sunday, September 26, 2010
Methodology
1. Modeling the DC-DC converter.
2. Enhancing the model with real parameters.
•
Real behavior passive components
•
Stray capacitances between PCB nodes
•
Inductances from PCB traces
•
Couplings between components
3. Identification of key parameters.
4. Improvement of board layout.
3
Sunday, September 26, 2010
Model of a dc-dc buck
converter
Lin
N1
+
Vin
Cin
Sw1
N2
Cin
N3
Sw2
N4
Lout
Cout
N6
4
Sunday, September 26, 2010
L
N5
Cout
Load
Model of a dc-dc buck
converter
Lin
N1
+
Vin
Cin
Sw1
N2
Cin
N3
Sw2
L
N4
Lout
Cout
N5
Cout
Load
N6
The switches will be replaced by AC voltage and current
sources, with the values extracted from the Fourier series of
the temporal signals.
4
Sunday, September 26, 2010
Model of a dc-dc buck
converter
Lin
N1
+
Vin
Cin
N2
Cin
N3
+
I
E
L
N4
Lout
Cout
N5
Cout
Load
N6
The switches will be replaced by AC voltage and current
sources, with the values extracted from the Fourier series of
the temporal signals.
4
Sunday, September 26, 2010
1º Real components
Lin
N1
+
Vin
Cin
Sw1
N2
Cin
N3
Sw2
N4
Lout
Cout
N6
Sunday, September 26, 2010
L
N5
Cout
Load
1º Real components
Lin
N1
+
Cin
Vin
Sw1
N2
Cin
L
N3
N4
Sw2
Real C
CC
LC
RC
Ideal components
Replaced
by
Real components
5
Sunday, September 26, 2010
N5
Cout
N6
C
Lout
Cout
Load
L
Real L
CL
LL
RL
1º Real components
Lin
CL
LL
N1
+
Vin
L
CL
RL
N2
Sw1
N3
LL
RL
N4
LL
RL
N5
CCin
CCout
CCout
LCin
LCin
LCout
LCout
RCin
RCin
RCout
RCout
Cin
Cout
N6
C
Real C
LC
RC
Ideal components
Replaced
by
Real components
5
Sunday, September 26, 2010
CL
CCin
Cin
CC
Lout
Load
Cout
L
Real L
CL
LL
RL
Behavior of real
components
|Z|
Real L
∠Z
-20 dB/decade
20 dB/decade
CL
LL
90º
RL
0º
-90º
20 log RL
RL
2πLL
|Z|
Real C
CC
LC
fo
f
20 dB/decade
f
90º
0º
-90º
20 log Rc
fo
6
Sunday, September 26, 2010
fo
∠Z
-20 dB/decade
RC
RL
2πLL
f
fo
f
First Design Considerations
Careful selection of low ESR&ESL components.
Put capacitors in parallel to decrease total equivalent
series inductance (ESL) of decoupling capacitors.
Proper selection of operation mode:
QSW operation: produces lower amplitude AC input
currents.
Increasing the switching frequency: it reduces the
amplitude of the AC currents source but not the AC
voltage source.
7
Sunday, September 26, 2010
2º Stray capacitances
N1
Vin
Lin
Cin
N3
N2
Sw1
Sw2
Cin
N4
L
Cout
N5
Lout
Load
Cout
N6
Earth
� �
n!
n
=
Nº of capacitances:
k
k! · (n − k)!
� �
7
= 21
2
8
Sunday, September 26, 2010
n: Nºof nodes
k:combinations
Obtaining Stray cap values
Softwares allow:
-Q3D:
Extraction of stray
capacitance values.
-Simplorer:
Sweep their value
through parametric
simulations.
Identify the most
important
capacitances for the
noise.
2.1cm
1.5cm
9
Sunday, September 26, 2010
Identifying critical Stray cap
N1
Vin
Lin
Cin
N3
N2
Sw1
Sw2
Cin
N6
Earth
10
Sunday, September 26, 2010
N4
L
Cout
N5
Lout
Load
Cout
Identifying critical Stray cap
N1
Vin
Lin
Cin
N3
N2
Sw1
Sw2
Cin
N4
L
Cout
N5
Lout
Load
Cout
N6
Earth
Impact mainly on CM noise
10
Sunday, September 26, 2010
Identifying critical Stray cap
Impact mainly on DM noise
N1
Vin
Lin
Cin
N3
N2
Sw1
Sw2
Cin
N4
L
Cout
N5
Lout
Load
Cout
N6
Earth
Impact mainly on CM noise
10
Sunday, September 26, 2010
Identifying critical Stray cap
Impact mainly on DM noise
N1
Vin
Lin
Cin
N3
N2
Sw1
Sw2
Cin
N4
L
Cout
N5
Lout
Load
Cout
N6
Earth
Impact mainly on CM noise
Not surprising that most of them are connected to N3 (phase)
node that develops the highest dV/dt.
10
Sunday, September 26, 2010
Second Design Considerations
Phase node must have the less possible area to
minimize the magnitude of the stray capacitances.
Phase node must be placed as far as possible from input
and output passive components, trying to have the less
electric coupling between them.
11
Sunday, September 26, 2010
3º Inductance of traces
L11 N1
Lin
M11
+
Vin
L12
M12
Cin
Lr11
N2
L22
N3
L34
M22
Lr22
N4
L45
N6 Lr34
Lout
M45
Cout
12
Sunday, September 26, 2010
L
M34
Sw2
Cin
Lr12
Sw1
N5
L55
M55
Cout
Lr45
Load
Lr55
3º Inductance of traces
L11 N1
Lin
M11
+
Vin
L12
M12
Cin
Lr11
N2
L22
N3
L34
M22
Lr22
N4
L45
N6 Lr34
12
Lout
M45
Cout
Self Partial Inductance
Sunday, September 26, 2010
L
M34
Sw2
Cin
Lr12
Sw1
N5
L55
M55
Cout
Lr45
Load
Lr55
3º Inductance of traces
L11 N1
Lin
M11
+
Vin
L12
M12
Cin
Lr11
N2
L22
N3
L34
M22
Lr22
N4
L45
N6 Lr34
Self Partial Inductance
12
Lout
M45
Cout
Mutual Inductance
Sunday, September 26, 2010
L
M34
Sw2
Cin
Lr12
Sw1
N5
L55
M55
Cout
Lr45
Load
Lr55
3º Inductance of traces
L11 N1
Lin
M11
+
Vin
L12
M12
Cin
Lr11
N2
L22
N3
L34
M22
L
N4
M34
Cout
N6 Lr34
Lr22
Self Partial Inductance
Lr11
NET
= Lr11 - M11
SELF
12
Lout
N5
L55
M55
Cout
Lr45
Mutual Inductance
Sunday, September 26, 2010
L45
M45
Sw2
Cin
Lr12
Sw1
Load
Lr55
3º Inductance of traces
L11 N1
Lin
M11
+
Vin
L12
M12
Cin
Lr11
N2
L22
N3
L34
M22
L
N4
M34
L45
Cout
N6 Lr34
Lr22
Lout
M45
Sw2
Cin
Lr12
Sw1
N5
L55
M55
Cout
Lr45
Load
Lr55
Mutual Inductance
Self Partial Inductance
Lr11
NET
= Lr11 - M11
SELF
The net inductance of a loop is the sum of its Net Partial Inductances
12
Sunday, September 26, 2010
Estimating Inductance values
Softwares allow:
-Q3D (EM simulation):
Extraction of self
and mutual
inductance values.
-Simplorer (circuit sim)
Sweep their value
through parametric
simulations
13
Sunday, September 26, 2010
Identify the most
critical inductances
for the noise
Critical Inductances
L11 N1
Lin
M11
+
Vin
L12
M12
Cin
Lr11
N2
L22
N3
M22
L34
Lr22
N4
L45
N6 Lr34
Lout
M45
Cout
14
Sunday, September 26, 2010
L
M34
Sw2
Cin
Lr12
Sw1
N5
L55
M55
Cout
Lr45
Load
Lr55
Critical Inductances
L11 N1
Lin
L12
M11
+
Vin
M12
Cin
Lr11
L22
NET
Sw1
N3
M22
L34
Lr22
& Lr34
NET
N4
L45
N6 Lr34
Lout
M45
Cout
N5
L55
M55
Cout
Lr45
big impact on CM noise
14
Sunday, September 26, 2010
L
M34
Sw2
Cin
Lr12
Lr22
N2
Load
Lr55
Critical Inductances
very low impact
L11 N1
Lin
L12
M11
+
Vin
M12
Cin
Lr11
L22
NET
Sw1
N3
M22
L34
Lr22
& Lr34
NET
N4
L45
N6 Lr34
Lout
M45
Cout
N5
L55
M55
Cout
Lr45
big impact on CM noise
14
Sunday, September 26, 2010
L
M34
Sw2
Cin
Lr12
Lr22
N2
Load
Lr55
Critical Inductances
very low impact
L11 N1
Lin
L12
M11
+
Vin
M12
Cin
Lr11
L22
NET
Sw1
N3
M22
L34
Lr22
& Lr34
NET
N4
L45
N6 Lr34
Lout
M45
Cout
N5
L55
M55
Cout
Lr45
big impact on CM noise
14
Sunday, September 26, 2010
L
M34
Sw2
Cin
Lr12
Lr22
N2
Very low impact
Load
Lr55
Ground bouncing and CM
Far
CM
Close
DM
15
Sunday, September 26, 2010
Third Design Considerations
The return path plane should have the minimum
inductance possible. For that, it is fundamental to use a
dedicated solid copper layer for return currents. This
layer should be as solid as possible.
Reducing the PCB thickness has a good impact on
reducing the Net partial inductance and loop
inductance, as it augments the mutual inductance.
The decoupling capacitor must be as close as possible
from switches or ASIC.
Try to place vias for the control signal out of the path
of the power current.
16
Sunday, September 26, 2010
4º Component’s couplings
CL
LL
CCin
+
Vin
RCin
LL
RL
M
LCin
CL
CL
M
LL
RL
CCout
M
LCin
LCout
M
RCin
RCout
CCin
M
RL
M
CCout
LCout
Load
RCout
Passive components are magnetically coupled between
each other
Not all the couplings included in the drawing for simplicity
17
Sunday, September 26, 2010
Obtaining coupling values
� �
7
Nº of couplings:
= 21 for 7 different components
2
18
Sunday, September 26, 2010
Important parameters
L2
Vin +
L1
1·I
17
L4
+
L3
16 · I
17
I
Noisy components
L6
L5
E
L7
Load
Susceptible components
L3 L4 L5
L1 L2 L6 L7
Couplings between susceptible components are not an issue.
Couplings between noisy components could have impact
Couplings between noisy and susceptible components must
be avoided. (principally with L4)
19
Sunday, September 26, 2010
Fourth Design Considerations
Minimize coupling with main inductor L4. (Topology
and shield)
Minimize coupling between noisy and susceptible
components. (segregation helps)
Just like the main inductor, the loop between the
MOSFET and decoupling capacitors will emit magnetic
field due to the large di/dt input current. Reduce the
size of this loop.
Avoid couplings between susceptible components of
different filters (input/output).
20
Sunday, September 26, 2010
Segregation & Shielding
L1
L2
L5
SMD
C
SMD
C
L4
L6
L7
SMD
C
SMD
C
Quiet components
Noisy components
21
Sunday, September 26, 2010
L3
Segregation & Shielding
L1
L2
L5
SMD
C
SMD
C
L4
L6
L7
SMD
C
SMD
C
Quiet components
L3
Noisy components
Physical segregation and correct orientation of components
have a good impact, and can be improved by shielding the
noisy part
21
Sunday, September 26, 2010
Segregation & Shielding
L1
L2
L5
SMD
C
SMD
C
L4
L6
L7
SMD
C
SMD
C
Quiet components
L3
Noisy components
Physical segregation and correct orientation of components
have a good impact, and can be improved by shielding the
noisy part
21
Sunday, September 26, 2010
Multiple decap of same
value in parallel
If same value, they share the same current
I
n times
I/n
I/n
I/n
CC
CC
CC
LC
LC
LC
RC
RC
RC
Zeq
Zeq
1
L R
=
+ jw +
jw(nC)
n
n
C augments n times, while L & R decrease n times.
22
Sunday, September 26, 2010
Multiple decap of same
value in parallel
If same value, they share the same current
I
n times
I/n
I/n
I/n
CC
CC
CC
LC
LC
LC
RC
RC
RC
Zeq
Zeq
1
L R
=
+ jw +
jw(nC)
n
n
C augments n times, while L & R decrease n times.
This is partially true!! It is just applicable if there is no
magnetic coupling between capacitors.
22
Sunday, September 26, 2010
Two decap of same value in
parallel
CC
Zeq
LC
RC
If k=0
L
Leq =
2
Sunday, September 26, 2010
M
CC
Zeq
1
(L + M ) R
=
+ jw
+
jw(2C)
2
2
LC
The equivalent inductance depends
R
of the coupling, as was stated before.
(L + M )
Leq =
2
�
Where M = k Lc · Lc = k · Lc & −1 ≤ k ≤ 1
C
If k=1
If k=-1
Leq = L
Leq = 0
23
Two decap of same value in
parallel
Case a) k is close to 1
Leq = L
Case b) k is close to -1
Leq = 0
Vias
I
I/2
I/2
SMD
C
SMD
C
I/2
I
Trace
SMD
C
Trace
I/2
SMD
C
Vias
Vias
Return Path
Bad
Sunday, September 26, 2010
Return Path
24
Good
Impact of decap orientations
on CM
Case a) k is close to 1
Leq = 0
I
I/2
I/2
SMD
C
I/2
I
Trace
SMD
C
Trace
I/2
SMD
C
Vias
Vias
Return Path
25
Sunday, September 26, 2010
Vias
SMD
C
Leq = L
Case b) k is close to -1
Return Path
Thanks for your attention
Acknowledgment
!
C. Fuentes is supported by MECESUP-Chile under grant FSM0601
C. Fuentes is supported by (CCTVal) N° FB0821 (2009-2013)
“VALPARAISO CENTER FOR SCIENCE AND TECHNOLOGY”
26
Sunday, September 26, 2010
BACKUP SLIDES
Sunday, September 26, 2010
Sources of noise
IL (t)
B2
N2
N3
L
m1
m2
0
t
�
�
1
m1 − m2
cn =
(1 − e−jnωs ton )
jnωs jnωs T
B1
+
I
m1 > 0
toff
ton
E
m2 < 0
VSw2 (t)
A
N6
A
cn =
(1 − e−jnωs ton )
jnωs T
0
t
ton
toff
ISw1 (t)
�
B2
m1
0
t
1
m1
B1
B2 −jnωs ton
−jnωs ton
cn =
(1 − e
)+
−
e
jnωs jnωs T
T
T
B1
ton
Sunday, September 26, 2010
toff
28
�
CCM vs QSW
Sunday, September 26, 2010
Filtering strategies
Low Impedance source of noise (as Voltage sources)
L
+
E
Lout
+
Cout
E
Cout
High Impedance source of noise (as current sources)
Lin
I
Sunday, September 26, 2010
I
Cin
Cin
Loop and partial inductance
Lloop
Lloop/4
Lloop/2
or
or
Lloop/4
Lloop/2
Lloop/4
Lloop/4
Partial inductance concept is needed, allowing us to define a
unique inductance associated with only part of the loop.
L1
M24
L4
M12~0
M13
Sunday, September 26, 2010
L1 , L3 , L2 , L4
L2
M23~0
L3
Self Partial Inductance
Net Partial Inductance
(L1 − M13 ), (L3 − M13 ), (L2 − M24 ), (L4 − M24 )
Loop is the sum of Net Partial Inductances
Lloop = (L1 − M13 ) + (L3 − M13 ) + (L2 − M24 ) + (L4 − M24 )
k factor for some cases
|k|=0.76
|k|=0.5
|k|=0.5
Leq = L
Leq = 0
Vias
I
I/2
I/2
SMD
C
Trace
SMD
C
SMD
C
I/2
I
Trace
I/2
SMD
C
Vias
Vias
Return Path
No worth it
Sunday, September 26, 2010
Return Path
Worth it
Inductor Couplings
k=0.1
k=0.013
k=0.014
k=0.00023
Sunday, September 26, 2010
Inductor/Cap coupling
k=0.08
Sunday, September 26, 2010
k=0.067
k=0.012
Measurement conducted EMI
Spectrum
Analyzer
LISN
LISN
Current
Probe
DC/DC
Sunday, September 26, 2010
LISN
Power
Supply
Power
Supply
Measurement conducted EMI
Spectrum
Analyzer
LISN
LISN
Current
Probe
DC/DC
Sunday, September 26, 2010
LISN
Power
Supply
Power
Supply