FlexRay Communications System
Electrical Physical Layer
Version 2.1
Revision B
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Application Notes
FlexRay Electrical Physical Layer Application Notes
Disclaimer
DISCLAIMER
This specification as released by the FlexRay Consortium is intended for the purpose of information only. The
use of material contained in this specification requires membership within the FlexRay Consortium or an
agreement with the FlexRay Consortium. The FlexRay Consortium will not be liable for any unauthorized use of
this Specification.
All details and mechanisms concerning the bus guardian concept are defined in the FlexRay Bus Guardian
Specifications.
The FlexRay Communications System is currently specified for a baud rate of 10 Mbit/s. It may be extended to
additional baud rates.
No part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical,
including photocopying and microfilm, without permission in writing from the publisher.
The word FlexRay and the FlexRay logo are registered trademarks.
Copyright © 2004-2006 FlexRay Consortium. All rights reserved.
Editor Chapter 1 - 2:
Bernd Elend, NXP Semiconductors
Editor Chapter 3
Harald Gall, Austria Microsystems
The Core Partners of the FlexRay Consortium are BMW AG, DaimlerChrysler AG, Freescale Halbleiter
Deutschland GmbH, General Motors Corporation, Philips GmbH, Robert Bosch GmbH, and Volkswagen AG.
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Following the completion of the development of the FlexRay Communications System Specifications commercial
exploitation licenses will be made available to End Users by way of an End User's License Agreement. Such
licenses shall be contingent upon End Users granting reciprocal licenses to all Core Partners and non-assertions
in favor of all Premium Associate Members and Associate Members.
FlexRay Electrical Physical Layer Application Notes
Table of contents
Table of contents
CHAPTER 1 INTRODUCTION ..................................................................................................................... 5
1.1 Objective............................................................................................................................................... 5
1.2 References ........................................................................................................................................... 5
1.3 Revision history .................................................................................................................................... 5
1.4 Open issues.......................................................................................................................................... 5
1.6 List of abbreviations.............................................................................................................................. 6
1.7 Notational conventions ......................................................................................................................... 7
1.7.1 Parameter prefix conventions ......................................................................................................... 7
CHAPTER 2 APPLICATION NOTES ........................................................................................................... 8
2.1 Application hint: Cable impedance ....................................................................................................... 8
2.2 Selection hint: Connectors.................................................................................................................... 9
2.3 Application hint: Split termination ....................................................................................................... 10
2.4 Application hint: Common mode chokes ............................................................................................ 11
2.5 Application hint: Exemplary cable shield connection ......................................................................... 12
2.6 Application hint: Network topology layout........................................................................................... 13
2.6.1 Examples for linear passive bus topologies.................................................................................. 14
2.6.2 Example for passive star topologies ............................................................................................. 14
2.7 Application hint: Termination concepts............................................................................................... 15
2.7.1 Termination concept for point to point connections ...................................................................... 15
2.7.2 Termination concept for passive star topologies .......................................................................... 15
2.7.3 Termination concept for passive linear bus topologies................................................................. 15
2.7.4 Termination in hybrid topologies ................................................................................................... 15
2.8 Application hint: Passive star - impedance adjustment...................................................................... 16
2.9 Application hint: AC busload test........................................................................................................ 18
2.10 Application hint: Increased ESD protection ...................................................................................... 19
2.11 Application hint: Propagation delay .................................................................................................. 20
2.12 Application hint: Host Software / ECU control .................................................................................. 20
2.13 Application hint: Operation at low voltage on VBAT ........................................................................... 20
2.14 Application hint: Protocol relevant parameters................................................................................. 21
CHAPTER 3 EXAMPLE CALCULATION FOR SYSTEM TIMING CONSTRAINTS................................. 22
3.1 Objective............................................................................................................................................. 22
3.2 Description of constraints given by [PS05]......................................................................................... 22
3.3 Contribution of the bus driver ............................................................................................................. 25
3.3.1 Transmitter .................................................................................................................................... 25
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1.5 Terms and definitions ........................................................................................................................... 6
FlexRay Electrical Physical Layer Application Notes
Table of contents
3.3.2 Receiver ........................................................................................................................................ 26
3.4 Asymmetric delays caused by the ECU ............................................................................................. 27
3.5 Requirements for the maximum network (passive star topology) ...................................................... 27
3.7 Requirements for components in the scope of FlexRay specification ............................................... 31
3.7.1 Oscillator Tolerance ...................................................................................................................... 31
3.7.2 Sending Communication Controller with PLL ............................................................................... 32
3.7.3 Sending Communication Controller without PLL .......................................................................... 32
3.7.4 Interface between Communication Controller and Bus Driver...................................................... 32
3.7.5 Non-monolithic Active Star devices .............................................................................................. 32
3.7.6 Example calculation maximum network and worst case EM interferences.................................. 32
3.7.7 Receiving Communication Controller with PLL ............................................................................ 35
3.7.8 Receiving Communication Controller without PLL (1 edge) ......................................................... 35
3.7.9 Receiving Communication Controller without PLL (2 edges) ....................................................... 35
3.7.10 Requirements for Bus Driver to handle the worst case .............................................................. 35
3.7.11 Requirements for Communication Controller to handle the worst case ..................................... 36
3.8 How to calculate different topologies.................................................................................................. 37
3.9 Conclusion with respect to topologies ................................................................................................ 38
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3.6 Asymmetric delays due to EMI jitter on different topologies .............................................................. 28
3.6.1 EMC calculation method ............................................................................................................... 29
3.6.2 Calculation example of electro-magnetic-interferences................................................................ 30
3.6.3 Glitches ......................................................................................................................................... 30
FlexRay Electrical Physical Layer Application Notes
Chapter 1: Introduction
Chapter 1
Introduction
1.1 Objective
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The objective of this document is to collect valuable information that shall help to implement FlexRay systems.
The content of this document is informative and not normative.
1.2 References
[EPL06] FlexRay Communications System - Electrical Physical Layer Specification, v2.1 Revision A,
FlexRay Consortium, November 2006
[EMC05] FlexRay Communications System - Physical Layer EMC Measurement Specification, v2.1.,
FlexRay Consortium, December 2005
[PS05] FlexRay Communications System - Protocol Specification, v2.1 Revision A,
FlexRay Consortium, December 2005
1.3 Revision history
v2.1 rev A
E-PL application notes v2.1 errata sheet rev. 4.
v2.1 rev B
E-PL application notes v2.1 rev A + errata sheet 2 rc 4
1.4 Open issues
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FlexRay Electrical Physical Layer Application Notes
Chapter 1: Introduction
1.5 Terms and definitions
FlexRay specific terms and definitions are listed in [PS05].
BD:
Bus Driver
BG:
Bus Guardian
BSS:
Byte Start Sequence
CC:
Communication Controller
CE:
Communication element
ECU:
Electronic Control Unit
SPI:
Serial peripheral interface
TSS:
Transmission Start Sequence
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1.6 List of abbreviations
uVBAT: Means a voltage applied at the VBAT pin relative to ground of the semiconductor device
uVECU: Means a voltage applied at the battery connector of an ECU relative to ground
X:
Don’t care
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FlexRay Electrical Physical Layer Application Notes
Chapter 1: Introduction
1.7 Notational conventions
<variable>
::= <prefix_1> [<prefix_2>] Name
<prefix_1>
::= a | c | v | g | p
<prefix_2>
::= d | l | n | u
Naming
Convention
Information Type
Description
a
Auxiliary
Parameter
Auxiliary parameter used in the definition or derivation of other
parameters or in the derivation of constraints.
c
Protocol Constant
Values used to define characteristics or limits of the protocol.
These values are fixed for the protocol and cannot be changed.
v
Node Variable
Values which will be changed depending on time, events, etc.
g
Cluster Parameter
Parameter that must have the same value in all nodes in a cluster.
p
Node Parameter
Parameter that may have different values in different nodes in the
cluster.
-
Prefix 1 can be omitted
This table is mirrored from [PS05], where the binding definitions are made!
Table 1-1: Prefix 1.
Naming
Convention
Information Type
Description
d
Time Duration
Value (variable, parameter, etc.) describing a time duration, the
time between two points in time
l
Length
Physical length of e.g. a cable
n
Amount
Number of e.g. stubs
u
Voltage
Differential voltage between two conducting materials (e.g. copper
wires)
The prefixes “l”, “n” and “u” are defined binding here. For all other prefixes refer to [PS05].
Table 1-2: Prefix 2.
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1.7.1 Parameter prefix conventions
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
Chapter 2
Application Notes
With a differential mode impedance in the range of [80 .. 110] Ω an optimum matching with the defined DC bus
load (see [EPL06]) can be achieved. Mismatches between DC bus load and cable impedance may be
intentionally applied, but need to be checked application specific.
The figure below shows the equivalent input circuit of a symmetric shielded two-wire transmission line.
The differential input impedance calculates to Z0 = (2 × Z) || Z12
Z
Z12
Z
ground
Z12
Z
Z
Figure 2-1: Cable impedance
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2.1 Application hint: Cable impedance
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
2.2 Selection hint: Connectors
This selection hint note does not prescribe certain connectors for FlexRay systems.
However, some recommendations are given:
Description
lContactDistanceBP-BM
Contact distance (*)
lContactMetal
Distance between outer metal parts and
center of contact
lECUCoupling
∆Z
Typ
Unit
≤ 4.5
mm
≥2
mm
Length of connector to control unit (**)
≤ 75
mm
Allowed impedance change per centimeter
< 50
Ω
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Name
(*) adjacent chambers shall be used
(**) to be measured from end of the twisted area in cable to PCB housing
Table 2-1: Connector parameters.
See also the section about connectors in [EPL06].
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FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
2.3 Application hint: Split termination
In order to achieve a better EMC performance, it is recommended to make use of a so-called split termination in
all ECUs, where the Termination resistance RT is split into two equal parts RTA and RTB.
ECU
BP
RTA
C1
R1
RTB
BM
Figure 2-2: ECU with split termination.
The serial RC combination (R1;C1) at the center tap of the split termination provides a termination to GND for
common mode signals. R1 is preferably omitted. Typical values are given in the following table:
Name
Description
Typ
Unit
R1
Resistor
< 10
Ω
C1
Capacitor
4700
pF
2 × |RTA - RTB| / (RTA + RTB)
Matching of termination resistors
≤2
%
Table 2-2: Termination parameters.
For RTA and RTB the use of 1% tolerated resistors leads to a matching of 2%; see table above.
The better the matching of the split termination resistors RTA and RTB , the lower the electromagnetic emission.
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BD
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
2.4 Application hint: Common mode chokes
To improve the emission and immunity performance, a common mode choke may be used. The function of the
common mode choke is to force the current in both signal wires to be of the same strength, but opposite
direction. Therefore, the choke represents high impedance for common mode signals. The parasitic stray
inductance should be as low as possible in order to keep oscillations on the bus low. The common mode choke
shall be placed between transceiver and split termination. The following figure shows how to integrate the
common mode choke in presence of a split termination.
BP
RTA
BD
C1
R1
RTB
BM
Figure 2-3: ECU with split termination and common mode choke.
The following table lists the recommended characteristics of common mode chokes in FlexRay networks:
Name
Description
Typ
Unit
RCMC
Resistance per line
LCMC
Main inductance
≥ 100
µH
Lσ
Stray inductance
<1
µH
≤1
Ω
Table 2-3: Common mode choke characteristics.
First field experience has shown that the maximum common mode attenuation should be achieved in the
frequency range from 20…50MHz.
Mind that in case the stray inductance exceeds a certain application specific limit, a sending node sees activity
on the bus temporarily immediately after stopping its own transmission. I.e. when last transmitted bit was
Data_1, then a Data_0 can be read and vice versa.
Up to 5 bit-times low at RxD after frame end sequence (FES) may occur, when a common mode choke is used.
When no common mode choke is used the last transmitted bit may be prolonged by up to 4 bit-times (=idle
reaction time) at RxD.
Chokes with bifilar winding have shown good results, since coupling factor is high and thus stray inductance low.
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ECU
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
The maximum mechanical overall dimensions should not exceed the limits listed below:
Name
Description
Min
Max
Unit
H
Height
5.2
mm
W
Width
6.0
mm
L
Length
10.0
mm
Table 2-4: Maximum mechanical dimensions.
The following figure shows an exemplary cable shield connection. It is also assumed that the connectors are
shielded, thus the shielding is not interrupted between two ECU housings.
Node n
CS
Node m
RS
Figure 2-4: Exemplary cable shield connection.
The short-circuited shield could cause resonances. Additional circuits to damp these resonances are up to the
application.
Name
Description
RS
Damping resistance
CS
Capacitance
Typ
Unit
1000
Ω
470
nF
Table 2-5: Shield connection - damping circuit.
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2.5 Application hint: Exemplary cable shield connection
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
2.6 Application hint: Network topology layout
Recommendations that are listed here should be followed when topologies are planned in order to increase the
chance to find a reasonable termination concept, so that the recommended eye-diagram at TP4 can be met for
possible combinations of sending and receiving nodes.
Name
Description
Min
lBus
Length of a point-to-point connection
Max
Unit
24
m
Name
Description
Min
lStubN + lStubM
Cable length between any two ECUs
nStubs
Number of stubs
Max
Unit
24
3
m
22
Table 2-7: Parameters of a passive star.
Name
Description
Min
lBus
Electrical distance between two ECUs in
the system
nStub
Number of stubs
Max
Unit
24
4
m
22
Table 2-8: Parameters of a linear passive bus structure.
Name
Description
Min
Max
Unit
lStarStar
Electrical distance between two active stars
24
m
lActiveStarN
Length of a branch from ECU N to the star
24
m
Table 2-9: Limitations of active star networks.
- Avoid "stubs on stubs". A splice shouldn't be connected to more than two other splices.
- Keep the cumulative cable length as short as possible. Avoid ΣlStubi + ΣlSpliceDistancei,j > 24m.
- Connect ECUs that are optional to a separate branch of an active star to avoid not terminated cable ends.
- Apply a split termination to each ECU.
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Table 2-6: Parameters of point to point connection.
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
2.6.1 Examples for linear passive bus topologies
Number of stubs nStubNodes
Bus length lBus
Length of lStub
6
12 m
2× 2m + 2× 1m
All ECUs with equal termination resistor value. Preliminary experimental results.
Table 2-10: Practical limitations of a linear passive bus.
Number of nodes nStarNodes
Length of lStub
6
<< 4m
5
6m
4
12m
3
12m
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2.6.2 Example for passive star topologies
All ECUs with equal termination resistor value. Preliminary experimental results.
Table 2-11: Practical limitations of a passive star topology.
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FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
2.7 Application hint: Termination concepts
2.7.1 Termination concept for point to point connections
Both cable ends are terminated with a resistor that has a resistance equal to the nominal cable impedance.
Limitations of cable impedance and DC busload are given in [EPL06].
2.7.2 Termination concept for passive star topologies
2.7.3 Termination concept for passive linear bus topologies
At those two nodes that have the maximum electrical distance on the bus, the cable ends are terminated with a
resistor that has a resistance equal or slightly higher to the nominal cable impedance. At all other nodes a high
ohmic split termination (e.g. 2x 1300Ω + 4.7nF) should terminate the cable. Limitations of cable impedance and
DC busload are given in [EPL06].
2.7.4 Termination in hybrid topologies
To each sub-section, the termination concept is chosen as outlined in the sections above.
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At those two nodes that have the maximum electrical distance over the passive star, the cable ends are
terminated with a resistor that has a resistance equal or slightly higher to the nominal cable impedance. At all
other nodes a high ohmic split termination (e.g. 2x 1300Ω + 4.7nF) should terminate the cable. Limitations of
cable impedance and DC busload are given in [EPL06].
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
2.8 Application hint: Passive star - impedance adjustment
Passive star topologies tend to reflections at their low resistive center. To avoid this, ferrite cores can be used for
increasing the impedance for high frequencies. Their selection is specific to the application.
Ferrite cores
BP
BM
BP
Optimized
RF impedance
BP
BM
Figure 2-5: Ferrite cores on each wire at a passive star.
BP
BM
This impedance adjustment might be also achieved by discrete components:
L1
optimized RF
impedance
R1
1st branch of the passive star
L1
R1
L1
optimized RF
impedance
R1
last branch of the passive star
L1
R1
Figure 2-6: Discrete elements for impedance adjustment at a passive star (no cable shield).
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BM
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
BP
BM
Shield
or, in case a cable shield is used in the system:
1st branch of the passive star
L1
R1
optimized RF
impedance
R1
L2
R3
R2
C1
L1
R1
optimized RF
impedance
L1
last branch of the passive star
R1
L2
R2
Figure 2-7: Discrete elements for impedance adjustment at a passive star (with cable shield).
Name
Description
Typ
Unit
R1
Series resistance at signal wire
22
Ω
L1
Series inductance at signal wire
220
nH
R2
Resistance at cable shield
100
Ω
L2
Inductance at cable shield
220
nH
R3
Resistance at shield to system ground
C1
Capacitance to system ground
1
100
MΩ
nF
Table 2-12: Typical values components for impedance adjustment.
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L1
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
2.9 Application hint: AC busload test
The figure 2-8 shows a load dummy that can be connected to TP2 for further investigations.
TP2
Stimuli on TxD
„0001000"
„1110111"
(100ns/bit)
18Ω
1 µH
330 nH
Transmission line
S1
Z = 90 Ω
1
τLtg = 9ns
αDC > -0.015dB
91Ω
91Ω
100 pF
α30MHz > -0.5dB
α100MHz > -1.4dB
α200MHz > 2.7dB
2
1 µH
58Ω
1 µH
330 pF
58Ω
Switch S1 is in default position ´1´, when the BD under test has a termination resistor; otherwise S1 is in position ´2´
Figure 2-8: AC busload dummy.
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BD under test
inclusive
termination
network
58Ω
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
2.10 Application hint: Increased ESD protection
To increase ESD protection capabilities of the ECU additional suppressor diodes can be applied. In the
equivalent schematic, those diodes appear as capacitive loads. Thus the capacitances CBP and CBM to GND
reflect the capacitive load from ESD protection devices.
The CDiff shown in figure 2-8 is not a concrete component; it’s the visualization of the resulting capacitive load
comprising the CBP, CBM and the input capacitance of the BD.
ECU
CBP
RTA
BD
CDiff
C1
RTB
R1
BM
CBM
Figure 2-9: Node with split termination and additional ESD protection devices.
Name
Description
Typ
Unit
CBP
Capacitance of BP to GND
< 50
pF
CBM
Capacitance of BM to GND
< 50
pF
CDiff
ECU’s differential input capacitance
< 40
pF
Hint: Capacitances to be measured at test frequency ftest = 5MHz.
Table 2-13: Capacitive load.
The ESD capacitances CBP and CBM should match as close as possible for EMC reasons.
Mind that resonances might appear when CBP and CBM are present; e.g. the common mode choke could be able
to damp the resonances.
For the split termination circuit formed by C1, R1 and RT see section 2.4 of this document.
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BP
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
2.11 Application hint: Propagation delay
The actual propagation delay influences the performance of the FlexRay system. An estimate of this influence
can be made by using the equations given in [PS05].
The following rules of thumb can be derived:
•
Minimize max { dPropagationDelayM,N } in order to achieve an optimum efficiency of the dynamic part
and short interslot gaps.
•
Minimize the difference [max { dPropagationDelayM,N } - min { dPropagationDelayM,N }] in order to
achieve an optimum precision of clock synchronization.
The application controller (host) has to ensure that the BD enters BD_Normal mode, before the CC enters one of
its states where the CC starts to listen to the channel.
In case the host commands BD_Normal and the BD does not enter BD_Normal, an error is indicated at the BD
host interface. In this case the host shall force the CC to step back to a non listening state.
The reason for this is that as long as the BD is not in BD_Normal mode, no information about the status of the
channel is available via the signals RxD and RxEN.
When shutting down the ECU, the host shall command the BD into a low power mode before commanding the
CC into a state, where the CC does not evaluate the RxD signal. This is to ensure that the CC does not miss any
communication element on the channel. Mind that the BD does not necessarily react on traffic when in a low
power mode.
For more information see [PS05], especially those sections that deal with Wake-up and Start-up.
2.13 Application hint: Operation at low voltage on VBAT
In case communication is required during crank then sufficient bypass capacitance is expected to be existent at
BD’s supply voltage pins. This applies specially to conditions as specified in ISO7637 part 1 - Testpulse 4
maximum severity level. Mind that the BD may enter a low power mode, when uVECU becomes less than 6.5V.
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2.12 Application hint: Host Software / ECU control
FlexRay Electrical Physical Layer Application Notes
Chapter 2: Application Notes
2.14 Application hint: Protocol relevant parameters
Name
Description
Min
Max
Unit
dFrameTSSTruncation0ASM,N
Truncation on a path without active stars
from node module M to node module N
100
450
ns
dFrameTSSTruncation1ASM,N
Truncation on a path with one active star
from node module M to node module N
200
900
ns
dFrameTSSTruncation2ASM,N
Truncation on a path with two active stars
from node module M to node module N
300
1350
ns
Table 2-14: TSS Truncation.
Name
Description
Min
Max
Unit
dSymbolLengthChange0ASM,N
Change of length of a symbol on a path
without active stars from node module M
to node module N
-400
300
ns
dSymbolLengthChange1ASM,N
Change of length of a symbol on a path
with one active star from node module M
to node module N
-800
600
ns
dSymbolLengthChange2ASM,N
Change of length of a symbol on a path
with two active stars from node module
M to node module N
-1200
900
ns
A negative value means that the symbol is shortened, a positive value means the symbol is elongated.
Table 2-15: Symbol length change.
Mind that the minimum and maximum values in both tables do not take jitter caused by EMC effects into
account.
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For calculating several protocol parameters the knowledge about the truncation and symbol length change is
necessary. Relevant values are given in the tables below.
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
Chapter 3 EXAMPLE CALCULATION FOR SYSTEM
TIMING CONSTRAINTS
A lot of influences onto a vehicle network results from external sources or at least cannot be avoided by the
FlexRay network components. Therefore these effects may cause disturbances on the network and need to be
considered during designing a FlexRay network. As the most of these influences are directly depending on
physical environments like vehicles design, harness routing etc. this chapter shows some of the variable impacts
on the FlexRay network and how to evaluate the effects on the system. The intention is to give advices to the
designer of a FlexRay system due to the most of the values are based on assumptions and experiences but
anyhow may vary in a certain range on environmental variables from the FlexRay Electrical Physical Layer point
of view.
Effects, influences and variables in the scope of FlexRay are discussed in the Electrical Physical Layer
Specification and will not be discusses herein. Some of the FlexRay system parameters are used in this
document for making exemplary worst case calculations.
3.2 Description of constraints given by [PS05]
The propagation of a signal through a FlexRay network introduces certain types of distortions in the signal. In
particular, various mechanisms cause the relationships between edges present in the received bitstream to differ
from the ideal. These changes can cause improper decoding of certain messages in a FlexRay network.
The decoding algorithm specified in [PS05] is able to tolerate a certain amount of variation in the position of
edges in the received waveform. This section briefly investigates the capabilities of the decoding algorithm with
respect to modifications in the positions of edges. The following information contains an overview of the
encoding and decoding mechanisms in the FlexRay protocol. Details of these mechanisms are defined in
[PS05].
The data in a FlexRay frame is represented as a series of extended byte sequences. Each extended byte
sequence consists of a two bit Byte Start Sequence (BSS) followed by eight data bits. If the extended byte
sequence is the last of the message it is followed by a two-bit Frame End Sequence (FES). If the extended byte
sequence is not the last of a message it is followed by the BSS of the next extended byte sequence.
The form of the BSS is fixed – it consists of one bit at logical “1” followed by one bit at logical “0”. As a result, the
BSS always contains a 1-0 transition. This transition is known as the logical “falling edge” of the BSS, even
though the actual voltages present on the physical media are not necessarily falling. The form of the FES is also
fixed – it consists of one bit at logical “0” followed by one bit at logical “1”. As a result, it is also possible to
consider the 0-1 of the FES as a logical “rising edge” in the FES.
The encoding and decoding processes in FlexRay are based on samples. The protocol defines a constant,
cSamplesPerBit, that identifies the number of samples in a nominal bit. In particular, each bit is defined as
exactly 8 samples. A transmitter sending a sequence of bits would generate 8 sample periods at logical “0” for
each “0” bit in the bit stream, and 8 samples periods at logical “1” for each “1” bit in the bit stream. At a nominal
bit rate of 10 Mbit/s, a nominal bit represents 100 ns and each nominal sample represents 12.5 ns. The sample
clock in a specific node is derived from local clocks in the nodes, i.e., there is no synchronization of the rate or
offset of the sample clocks in the various nodes.
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3.1 Objective
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
At the start of each extended bit sequence the decoding algorithm performs a resynchronization of the sample
counter on the falling edge of the BSS. When enabled, a falling edge detection algorithm looks for a 1-0
transition in the incoming sample stream by detecting a situation where the current sample was a “0” while the
previous sample was a “1”. When it sees this condition it assumes that a falling edge occurred somewhere
between the two samples, and the sample counter is resynchronized such that the first “0” sample is considered
to be the first sample of the low bit of the BSS. This is actually done by changing the sample counter to 2 for the
sample following the first “0” sample. In this way, the detection of the falling edge of the BSS resynchronizes the
receiver’s sample counter to the falling edge, which in turn sets up the timing for making the bit decisions of all
subsequent bits of the extended byte sequence. This is done by having the resynchronized sample counter
count in a sequence that runs from 1-8, starting again at 1 after it has reached 8. Each transition of the sample
counter from 8 to 1 corresponds to a bit boundary – for example, the first 8 – 1 transition occurs at the end of the
low bit of the BSS, the second 8 – 1 transition occurs at the end of the first bit of the data portion of the extended
byte sequence, etc. It is possible to think of the resynchronization of the sample counter as setting up an
“expectation” of the position of the boundaries between bits based on the occurrence of the falling edge in the
BSS.
Bit decisions are made in the decoder by “strobing” the sample value each time the sample counter is equal to
the constant cStrobeOffset, which is equal to 5. In other words, the decoding algorithm decides that the value of
a particular bit is whatever the sample value is when the sample counter equals 5. This technique is repeated,
first strobing the value of the low bit of the BSS and then strobing each of the eight bit values in the data portion
of the extended byte sequence. An illustration of the resynchronization and strobing process is shown in Figure
Figure 3-1.
BSS “1”
BSS “0”
1st Bit
X X X
2nd Bit
3rd Bit
1 2 3 4 5 6 7 8
X 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
Bit strobed as 0
at sample 5
Bit strobed as 0
at sample 5
4th Bit
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
Bit strobed as 1
at sample 5
Bit strobed as 0
at sample 5
1 2 3
Bit strobed as 1
at sample 5
Resynchronization
Figure 3-1: Ideal resynchronization and strobing.
As mentioned previously, the transmission and reception processes have various distortions that, in effect,
change the relative positions of edges within the received data stream. As the bit decisions are made using a
sample clock that is resynchronized to the falling edge of the BSS, it is possible to consider these distortions in
bit edge position as representing edges that are either earlier or later than expected based on the occurrence of
the falling edge of the BSS.
How can the existence of early or late edges affect the decoding process? It is possible that if an edge is early or
late by a significant amount that the strobe point will no longer result in a correct bit decision. Consider first the
case where a bit has a different value than the bit that follows it in the bit sequence. This implies that there is an
edge that occurs at the end of the first bit. If the position of the edge between the first and second bits moves
earlier by a large amount it is possible that the strobe point of the first bit will actually strobe the value of the
second bit.
Next consider the case where a bit has a different value than the bit that precedes it in the bit sequence. Again,
this implies that there is an edge that occurs at the end of the first bit. If the position of the edge between the first
and the second bit moves later by a large enough amount it is possible that the strobe point of the second bit will
actually strobe the value of the first bit. In both cases, the bit decision will be wrong, resulting in an error in the
frame, causing the frame to be lost.
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Receiving nodes also use a sample clock, again running at 8 times the nominal bit rate, to sample the incoming
waveform. These samples are examined by the decoding algorithm, which makes bit decisions from the
sequence of samples. The samples within a particular bit are numbered from 1 through 8.
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
In the ideal case edges should occur 8n sample times after the falling edge of the BSS, where n is an integer
from 1 – 10 representing the number of bits. For example, the edge at the end of the low bit of the BSS (if such
an edge is present), which represents the n = 1 case, should be exactly 8 samples times later than the falling
edge of the BSS. Similarly, the rising edge of the FES (the n = 10 case), should be exactly 80 sample times after
the falling edge of the BSS.
A logical question related to the ability of the decoder to track such variations in edge position is to identify the
smallest possible edge position deviation that could result in an incorrect bit decision. If the actual amount of
deviation is less than this amount then there will be no decoding error for that bit. If the deviation in edge position
is larger than this amount then decoding errors are possible.
The worst case (i.e., the smallest early deviation from ideal that could result in such an error) would happen
when the falling edge of the BSS occurs the instant after the sample of the last “1” prior to bit resynchronization
and when the edge between the bits occurs the instant before the sample counter becomes equal to 5 for the bit
in question. The distance between the two edges in this case is 8(n-1) + 5 = 8n – 3 sample times. As the
“expected” distance between the edges is 8n sample times, this represents an edge that is 3 sample times
earlier than expected. In other words, the decoding mechanism can tolerate edges that are up to 3 samples
earlier than expected. An example for n = 4 is shown in Figure 3-3.
BSS “1”
BSS “0”
Ideal
Waveform
1st Bit
2nd Bit
3rd Bit
4th Bit
8n = 32 sample times
Edge early by
3 sample times
8n - 3 = 29 sample times
X X
6 7 8 1 2 3 4 5 6 7 8 1
Distorted X X 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5
Waveform
Bit strobed as 0
at sample 5
Bit strobed as 0
at sample 5
Bit strobed as 0
at sample 5
Bit strobed as 1
at sample 5
ERROR
Resynchronization
Figure 3-2: Example of early edge for n = 4.
Consider next the situation where an edge is later than expected. In this situation an error can occur if the bit
before the bit of interest has the opposite value and the edge between the bits is late enough that the sample
counter becomes equal to 5 before the edge is observed.
The worst case (i.e., the smallest late deviation from ideal that could result in such an error) would happen when
the falling edge of the BSS occurs the instant before the sample of the first “0” that causes edge
resynchronization and when the edge between the bits occurs the instant after the sample counter becomes 5
for the bit in question. The distance between the two edges in this case is 8(n – 1)+ 4 = 8n – 4 sample times. As
the “expected” distance between the edges is 8(n – 1) sample times, this represents an edge that is 4 sample
times later than expected. In other words the decoding mechanism can tolerate edges that are up to 4 samples
later than expected. An example for n = 4 is shown in Figure 3-3.
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Consider first the situation where an edge is earlier than expected. In this situation an error can occur if the bit
following the bit of interest has the opposite value and the edge between the bits is early enough that the sample
counter becomes equal to 5 after the edge has already been observed.
FlexRay Electrical Physical Layer Application Notes
BSS “1”
BSS “0”
Ideal
Waveform
Chapter 3: Example calculation
1st Bit
2nd Bit
3rd Bit
4th Bit
Edge late by
4 sample times
8(n-1) = 24 sample times
8n - 4 = 28 sample times
X X X
Distorted
Waveform
6 7 8 1 2 3 4 5 6 7 8 1
X 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5
Bit strobed as 0
at sample 5
Bit strobed as 0
at sample 5
Bit strobed as 0
at sample 5
Bit strobed as 0
at sample 5
ERROR
Resynchronization
Using a nominal sample time of 12.5 ns, these results imply that the decoder can tolerate an edge that is earlier
than expected by 3 x 12.5 ns = 37.5 ns, and later than expected by 4 x 12.5 ns = 50 ns. As will be described in
later sections, the uncertainty in edge position occurs as a result of various asymmetries in the communication
process. The previous results can be expressed in terms of asymmetry by saying that the decoder described in
[PS05] can tolerate a negative asymmetry of 37.5 ns and a positive asymmetry of 50 ns.
The asymmetric effects depend on the type of edge (i.e., rising vs. falling). As will be described later, the worst
case is the uncertainty related to a rising edge. Also, the asymmetric effects related to clock oscillator differences
increase the farther an edge is from the resynchronization at the falling edge of the BSS. The longest possible
time occurs for the rising edge of the FES, which nominally occurs 80 sample times after the falling edge of the
BSS. This represents the worst case that is analyzed in the remainder of this chapter.
3.3 Contribution of the bus driver
3.3.1 Transmitter
The transmitter consists of a high side driver (pull up) and a low side driver (pull down) for the BP line as well
as the BM line. This architecture is able to guarantee the symmetry in a certain range of the voltages on BP
and BM lines with respect to the VDD/2 level during the transition phases.
Control mechanism of edges is not fully symmetrically. Due to current consumption reduction and two
different output drivers (N; P) a fully symmetrically edge control cannot be met.
In respect to the input signal of TxD and the dependency on the slew rates of rising and falling edges, the
output stage is transmitting accordingly to the bit times on the bus.
According to the Bus Driver output stage architecture, two effects are contributing to the asymmetric propagation
delay:
Slew rates of falling and rising edge are not completely symmetric
Rise and fall edge timing from the specified 10% to 90% may differ, that means
(dBusTx01)/2 ≠ (dBusTx10)/2
Switching from the NP driver to PN driver may cause a delay, which is calculated in both rising and falling edge
slew rate (dBusTx01 and dBusTx10) (according Figure 3-4).
These two assumptions on the transmitter bus driver lead to the conclusion, dBusTx01 ≠ dBusTx10.
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Figure 3-3: Example of late edge for n = 4.
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
3.3.2 Receiver
Slew rates of rising and falling edges are different on the RxD output
Receiving hysteresis for digital conversion implemented. Those thresholds due the voltage range may be
different
dRxD01 ≠ dBusRx01 and dRxD10 ≠ dRxD10
Rise and fall edge times from the bus input are different to the introduced rise and fall edge times on the RxD
transceiver output pin. This may cause an additional asymmetric propagation delay on the receiver bus
driver.
As in Figure 3-5 depicted, asymmetric delays may be introduced on the RxD output because of the input
hysteresis tolerance.
uBus @ TP4
uRxData
100%
300 mV
uBus @ TP1
0V
100%
uBDTx
t
90%
-300 mV
t
-uRxData
0%
dRx01
10%
-uBDTx
RxD
dRx 10
dBDRx 01
dBDRx 10
dBDRx 01
0%
dBusTx01
dBusTx10
100% V DIG
70% V DIG
30% V DIG
0% V DIG
t
dRxD01
Figure 3-4: Transmitter asymmetric
propagation delay contribution.
Version 2.1 Revision B
dRxD10
Figure 3-5: Receiver asymmetric propagation delay
contribution.
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Mainly the effects on the receiver busdriver stage as listed below are contributing to the overall asymmetric
propagation delay:
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
3.4 Asymmetric delays caused by the ECU
The keyword “ECU” summarizes production specific amounts to the asymmetric delay caused by:
asymmetric load to ground e. g. by an asymmetric geometry inside the differential signal chain
briefly reduced slew-rate e. g. by additional parasitic capacities, inductivities and resistors due to PCB wires
and layout behaviors
Node
Active Star
Transmitting
Receiving
Transmitting
Receiving
Static asymmetric delay
Stochastic asymmetric delay
0.25ns
0.25ns
0.25ns
0.25ns
0.25ns
0.25ns
0.25ns
0.25ns
Table 3-1: Experience based assumption of various ECU-related asymmetric delays.
3.5 Requirements for the maximum network (passive star topology)
The following analysis describes the static asymmetric contribution in “maximum networks”, due to slew-rate
variations on the branches and due to the receiver threshold mismatches.
Influence between slew rate, threshold matching and asymmetric delay is below depictured:
dBit_1 e. g. 80ns
dBit_2 e. g. 80ns
TX
TX
Vdif,bus
Vdif,bus
Minimum slew rate to achieve
5ns asymmetric BD delay:
600mV/22.5ns
e. g. 400mV
e. g. 400mV
threshold
e. g. 200mV
e. g. 200mV
threshold
local low slew rate area
due to e. g. reflections
assumption: 600mV/100ns
time
e. g. -170mV
e. g. -200mV
e. g. -400mV
time
thresholds
dBit_1
RX (perfect symmetric
threshold)
e. g. -170mV
e. g. -200mV
thresholds
e. g. -400mV
dBit_2
RX (perfect symmetric
threshold)
? dBit_1
? dBit_2
RX (30mV threshold
missmatch)
RX (30mV threshold
missmatch)
Max. asymmetric delay
due to receiver threshold mismatch
30mV * 22.5ns/600mV = 1.125ns
Max. asymmetric delay
due to receiver threshold mismatch
30mV * 100ns/600mV = 5ns
Test signal achieved by point to point and daisy chain
(expected best case)
Worst case effect of a passive star (local low slew
rates)
Figure 3-6: Asymmetric delays in a maximum net.
The left figure shows the asymmetric delay amount in point-to-point connection due to the accepted slew-rate
and the accepted threshold mismatch. The right figure shows the asymmetric delay amount in passive star
networks.
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The asymmetries and the parasitic will enlarge the static and the stochastic asymmetric delay when interacting
with thresholds and hysteretic of the other involved circuits like e.g. BDs.
Name
uRxThMismatchMax
SlewRateNominal
SlewRateMin
dPassive
Chapter 3: Example calculation
Value
Hint
Description
30mV
EPL
Maximal mismatch of the receiver threshold
voltages
600mV/22.5ns
EPL
Slew-rate of the test-signalRemark:The test signal
has a trapezoid shape
600mV/100ns
Estimation
based on
experience
Estimated minimal slew-rate at the input of a
receiver near to the receiver thresholdsRemark:The
expected input signal is triangular with wavy edges
due to reflections on the lines.
4ns
-
Additional asymmetric delay when using a passive
star.
dPassive ≥
uRxThMismatchMax x
( 1/ SlewRateMin
- 1/ SlewRateNominal)
=
30mV / 600mV x (100ns - 22.5ns)
=
3.875ns
≈
4ns
Table 3-2: Equation and parameters to calculate the additional asymmetric delay
when using a passive star.
3.6 Asymmetric delays due to EMI jitter on different topologies
The keyword “EMI” summarizes all effects to the asymmetric delay when irradiating signals to a FlexRay
network:
field-coupled modulated or non-modulated continuous wave signals, e. g. portable phones, broadcast
stations
line coupled transient signals, e.g. PWM-switched inductive loads
Standardized procedures and set-ups are available to evaluate the effects of irradiated signals:
capacitive coupled modulated or non-modulated continuous wave signals according the FlexRay EMC
Conformance Test Specification e.g. 100 MHz carrier signal with a 1 kHz amplitude modulation (80% ratio)
capacitive coupled transient signals according the FlexRay EMC Conformance Test Specification e.g. ISO
7637-2 test pulses 3a and 3b
Following values are measured and approximated values due to EMI jitters on the 3 main passive network types.
Chapter 12.4.5 of [EPL06] describes potential disquieted and standardized evaluation procedures based on
these values.
Remark
Static asymmetric delay
Stochastic asymmetric delay
Point to point
Experience
0ns
4ns
Daisy chain
Approximation
0ns
8ns
Passive star
Approximation
0ns
8ns
Table 3-3: EMI related asymmetric delays.
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FlexRay Electrical Physical Layer Application Notes
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
EMC related worst case limits can not be calculated
EMC related signals mainly effect the receiving BDs via the bus-linesall other effects can be neglected
Achievable EMC limits are mainly influenced by:
o
Receiver stage of the BD
o
Schematic of the termination circuits
o
Parasitic of the used circuits
o
Cable shielding
o
Twisting of lines
o
Ground connection
o
Layout of the harness inside a vehicle
The EMC behavior of Point-To-Point lines and their receiving Bus Drivers can be specified
o
based on experience in serial automotive busses
o
based on experiences in evaluating BD-prototype samples (DPI measurements)
The EMC behavior of daisy-chain networks and passive star networks can be approximated
o
based on experience in serial automotive busses
o
based on experiences in evaluating BD-prototype samples
3.6.1 EMC calculation method
According to the topology, EM interferes more than one branch. There are two main approaches to consider the
combination of influences on several branches.
The first is the geometric calculation. It is assumed that the different EM interferences on the cable segments are
uncorrelated and independent from each other because of the signal propagation delay in the coupling elements.
Therefore a statistical compensation will occur partly. Thus according to “central limit theorem of statistics” the
resulting EMC budget for the whole system should be calculated statistically by using geometric addition.
The second approach is the linear calculation. It is assumed that the influences on several branches can occur
simultaneously. Therefore all possible influences on several legs shall be added.
The linear calculation is the upper limit for calculating the asymmetric delay contribution. It should be used for
the determination of requirements for systems that cannot deal with lost frames without decreasing the
performance.
For the derivation of system requirements, the EM interferences on one branch (i.e. external EMI and internal
pulses) have to be combined geometric. The result is added linear for several branches.
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The following statements are based on experience and represent the common knowledge:
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
3.6.2 Calculation example of electro-magnetic-interferences
CW
transient
R
CW:
8ns
transient: 8ns
(8ns )2 + (8ns )2
hard:
soft:
= 11.3ns
CW:
4ns
transient: 4ns
(4ns )2 + (4ns )2
CW:
8ns
transient: 8ns
(8ns )2 + (8ns )2
= 5.66ns
= 11.3ns
11.3ns + 5.66ns + 11.3ns = 28.3ns
(11.3ns )2 + (5.66ns )2 + (11.3ns )2
= 17 ns
Figure 3-7: Example calculation of EMI to the asymmetric delay.
Legend:
CW
Continuous Wave
T
Transmitting Node
R
Receiving Node
3.6.3 Glitches
A glitch is a short duration electrical pulse that is usually the result of a fault or design error. It may be caused
also by external influences on particularly digital circuits. In case of network evaluation, glitches are considered
only due to external influences on the network which may harm the networks performance.
Glitches on the bus lines cannot be avoided under all circumstances. During damage tests ISO 7637-2 with
pulses 3a and 3b, coupling directly on the bus lines, glitches have been detected on the RxD lines (please refer
to overview in Table 3-4).
Whether or not such ISO 7637-2 pulse results in a glitch depends when it occurs. If it happens near the edge of
a signal it may only delay an edge. Both delayed edges and actual glitches were observed in the tests.
It is possible that a glitch starts out with very short (essentially zero) time duration and is subsequently extended
by the asymmetric effects in the system.
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T
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
From laboratory experience, applying EMC guidelines when stressing the system with standardized pulses, no
glitches could be observed. However glitches cannot be excluded, basically in dependence of the bustermination, or avoided, and need to be considered as a potential additional contribution to stochastic
asymmetric delays. The most effective way to produce inherent glitch resistance is to use a split-termination
together with a Common Mode Choke.
As an example, the usage of a split-termination brings following considerations:
Sum DC load in the complete system shall not exceed an certain value [EPL06 – Chapter 4.6 DC bus load],
Resistors needs to be adapted to the amount of nodes on FlexRay (varying the resistors on amount of
nodes)
Common Mode Choke
No Common Mode Choke
Split Termination
No glitches
No glitches (only on higher voltages
detected)
No Split Termination
Glitches observed (more sensitive for
glitches as variant without CMC and no
split termination)
Glitches observed
Table 3-4: Exemplary measurements in laboratory condition to detect glitches.
During this measurements following external electronic components have been used:
Common mode choke: 100µH
Split termination capacitor: 4.7nF
Split termination resistors: (2 x) 56 Ohm
3.7 Requirements for components in the scope of FlexRay specification
3.7.1 Oscillator Tolerance
In the current implementation of the Communication Controller [PS05], the worst case would be the rising edge
of the FES or the falling edge in the subsequent BSS, as those represent the maximum time possible without bit
clock alignment. The maximum time without clock alignment is 10 bits multiplied by the nominal bit time gdBit
(1µs).
The FlexRay protocol specification [PS05] specifies a maximum oscillator tolerance of ±1500 ppm (±0.15%).
The tolerance of a FlexRay system to asymmetry improves when higher precision oscillators are employed. In
the following analysis an oscillator tolerance of ±500 ppm (i.e. ±0.05%) is assumed, as this tolerance should be
able to be achieved with the selection of high quality components.
Remark:
As the maximum length without clock synchronization is 10 bits and only reflects the requirement for the coding
and decoding process within the Communication Controller, for the calculation of worst case timings, the clocktree deviation for the Communication Controller on sending and receiving side differs with factor 10 from the
calculation for the Bus Driver and Active Star calculation.
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As the occurrence of glitches cannot be avoided, inverted samples or inverted groups of samples are fed into the
decoding process. Glitches near to edges, even falling or rising, may have the worst influence on the decoding
process.
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
3.7.2 Sending Communication Controller with PLL
For the sending Communication Controller with PLL, asymmetric delay proportion for I/O buffer, pin pads and the
PLL are defined with 2.66 ns, whereby the static proportion amounts to 2 ns and the stochastic to 0.66 ns.
3.7.3 Sending Communication Controller without PLL
If there is no PLL used for the sending Communication Controller, the total asymmetric delay, including I/O
buffer, pin pads and the clock tree proportions, 2.16 ns is calculated. The static proportion amounts to 1.5 ns and
the stochastic to 0.66 ns.
The connection between the Communication Controller and the Bus Driver is assumed as a micro strip line with
600 ps symmetric propagation delay and 70 Ω line impedance. Additionally due to the slew rate mismatch of
both devices an overall asymmetric delay of about 1.2 ns is assumed.
The total assumed asymmetric delay contribution of 1.2 ns is valid for sending and receiving node, with the
difference, that in the sending node, this contribution can be observed only after the Bus Driver and for the
receiving node firstly only after the Communication Controller. For the requirement calculation the appearance of
the individual contribution have to be considered.
3.7.5 Non-monolithic Active Star devices
Designing an Active Star for a FlexRay network provides the possibility to use more than one monolithic device
in a parallel circuitry. With this possibility a high grade of flexibility can be reached, but even may cause an
additional contribution to the asymmetric delay of the system. In the following an Active Star with at least two
Active Star devices is presumed, which a total asymmetric propagation delay of 10 ns within the Active Star.
3.7.6 Example calculation maximum network and worst case EM interferences
To define the allowable limits for semiconductor devices in a FlexRay system, first the sum of worst case
assumptions to be subtracted from the nominal bit length, gives at the certain point of signal chain the remaining
bit length which represents at this point the requirement for the device.
In this example the maximum network, is a topology with two cascaded Active Stars and two Passive Stars. A
Passive Star is assumed with an asymmetric delay proportion of 8 ns, which stochastically may appear,
depending on the layout of this network type (one Passive Star has 4 ns asymmetric delay contribution).
The EMC contribution for this network topology with linear calculation amounts in a total stochastic asymmetric
delay of 28.3 ns, whereby passive star networks with 11.31 ns and peer-2-peer connection with 5.66 ns are
assumed (for more details on EMC contribution please refer to Chapter 3.6).
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3.7.4 Interface between Communication Controller and Bus Driver
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
3.7.6.1 Worst-case calculation for the Bus Driver and Active Star
Summing up of the worst case asymmetric delays in the worst case topology under consideration of the worst
case EMI following asymmetric delays will be seen on the input of the Bus Driver and the Active Star:
Proportion
Sending Node
Crystal (500ppm)
0.05
ns
Sending Communication Controller with PLL
2.16
ns
Sending Bus Driver
4.00
ns
TxD line (interface between CC and BD)
1.20
ns
ECU contribution sending node
0.50
ns
Passive star net
4.00
ns
EMC contribution passive star network
11.31
ns
Active Star device (non-monolithic)
10.00
ns
1.00
ns
34.22
ns
5.66
ns
10.00
ns
1.00
ns
50.88
ns
Network Lines
1st Active Star ECU
Value
ECU contribution Active Star
Max. asymmetric delay on the receiving Active Star input
Network Lines
EMC contribution p2p network
2nd Active Star ECU
Active Star device (non-monolithic)
ECU contribution Active Star
Max. asymmetric delay on the receiving Bus Driver input
Table 3-5
In order to find out the worst-case requirements for the physical devices in a FlexRay network, following
calculation shows the worst-case minimum bit time on the input of these devices in dependency of the baud-rate:
Bit Rate
2.5
Nominal bit time
5
400
10
200
MBit/s
100
ns
Max. asymmetric delay at the Active Star input
-34.22
ns
Max. asymmetric delay at the Receiving Bus Driver input
-50.88
ns
Min. bit time at the Active Star input
365.78
165.78
65.78
ns
Min. bit time at the Bus Driver input
349.12
149.12
49.12
ns
Table 3-6
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Component Description
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
3.7.6.2 Worst-case calculation for the receiving Communication Controller
Summing up of the worst case asymmetric delays in the worst case topology under consideration of the worst
case EMI following asymmetric delays will be seen on the input of the receiving Communication Controller:
Proportion
Sending Node
Crystal (500ppm after the 10th bit - 1µsec)
0.50
ns
Sending Communication Controller with PLL
2.16
ns
TxD line (interface between CC and BD)
1.20
ns
Sending Bus Driver
4.00
ns
ECU contribution sending node
0.50
ns
Passive star net
4.00
ns
EMC contribution passive star network
11.31
ns
Active Star device (non-monolithic)
10.00
ns
ECU contribution Active Star
1.00
ns
Network Lines
EMC contribution p2p network
5.66
ns
2nd Active Star ECU
Active Star Device (non-monolithic)
10.00
ns
ECU contribution Active Star
1.00
ns
Passive Star net
4.00
ns
11.31
ns
Crystal (500ppm after the 10th bit - 1µsec)
0.50
ns
ECU contribution receiving node
0.50
ns
Receiving Bus Driver
5.00
ns
Max. asymmetric delay on the receiving Communication Controller input
72.64
ns
Network Lines
1st Active Star ECU
Network Lines
Value
EMC contribution passive star network
Receiving Node
Table 3-7
In order to find out the worst-case requirements for the Communication Controller in a FlexRay network,
following calculation shows the worst-case minimum bit time on the input of the CC in dependency of the baudrate:
Bit Rate
2.5
Nominal bit time
5
400
Max. asymmetric delay at the receiving Communication Controller
Min. bit time at the receiving Communication Controller input
10
200
MBit/s
100
-72.64
327.36
127.36
ns
ns
27.36
ns
Table 3-8
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Component Description
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
3.7.7 Receiving Communication Controller with PLL
For the receiving Communication Controller with PLL, asymmetric delay proportion for I/O buffer, pin pads and
the PLL are defined as 2.66 ns, whereby the static proportion amounts to 2 ns and the stochastic to 0.66 ns.
3.7.8 Receiving Communication Controller without PLL (1 edge)
If there is for the receiving Communication Controller no PLL used with triggering on one edge, the total
asymmetric delay, including I/O butter, pin pads and the clock tree proportions, is assumed to be 2.16 ns. The
static proportion amounts to 1.5 ns and the stochastic to 0.66 ns.
3.7.9 Receiving Communication Controller without PLL (2 edges)
3.7.10 Requirements for Bus Driver to handle the worst case
According to the timing constraints described above, following minimum bit times for the input of the Bus Driver
(TP4) are derived in order to ensure stable networking with all network topologies.
Topologies with 2 Active Stars, requires the specification of a minimum bit-time sensitiveness of the receiving
Bus Driver. This value is calculated as summation of static and stochastic asymmetric delays from the
components used in a maximum network, including the influence of due to EM effects as described in Chapter
3.6. The values are derived from the worst-case calculation in Chapter 3.7.6.1.
Name
Description
Min
Max
Unit
dBDRxBit @ 10MBit/s
Worst case bit time to be transmitted by the receiving Bus
Driver to the Communication Controller with 10 MBit/s
transmission speed
53
ns
dBDRxBit @ 5MBit/s
Worst case bit time to be transmitted by the receiving Bus
Driver to the Communication Controller with 5 MBit/s
transmission speed
153
ns
dBDRxBit @ 2.5MBit/s
Worst case bit time to be transmitted by the receiving Bus
Driver to the Communication Controller with 2.5 MBit/s
transmission speed
353
ns
dASRxBit @ 10MBit/s
Worst case bit time to be transmitted by the Active Star device
from the receiving branch to the sending branches in a 10
MBit/s network
67
ns
dASRxBit @ 5MBit/s
Worst case bit time to be transmitted by the Active Star device
from the receiving branch to the sending branches in a 5
MBit/s network
167
ns
dASRxBit @ 2.5MBit/s
Worst case bit time to be transmitted by the Active Star device
from the receiving branch to the sending branches in a 2.5
MBit/s network
367
ns
Table 3-9: Requirements for physical interface devices to handle the worst case.
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In order to use a slower clock frequency, the Communication Controller can be triggered on the falling and rising
edge of the used clock. This amounts in a total asymmetric delay of 4.66 ns, including I/O buffer, pin pads and
the sampling clock proportions. The static amount is assumed to be 4 ns and the stochastic to be 0.66 ns.
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
3.7.11 Requirements for Communication Controller to handle the worst case
In order to determine the requirements of the Communication Controller, the key parameters for involving the
digital (de-)coding algorithm together with the analog device behavior are depicted with the maximum
asymmetric delay contribution for sending and receiving and the worst case bit time for a correct decoding
algorithm on the receiving Communication Controller. The values are derived from the worst-case calculation in
Chapter 3.7.6.2.
Description
Min
Max
Unit
dCCRxBit @ 10MBit/s
Worst case bit time to be correctly detected as bit on the
decoding (receiving) Communication Controller with 10 MBit/s
transmission speed.
31
ns
dCCRxBit @ 5MBit/s
Worst case bit time to be correctly detected as bit on the
decoding (receiving) Communication Controller with 5 MBit/s
transmission speed.
131
ns
dCCRxBit @ 2.5MBit/s
Worst case bit time to be correctly detected as bit on the
decoding (receiving) Communication Controller with 2.5
MBit/s transmission speed.
331
ns
dCCTxAsym
Asymmetric delay of the coding (sending) Communication
Controller device
2.16
ns
dCCRxAsym
Asymmetric delay of the decoding (receiving) Communication
Controller device
2.16
ns
Table 3-10: Requirements for the Communication Controller to handle the worst case.
3.7.11.1 Generic calculation method for the Communication Controller requirements
Another way for the definition of the parameters of the Communication Controller is to calculate under
consideration the relation of offset strobing and the samples per bit the worst case bit time with usage of the
nominal bit time:
dCCRxBit ≤ (1 – nStrobeOffset / nSamplesPerBit ) x gdBit
Equation 3-1: Communication Controller parameter equation based on [PS05] implementation.
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Name
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
3.8 How to calculate different topologies
In the following there are the asymmetric contributions exemplary for an Active Star and a passive star network
calculated. As mainly the stochastic contributions but even some static contributions are based assumptions and
experiences, the final value for calculation is up to the system designer.
Transmitting
Node
Receiving
Node
Network
EMC
CC
dTxCCstatic
BD + Tx line
ECU
ECU
dTxBD
dTxEcuStatic
dRxCCstatic
BD
CC + Rx line
Active Star
Active Star
ECU
Passive Star
point-to-point
point-topoint+passive
star
Σ
Maximum
Stochastic Asymmetric
Delay
Value
Maximum
dTxCCstoch
1ns
5.2 ns
1 ns
1 ns
dTxEcuStoch
dRxCCstoch
1ns
1ns
dRxBD
dRxEcuStatic
dAS
dASEcuStatic
5 ns
5.2 ns
8 ns
1 ns
dRxEcuStoch
dASEcuStoch
1ns
1ns
dPassivePath
-
4 ns
-
4 ns
dStaticAsymmetryMax
dEMC
12 ns
dStochasticAsymmetryMax
Table 3-11: Example to calculate the values dStaticAsymmetryMax and dStochasticAsymmetryMax.
According Table 3-7 an exemplary calculation of dStaticAsymmetryMax and dStochasticAsymmetryMax in a
network with one Active Star, whereby one branch is build as a passive star and the other branches are point-topoint connections results in:
dStaticAsymmetryMax = 34.4 ns
dStochasticAsymmetryMax = 17 ns
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Static Asymmetric
Delay
Value
active
Star
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
3.9 Conclusion with respect to topologies
This sub-chapter summarizes the previous sub-chapters regarding:
amount of asymmetric delays of several topologies
limits given by the CC and the BD regarding asymmetric delays
absolute
asymmetric
delay in ns
xx ns
worst case asymmetric delay in ns (all influences without the crystals)
visualization of the probability density distribution
minimum probability density at the worst case
maximal propagation density nearby 0 ns
topology consisting of:
active star (circle)
node (square)
wires (lines)
Figure 3-8: Legend for the following figure.
absolute
asymmetric
delay in ns
80ns
73ns
Decoder 2.1 @ 5MBit/s
36.5ns
Decoder 2.1 @ 10MBit/s
50ns
80ns BD 2.1 @10MBit/s
31.4ns
28.2ns
20ns
10ns
19.2ns
32.2ns
36.2ns
45.2ns
23.2ns
0ns
topology
Figure 3-9: Overview of asymmetric delays and their limits (without EM interferences).
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Limit in ns (the influence of the crystals is included)
given by the CC
given by the BD
xx ns
FlexRay Electrical Physical Layer Application Notes
Chapter 3: Example calculation
Assumptions:
Figures are derived from previous sub-chapters using 500ppm crystals (derivation of the figures described in
chapter 3.7 “Requirements for components in the scope of FlexRay specification”).
In general there exist two limitation factors when transmitting a FlexRay data stream:
The decoder [PS05] inside the receiving CC requires an asymmetric delay of less than 3 sample-periods
The receiving BD requires that the shortest duration of a single bit is longer/equal than 80ns at the input.
Both conditions have to be met by each topology.
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Asymmetric delays resulting from irradiation (EMI) are not included in the figure. The system designer is
responsible for accounting for EM effects on his system. For each individual network, measurements are
necessary and recommended (e. g. according to standardized EMC specifications). If EMC results are not
available it is recommended that the considerations according to chapter 3.6 are used.
=== END OF DOCUMENT ===
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