EVAL-AD8348EB AD8348 Evaluation Board Data Sheet (Rev. 0)

AD8348 Evaluation Board EVAL-AD8348EB BOARD DESCRIPTION Figure 1 shows the schematic for the EVAL-AD8348EB. Note that uninstalled components are indicated with the OPEN designation. The board is powered by a single supply in the range of 2.7 V to 5.5 V. Table 1 details the various configuration options of the evaluation board. Table 2 shows the various jumper configurations for operating the evaluation board with different signal paths. Power to operate the board can be fed to a single +VS test point located near the LO input port at the top of the evaluation board. A GND test point is conveniently provided next to the +VS test point for the return path. The device is enabled by moving Switch SW11 (at the bottom left of the evaluation board) to the ENBL position. The device is disabled by moving SW11 to the DENBL position. If desired, the device can be enabled and disabled from an external source that can be fed into the ENBL SMA connector or the VENB test point, in which case SW11 should be placed in the DENBL position. The IF and MX inputs are selected via SW12. The switch should be moved in the direction of the desired input. For convenience, a potentiometer, R15, is provided to allow for changes in gain without the need for an additional dc voltage source. To use the potentiometer, the SW13 switch must be set to the POT position. Alternatively, an external voltage applied to either the test point or SMA connector labeled VGIN can set the gain. SW13 must be set to the EXT position when an external gain control voltage is used. The local oscillator signal should be fed to the SMA connector J21. This port is terminated in 50 Ω. The LO power input range is from –12 dBm to 0 dBm and at a frequency equal to double that of the IF/MX frequency. The IF input should be fed into the SMA connector IFIP. The VGA must be enabled when this port is used (SW12 in the IF position). The EVAL-AD8348EB is by default set for differential MX drive through a balun (T41) from a single-ended source fed into the MXIP SMA connector. To change to a differential driving source, T41 should be removed along with Resistor R42. The 0 Ω Resistors R43 and R44 should be installed in place of T41 to bridge the gap in the input traces. This will present a nominal differential impedance of 200 Ω (100 Ω each side). The differential inputs should then be fed into SMA connectors MXIP and MXIN. The baseband outputs are made available at the IOPP, IOPN, QOPP, and QOPN test points and SMA connectors. These outputs are not designed to be connected directly to 50 Ω loads and should be presented with loads of approximately 2 kΩ or more. The dc bias level of the baseband amplifier outputs are by default tied to VREF through LK11. If desired, the dc bias level can be changed by removing LK11 and driving a dc voltage onto the VCMO test point. ORDERING GUIDE AD8348 Products AD8348-EVAL Package Description Evaluation Board ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved. EVAL-AD8348EB J21 LO +VS C52 0.1µF 4 5 C51 100pF IOPN J3I IOPN GND T21 ETC1-1-13 QOPN 3 1 GND C9I OPEN R5I 0Ω IOPP C8I OPEN R4I 0Ω C21 1000pF R21 60.4Ω C22 1000pF R5Q 0Ω C9Q OPEN GND R4Q 0Ω C8Q OPEN QOPP J3Q QOPN AD8348 J2I IOPP 1 LOIP LOIN 28 J2Q QOPP 2 VPOS1 COM1 27 3 IOPN C10I 0Ω LK2I R2I OPEN C7I OPEN C13 0.1µF LK4I IMXO L3I OPEN L2I OPEN L1I OPEN LK3I C3I OPEN C2I OPEN C1I OPEN LK1I C6I OPEN C5I OPEN C4I OPEN 4 IOPP QOPP 25 5 VCMO ENVG 24 LK4Q 6 IAIN R1I OPEN COM3 22 8 IMXO QMXO 21 R31 R32 57.6Ω 174Ω C31 1000pF C53 100pF LK5I MXIP 18 12 VPOS2 VGIN 17 13 IOFS QOFS 16 14 VREF ENBL 15 QMXO L1Q OPEN L2Q OPEN L3Q OPEN LK1Q C1Q OPEN C2Q OPEN C3Q OPEN R1Q OPEN C4Q OPEN C55 100pF MXIN 19 11 IFIP C5Q OPEN C56 0.1µF VREF ENBL DENBL IOFS LK2Q C7Q OPEN R2Q OPEN VCMO +VS R44 OPEN R42 C43 1000pF 0Ω MXIN T41 ETK4-2T R43 OPEN LK5Q C11 4.7µF C12 0.1µF POT QOFS C0I 0.1µF Figure 1. Evaluation Board Schematic Rev. 0 | Page 2 of 8 C0Q 0.1µF C42 R41 1000pF OPEN R14 10kΩ SW13 R11 49.9Ω J1Q QMXO C10Q 0Ω MXIP VENB SW11 C6Q OPEN C41 1µF +VS R12 10kΩ ENBL VCMO LK3Q 9 COM2 VPOS3 20 C32 1000pF C54 0.1µF QAIN 23 7 COM3 10 IFIN +VS R3Q 49.9Ω LK11 VCMO IFIP MX SW12 R3I 49.9Ω J1I IMXO IF EXT R13 OPEN R15 10kΩ POT VGIN 04468-0-059 VCMO +VS QOPN 26 04468-0-060 EVAL-AD8348EB Figure 2. Evaluation Board Top Layer Rev. 0 | Page 3 of 8 04468-0-061 EVAL-AD8348EB Figure 3. Evaluation Board Top Silkscreen Rev. 0 | Page 4 of 8 04468-0-062 EVAL-AD8348EB Figure 4. Evaluation Board Bottom Layer Rev. 0 | Page 5 of 8 04468-0-063 EVAL-AD8348EB Figure 5. Evaluation Board Bottom Silkscreen Rev. 0 | Page 6 of 8 EVAL-AD8348EB Table 1. Evaluation Board Configuration Options Component +VS, GND SW11, ENBL SW13, R15, VGIN SW12 IFIP, R31, R32 MXIP, MXIN T41, R41, R42, C42, C43 LK11, VCMO C8, C9, R4, R5 (I and Q) C10 (I and Q) C1–C7 R1, R2 L1–L3 (I and Q) LK5 (I and Q) Function Power Supply and Ground Vector Pins. Device Enable. Place SW11 in the ENBL position to connect the ENBL pin to +VS. Place SW11 in the DENBL position to disable the device by grounding the ENBL pin through a 50 Ω pull-down resistor. The device may also be enabled via an external voltage applied to ENBL or VENB. Gain Control Selection. With SW13 in the POT position, the gain of the VGA can be set using the R15 potentiometer. With SW13 in the EXT position, the VGA gain can be set by an external voltage to the SMA connector VGIN. For VGA operation, the VGA must first be enabled by setting SW12 to the IF position. VGA Enable Selection. With SW12 in the IF position, the ENVG pin is connected to +VS and the VGA is enabled. The IF input should be used when SW12 is in the IF position. With SW12 in the MX position, the ENVG pin is grounded and the VGA is disabled. The MX inputs should be used when SW12 is in the MX position. IF Input: The single-ended IF signal should be connected to this SMA connector. R31 and R32 form an L Pad that presents a 50 Ω termination to the input. Mixer Inputs. These inputs can be configured for either differential or single-ended operation. The evaluation board is by default set for differential MX drive through a balun (T41) from a single-ended source fed into the MXIP SMA connector. To change to a differential driving source, T41 should be removed along with Resistor R42. The 0 Ω Resistors R43 and R44 should be installed in place of T41 to bridge the gap in the input traces. This will present a nominal differential impedance of 200 Ω (100 Ω each side). The differential inputs should then be fed into SMA connectors MXIP and MXIN. Baseband Amplifier Output Bias. Installing LK11 connects VREF to VCMO. This sets the bias level on the baseband amplifiers to VREF, which is equal to approximately 1 V. Alternatively, with LK11 removed, the bias level of the baseband amplifiers can be set by applying an external voltage to the VCMO test point. Baseband Amplifier Outputs and Output Filter. Additional low-pass filtering can be provided at the baseband output with these filters. Mixer Output DC Blocking Capacitors. The mixer outputs are biased to VCMO. To prevent damage to test equipment that cannot tolerate dc biases, C10 is provided to block the dc component, thus protecting the test equipment. Baseband Filter. These components are provided for baseband filtering between the mixer outputs and the baseband amplifier inputs. The baseband amplifier input impedance is high and the filter termination impedance is set by R2. See Table 2 for the jumper settings. Table 2. Filter Jumper Configuration Options LK1x LK2x LK3x • • • • • Rev. 0 | Page 7 of 8 • SW2 = POT SW12 = IF R31 = 57.6 Ω R32 = 174 Ω T41 = M/A-COM ETK4-2T R41, C42, C43 = OPEN R42 = 0 Ω LK11 Installed R4, R5 = 0 Ω C10 = 0 Ω All = OPEN LK5x = OPEN Offset Compensation Loop Disable. Installing these jumpers will disable the offset compensation loop for the corresponding channel. Condition xMXO to xAIN Direct xMXO to xAIN via Filter xMXO to J1x Direct, xAIN Unused xMXO to J1x via Filter, xAIN Unused Drive xAIN from J1x Default Condition Not Applicable SW11 = ENBL LK4x • • • EVAL-AD8348EB NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04468–0–9/03(0) Rev. 0 | Page 8 of 8

EVAL-AD8348EB AD8348 Evaluation Board Data Sheet (Rev. 0)

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